Display panel and preparation method therefor, and display device

Abstract

A display panel (1100), comprising a first substrate (100). The first substrate (100) comprises a first base (10) and at least one group of shielding structures (20) arranged on one side of the first base (10). Each group of shielding structures (20) comprises a stacked film layer (30). The stacked film layer (30) comprises a first metal layer (31), a first dielectric layer (32), a second metal layer (33) and a second dielectric layer (34) which are stacked, wherein the refractive index of the first dielectric layer (32) and the second dielectric layer (34) is a first refractive index K1, the refractive index of the first metal layer (31) and the second metal layer (33) is a second refractive index K2 greater than the first refractive index K1, and the thickness difference between the first metal layer (31) and the second metal layer (33) is greater than a preset numerical value.

Description

Display panel and manufacturing method thereof, and display device

[0001] This application claims priority to international patent application No. PCT / CN2023 / 143109 filed on December 29, 2023, and priority to international patent application No. PCT / CN2024 / 084550 filed on March 28, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0003] With the continuous development of display technology, display devices have been widely used. Common display devices may include but are not limited to liquid crystal display devices (Liquid Crystal Display; LCD for short) and transparent display devices. The above display devices all include a structure for reducing the reflectivity of ambient light and improving the display contrast (referred to as an anti-reflection structure in this article); the anti-reflection structure may be, for example, a black matrix (BM). In addition, as people's requirements for display devices are getting higher and higher, high pixel density (Pixels Per Inch; PPI for short) and high transmittance have become an important development direction for display devices. The critical size of the anti-reflection structure has become an important factor affecting the pixel density and transmittance of the display device. Designing an anti-reflection structure that can adapt to high pixel density and high transmittance has become a technical problem that needs to be solved urgently.

[0004] Summary of the Invention

[0005] In one aspect, a display panel is provided. The display panel includes a first substrate. The first substrate includes a first underlayer and at least one group of shielding structures disposed on one side of the first substrate. Each group of shielding structures includes stacked film layers, the stacked film layers including a first metal layer, a first dielectric layer, a second metal layer, and a second dielectric layer. The refractive index of the first dielectric layer and the second dielectric layer is a first refractive index, the refractive index of the first metal layer and the second metal layer is a second refractive index greater than the first refractive index, and the difference in thickness between the first metal layer and the second metal layer is greater than a preset value.

[0006] In some embodiments, the preset value is 1 nm to 200 nm.

[0007] In some embodiments, the preset value is 20 nm to 100 nm.

[0008] In some embodiments, an angle between a sidewall of the stacked film layer and a reference plane is 15° to 60°. The reference plane is parallel to the first substrate.

[0009] In some embodiments, the thickness of the stacked film layers is less than 1 μm.

[0010] In some embodiments, the light reflectivity of the stacked film layers is less than 6%.

[0011] In some embodiments, the first substrate further includes a first transistor and a first signal line, the first signal line being electrically connected to the first transistor. The orthographic projection of the shielding structure on the first substrate at least partially overlaps with the orthographic projection of at least one of the first transistor and the first signal line on the first substrate. The display panel further includes a second substrate and a liquid crystal layer, the second substrate being disposed opposite the first substrate, the liquid crystal layer being disposed between the first and second substrates.

[0012] In some embodiments, the first substrate further comprises a color filter layer, the color filter layer being disposed on a side of the first transistor and the first signal line away from the first substrate. The at least one group of blocking structures comprises a first group of blocking structures, the first group of blocking structures being disposed on a side of the color filter layer away from the first substrate, and an orthographic projection of the first group of blocking structures on the first substrate at least partially overlapping with an orthographic projection of the first signal line on the first substrate, but not overlapping with an orthographic projection of the color filter layer on the first substrate.

[0013] In some embodiments, the at least one group of blocking structures also includes a second group of blocking structures, and the second group of blocking structures is arranged between the first transistor and the first substrate, and the orthographic projection of the second group of blocking structures on the first substrate at least partially overlaps with the orthographic projection of the first transistor on the first substrate.

[0014] In some embodiments, the first substrate has a display area and a peripheral area, the first transistor is disposed in the display area, and the first substrate further includes a second transistor disposed in the peripheral area, wherein the source and drain of the second transistor are made of the same material and disposed in the same layer as the first gate of the first transistor.

[0015] In some embodiments, a material of the first semiconductor layer of the first transistor is a metal oxide semiconductor material, and a material of the second semiconductor layer of the second transistor is a low-temperature polysilicon material.

[0016] In some embodiments, the first substrate further includes a first semiconductor layer, a first insulating layer, a first gate conductive layer, a second insulating layer, a third insulating layer, and a first source-drain conductive layer, which are sequentially arranged in a direction away from the first substrate. The first transistor includes a first semiconductor pattern located in the first semiconductor layer and a first gate located in the first gate conductive layer. The first substrate further includes a first via and a second via. The first via penetrates the first insulating layer and the second insulating layer and exposes the first semiconductor pattern. The second via penetrates the third insulating layer and is connected to the first via, and the orthographic projection of the second via on the first substrate partially overlaps with the orthographic projection of the first via on the first substrate. Part of the first source-drain conductive layer is electrically connected to the first semiconductor pattern through the second via and the first via.

[0017] In some embodiments, one first via and one second via are provided corresponding to each first transistor, and the first via exposes a first region of the first semiconductor pattern. The first signal line is located in the first source-drain conductive layer, and the first signal line is electrically connected to the first region through the second via and the first via. The first substrate further includes a fourth insulating layer, a third via, and a first electrode. The fourth insulating layer is provided between the first source-drain conductive layer and the first electrode, and the third via penetrates the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer, exposing the second region of the first semiconductor pattern, and the first electrode is electrically connected to the second region through the third via.

[0018] In some embodiments, two first vias and two second vias are provided corresponding to one first transistor, and the two first vias expose the first region and the second region of the first semiconductor pattern, respectively. The first signal line is located in the first source-drain conductive layer, and the first signal line is electrically connected to the first region through the second via and the first via. The first substrate further includes a fourth insulating layer, a fourth via, and a first electrode. The fourth insulating layer is provided between the first source-drain conductive layer and the color filter layer. The fourth via passes through the fourth insulating layer and is connected to another second via and the first via. The first electrode is provided on a side of the fourth insulating layer away from the first substrate, and a portion of the first electrode passes through the fourth via, the second via, and the first via to be electrically connected to the second region.

[0019] In some embodiments, the aperture of the second via hole is smaller than that of the first via hole, and the orthographic projection of the second via hole on the first substrate is within the range of the orthographic projection of the first via hole on the first substrate.

[0020] In some embodiments, an orthographic projection of the second via hole on the first substrate partially overlaps with an orthographic projection of the first via hole on the first substrate.

[0021] In some embodiments, the at least one group of blocking structures includes a third group of blocking structures, the orthographic projections of the third group of blocking structures on the first substrate enclosing a plurality of opening regions. The first substrate further includes a color filter layer, disposed on a side of the third group of blocking structures distal from the first substrate, comprising a plurality of filter portions, at least portions of which are disposed within the opening regions. The display panel further includes a third substrate and a liquid crystal layer, the third substrate being disposed opposite the first substrate, the third substrate including pixel circuitry, and the liquid crystal layer disposed between the first and third substrates.

[0022] In some embodiments, the first substrate includes a light-emitting area and a transparent area. The first substrate further includes a drive circuit layer, the drive circuit layer being disposed in the light-emitting area of ​​the first substrate, the drive circuit layer including a plurality of binding pins. The drive circuit layer includes the shielding structure, and / or the orthographic projection of the shielding structure on the first substrate at least partially overlaps with the drive circuit layer. The display panel further includes a light-emitting element connected to the plurality of binding pins.

[0023] In some embodiments, the driver circuit layer includes a plurality of second signal lines and a plurality of third transistors. The at least one group of shielding structures includes a fourth group of shielding structures, the fourth group of shielding structures being disposed on a side of the driver circuit away from the first substrate, the orthographic projections of the fourth group of shielding structures on the first substrate covering the orthographic projections of the plurality of second signal lines on the first substrate.

[0024] In some embodiments, the fourth group of shielding structures includes a fourth shielding portion, the orthographic projection of the fourth shielding portion on the first substrate covers the orthographic projections of the multiple second signal lines on the first substrate, and there is a first interval between the boundary of the fourth shielding portion and the boundary of the second signal line, and the first interval is greater than or equal to 1μm and less than or equal to 15μm.

[0025] In some embodiments, the driving circuit layer includes a plurality of metal conductive layers, and at least one of the metal conductive layers includes the stacked film layer.

[0026] In another aspect, a method for manufacturing a display panel is provided. The method comprises: forming an initial first metal layer on a substrate motherboard; the substrate motherboard includes multiple spaced-apart panel regions, each panel region being configured to form a display panel; the initial first metal layer covers the substrate motherboard; removing portions of the initial first metal layer outside the panel regions to form an intermediate first metal layer; forming a first dielectric layer and an initial second metal layer in sequence on a side of the intermediate first metal layer facing away from the substrate motherboard; the first dielectric layer and the initial second metal layer covering the substrate motherboard; removing portions of the initial second metal layer and the first dielectric layer outside the panel regions to form an intermediate second metal layer; and forming a second dielectric layer on a side of the intermediate second metal layer facing away from the substrate motherboard. Patterning the second dielectric layer, the intermediate second metal layer, the first dielectric layer, and the intermediate first metal layer to form a shielding structure, the shielding structure comprising a stacked first metal layer, a first dielectric layer, a second metal layer, and a second dielectric layer.

[0027] In some embodiments, the fabrication method further includes: sequentially forming a first semiconductor layer, a first insulating layer, a first gate conductive layer, and a second insulating layer on the substrate motherboard; forming a first via hole penetrating the second insulating layer and the first insulating layer, the first via hole exposing a third region of the first semiconductor layer; forming a third insulating layer on a side of the second insulating layer away from the substrate motherboard, the third insulating layer covering the first via hole; and forming a second via hole penetrating the third insulating layer, the second via hole exposing a portion of the first via hole, and exposing a portion of the third region through the second via hole.

[0028] On the other hand, a display device is provided, comprising the display panel as described in any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0030] FIG1 is a schematic structural diagram of a display device according to some embodiments;

[0031] 2 to 7 are structural diagrams of stacked film layers according to some embodiments;

[0032] FIG8 is a structural diagram of a shielding structure according to some embodiments;

[0033] FIG9 is a structural diagram of a display panel according to some embodiments;

[0034] FIG10 is a planar structural diagram of an array substrate according to some embodiments;

[0035] FIG11 is a cross-sectional structural diagram of an array substrate according to some embodiments;

[0036] FIG12 is another planar structural diagram of an array substrate according to some embodiments;

[0037] FIG13 is another cross-sectional structural diagram of an array substrate according to some embodiments;

[0038] FIG14 is a structural diagram of a second substrate according to some embodiments;

[0039] FIG15 is a structural diagram of orthographic projections of a first group of shielding structures and a second group of shielding structures on a first substrate according to some embodiments;

[0040] FIG16 is a planar structural diagram of a shielding structure according to some embodiments;

[0041] FIG17 is another cross-sectional structural diagram of an array substrate according to some embodiments;

[0042] FIG18 is another cross-sectional structural diagram of an array substrate according to some embodiments;

[0043] FIG19 is another cross-sectional structural diagram of an array substrate according to some embodiments;

[0044] FIG20 is another cross-sectional structural diagram of an array substrate according to some embodiments;

[0045] FIG21 is a schematic diagram of a projection structure of a first via hole and a second via hole according to some embodiments;

[0046] FIG22 is a schematic diagram of another projection structure of the first via hole and the second via hole according to some embodiments;

[0047] FIG23 is a schematic diagram of another projection structure of the first via hole and the second via hole according to some embodiments;

[0048] FIG24 is a structural diagram of a case where the first substrate is a color filter substrate according to some embodiments;

[0049] FIG25 is a structural diagram of a case where the first substrate is a transparent display substrate according to some embodiments;

[0050] FIG26 is a projection diagram of a fourth group of shielding structures and a second signal line according to some embodiments;

[0051] FIG27 is a structural diagram of a case where the first substrate is a transparent display substrate according to some embodiments;

[0052] 28A to 28F are diagrams illustrating a manufacturing process of a display panel according to some embodiments;

[0053] 29A to 29E are diagrams illustrating another process for manufacturing a display panel according to some embodiments. DETAILED DESCRIPTION

[0054] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, rather than all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0055] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0056] In this disclosure, terms such as "lower," "below," "above," and "upper," and similar terms are used to explain the relationships between components shown in the drawings. These terms may be relative and described based on directions shown in the drawings, or based on the order in which process steps are formed, but are not limited thereto.

[0057] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0058] The term "opposite" means that the first element may be directly or indirectly opposite to the second element. In the case where a third element is interposed between the first and second elements, the first and second elements may be understood to be indirectly opposite to each other although they are still opposite to each other.

[0059] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0060] When describing some embodiments, the word "connected" and its derivatives may be used. The term "connected" should be understood broadly. For example, "connected" can mean fixed, removable, or integrated; it can be directly connected or indirectly connected through an intermediary. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0061] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0062] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0063] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0064] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0065] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0066] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0067] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0068] 1 , an embodiment of the present disclosure provides a display device, wherein display device 1000 is a product having an image display function. For example, display device 1000 can be any device that displays either moving (e.g., video) or fixed (e.g., still images), and whether text or images.

[0069] Exemplarily, the display device 1000 can be a television, a laptop computer, a tablet computer, a personal digital assistant (PDA), a mobile phone (cell phone), a watch, a clock, a calculator, a GPS receiver / navigator, a camera, a camera view display (for example, a display of a rearview camera in a vehicle), a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, a mixed reality (MR) device, an in-vehicle display, an aircraft display, or any other product or component with a display function.

[0070] In some embodiments, the display device 1000 may be a liquid crystal display (LCD) or a transparent display device, based on its light-emitting type. The display device 1000 may be a flat display or a curved display, based on its form. The display device 1000 may be rectangular or circular, based on its shape. Of course, the embodiments of the present disclosure are not limited thereto, and any other display device may be considered, as long as the same technical concepts are applied.

[0071] In some embodiments, the display device 1000 includes a display panel 1100 (also referred to as a display substrate) and a driver circuit board. The driver circuit board may include, for example, a timing controller (TCON), a power management chip (DC / DC), and an adjustable resistor divider circuit (generating Vcom) and other driving circuits. The driver circuit board may also include other circuit structures, which are not listed here one by one. The driver circuit board is electrically connected to the display panel 1100 and is used to transmit a control signal to the display panel 1100, thereby driving the display panel 1100 to realize image display. In addition, the display device 1000 may also include a touch structure, an under-screen camera, and an under-screen fingerprint recognition sensor, so that the display device 1000 can realize a variety of different functions such as touch, photo taking, video recording or fingerprint recognition, which are not listed here one by one.

[0072] The display panel 1100 may include an anti-reflection structure that can shield at least a portion of metal traces (such as first signal lines and gate lines) in the display panel at an observation angle, and the light reflectivity of the anti-reflection structure is less than a preset threshold. In this way, at least a portion of the light reflected by the metal traces is shielded by the anti-reflection structure, thereby reducing the display panel's reflection of ambient light. Furthermore, the anti-reflection structure can separate adjacent sub-pixels, thereby reducing light crosstalk between adjacent sub-pixels and improving the display contrast of the display panel.

[0073] A display device is provided in the related art, which uses a black matrix (BM) on a color film (CF) substrate as an anti-reflection structure. The black matrix can be prepared by organic materials. Due to the limitations of the materials and preparation process of the black matrix, the critical dimension (CD) of the black matrix cannot be further reduced. For example, the critical dimension of the black matrix pattern is usually greater than 2.5μm, which cannot meet the requirements of a smaller size, resulting in the inability to meet the display technology requirements of a display resolution ≥1500PPI, especially in display devices such as augmented reality (AR) devices, virtual reality (VR) devices, and mixed reality (MR) devices with high PPI requirements. Moreover, the thickness of the black matrix prepared by organic materials is usually greater than or equal to 1μm, and it cannot be thinned to a thinner thickness.

[0074] To address at least one of the aforementioned technical issues, an embodiment of the present disclosure provides a display panel 1100. Referring to FIG2 , the display panel 1100 includes a first substrate 100. The first substrate 100 includes a first backing 10 and at least one group of shielding structures 20 disposed on one side of the first backing 10. Each group of shielding structures 20 includes a stacked film layer 30, which includes a first metal layer 31, a first dielectric layer 32, a second metal layer 33, and a second dielectric layer 34. The refractive index of the first dielectric layer 32 and the second dielectric layer 34 is a first refractive index K1, and the refractive index of the first metal layer 31 and the second metal layer 33 is a second refractive index K2 that is greater than the first refractive index K1, i.e., K2>K1. Furthermore, the difference in thickness between the first metal layer 31 and the second metal layer 33 is greater than a predetermined value, where the thickness of the first metal layer 31 can be greater than the thickness of the second metal layer 33, or the thickness of the first metal layer 31 can be less than the thickness of the second metal layer 33.

[0075] The stacked film layer 30 can form an anti-reflection structure to replace the black matrix used in traditional technologies. The stacked film layer 30 not only blocks the reflection of the relevant metal traces in the display panel 1100, but also effectively prevents the problem of cross-color between adjacent sub-pixels when the stacked film layer 30 is used in the anti-reflection structure, thereby ensuring the display effect of the display panel 1100. The stacked film layer 30 includes a first metal layer 31, a first dielectric layer 32, a second metal layer 33, and a second dielectric layer 34. During the actual preparation process of the stacked film layer 30 through processes such as exposure and etching, the critical dimension of the pattern of the stacked film layer 30 can be set to less than 2μm, the total thickness of the stacked film layer 30 can be set to less than 1μm, and the reflectivity of the stacked film layer 30 can be reduced to less than 6%. In other words, the use of the stacked film layer 30 in the embodiment of the present disclosure can not only effectively reduce the size of the critical dimension of the pattern of the shielding structure 20, but also effectively reduce the total thickness of the shielding structure 20. Based on this, not only can the aperture ratio and transmittance of the display panel 1100 be improved by stacking the film layer 30 and the risk of cross-color between adjacent pixels be reduced, but the display contrast of the display device can also be improved by reducing the light reflectivity of the display panel 1100, thereby providing the possibility for high PPI (for example, greater than 1500PPI) design of the display product, which is conducive to the high PPI design of the display panel 1100.

[0076] It should be noted that the reflectivity of the blocking structure 20 and / or the stacked film layer 30 is described in multiple embodiments of the present disclosure, but the blocking structure 20 and the stacked film layer 30 are both integrated into the display device rather than a single structure. Based on this, when describing or defining the "reflectivity of the stacked film layer (or blocking structure)" in any embodiment, the reflectivity of the stacked film layer (or blocking structure) can be actually measured by preparing a stacked film layer with the same structure (the position, material and thickness of each film layer are correspondingly equal), and then measuring the reflectivity of the stacked film layer; or, it can also be simulated and measured by an optical simulation device based on data such as the position, thickness, material and refractive index of each film layer. Of course, the specific measurement method of the reflectivity of the stacked film layer (or blocking structure) is not limited to this, and any other method that can actually measure the reflectivity of the corresponding stacked film layer (or blocking structure) can be used to measure the reflectivity of the corresponding stacked film layer (or blocking structure).

[0077] Exemplarily, the refractive index K1 of the first dielectric layer 32 and the second dielectric layer 34 can be 1.8, and the refractive index of the first metal layer 31 and the second metal layer 33 can be 3.5. Of course, the specific materials of each film layer in the stacked film layer 30 can also be set, and the refractive index of the corresponding film layer can be set according to actual application needs. In this way, when the stacked film layer 30 is placed above the relevant metal traces to form the shielding structure 20, the reflection of the corresponding traces covered by the shielding structure 20 can be effectively blocked, thereby effectively reducing the reflection of light by the display panel through the stacked film layer 30. In addition, the difference in thickness between the first metal layer 31 and the second metal layer 33 is greater than a preset value. Exemplarily, the thickness of the first metal layer 31 is greater than the thickness of the second metal layer 33, and the difference between the thickness of the first metal layer 31 and the thickness of the second metal layer 33 is greater than a preset value. Exemplarily, the thickness of the first metal layer 31 is 100 nm, and the thickness of the second metal layer 33 is 6 nm, and the preset value is 30 nm. In the embodiments of the present disclosure, when describing the thickness of a structure or film layer, it refers to the dimension of the portion of the structure or film layer parallel to the first substrate 10 in a direction perpendicular to the first substrate 10. The structure of the stacked film layer 30 is described below using several exemplary embodiments. It should be understood that the embodiments of the present disclosure include but are not limited to the following exemplary embodiments.

[0078] In some embodiments, the preset value may be in the range of 1 nm to 200 nm. In this case, the shielding structure formed by the stacked film layer 30 can have a good light shielding effect and effectively reduce light reflection. For example, the preset value may be in the range of 1 nm to 20 nm, 20 nm to 100 nm, or 100 nm to 200 nm, etc., which are not listed one by one in the embodiments of the present disclosure.

[0079] In some embodiments, the preset value may range from 20 nm to 100 nm. For example, the preset value may be 20 nm, 30 nm, 50 nm, 94 nm or 100 nm, etc. The specific value of the preset value may be set according to actual application needs and is not specifically limited here.

[0080] In an exemplary embodiment, as shown in FIG2 , a first metal layer 31, a first dielectric layer 32, a second metal layer 33, and a second dielectric layer 34 are sequentially arranged away from the first substrate 10, and the thickness of the first metal layer 31 is greater than the thickness of the second metal layer 33. In this exemplary embodiment, the stacked film layer 30 can achieve a single-sided anti-reflection effect (i.e., reducing single-sided reflected light). Accordingly, when the stacked film layer 30 is used in the shielding structure 20, the stacked film layer 30 essentially forms a blackened anti-reflection film that reduces single-sided reflection.

[0081] For example, as shown in FIG2 , the materials of the first metal layer 31 and the second metal layer 33 may include, but are not limited to, at least one of molybdenum (Mo), tungsten (W), copper (Cu), aluminum (Al), and molybdenum-tungsten alloy (MoW); the materials of the first dielectric layer 32 and the second dielectric layer 34 may include, but are not limited to, at least one of silicon nitride (SiNx, where x>0), silicon dioxide (SiO2), aluminum oxide (Al2O3), and titanium oxide (TiO2). The thickness of the first metal layer 31 may be no less than 40 nm, for example, the thickness of the first metal layer 31 may be in the range of 50 nm to 300 nm; the thickness of the second metal layer 33 may be in the range of 1 nm to 100 nm; the thickness of the first dielectric layer 32 may be in the range of 10 nm to 100 nm, and the thickness of the second dielectric layer 34 may be in the range of 10 nm to 300 nm.

[0082] For example, in a specific embodiment of the stacked film layer 30 shown in FIG2 , the first metal layer 31 and the second metal layer 33 are made of Mo, the first dielectric layer 32 and the second dielectric layer 34 are made of SiNx, the thickness of the first metal layer 31 is 100 nm, and the thickness of the second metal layer 33 is 6 nm, with the preset value being 94 nm. In this specific embodiment, the stacked film layer 30 achieves a single-sided reflectivity of 1.4% and a transmittance of 0.0035% for light with a wavelength of 550 nm. This demonstrates that the stacked film layer 30 exhibits excellent anti-reflection and light-shielding effects.

[0083] In another exemplary embodiment, as shown in FIG3 , based on the stacked film layer 30 shown in FIG2 , the stacked film layer 30 further includes a third dielectric layer 35, a third metal layer 36, and a fourth dielectric layer 37, which are sequentially disposed away from the first substrate 10. The first metal layer 31 is located between the fourth dielectric layer 37 and the first dielectric layer 32. The refractive indexes of the third dielectric layer 35 and the fourth dielectric layer 37 are the first refractive index K1, the refractive index of the third metal layer 36 is the second refractive index K2, and the thickness of the third metal layer 36 is less than the thickness of the first metal layer 31. In this exemplary embodiment, the stacked film layer 30 can achieve a double-sided anti-reflection effect (i.e., reducing double-sided reflected light). Accordingly, when the stacked film layer 30 is used in the shielding structure 20, the stacked film layer 30 essentially forms a blackened anti-reflection film that reduces single-sided reflection.

[0084] For example, as shown in FIG3 , the materials of the first metal layer 31, the second metal layer 33, and the third metal layer 36 may include, but are not limited to, at least one of molybdenum (Mo), tungsten (W), and a molybdenum-tungsten alloy (MoW); the materials of the first dielectric layer 32, the second dielectric layer 34, and the third dielectric layer 35 may include, but are not limited to, at least one of silicon nitride (SiNx), silicon dioxide (SiO2), aluminum oxide (Al2O3), and titanium oxide (TiO2). The thickness of the first metal layer 31 is not less than 40 nm; the thickness of the second metal layer 33 and the third metal layer 36 is in the range of 5 nm to 8 nm; the thickness of the first dielectric layer 32 is in the range of 40 nm to 70 nm, the thickness of the second dielectric layer 34 is in the range of 40 nm to 70 nm, the thickness of the third dielectric layer 35 is in the range of 40 nm to 70 nm, and the thickness of the fourth dielectric layer 37 is in the range of 40 nm to 70 nm.

[0085] For example, in a specific embodiment of the stacked film layer 30 shown in FIG3 , the first metal layer 31 is made of Mo and has a thickness of 100 nm; the first dielectric layer 32 is made of SiNx and has a thickness of 45 nm; the second metal layer 33 is made of Mo and has a thickness of 6 nm; the second dielectric layer 34 is made of SiNx and has a thickness of 65 nm; the third dielectric layer 35 and the fourth dielectric layer 37 are both made of SiNx and have a thickness of 50 nm; and the third metal layer 36 is made of Mo and has a thickness of 50 nm. In this specific embodiment, the stacked film layer 30 can achieve a double-sided reflectivity of 1.4% and a transmittance of 0.0035% for light with a wavelength of 550 nm. Therefore, the stacked film layer 30 can provide excellent anti-reflection and light-shielding effects.

[0086] In yet another exemplary embodiment, as shown in FIG4 , in addition to the stacked film layer 30 shown in FIG2 , the stacked film layer 30 further includes a first functional layer 38 positioned between the first dielectric layer 32 and the second metal layer 33. The refractive index K3 of the first functional layer 38 is less than the refractive index K2 of the second metal layer 33, and greater than the refractive index K1 of the first dielectric layer 32; that is, K3 is between K1 and K2. In this exemplary embodiment, the stacked film layer 30 can achieve a single-sided anti-reflection effect. Accordingly, when the stacked film layer 30 is used in a shielding structure, the stacked film layer 30 is essentially a blackened anti-reflection film that provides single-sided anti-reflection.

[0087] 4 , the materials of the first metal layer 31 and the second metal layer 33 may include but are not limited to at least one of molybdenum (Mo), tungsten (W) and molybdenum-tungsten alloy (MoW); the materials of the first dielectric layer 32, the second dielectric layer 34 and the first functional layer 38 may include but are not limited to at least one of silicon nitride (SiNx), silicon dioxide (SiO2), aluminum oxide (Al2O3) and titanium oxide (TiO2).

[0088] In a specific embodiment of the stacked film layer 30 shown in FIG4 , the first metal layer 31 and the second metal layer 33 are made of Mo, the first functional layer 38 is made of TiN, and the first dielectric layer 32 and the second dielectric layer 34 are made of SiNx. The stacked film layer 30 shown in FIG4 can achieve a single-sided reflectivity of 0.15% and a transmittance of 0.0026% for light with a wavelength of 550 nm. In specific implementations, the stacked film layer 30 shown in FIG4 can further reduce light reflectivity and transmittance compared to the stacked film layer 30 shown in FIG2 .

[0089] In an exemplary embodiment, as shown in FIG5 , based on the stacked film layer shown in FIG2 , the stacked film layer 30 further includes a fifth dielectric layer 39, a fourth metal layer 310, a second functional layer 311, and a sixth dielectric layer 312, which are sequentially disposed away from the first substrate. The refractive indexes of the fifth dielectric layer 39 and the sixth dielectric layer 312 are both the first refractive index K1, the refractive index of the fourth metal layer 310 is the second refractive index K2, and the refractive index of the second functional layer 311 is less than the refractive index of the second metal layer 33 and greater than the first refractive index K1. In this exemplary embodiment, the stacked film layer 30 can achieve a double-sided anti-reflection effect. Accordingly, when the stacked film layer 30 is used in the shielding structure 20, the stacked film layer 30 is essentially a blackened anti-reflection film for double-sided anti-reflection.

[0090] Exemplarily, the first dielectric layer 32, the second dielectric layer 34, the fifth dielectric layer 39, and the sixth dielectric layer 312 are made of SiNx; the first metal layer 31, the second metal layer 33, and the fourth metal layer 310 are made of Mo; and the first functional layer 38 and the second functional layer 311 are made of TiN. In a specific embodiment, the stacked film layer 30 shown in FIG5 can achieve a double-sided reflectivity of 0.15% and a transmittance of 0.0006% for light with a wavelength of 550 nm. Compared to the stacked film layer 30 shown in FIG3, the stacked film layer 30 shown in FIG5 can further reduce the reflectivity of the corresponding substrate to light.

[0091] In an exemplary embodiment, as shown in FIG6 , a first metal layer 31, a first dielectric layer 32, a second metal layer 33, and a second dielectric layer 34 are sequentially disposed near the first substrate 10, and the thickness of the first metal layer 31 is greater than the thickness of the second metal layer 33. In this exemplary embodiment, the stacked film layer 30 can achieve a single-sided anti-reflection effect. Accordingly, when the stacked film layer 30 is used in the shielding structure 20, the stacked film layer 30 is essentially a blackened anti-reflection film that provides single-sided anti-reflection.

[0092] Exemplarily, the material of the first metal layer 31 and the second metal layer 33 is Mo, and the material of the first dielectric layer 32 and the second dielectric layer 34 is SiNx. Exemplarily, the stacked film layer 30 shown in FIG6 can achieve a single-sided reflectivity of 1.4% and a transmittance of 0.0035% for light with a wavelength of 550 nm. It should be noted that the stacked film layer 30 shown in FIG2 and the stacked film layer 30 shown in FIG6 are actually prepared in a different order. Moreover, in the embodiment shown in FIG2, the stacked film layer 30 can anti-reflect light incident from the second dielectric layer 34; in the embodiment shown in FIG6, the stacked film layer 30 can anti-reflect light incident from the first substrate.

[0093] In an exemplary embodiment, as shown in FIG7 , a first metal layer 31, a first dielectric layer 32, a second metal layer 33, and a second dielectric layer 34 are sequentially disposed near the first substrate 10, and a third functional layer 313 is further disposed between the first dielectric layer 32 and the second metal layer 33. The refractive index of the third functional layer 313 is less than that of the second metal layer 33, but greater than that of the first dielectric layer 32 and the second dielectric layer 34. In this embodiment, the stacked film layer 30 can achieve a single-sided anti-reflection effect. Accordingly, when the stacked film layer 30 is used in the shielding structure 20, the stacked film layer 30 is essentially a blackened anti-reflection film that provides single-sided anti-reflection.

[0094] Exemplarily, the first metal layer 31 and the second metal layer 33 are made of Mo; the third functional layer 313 is made of TiN; and the first dielectric layer 32 and the second dielectric layer 34 are made of SiNx. Exemplarily, the stacked film layer 30 shown in FIG7 can achieve a single-sided reflectivity of 0.15% and a transmittance of 0.0026% for light with a wavelength of 550 nm. In specific implementations, the stacked film layer 30 shown in FIG7 can further reduce the reflectivity of the corresponding substrate to light compared to the stacked film layer 30 shown in FIG6 .

[0095] It should be noted that, in addition to setting the stacked film layer 30 according to the multiple exemplary embodiments mentioned above (such as the solutions shown in Figures 2 to 7), the specific structure of the stacked film layer 30 and the specific thickness of each film layer can also be set according to actual application needs. The embodiments of the present disclosure will not give examples one by one. In the following embodiments of the present disclosure, the stacked film layer 30 shown in Figure 2 is used as an example to illustrate the present disclosure, but the embodiments of the present disclosure are not limited to this, and the shielding structure 20 can consider any other suitable stacked film layer 30.

[0096] In some embodiments, as shown in FIG8 , the contacting surfaces of two adjacent film layers in the stacked film layers 30 included in each group of shielding structures 20 overlap, and the stacked film layers 30 may be the stacked film layers 30 in any of the above-mentioned embodiments. Based on this, in the actual preparation process of the stacked film layers 30 of the desired pattern by processes such as exposure and etching (the specific preparation process can be referred to steps S11 to S16 of the method for preparing the display panel below), the multiple film layers included in the stacked film layers 30 can be deposited in sequence first, and then the multiple film layers included in the stacked film layers 30 can be patterned simultaneously. For example, the first metal layer 31, the first dielectric layer 32, the second metal layer 33, and the second dielectric layer 34 are first formed within the range of the display panel, and then the first metal layer 31, the first dielectric layer 32, the second metal layer 33, and the second dielectric layer 34 are patterned simultaneously by a dry etching process to form the desired pattern. In this way, the requirements for the alignment accuracy during the patterning process of two adjacent film layers in the stacked film layer 30 can be reduced, and the risk of steps forming between the two adjacent film layers or the upper film layer covering the edge of the lower film layer can be reduced, thereby reducing the key dimension deviation of the stacked film layer 30, which is conducive to reducing the size of the shielding structure 20, thereby improving the opening ratio and light output rate of the display panel 1100.

[0097] For example, when the stacked film layer 30 is composed of a first metal layer 31, a first dielectric layer 32, a second metal layer 33 and a second dielectric layer 34, the surfaces of the first metal layer 31 and the first dielectric layer 32 in contact with each other may overlap, the surfaces of the first dielectric layer 32 and the second metal layer 33 in contact with each other may overlap, and the surfaces of the second metal layer 33 and the second dielectric layer 34 in contact with each other may overlap.

[0098] Continuing to refer to FIG8 , in some embodiments, the angle α between the sidewall of the stacked film layer 30 included in each group of shielding structures 20 and the reference plane is 15° to 60°; the reference plane is parallel to the first substrate 10. In other words, the inclination angle of the sidewall of the stacked film layer 30 ranges from 15° to 60°. This is beneficial for reducing the line width of the stacked film layer 30, reducing the impact of the stacked film layer 30 on the pixel opening of the display panel, and ensuring the area of ​​the positive projection of the pixel opening of the display panel on the first substrate. For example, the angle α between the sidewall of the stacked film layer 30 and the reference plane can be 15°, 30°, 41°, 55° or 60°, etc., and the embodiments of the present disclosure will not list them one by one.

[0099] In addition, the higher the pixel density / resolution of the display panel, the larger the value of the angle α can be set to reduce the impact on the opening. For example, for a display panel with a pixel density of less than 1000 PPI, the angle α between the sidewall of the stacked film layer 30 and the reference plane can be greater than or equal to 15° and less than or equal to 80°; for a display panel with a pixel density of 1000+PPI, the angle α between the sidewall of the stacked film layer 30 and the reference plane can be greater than or equal to 40° and less than or equal to 80°; for a display panel with a pixel density of 1500+PPI, the angle α between the sidewall of the stacked film layer 30 and the reference plane can be greater than or equal to 50° and less than or equal to 80°; for a display panel with a pixel density of 2000+PPI, the angle α between the sidewall of the stacked film layer 30 and the reference plane can be greater than or equal to 60° and less than or equal to 80°.

[0100] In some embodiments, the total thickness of the stacked film layer 30 is less than 1 μm, that is, the sum of the thicknesses of all film layers included in the stacked film layer 30 is less than 1 μm. For example, the specific film layer structure of the stacked film layer 30 and the specific thickness of each film layer can be set according to actual application needs, but the total thickness is less than 1 μm. In this way, it is beneficial to control the key graphic dimensions of the stacked film layer 30, to improve the aperture ratio and light transmittance of the display panel, and to reduce the risk of cross-color between adjacent sub-pixels, and to improve the display contrast of the display panel, which is beneficial to the design of high pixel density (such as greater than 1500PPI) of the display panel. For example, the thickness of the stacked film layer 30 can be 0.5 μm, 0.6 μm, 0.85 μm or 1 μm, etc., and the embodiments of the present disclosure will not list them one by one.

[0101] In some embodiments, the light reflectivity of the stacked film layer 30 can be less than 6%. In this way, when the stacked film layer 30 is placed above the relevant metal traces, the reflection of the relevant metal traces can be effectively blocked, thereby effectively reducing the light reflection of the relevant metal traces through the stacked film layer 30.

[0102] The following describes the embodiments of the present application by taking a liquid crystal display device and a transparent display device as examples. Of course, the embodiments of the present disclosure are not limited thereto, and any other suitable display device may be considered.

[0103] In the case where the display device 1000 is a liquid crystal display device, in addition to including a display panel and a driver circuit board, the display device 1000 may also include a backlight disposed on the backlight side of the display panel 1100. For example, the backlight may be a direct-lit backlight or an edge-lit backlight, etc., and the backlight is used to provide light for the display panel 1100. The display panel 1100 includes a plurality of sub-pixels, each of which can adjust the amount of light passing through the sub-pixel, thereby enabling each sub-pixel to display the same or different grayscales to achieve the purpose of image display.

[0104] Referring to FIG9 , in the case where the display panel 1100 is a liquid crystal display substrate, the display panel 1100 may include a first substrate 100 and a second substrate 200 disposed opposite each other, and a liquid crystal layer 300 disposed between the first substrate 100 and the second substrate 200. Of course, the structure of the display panel 1100 is not limited thereto, and the display panel 1100 may also include other structures as long as the same technical concept is adopted. For example, the display panel 1100 may further include a first alignment film (not shown in the figure) disposed on a side of the first substrate 100 close to the liquid crystal layer 300, and a second alignment film (not shown in the figure) disposed on a side of the second substrate 200 close to the liquid crystal layer 300.

[0105] One of the first substrate 100 and the second substrate 200 is an array substrate, and the other is a color filter substrate, which may also be referred to as an opposing substrate or a packaging substrate. In the embodiment of the present disclosure, the first substrate 100 includes at least one set of blocking structures 20. In other words, at least one set of blocking structures 20 is provided on both the array substrate and the color filter substrate.

[0106] In some embodiments, referring to Figures 10 and 11 , the first substrate 100 further includes a first transistor T1 and a first signal line DL. In this embodiment, the first substrate 100 is configured as an array substrate, and the second substrate 200 is configured as a color filter substrate or a package substrate. At least one set of shielding structures 20 is provided on the first substrate 100 (array substrate). The shielding structures 20 can be used to shield signal lines (such as the first signal line) on the first substrate 100 to reduce light reflection from corresponding signal lines (such as the first signal line) on the first substrate 100.

[0107] In one embodiment, as shown in FIG11 , the first substrate 100 may include a first semiconductor layer ACT1, a first insulating layer GI2, a first gate conductive layer Gate1, a second insulating layer ILD1, and a first source / drain conductive layer SD1, sequentially arranged in a direction away from the first substrate 10 (from bottom to top in FIG11 ). The first transistor T1 may include a first semiconductor pattern 11 located in the first semiconductor layer ACT1 and a first gate electrode 12 located in the first gate conductive layer Gate1. A first signal line DL may be located in the first source / drain conductive layer SD1 and may be connected to the first semiconductor pattern 11 of the first transistor T1, such as to a source contact region of the first semiconductor pattern 11. The first signal line DL may be a data signal line configured to transmit a data signal, and the portion of the first signal line DL connected to the first semiconductor pattern 11 forms the source or drain of the first transistor T1.

[0108] For example, as shown in FIG10 , the first gate conductive layer Gate1 includes a plurality of gate lines GL, which intersect with a plurality of first signal lines DL to form a plurality of grids, each grid defining a pixel region 101. The first substrate 100 includes a plurality of pixel regions 101. In the embodiment of the present disclosure, the extending direction of the gate lines GL is a first direction X, and the extending direction of the first signal lines DL is a second direction Y. The first direction X intersects the second direction Y; for example, the first direction X is perpendicular to the second direction Y.

[0109] As shown in Figures 10 and 11, the first substrate 100 may further include a first electrode 51 and a second electrode 52 disposed on a side of the first signal line DL away from the first substrate 10, wherein the second electrode 52 is not shown in Figure 10. One of the first electrode 51 and the second electrode 52 is configured as a pixel electrode and electrically connected to the first transistor T1, and the other is configured as a common electrode and connected to the common voltage signal line. For example, the first electrode 51 is configured as a pixel electrode and electrically connected to the first transistor T1, and the second electrode 52 is configured as a common electrode.

[0110] Continuing with FIG11 , in some embodiments, the first electrode 51 may include a first sub-electrode 511, a second sub-electrode 512, and a third sub-electrode 513. The first sub-electrode 511 is disposed on a side of the fourth insulating layer PVX1 away from the first substrate 10 and is electrically connected to the first semiconductor pattern 11 through a via. The second sub-electrode 512 is disposed on a side of the first sub-electrode 511 away from the first substrate 10, and a first planar layer PLN1 is disposed between the second sub-electrode 512 and the first sub-electrode 511.

[0111] The second sub-electrode 512 is electrically connected to the first sub-electrode 511 via a via extending through the first planar layer PLN1. The third sub-electrode 513 is disposed on the side of the second sub-electrode 512 facing away from the first substrate 10. A second planar layer PLN2 is located between the third sub-electrode 513 and the second sub-electrode 512. The second planar layer PLN2 is located within the via formed in the first planar layer PLN1 and serves to increase the flatness of the third sub-electrode 513. This helps reduce surface roughness and improves the flatness of the third sub-electrode 513, thereby enhancing the uniformity of the electric field formed between the third sub-electrode 513 and the common electrode 52. A sixth insulating layer PVX2 is also located between the third sub-electrode 513 and the second electrode 52. It should be understood that the structure of the first and second electrodes 51 and 52 shown in FIG11 is only one specific embodiment, not the only feasible implementation. The structures of the first and second electrodes 51 and 52 can be customized based on actual needs.

[0112] In one exemplary embodiment, the first signal line DL and the first electrode 51 (first sub-electrode 511) are electrically connected to the source contact region and the drain contact region of the first semiconductor pattern 11, respectively. The first signal line DL transmits a data signal. When the first transistor T1 is turned on under the control of the first gate electrode 12, the first signal line DL transmits the data signal to the first electrode 51. An electric field is formed between the first electrode 51 and the second electrode 52, driving the liquid crystal molecules in the liquid crystal layer to deflect, thereby regulating the light passing through the liquid crystal layer.

[0113] Referring to Figures 10 and 11, at least one group of shielding structures 20 may include a first group of shielding structures 21, that is, the first substrate 100 includes a first group of shielding structures 21. The first group of shielding structures 21 includes the stacked film layer 30 described in any of the above embodiments. The first group of shielding structures 21 can be arranged between the second electrode 52 and the sixth insulating layer PVX2. The orthographic projection of the first group of shielding structures 21 on the first substrate 10 at least partially overlaps with the orthographic projection of the first signal line DL on the first substrate 10 to reduce the reflection of light by the first signal line DL. In addition, the first group of shielding structures 21 can also separate adjacent pixel areas 101 to avoid cross-color between adjacent pixel areas 101.

[0114] For example, as shown in FIG10 , the orthographic projection of the first group of shielding structures 21 on the first substrate 10 covers the orthographic projection of the first signal line DL on the first substrate 10, and there is a second interval D2 between the boundary of the orthographic projection of the first group of shielding structures 21 on the first substrate 10 and the boundary of the orthographic projection of the first signal line DL on the first substrate 10. The second interval D2 is greater than or equal to 1 μm and less than or equal to 15 μm, that is, 1 μm ≤ D2 ≤ 15 μm. In this way, the first group of shielding structures 21 can greatly block the light reflected by the first signal line DL, reduce the reflection of light by the first substrate 100, and improve the display effect of the display panel. For example, the second interval D2 can be 1 μm, 3 μm, 5 μm, 10 μm or 15 μm, and the embodiments of the present disclosure will not list them one by one.

[0115] Referring to Figures 12 and 13 , in some embodiments, in addition to the first substrate 100 shown in Figures 10 and 11 , the first substrate 100 further includes a color filter layer 40. The color filter layer 40 is disposed on a side of the first transistor T1 and the first signal line DL that is away from the first substrate 10. In other words, the array substrate may utilize color film on array (COA) technology. This significantly improves the alignment accuracy between the color filter layer 40 and the first substrate 100, reduces the impact of the alignment accuracy between the first substrate 100 and the second substrate 200 on the aperture ratio of the display panel, and thereby improves the aperture ratio and light extraction efficiency of the display panel.

[0116] Exemplarily, the color filter layer 40 may include multiple filter sections 41, with one filter section 41 disposed within each pixel region 101. The multiple filter sections 41 are configured to filter light passing therethrough, allowing only light of a single color to pass through. For example, the multiple filter sections 41 may include, but are not limited to, a red filter section, a blue filter section, and a green filter section. The red filter section only allows red light to pass through, the blue filter section only allows blue light to pass through, and the green filter section only allows green light to pass through. The color filter layer 40 enables the display panel to display color images.

[0117] As shown in Figure 13, in this embodiment, the first electrode 51 may include a first sub-electrode 511 and a second sub-electrode 512. The first sub-electrode 511 is disposed on the side of the fourth insulating layer PVX1 facing away from the first substrate 10 and is electrically connected to the first semiconductor pattern 11 through a via. A color filter layer 40 may be disposed between the first sub-electrode 511 and the first planar layer PLN. The color filter layer 40 includes a plurality of filter portions 41. The first planar layer PLN1 covers the color filter layer 40 to improve the flatness of the plane where the second sub-electrode 512 is located. The second sub-electrode 512 is electrically connected to the first sub-electrode 511 through a via extending through the first planar layer PLN1. A sixth insulating layer PVX2 is also included between the second sub-electrode 512 and the second electrode 52. The first substrate 100 may also include a spacer PS disposed on the side of the sixth insulating layer PVX2 facing away from the first substrate 10. The spacer PS may be used to support the first substrate 100 and the second substrate 200, thereby maintaining the thickness of the liquid crystal between the first substrate 100 and the second substrate 200.

[0118] As shown in Figures 12 and 13, in this embodiment, at least one group of shielding structures 20 may include a first group of shielding structures 21, that is, the first substrate 100 includes a first group of shielding structures 21. The first group of shielding structures 21 includes the stacked film layer 30 described in any of the above embodiments. The first group of shielding structures 21 can be arranged between the second electrode 52 and the sixth insulating layer PVX2. The orthographic projection of the first group of shielding structures 21 on the first substrate 10 at least partially overlaps with the orthographic projection of the first signal line DL on the first substrate 10 to reduce the reflection of light by the first signal line DL. In addition, the first group of shielding structures 21 can also separate adjacent pixel areas 101 to reduce the problem of cross-color between adjacent pixel areas 101.

[0119] Referring to Figures 10 to 13 , at least one group of shielding structures 20 may include a first group of shielding structures 21. Specifically, the first substrate 100 includes the first group of shielding structures 21. The first group of shielding structures 21 includes the stacked film layer 30 described in any of the aforementioned embodiments. The first group of shielding structures 21 is disposed on a side of the first transistor T1 and the first signal line DL away from the substrate 10. The orthographic projection of the first group of shielding structures 21 on the first substrate 10 at least partially overlaps with the orthographic projection of the first signal line DL on the first substrate 10, thereby reducing light reflection from the first signal line DL.

[0120] Referring to Figures 10 and 12 , in some embodiments, the first set of shielding structures 21 includes a plurality of first shielding portions 211 extending along the second direction Y. The first shielding portions 211 extend in the same direction as the first signal lines DL. Each first shielding portion 211 corresponds to one first signal line DL, and the orthographic projection of a first shielding portion 211 on the first substrate 10 covers the orthographic projection of the corresponding first signal line DL on the first substrate 10. In this way, the first shielding portions 211 can effectively prevent light reflection from the first signal lines in the first substrate 100.

[0121] Along the first direction X, a first gap exists between two adjacent filter portions 41. The orthographic projection of the first blocking portion 211 on the first substrate 10 can cover the orthographic projection of the first gap on the first substrate 10. Alternatively, the orthographic projection of the first blocking portion 211 on the first substrate 10 can completely overlap with the orthographic projection of the first gap on the first substrate 10. Alternatively, the orthographic projection of the first gap on the first substrate 10 covers the orthographic projection of the first blocking portion 211 on the first substrate 10, and a certain gap can exist between the orthographic projections of the first blocking portion 211 and the first substrate 10. In this way, the first blocking portion 211 can effectively avoid the risk of cross-color between adjacent pixel regions 101, thereby ensuring the display quality of the display panel.

[0122] In some embodiments, referring to Figures 10 to 13, the first substrate 100 may further include a light-shielding layer LS. The light-shielding layer LS is disposed on a side of the first transistor T1 that is close to the first substrate 10, and the orthographic projection of the light-shielding layer LS on the first substrate 10 partially overlaps with the orthographic projection of the first transistor T1 on the first substrate 10. Exemplarily, the orthographic projection of the light-shielding layer LS on the first substrate 10 covers the orthographic projection of the channel structure of the first semiconductor pattern 11 of the first transistor T1 on the first substrate 10. The light-shielding layer LS is used to reduce the amount of light directed toward the channel structure of the first semiconductor pattern 11, thereby improving the light stability of the first transistor T1. In addition, the orthographic projection of the light-shielding layer LS on the first substrate 10 may also cover the orthographic projection of the gate line GL on the first substrate 10.

[0123] As shown in Figures 10 to 13 , the first substrate 100 includes the first set of shielding structures 21, and the first shielding portions 211 extend along the second direction Y. As shown in Figure 14 , the second substrate 200 may further include a second substrate 210 and a fifth set of shielding structures 25 disposed on the second substrate 210. The fifth set of shielding structures 25 includes fifth shielding portions 251 extending along the first direction X. The fifth shielding portions 251 include the stacked film layer 30 described in any of the above embodiments. A second gap exists between two adjacent rows of filter portions 41 on the first substrate 100, and the orthographic projection of the fifth shielding portion 251 on the second substrate 210 overlaps the orthographic projection of the second gap between two adjacent filter portions 41 on the second substrate 210. The orthographic projections of the second shielding portions 221 and the first shielding portions 211 on the same substrate (either the first substrate 10 or the second substrate 210) enclose multiple opening areas H in the first substrate 100. Each opening area H corresponds to a corresponding filter portion 41.

[0124] The embodiment of the second substrate 200 shown in FIG14 can be combined with the first substrate 100 in any of the embodiments of FIG10 to FIG13 . That is, the display panel includes not only the first group of shielding structures 21 disposed on the first substrate 100, but also the fifth group of shielding structures 25 disposed on the second substrate 200. Specifically, the first group of shielding structures 21 is located on the side of the color filter layer 40 away from the first substrate 10, and the first group of shielding structures 21 has a first shielding portion 211 extending along the second direction Y. The first shielding portion 211 includes the stacked film layer 30 shown in any of the above embodiments. The second substrate 200 also includes a second substrate 210. The fifth group of shielding structures 25 is disposed on the second substrate 210. The fifth group of shielding structures 25 has a fifth shielding portion 251 extending along the first direction X. The fifth shielding portion 251 includes the stacked film layer 30 shown in any of the above embodiments. The orthographic projection of the fifth shielding portion 251 on the second substrate 210 covers the orthographic projection of the second gap between two adjacent filter portions 41 on the second substrate 210, and may also partially overlap with the orthographic projection of the gate line GL on the second substrate 210 to block light reflected by the gate line GL. In this embodiment, the first gap extends along the second direction Y, and the second gap extends along the first direction X. FIG14 is a schematic top view of one embodiment of the fifth group of shielding structures 25 in the second substrate 200, and FIG15 is a schematic top view of one embodiment of the shielding structure (including the first group of shielding structures and the fifth group of shielding structures) after the first substrate 100 shown in FIG10 or FIG12 is aligned with the second substrate 200 shown in FIG14. In this way, when the first group of shielding structures 21 and the fifth group of shielding structures 25 are subsequently used as shielding structures, cross-color problems between adjacent sub-pixels can be avoided, and the light reflectivity of the display panel can also be reduced. Furthermore, in this embodiment, the orthographic projections of the fifth shielding portion 251 and the first shielding portion 211 on the same substrate (the first substrate or the second substrate) enclose a plurality of opening regions H of the first substrate 100, and each opening region H is provided corresponding to a corresponding filter portion 41. In other words, in actual applications, the pixel region 101 of the display panel can be formed by designing the fifth shielding portion 251 and the first shielding portion 211 accordingly.

[0125] In some embodiments, when the first substrate 100 includes the first group of shielding structures 21, the first group of shielding structures 21 may also be a grid structure as shown in FIG16 . In this case, the fifth group of shielding structures may not be provided on the second substrate 200. This simplifies the manufacturing process of the second substrate, thereby reducing the overall manufacturing difficulty and cost of the display panel. For example, the first group of shielding structures 21 includes a plurality of sixth shielding portions 212 extending along the first direction X and spaced apart along the second direction Y, and a plurality of first shielding portions 211 extending along the second direction Y and spaced apart along the first direction X. The plurality of sixth shielding portions 212 and the plurality of first shielding portions 211 intersect with each other to form a grid structure.

[0126] Referring to FIG. 17 , in some embodiments, at least one set of shielding structures 20 further includes a second set of shielding structures 22 . That is, when the first substrate 100 is an array substrate, the first substrate 100 includes both a first set of shielding structures 21 and a second set of shielding structures 22 . The first set of shielding structures 21 includes a plurality of first shielding portions extending along the second direction Y and spaced apart along the first direction X. The second set of shielding structures 22 is disposed between the first transistor T1 and the first substrate 10 . The orthographic projection of the second set of shielding structures 22 on the first substrate 10 at least partially overlaps with the orthographic projection of the first transistor T1 on the first substrate 10 . The second set of shielding structures 22 not only reduces the amount of light directed toward the channel structure of the first semiconductor pattern 11, improving the light stability of the first transistor T1, but also, together with the first set of shielding structures 21, reduces the risk of cross-coloring between adjacent sub-pixels. Compared to the array substrate shown in FIG. 13 , the array substrate shown in FIG. 17 replaces the second set of shielding structures 22 with a light-shielding layer LS.

[0127] In one embodiment, the first set of shielding structures 21 includes a plurality of first shielding portions extending along the second direction Y and spaced apart along the first direction X. The second set of shielding structures 22 may include a plurality of second shielding portions extending along the first direction X, with the plurality of second shielding portions extending along the second direction Y. The orthographic projections of the plurality of first shielding portions 211 and the plurality of second shielding portions 221 on the first substrate 10 enclose a plurality of opening regions of the first substrate 100, each opening region being disposed corresponding to a corresponding light filter portion 41. In this embodiment, the second substrate 200 may include a fifth set of shielding structures 25, as shown in FIG. 14 . The fifth set of shielding structures 25 may be used to shield light, such as light reflected by the gate lines GL. The structure of the second substrate 200 can be found above and will not be further described here.

[0128] It should be noted that, when the first substrate 100 is an array substrate and the second substrate 200 is an opposing substrate, the arrangement and combination of the shielding structure 20 are not limited to the above-mentioned multiple embodiments. In actual applications, shielding structures of appropriate shapes can be set at different positions as needed, and the embodiments of the present disclosure will no longer list them one by one.

[0129] In some embodiments, referring to FIG18 , the first substrate 100 has a display area AA and a peripheral area BB. For example, the peripheral area BB can be arranged around the display area AA. The first substrate 100 is used to form an array substrate, and the first substrate 100 includes a plurality of first transistors T1 and a plurality of second transistors T2. The first transistor T1 is arranged in the display area AA, and the second transistor T2 is arranged in the peripheral area BB. FIG18 illustrates a case where there is one first transistor T1 and one second transistor T2. Of course, the specific number of the plurality of first transistors T1 and the plurality of second transistors T2 can be set according to actual application needs and is not limited here.

[0130] As shown in FIG18 , the first substrate 100 further includes a second semiconductor layer ACT2 and a first gate insulating layer GI1 located between the first substrate 10 and the light shielding layer LS. The source 15 and drain 16 of the second transistor T2 and the first gate G1 of the first transistor T1 are made of the same material and are disposed on the same layer. For example, the source 15 and drain 16 of the second transistor T2 and the first gate G1 are all located in the first gate conductive layer Gate1.

[0131] For example, the second transistor T2 may include a second semiconductor pattern 13 located in the second semiconductor layer ACT2, a gate 14 located in the light shielding layer LS, and a source 15 and a drain 16 located in the first gate conductive layer Gate1. In this way, connecting vias can be formed first between the source 15 and the drain 16 of the second transistor T2 and the second semiconductor pattern 13. During the formation of the connecting vias, vias that expose the first semiconductor pattern 11 are not formed, thereby avoiding damage to the first semiconductor pattern 11.

[0132] In some embodiments, the material of the first semiconductor layer ACT1 of the first transistor T1 includes a metal oxide semiconductor material, and the material of the second semiconductor layer ACT2 of the second transistor T2 includes a low-temperature polysilicon (LTPS) material. That is, the first semiconductor pattern 11 of each first transistor T1 is a metal oxide semiconductor material, and the second semiconductor pattern 13 of each second transistor T2 is a low-temperature polysilicon material. In this way, each first transistor T1 is essentially an oxide transistor with a small leakage current, and each second transistor T2 is essentially a low-temperature polysilicon transistor with a high mobility. Moreover, it can be made thinner and smaller, with lower power consumption. The embodiments of the present disclosure can combine the two transistor manufacturing processes of LTPS transistors and oxide transistors to prepare a low-temperature polysilicon + oxide (LTPO) circuit structure of low-temperature polysilicon oxide. By integrating the first semiconductor pattern 11 using oxide semiconductor (Oxide) and the second semiconductor pattern 13 using low-temperature polysilicon on a first substrate 100, the advantages of both can be utilized to achieve low-frequency driving, reduce power consumption, and improve display quality.

[0133] Referring to Figure 19, in some embodiments of the present disclosure, the first substrate 100 may include a second semiconductor layer ACT2, a first gate insulating layer GI1, a light-shielding layer LS, a seventh insulating layer ILD3, a first semiconductor layer ACT1, a first insulating layer GI2, a first gate conductive layer Gate1, a second insulating layer ILD1, a third insulating layer ILD2, a first source and drain conductive layer SD1, a first via V1 and a second via V2, which are arranged in sequence along a direction away from the first substrate 10 (from bottom to top in Figure 19). Among them, the first via hole V1 passes through the first insulating layer GI2 and the second insulating layer ILD1, and exposes the first area 111 of the first semiconductor pattern 11. The second via hole V2 passes through the third insulating layer ILD2 and is connected to the first via hole V1, and the orthographic projection of the second via hole V2 on the first substrate 10 partially coincides with the orthographic projection of the first via hole V1 on the first substrate 10. This arrangement can reduce the area of ​​the connecting via between the first source-drain conductive layer SD1 and the first semiconductor pattern 11, which not only reduces the risk of short circuit between the first signal line DL and the first gate G1, but also helps to reduce the line width of the first signal line DL and improve the pixel density and transmittance of the display panel.

[0134] In one embodiment, as shown in FIG19 , a first via V1 and a second via V2 are provided corresponding to each first transistor T1. In this case, the first via V1 exposes the first region 111 of the first semiconductor pattern 11. A first signal line DL is located in the first source-drain conductive layer SD1 and is electrically connected to the first semiconductor pattern 11 through the second via V2 and the first via V1. The first substrate 100 further includes a fourth insulating layer PVX1, a third via V3, and a first electrode 51. The fourth insulating layer PVX1 is provided between the first source-drain conductive layer SD1 and the first electrode 51 (first sub-electrode 511). The third via V3 penetrates the fourth insulating layer PVX1, the third insulating layer ILD2, the second insulating layer ILD1, and the first insulating layer GI2, exposing the second region 112 of the first semiconductor pattern 11. The first electrode 51 is electrically connected to the second region 112 through the third via V3. Exemplarily, the first region 111 and the second region 112 are respectively located on both sides of the channel structure of the first semiconductor pattern 11 , and one of the first region 111 and the second region 112 is a source contact region, and the other is a drain contact region.

[0135] In one embodiment, referring to FIG. 20 , two first vias V1 and two second vias V2 are provided corresponding to one first transistor T1. The two first vias V1 expose the first region 111 and the second region 112 of the first semiconductor pattern 11, respectively. Exemplarily, the first region 111 and the second region 112 are located on either side of the channel structure of the first semiconductor pattern 11, with one of the first region 111 and the other being a drain contact region. A first signal line DL is located in the first source-drain conductive layer SD1 and is electrically connected to the first region 111 via one second via V2 and one first via V1. The first substrate 100 also includes a fourth insulating layer PVX1, a fourth via V4 and a first electrode 51. The fourth insulating layer PVX1 is arranged between the first source-drain conductive layer SD1 and the first electrode 51 (first sub-electrode 511). The fourth via V4 penetrates the fourth insulating layer PVX1 and is connected to another second via V2 and the first via V1. The first electrode 51 is arranged on the side of the fourth insulating layer PVX1 away from the first substrate 10, and part of the first electrode 51 passes through the fourth via V4, the second via V2 and the first via V1 and is electrically connected to the second region 112.

[0136] It should be noted that in the embodiments shown in Figures 18, 19 and 20, the array substrate also includes other structures including but not limited to a light-shielding layer LS, a color filter layer 40, a second electrode 52 and a first group of shielding structures 21. The setting method of these structures can refer to the introduction in the above embodiments, and the embodiments of the present disclosure will not be repeated here.

[0137] Referring to Figure 21, in some embodiments, the aperture of the second via V2 is smaller than that of the first via V1, and the orthographic projection of the second via V2 on the first substrate 10 is within the range of the orthographic projection of the first via V1 on the first substrate 10. In other words, the second via V2 and the first via V1 form a nested-hole structure. In this case, the opening area of ​​the second via V2 corresponds to the direct contact area between the first signal line DL and the first semiconductor pattern 11. This not only reduces the area of ​​the connecting via between the first source-drain conductive layer SD1 and the first semiconductor pattern 11, but also helps reduce the line width of the first signal line DL, thereby improving the pixel density and light transmittance of the display panel. It also helps reduce the impact of light leakage from the first and second vias V1 and V2 on the display quality of the display panel.

[0138] For example, as shown in FIG21 , the aperture of the first via hole V1 may be 2 μm to 8 μm, for example, the aperture of the first via hole V1 may be 2 μm, 3 μm, 5 μm, 6 μm, or 8 μm, etc. The aperture of the second via hole V2 may be 0.1 μm to 0.7 μm, for example, the aperture of the first via hole V1 may be 0.1 μm, 0.3 μm, 0.5 μm, 0.6 μm, or 0.7 μm, etc. The embodiments of the present disclosure will not be listed one by one.

[0139] Referring to Figures 22 and 23, in some embodiments, the orthographic projection of the second via V2 on the first substrate 10 partially overlaps with the orthographic projection of the first via V1 on the first substrate 10. In this case, the overlapping portion of the second via V2 and the first via V1 represents the direct contact area between the first signal line DL and the first semiconductor pattern 11. This not only reduces the area of ​​the connecting via between the first source-drain conductive layer SD1 and the first semiconductor pattern 11, thereby reducing the line width of the first signal line DL and improving the pixel density and light transmittance of the display panel, but also reduces the alignment accuracy requirements between the first via V1 and the second via V2, thereby simplifying the manufacturing process of the array substrate.

[0140] For example, as shown in FIG22 , the aperture of the second via hole V2 is smaller than the aperture of the first via hole V1. In this case, the aperture of the first via hole V1 can be 2 μm to 8 μm. For example, the aperture of the first via hole V1 can be 2 μm, 3 μm, 5 μm, 6 μm, or 8 μm. The aperture of the second via hole V2 can be 0.1 μm to 0.7 μm. For example, the aperture of the first via hole V1 can be 0.1 μm, 0.3 μm, 0.5 μm, 0.6 μm, or 0.7 μm. The embodiments of the present disclosure will not list them one by one. Alternatively, as shown in FIG23 , the aperture of the second via hole V2 is greater than or equal to the aperture of the first via hole V1. In this case, the aperture of the first via hole V1 can be 2 μm to 8 μm. For example, the aperture of the first via hole V1 can be 2 μm, 3 μm, 5 μm, 6 μm, or 8 μm. The diameter of the second via hole V2 may be 2 μm to 10 μm. For example, the diameter of the first via hole V1 may be 2 μm, 4 μm, 5 μm, 8 μm or 10 μm, etc. The embodiments of the present disclosure will not list them one by one.

[0141] In some embodiments, when the display panel 1100 is a liquid crystal display panel, the display panel 1100 may also include a first substrate 100, a third substrate, and a liquid crystal layer, wherein the first substrate and the third substrate are disposed opposite each other, and the liquid crystal layer is disposed between the first substrate 100 and the third substrate. The first substrate 100 may be configured to form a color filter substrate, and the third substrate may be configured to form an array substrate.

[0142] Referring to FIG. 24 , when the first substrate 100 is configured to form a color filter substrate, at least one group of blocking structures 20 includes a third group of blocking structures 23. Specifically, the first substrate 100 includes the third group of blocking structures 23. The orthographic projections of the third group of blocking structures 23 on the first substrate 10 enclose a plurality of opening regions 102. The first substrate 100 also includes a color filter layer 40, which is disposed on a side of the third group of blocking structures 23 facing away from the first substrate 10. The color filter layer 40 includes a plurality of filter portions 41, at least portions of which are disposed within the opening regions 102. The first substrate 100 is configured to form a color filter substrate. The third group of shielding structures 23 includes the stacked film layer 30 described in any of the above embodiments. The stacked film layer 30 includes a first metal layer 31, a first dielectric layer 32, a second metal layer 33, and a second dielectric layer 34. During the actual preparation of the stacked film layer 30 with the desired pattern through processes such as exposure and etching, the graphic CD of the stacked film layer 30 can be set to less than 2μm, and the total thickness of the stacked film layer 30 can be set to less than 0.25μm, and the module reflectivity can be reduced to less than 6%. In other words, the use of the stacked film layer 30 in the embodiment of the present disclosure can not only effectively reduce the size of the corresponding graphic CD, but also effectively reduce the total thickness of the stacked film layer 30. Based on this, not only can the stacked film layer 30 improve the aperture ratio and transmittance of the display panel and reduce the risk of cross-color between adjacent pixels, but also the display contrast can be improved by reducing the light reflectivity of the display panel, thereby providing a possibility for high PPI design of display products, that is, it is conducive to high PPI design of display panels.

[0143] When the third substrate can be configured to form an array substrate, the third substrate can include pixel circuits for generating an electric field and driving the liquid crystal molecules in the liquid crystal layer to deflect. The structure of the third substrate can be the same as or different from that of the first substrate when used as an array substrate in any of the above embodiments. In this embodiment, the structure of the third substrate is not specifically limited.

[0144] Referring to FIG. 25 , in some embodiments, when the display device 1000 is a transparent display device, the display panel may include a first substrate 100 and a light-emitting element (not shown in the figure). In this case, the first substrate 100 may be a display substrate. The first substrate 100 includes a first substrate 10 and a driving circuit layer 60. The first substrate 10 includes a light-emitting area 103 and a transparent area 104. The driving circuit layer 60 is provided in the light-emitting area 103 of the first substrate 10, and the driving circuit layer 60 includes a plurality of binding pins 61. The light-emitting element is connected to the plurality of binding pins 61. By way of example, the light-emitting element may include, but is not limited to, a mini-LED light-emitting device or a micro-LED light-emitting device.

[0145] Continuing with FIG. 25 , in one embodiment, the driving circuit layer 60 includes a plurality of second signal lines 62 and a plurality of third transistors T3. At least one set of shielding structures 20 includes a fourth set of shielding structures 24. The fourth set of shielding structures 24 is disposed on a side of the driving circuit layer 60 away from the first substrate 10. The orthographic projections of the fourth set of shielding structures 24 on the first substrate 10 cover the orthographic projections of the plurality of second signal lines 62 on the first substrate 10. The fourth set of shielding structures 24 may include the stacked film layer 30 described in any of the above embodiments. The second signal lines 62 may include, but are not limited to, data signal lines, scan signal lines, and power supply voltage signal lines.

[0146] As transparent display applications expand, the requirements for light transmittance and pixel density of transparent display devices are becoming increasingly higher. In addition to reducing the area of ​​the third transistor T3 and the size of the second signal line within the first substrate 100, the improvement in light transmittance and pixel density also requires a more refined shielding structure. Because there is a large step difference between the transparent area and the luminous area of ​​the first substrate, when an organic black matrix is ​​used to form a shielding structure, the black matrix is ​​prone to residue in the area near the junction of the transparent area and the luminous area, resulting in a decrease in the aperture ratio and light transmittance of the first substrate.

[0147] In an embodiment of the present disclosure, when the display device 1000 is a transparent display device, the first substrate 100 may include at least one set of shielding structures 20. The shielding structure 20 includes the stacked film layer 30 described in any of the above embodiments. The stacked film layer 30 includes a first metal layer 31, a first dielectric layer 32, a second metal layer 33, and a second dielectric layer 34. During the actual preparation of the stacked film layer 30 with the desired pattern through processes such as exposure and etching, the pattern CD of the stacked film layer 30 can be set to less than 2μm, the total thickness of the stacked film layer 30 can be set to less than 0.25μm, and the module reflectivity can be reduced to less than 6%. In addition, the risk of the shielding structure 20 remaining in the interface area between the transparent area and the light-emitting area can be reduced. In other words, the use of the stacked film layer 30 in the embodiment of the present disclosure can not only effectively reduce the size of the corresponding pattern CD, but also effectively reduce the total thickness of the stacked film layer 30. Based on this, not only can the aperture ratio and transmittance of the display panel be improved by stacking the film layer 30 and the risk of cross-color between adjacent pixels be reduced, but the display contrast can also be improved by reducing the light reflectivity of the display panel, thereby providing the possibility for high PPI design of display products, which is conducive to high PPI design of display panels.

[0148] In some embodiments, referring to FIG26 , the fourth group of shielding structures 24 includes a fourth shielding portion 241, the orthographic projection of the fourth shielding portion 241 on the first substrate 10 covers the orthographic projection of the plurality of second signal lines 62 on the first substrate 10, and there is a first interval D1 between the boundary of the fourth shielding portion 241 and the boundary of the first signal line, and the first interval D1 is greater than or equal to 1 μm and less than or equal to 15 μm, that is, 1 μm ≤ D1 ≤ 15 μm. In this way, the fourth group of shielding structures 24 can greatly block the light reflected by the second signal line, reduce the reflection of the light by the first substrate, and enhance the display effect of the first substrate. Exemplarily, the first interval D1 can be 1 μm, 3 μm, 5 μm, 10 μm or 15 μm, and the embodiments of the present disclosure will not list them one by one.

[0149] The embodiments of the present disclosure do not specifically limit the shape and size of the orthographic projection of the fourth group of shielding structures 24 on the first substrate 10. During the actual manufacturing process, the coverage area of ​​the fourth group of shielding structures 24 can be flexibly set as needed. In addition, the fourth group of shielding structures 24 can include, but are not limited to, the stacked film layers 30 described in any of the above embodiments, and the film layer structure thereof will not be further described here.

[0150] In other embodiments, referring to FIG. 27 , the driving circuit layer 60 includes a plurality of stacked film layers 30 , and at least one metal conductive layer 70 includes the stacked film layer 30 , that is, at least one metal conductive layer 70 is formed by the stacked film layer 30 . In this way, the reflection of light by the metal conductive layer 70 can be directly reduced.

[0151] For example, referring to FIG. 27 , the first substrate 100 may include, arranged in sequence along a direction away from the first substrate 10, a third semiconductor layer ACT3, a second gate insulating layer GI4, a second gate conductive layer Gate2, a second gate insulating layer GI5, a third gate conductive layer Gate3, an interlayer dielectric layer ILD4, a second source-drain conductive layer SD2, a third planarization layer PLN3, a first passivation layer PVX3, a third source-drain conductive layer SD3, a fourth planarization layer PLN4, a second passivation layer PVX4, a bonding pin 61, and a third passivation layer PVX5. The third transistor T3 may include a third semiconductor pattern located in the third semiconductor layer ACT3, a third gate located in the second gate conductive layer Gate2, and a third source and a third drain located in the second source-drain conductive layer SD2. The plurality of second signal lines 62 may be located on one or more of the second gate conductive layer Gate2, the third gate conductive layer Gate3, and the second source-drain conductive layer SD2.

[0152] For example, as shown in FIG27 , the second gate conductive layer Gate2 and the third gate conductive layer Gate3 may include a stacked film layer 30, that is, the second gate conductive layer Gate2 and the third gate conductive layer Gate3 are formed by the stacked film layer 30. Of course, in some other embodiments, one or more of the second gate conductive layer Gate2, the third gate conductive layer Gate3, and the second source-drain conductive layer SD2 may include the stacked film layer 30. For example, only the second gate conductive layer Gate2 may include the stacked film layer 30, or only the third gate conductive layer Gate3 may include the stacked film layer 30, or only the second source-drain conductive layer SD2 may include the stacked film layer 30, or both the second gate conductive layer Gate2 and the second source-drain conductive layer SD2 may include the stacked film layer. The embodiments of the present disclosure are not limited thereto, and any other suitable manner may be considered to form the corresponding conductive layer in the form of the stacked film layer 30.

[0153] Some embodiments of the present disclosure further provide a method for manufacturing a display panel, which is used to manufacture the display panel described in any of the above embodiments. The method may include steps S11 to S16.

[0154] S11 , referring to FIG. 28A , an initial first metal layer 410 is formed on a substrate motherboard 400 .

[0155] Among them, the substrate motherboard 400 includes a plurality of panel areas 401 distributed at intervals, and one panel area 401 is configured to prepare a display panel. The initial first metal layer 410 covers the substrate motherboard 400. For example, the above-mentioned initial first metal layer 410 can be formed by a method including but not limited to magnetron sputtering. The material of the initial first metal layer 410 may include at least one of molybdenum (Mo), tungsten (W) and molybdenum-tungsten alloy (MoW). The thickness of the initial first metal layer 410 is not less than 40nm. For example, the thickness of the initial first metal layer 410 can be 50nm to 300nm. For example, the thickness of the initial first metal layer 410 can be 50nm, 100nm, 150nm, 200nm or 300nm, etc., and the embodiments of the present disclosure will not list them one by one.

[0156] S12 , referring to FIG. 28B , a portion of the initial first metal layer 410 outside the panel region 401 is removed to form an intermediate first metal layer 411 .

[0157] Exemplarily, the initial first metal layer 410 is patterned using a dry etching process or a wet etching process. In this step, only the portion of the initial first metal layer 410 located outside the panel region 401 is removed, while the portion of the initial first metal layer 410 located within the panel region 401 is not patterned. In this way, the formed first metal layer 411 can cover multiple panel regions 401 of the substrate motherboard 400.

[0158] S13 , referring to FIG. 28C , a first dielectric layer (not shown) and an initial second metal layer 420 are sequentially formed on a side of the intermediate first metal layer 411 away from the substrate motherboard 400 .

[0159] The first dielectric layer and the initial second metal layer 420 cover the substrate motherboard 400 , that is, the first dielectric layer and the initial second metal layer 420 are both integral layers.

[0160] Exemplarily, the material of the first dielectric layer may include at least one of silicon nitride (SiNx), silicon dioxide (SiO2), aluminum oxide (Al2O3), and titanium oxide (TiO2). The thickness of the first dielectric layer may range from 10 nm to 100 nm. For example, the thickness of the first dielectric layer may be 10 nm, 40 nm, 70 nm, 85 nm, or 100 nm. Furthermore, the first dielectric layer may be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other methods.

[0161] For example, the material of the initial second metal layer 420 may include at least one of molybdenum (Mo), tungsten (W), and molybdenum-tungsten alloy (MoW). The initial second metal layer 420 may be formed by methods including, but not limited to, magnetron sputtering. For example, the thickness of the initial second metal layer 420 may be 1 nm to 100 nm. The thickness of the initial second metal layer 420 may be 1 nm, 10 nm, 50 nm, 80 nm, or 100 nm, etc., which are not listed one by one in the embodiments of the present disclosure.

[0162] S14 , referring to FIG. 28D , the initial second metal layer 420 and the portion of the first dielectric layer 32 outside the panel region 401 are removed, and the initial second metal layer 420 forms an intermediate second metal layer 421 .

[0163] Exemplarily, the initial second metal layer 420 and the first dielectric layer 32 are patterned using a dry etching process or a wet etching process. In this step, only the portions of the initial second metal layer 420 and the first dielectric layer 32 located outside the panel region 401 are removed, while the portions of the initial first metal layer 410 and the first dielectric layer 32 located within the panel region 401 are not patterned. In this way, the formed second metal layer 421 can cover multiple panel regions 401 of the substrate motherboard 400.

[0164] S15 , forming a second dielectric layer on a side of the middle second metal layer 421 away from the substrate motherboard 400 .

[0165] The orthographic projection of the second dielectric layer on the substrate motherboard 400 may cover the substrate motherboard 400 , that is, the second dielectric layer formed in this step may be a whole layer structure.

[0166] Exemplarily, the material of the second dielectric layer may include at least one of silicon nitride (SiNx), silicon dioxide (SiO2), aluminum oxide (Al2O3), and titanium oxide (TiO2). The thickness of the second dielectric layer may range from 10 nm to 300 nm. For example, the thickness of the second dielectric layer may be 10 nm, 50 nm, 100 nm, 200 nm, or 300 nm. Furthermore, the second dielectric layer may be formed using CVD, PVD, ALD, or other methods.

[0167] S16 , referring to FIG. 28E and FIG. 28F , the second dielectric layer 34 , the middle second metal layer 421 , the first dielectric layer 32 and the middle first metal layer 411 are patterned to form the shielding structure 20 .

[0168] Among them, the shielding structure 20 includes a stacked film layer 30, and the stacked film layer 30 includes a first metal layer 31 (formed by patterning the intermediate first metal layer 411), a first dielectric layer 32, a second metal layer 33 (formed by patterning the intermediate second metal layer 421), and a second dielectric layer 34. In addition, the refractive index of the first dielectric layer 32 and the second dielectric layer 34 is a first refractive index K1, and the refractive index of the first metal layer 31 and the second metal layer 33 is a second refractive index K2 greater than the first refractive index K1, that is, K2>K1. In this way, the stacked film layer 30 can form a shielding structure to replace the black matrix in traditional technology. The stacked film layer 30 can not only block the reflection of the relevant metal wiring in the display panel, but also when the stacked film layer 30 is used for the shielding structure, it can effectively prevent the problem of cross-color, thereby ensuring the display effect of the display panel. In the actual preparation process of the stacked film layer 30 through processes such as exposure and etching, the pattern CD of the stacked film layer 30 can be set to less than 2μm, the total thickness of the stacked film layer 30 can be set to less than 1μm, and the reflectivity of the stacked film layer 30 can be reduced to less than 6%. In other words, the use of the stacked film layer 30 in the embodiment of the present disclosure can not only effectively reduce the size of the corresponding pattern CD, but also effectively reduce the total thickness of the stacked film layer 30. Based on this, not only can the aperture ratio and transmittance of the display panel be improved by the stacked film layer 30, and the risk of cross-color between adjacent pixels can be reduced, but the display contrast can also be improved by reducing the light reflectivity of the display panel, thereby providing a possibility for high PPI design of display products, that is, it is conducive to high PPI design of display panels.

[0169] In the related art, the preparation method of the stacked film layer is usually to prepare it layer by layer and pattern it layer by layer. For example, first prepare the first metal layer, and then pattern the first metal layer to form the pattern required for the shielding structure; then form a dielectric layer and a second metal layer, and pattern the second metal layer to form the pattern required for the shielding structure; in the process of forming the first metal layer and the second metal layer respectively through two patterning processes, the pattern of the first metal layer and the pattern of the second metal layer may be misaligned with each other due to the influence of the alignment accuracy. In addition, in the process of patterning each metal layer using an etching process, in order to etch the required pattern of each metal layer, it is usually necessary to perform a certain amount of over-etching on each metal layer. At the location where the metal layer is thinner (such as where the metal layer is located at the via or the protrusion climbing), the over-etching amount of multiple metal layers is superimposed, which may cause the film layer on the lower side of the shielding structure to be etched through, thereby causing the conductive layer formed above the shielding structure to short-circuit with the conductive layer on the lower side of the shielding structure.

[0170] Through the above-mentioned preparation method (S11 to S16) provided by the embodiment of the present disclosure, within the panel area 401, the stacked film layer 30 includes multiple film layers, and the portion within the panel area is patterned using an etching process. On the one hand, the pattern misalignment problem caused by the alignment accuracy between different film layers can be eliminated, so that the contacting surfaces of two adjacent film layers in the stacked film layer 30 overlap. In this way, the alignment accuracy requirements for the patterning process of the two adjacent film layers in the stacked film layer 30 can be reduced, and the risk of forming steps between the two adjacent film layers or the edge of the upper film layer covering the lower film layer can be reduced, thereby reducing the CD deviation of the stacked film layer 30, which is beneficial to reducing the size of the shielding structure 20, thereby improving the aperture ratio and light output rate of the display panel. On the other hand, the overall over-etching amount of the stacked film layer 30 can be reduced to reduce the risk of etching through the lower film layer during the etching process of the stacked film layer, and reduce the risk of short-circuiting the upper and lower film layers of the stacked film layer (shielding structure 20).

[0171] In some embodiments, the method for preparing a display panel may include S21 to S24.

[0172] S21 , referring to FIG. 29A , a first semiconductor layer ACT1 , a first insulating layer GI2 , a first gate conductive layer Gate1 and a second insulating layer ILD2 are sequentially formed on a substrate motherboard 400 .

[0173] Among them, the material of the first semiconductor layer ACT1 may include a metal oxide semiconductor material. The material of the first insulating layer GI2 may include silicon nitride (SiNx) and / or silicon dioxide (SiO2). The material of the first gate conductive layer Gate1 may include a metal conductive material. The material of the second insulating layer ILD2 may include silicon nitride (SiNx) and / or silicon dioxide (SiO2). In addition, the above-mentioned first semiconductor layer ACT1, the first insulating layer GI2, the first gate conductive layer Gate1 and the second insulating layer ILD2 can be formed by any suitable process according to actual needs. The thickness of the second insulating layer ILD2 can range from 100nm to 800nm, so that the second insulating layer ILD2 can better cover the first gate conductive layer Gate1. For example, the thickness of the second insulating layer ILD2 can be 100nm, 200nm, 500nm, 700nm or 800nm, etc., and the embodiments of the present disclosure will not list them one by one.

[0174] S22 , referring to FIG. 29B , forming a first via hole V1 penetrating the second insulating layer ILD2 and the first insulating layer GI1 , wherein the first via hole V1 exposes the third region 133 of the first semiconductor layer ACT1 .

[0175] For example, the second insulating layer ILD2 and the first insulating layer GI1 may be etched by, for example, an exposure and etching process.

[0176] S23 , referring to FIG. 29C , a third insulating layer ILD2 is formed on a side of the second insulating layer ILD2 away from the substrate motherboard 400 .

[0177] The third insulating layer ILD2 covers the first via V1. For example, the third insulating layer ILD2 can be formed using one of CVD, PVD, and ALD methods. The material of the third insulating layer ILD2 can include one or both of silicon nitride (SiNx) and silicon dioxide (SiO2), and the thickness of the third insulating layer ILD2 can be 100 nm to 600 nm. For example, the thickness of the third insulating layer ILD2 can be 100 nm, 200 nm, 350 nm, 500 nm, or 600 nm, etc., which are not listed in detail in the embodiments of the present disclosure.

[0178] S24 , referring to FIG. 29D , a second via hole V2 is formed penetrating the third insulating layer ILD2 , wherein the second via hole V2 exposes a portion of the first via hole V1 , and a portion of the third region 133 is exposed through the second via hole V2 .

[0179] For example, the second via hole V2 may be formed by etching the third insulating layer ILD2 through an exposure and etching process, for example.

[0180] Through the above steps S21 to S24 , the area of ​​the connection via between the first source-drain conductive layer SD1 and the first semiconductor pattern 11 can be reduced, which is beneficial to reducing the line width of the first signal line DL and improving the pixel density and transmittance of the display panel.

[0181] It should be noted that the method for preparing the display panel includes but is not limited to the above steps. For example, after the above step S24, the method for preparing the display panel may further include step S25.

[0182] S25, referring to FIG. 29E, a first source-drain conductive layer SD1 is formed on a side of the third insulating layer ILD2 away from the substrate motherboard 400. Portions of the first source-drain conductive layer SD1 pass through the second via hole V2 and the first via hole V1 and are electrically connected to the first semiconductor layer ACT1.

[0183] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel, comprising: A first substrate, comprising a first substrate and at least one set of shielding structures disposed on one side of the first substrate, each set of the shielding structures comprising a stacked film layer, the stacked film layer comprising a first metal layer, a first dielectric layer, a second metal layer, and a second dielectric layer stacked thereon, the refractive indices of the first dielectric layer and the second dielectric layer being a first refractive index, the refractive indices of the first metal layer and the second metal layer being a second refractive index greater than the first refractive index, and the thickness difference between the first metal layer and the second metal layer being greater than a preset value.

2. The display panel according to claim 1, wherein, The preset value is 1 nm to 200 nm.

3. The display panel according to claim 1, wherein, The preset value is 20 nm to 100 nm.

4. The display panel according to any one of claims 1 to 3, wherein, The included angle between the sidewall of the stacked film layer and a reference plane is 15° to 60°; the reference plane is parallel to the first substrate.

5. The display panel according to claim 1, wherein, The thickness of the stacked film layer is less than 1 μm.

6. The display panel according to claim 1, wherein, The light reflectivity of the stacked film layer is less than 6%.

7. The display panel according to any one of claims 1 to 6, wherein The first substrate further comprises a first transistor and a first signal line, the first signal line being electrically connected to the first transistor; the orthographic projection of the shielding structure on the first substrate at least partially overlaps with the orthographic projection of at least one of the first transistor and the first signal line on the first substrate; The display panel further comprises a second substrate and a liquid crystal layer, the second substrate being disposed opposite to the first substrate, and the liquid crystal layer being disposed between the first substrate and the second substrate.

8. The display panel according to claim 7, wherein The first substrate further comprises a color filter layer, the color filter layer being disposed on a side of the first transistor and the first signal line away from the first substrate; The at least one set of shielding structures comprises a first set of shielding structures, the first set of shielding structures being disposed on a side of the color filter layer away from the first substrate, and the orthographic projection of the first set of shielding structures on the first substrate at least partially overlaps with the orthographic projection of the first signal line on the first substrate and does not overlap with the orthographic projection of the color filter layer on the first substrate.

9. The display panel according to claim 7 or 8, wherein, The at least one set of shielding structures further comprises: A second set of shielding structures, disposed between the first transistor and the first substrate, the orthographic projection of the second set of shielding structures on the first substrate at least partially overlaps with the orthographic projection of the first transistor on the first substrate.

10. The display panel according to any one of claims 7 to 9, wherein The first substrate has a display area and a peripheral area, the first transistor being disposed in the display area; The first substrate further comprises a second transistor disposed in the peripheral area, the source and drain of the second transistor and the first gate of the first transistor being made of the same material and disposed in the same layer.

11. The display panel according to claim 10, wherein, The material of the first semiconductor layer of the first transistor is a metal oxide semiconductor material, and the material of the second semiconductor layer of the second transistor is a low-temperature polycrystalline silicon material.

12. The display panel according to claim 10 or 11, wherein, The first substrate further comprises: A first semiconductor layer, a first insulating layer, a first gate conductive layer, a second insulating layer, a third insulating layer, and a first source-drain conductive layer sequentially arranged in a direction away from the first substrate; wherein, the first transistor includes a first semiconductor pattern located in the first semiconductor layer and a first gate located in the first gate conductive layer; A first via hole, penetrating through the first insulating layer and the second insulating layer, and exposing the first semiconductor pattern; A second via hole, penetrating through the third insulating layer and communicating with the first via hole, and a positive projection of the second via hole on the first substrate partially coincides with a positive projection of the first via hole on the first substrate; Wherein, a part of the first source-drain conductive layer is electrically connected to the first semiconductor pattern through the second via hole and the first via hole.

13. The display panel according to claim 12, wherein, One first via hole and one second via hole are correspondingly arranged for one first transistor, and the first via hole exposes a first region of the first semiconductor pattern; The first signal line is located in the first source-drain conductive layer, and the first signal line is electrically connected to the first region through the second via hole and the first via hole; The first substrate further includes a fourth insulating layer, a third via hole, and a first electrode, the fourth insulating layer is disposed between the first source-drain conductive layer and the first electrode, the third via hole penetrates through the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer, and exposes a second region of the first semiconductor pattern, and the first electrode is electrically connected to the second region through the third via hole.

14. The display panel according to claim 12, wherein, Two first via holes and two second via holes are correspondingly arranged for one first transistor, and the two first via holes respectively expose a first region and a second region of the first semiconductor pattern; The first signal line is located in the first source-drain conductive layer, and the first signal line is electrically connected to the first region through the second via hole and the first via hole; The first substrate further includes a fourth insulating layer, a fourth via hole, and a first electrode, the fourth insulating layer is disposed between the first source-drain conductive layer and the color filter layer, the fourth via hole penetrates through the fourth insulating layer and communicates with the other second via hole and the first via hole; the first electrode is disposed on a side of the fourth insulating layer away from the first substrate, and a part of the first electrode passes through the fourth via hole, the second via hole, and the first via hole and is electrically connected to the second region.

15. The display panel according to any one of claims 12 to 14, wherein, The aperture of the second via hole is smaller than the aperture of the first via hole, and a positive projection of the second via hole on the first substrate is located within a range of a positive projection of the first via hole on the first substrate.

16. The display panel according to any one of claims 12 to 14, wherein, A positive projection of the second via hole on the first substrate partially coincides with a positive projection of the first via hole on the first substrate.

17. The display panel according to any one of claims 1 to 6, wherein the at least one set of light-shielding structures includes a third set of light-shielding structures, and a plurality of opening regions are defined by the orthographic projection of the third set of light-shielding structures on the first substrate; the first substrate further includes a color filter layer disposed on a side of the third set of light-shielding structures away from the first substrate, the color filter layer includes a plurality of light-filtering portions, and at least a part of the light-filtering portions is disposed within the opening regions; the display panel further includes a third substrate and a liquid crystal layer, the third substrate is disposed opposite to the first substrate, the third substrate includes a pixel circuit, and the liquid crystal layer is disposed between the first substrate and the third substrate.

18. The display panel according to any one of claims 1 to 6, wherein the first substrate includes a light-emitting region and a transparent region; the first substrate further includes a driving circuit layer disposed in the light-emitting region of the first substrate, the driving circuit layer includes a plurality of bonding pins; the driving circuit layer includes the light-shielding structures, and / or, the orthographic projection of the light-shielding structures on the first substrate at least partially coincides with the driving circuit layer; the display panel further includes a light-emitting element connected to the plurality of bonding pins.

19. The display panel according to claim 18, wherein the driving circuit layer includes a plurality of second signal lines and a plurality of third transistors; the at least one set of light-shielding structures includes a fourth set of light-shielding structures disposed on a side of the driving circuit away from the first substrate, and the orthographic projection of the fourth set of light-shielding structures on the first substrate covers the orthographic projection of the plurality of second signal lines on the first substrate.

20. The display panel according to claim 19, wherein the fourth set of light-shielding structures includes a fourth light-shielding portion, the orthographic projection of the fourth light-shielding portion on the first substrate covers the orthographic projection of the plurality of second signal lines on the first substrate, and a first gap is provided between the boundary of the fourth light-shielding portion and the boundary of the second signal lines, and the first gap is greater than or equal to 1 μm and less than or equal to 15 μm.

21. The display panel according to claim 18, wherein the driving circuit layer includes a plurality of metal conductive layers, and at least one of the metal conductive layers includes the stacked film layer.

22. A method for manufacturing a display panel, comprising: forming an initial first metal layer on a substrate mother board; the substrate mother board includes a plurality of panel regions distributed at intervals, and one panel region is configured to form a display panel, and the initial first metal layer covers the substrate mother board; removing a part of the initial first metal layer located outside the panel regions to form an intermediate first metal layer; forming a first dielectric layer and an initial second metal layer in sequence on a side of the intermediate first metal layer away from the substrate mother board; the first dielectric layer and the initial second metal layer cover the substrate mother board; removing a part of the initial second metal layer and the first dielectric layer located outside the panel regions, and the initial second metal layer forms an intermediate second metal layer; A second dielectric layer is formed on a side of the intermediate second metal layer away from the substrate mother board; The second dielectric layer, the intermediate second metal layer, the first dielectric layer, and the intermediate first metal layer are patterned to form a shielding structure, and the shielding structure includes a first metal layer, a first dielectric layer, a second metal layer, and a second dielectric layer which are stacked; 23. The manufacturing method according to claim 22 further includes: A first semiconductor layer, a first insulating layer, a first gate conductive layer, and a second insulating layer are sequentially formed on the substrate mother board; A first via hole penetrating through the second insulating layer and the first insulating layer is formed, and the first via hole exposes a third region of the first semiconductor layer; A third insulating layer is formed on a side of the second insulating layer away from the substrate mother board, and the third insulating layer covers the first via hole; A second via hole penetrating through the third insulating layer is formed, and the second via hole exposes a partial region of the first via hole and exposes a partial region of the third region through the second via hole; 24. A display device includes the display panel according to any one of claims 1 to 21.

Images