Coding method and apparatus, and decoding method and apparatus

Abstract

A coding method and apparatus, and a decoding method and apparatus, which are applied to support IEEE 802.11ax next-generation Wi-Fi protocols (e.g., 802.11be, Wi-Fi 7 or EHT), or IEEE 802.11be next-generation Wi-Fi protocols (e.g., 802.11bn, Wi-Fi 8 or UHR) or Wi-Fi AI or millimeter wave (MMW) or ultra wide band (UWB) or sensing, etc. After acquiring an information bit sequence, a first communication apparatus performs LDPC coding on the information bit sequence on the basis of a check matrix, so as to obtain a coded sequence, and outputs the sequence, wherein the length of the sequence is N1, N1 is n times 1944, and n is an integer greater than or equal to 2; and Z of the check matrix may be equal to 81. After obtaining information to be decoded, a second communication apparatus performs LDPC decoding in view of the check matrix, so as to obtain the information bit sequence. The method can improve the decoding performance.

Description

Coding method, decoding method and device

[0001] This application claims priority to Chinese patent application No. 202311805346.4 filed with the State Intellectual Property Office of China on December 25, 2023, and priority to Chinese patent application No. 202311805346.4, entitled “Encoding Method, Decoding Method and Device”, the entire contents of which are incorporated herein by reference. This application claims priority to Chinese patent application No. 202410787720.0 filed with the State Intellectual Property Office of China on June 17, 2024, and priority to Chinese patent application No. 202410787720.0, entitled “Encoding Method, Decoding Method and Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present application relates to the field of communication technology, and in particular to an encoding method, a decoding method and a device. Background Art

[0003] The Institute of Electrical and Electronics Engineers (IEEE) 802.11n / ac / ax / be wireless local area network (WLAN) transmission standards primarily focus on improving the user experience in high-bandwidth scenarios (e.g., 60 GHz), including increasing average user throughput and energy efficiency for battery-powered devices. High-bandwidth scenarios require high-speed, reliable transmission of data, video, and other services within limited frequency and power resources, necessitating highly reliable and efficient channel coding schemes.

[0004] In the field of channel coding, concatenated codes (such as Turbo codes) and low-density parity-check (LDPC) codes are currently the two most mature and widely used channel coding methods. Both have performance close to the Shannon limit. Compared with concatenated codes, LDPC codes offer the following advantages: excellent bit error performance without the need for a deep interleaver; improved frame error rate performance; significantly reduced error floor; non-trellis-based decoding; support for parallel decoding and minimal decoding latency. Therefore, LDPC codes have become the standard channel coding scheme for low-frequency, short-range WLAN communication systems such as IEEE 802.11n / ac / ax.

[0005] How to further improve the decoding performance of LDPC codes needs to be solved urgently. Summary of the Invention

[0006] The embodiments of the present application provide an encoding method, a decoding method, and an apparatus that can support LDPC codes with longer code lengths and improve decoding performance.

[0007] In a first aspect, an embodiment of the present application provides an encoding method, which is applied to a first communication device, where the first communication device includes a Wi-Fi device, or a chip or functional module disposed in the Wi-Fi device, and the method includes:

[0008] Obtain an information bit sequence; perform low-density parity check (LDPC) encoding on the information bit sequence based on a check matrix to obtain an encoded sequence, where the length of the encoded sequence is N1, where N1 is n times 1944, where n is an integer greater than or equal to 2, and an expansion factor Z of the check matrix is ​​81; and output the encoded sequence.

[0009] In the embodiment of the present application, the parity check matrix can be applied to an information bit sequence with a code length of n times 1944, where n is an integer greater than or equal to 2, thereby improving the transmission reliability of the system and improving decoding performance. Generally speaking, the longer the applicable code length, the better the reliability of the parity check matrix and the better the decoding performance.

[0010] In a second aspect, an embodiment of the present application provides a decoding method, which is applied to a second communication device, where the second communication device includes a Wi-Fi device, or a chip or functional module disposed in the Wi-Fi device, and the method includes:

[0011] Obtain information to be decoded, where the length of the information to be decoded is N1, where N1 is n times 1944, and n is an integer greater than or equal to 2; perform low-density parity check (LDPC) decoding on the information to be decoded based on a check matrix to obtain an information bit sequence, where an expansion factor of the check matrix is ​​Z=81.

[0012] In combination with the first aspect or the second aspect, in one possible implementation, the check matrix is ​​obtained by performing diagonal expansion or anti-diagonal expansion on the elements of the x-th row and y-th column in the matrix prototype of the basic check matrix, the code length N0 corresponding to the basic check matrix is ​​less than or equal to 1944, the code rate corresponding to the basic check matrix is ​​the same as the code rate corresponding to the check matrix, the elements of the x-th row and j-th column are greater than or equal to 0, and x and y are both positive integers.

[0013] In combination with the first aspect or the second aspect, in a possible implementation method, the check matrix is ​​obtained by performing diagonal expansion or anti-diagonal expansion on the elements of the x-th row and y-th column in the matrix prototype of the basic check matrix, including: the matrix prototype of the check matrix is ​​determined based on the matrix prototype of the basic check matrix and an extended indicator matrix, the size of the extended indicator matrix is ​​the same as the size of the matrix prototype of the basic check matrix, and the elements of the x-th row and y-th column in the extended indicator matrix are used to indicate: the square matrix at the corresponding position in the matrix prototype of the check matrix is ​​obtained by performing diagonal expansion or anti-diagonal expansion on the elements of the x-th row and y-th column in the matrix prototype of the basic check matrix.

[0014] In combination with the first aspect or the second aspect, in a possible implementation method, the first column and the second column in the matrix corresponding to the check bit in the matrix prototype of the check matrix are: the first element and the last element in the first column in the matrix corresponding to the check bit in the matrix prototype of the basic check matrix are obtained after both are diagonally expanded or both are anti-diagonally expanded.

[0015] Generally speaking, the first column of the matrix corresponding to the check bit in the matrix prototype of the basic check matrix has a "1-0-1" structure, that is, the first row and the last row of the first column from top to bottom are both 1, and the remaining rows are all 0. Therefore, in an embodiment of the present application, the expansion method of the first element (such as 1) and the last element (such as 1) in the first column of the matrix corresponding to the check bit in the matrix prototype of the basic check matrix can be the same. The elements in the corresponding positions in the first column and the second column of the matrix corresponding to the check bit in the matrix prototype of the check matrix can be obtained through the same expansion method, so that the matrix corresponding to the check bit can still maintain a similar structure (such as the first element or the second element in the first column is 1, and the last element or the second to last element in the first column is 1), which can ensure a fast and efficient coding algorithm for LDPC codes.

[0016] In combination with the first aspect or the second aspect, in one possible implementation, the elements in the matrix prototype of the check matrix corresponding to the check bits, except for the first and second columns, are obtained by diagonally expanding all the elements 0 in the matrix prototype of the basic check matrix corresponding to the check bits, except for the first column.

[0017] In the embodiment of the present application, the expansion method of other elements except the first column in the matrix prototype of the basic check matrix corresponding to the check bits is diagonal expansion. The check matrix obtained by the above expansion method can not only ensure fast and efficient encoding, but also reduce the implementation complexity due to the same expansion method.

[0018] For example, the matrix prototype of the basic parity check matrix corresponds to a code length of 1944 bits. Using LDPC codes at different code rates with a code length of 1944 bits for the WLAN system as the basic matrix, parity check matrices with code lengths of 3888 bits for the corresponding code rates are obtained. This allows the encoding and decoding architecture of the existing WLAN LDPC code to be reused as much as possible, minimizing the changes to the LDPC encoding and decoding modules for the new LDPC long code, thereby reducing implementation complexity.

[0019] In combination with the first aspect or the second aspect, in one possible implementation, the matrix corresponding to the information bit in the matrix prototype of the check matrix is: obtained by performing diagonal expansion or anti-diagonal expansion on the elements in the x-th row and y-th column of the matrix corresponding to the information bit in the matrix prototype of the basic check matrix.

[0020] [Corrected 10.02.2025 according to Rule 26] In combination with the first aspect or the second aspect, in one possible implementation, when the code rate R of the information bit sequence is 1 / 2, the matrix prototype of the check matrix is ​​the following matrix 1:

[0021] Among them, -1 represents a Z*Z all-zero matrix, 0 represents a Z*Z unit matrix, and elements greater than 0 represent the cyclic shift matrix CPM of the Z*Z unit matrix.

[0022] The “1” in the matrix 1 or the “2” in the matrix 2 shown in the embodiment of the present application is for distinguishing different matrices and facilitating subsequent references.

[0023] [Corrected 10.02.2025 according to Rule 26] In conjunction with the first aspect or the second aspect, in one possible implementation, the extended indicator matrix corresponding to the matrix 1 is:

[0024] Here, -1 indicates that the element at the corresponding position in the matrix prototype of the check matrix is ​​obtained by expanding element j1 in the matrix prototype of the basic check matrix into a 2*2 all-zero matrix; 0 indicates that the element at the corresponding position in the matrix prototype of the check matrix is ​​obtained by diagonally expanding element j2 in the matrix prototype of the basic check matrix; and 1 indicates that the element at the corresponding position in the matrix prototype of the check matrix is ​​obtained by anti-diagonally expanding element j3 in the matrix prototype of the basic check matrix. The description of each element in the matrix prototype is also applicable to matrices 2 to 14 shown below and will not be repeated here.

[0025] [Corrected 10.02.2025 according to Rule 26] In combination with the first aspect or the second aspect, in one possible implementation, when the code rate R of the information bit sequence is 1 / 2, the matrix prototype of the check matrix is ​​the following matrix 2:

[0026] [Corrected 10.02.2025 according to Rule 26] In conjunction with the first aspect or the second aspect, in one possible implementation, the extended indicator matrix corresponding to matrix 2 is:

[0027] [Corrected 10.02.2025 according to Rule 26] In combination with the first aspect or the second aspect, in one possible implementation, when the code rate R of the information bit sequence is 1 / 2, the matrix prototype of the check matrix is ​​the following matrix 3:

[0028] [Corrected 10.02.2025 according to Rule 26] In conjunction with the first aspect or the second aspect, in one possible implementation, the extended indicator matrix corresponding to matrix 3 is:

[0029] [Corrected 10.02.2025 according to Rule 26] In combination with the first aspect or the second aspect, in one possible implementation, when the code rate R of the information bit sequence is 2 / 3, the matrix prototype of the check matrix is ​​the following matrix 4:

[0030] [Corrected 10.02.2025 according to Rule 26] In conjunction with the first aspect or the second aspect, in one possible implementation, the extended indicator matrix corresponding to matrix 4 is:

[0031] [Corrected 10.02.2025 according to Rule 26] In combination with the first aspect or the second aspect, in one possible implementation, when the code rate R of the information bit sequence is 2 / 3, the matrix prototype of the check matrix is ​​the following matrix 5:

[0032] [Corrected 10.02.2025 according to Rule 26] In conjunction with the first aspect or the second aspect, in one possible implementation, the extended indicator matrix corresponding to the matrix 5 is:

[0033] [Corrected 10.02.2025 according to Rule 26] In combination with the first aspect or the second aspect, in one possible implementation, when the code rate of the information bit sequence is R=2 / 3, the matrix prototype of the check matrix is ​​the following matrix 6:

[0034] [Corrected 10.02.2025 according to Rule 26] In conjunction with the first aspect or the second aspect, in one possible implementation, the extended indicator matrix corresponding to matrix 6 is:

[0035] [Corrected 10.02.2025 according to Rule 26] In combination with the first aspect or the second aspect, in one possible implementation, when the code rate of the information bit sequence is R=3 / 4, the matrix prototype of the check matrix is ​​the following matrix 7:

[0036] [Corrected 10.02.2025 according to Rule 26] In conjunction with the first aspect or the second aspect, in one possible implementation, the extended indicator matrix corresponding to the matrix 7 is:

[0037] [Corrected 10.02.2025 according to Rule 26] In combination with the first aspect or the second aspect, in one possible implementation, when the code rate of the information bit sequence is R=3 / 4, the matrix prototype of the check matrix is ​​the following matrix 8:

[0038] [Corrected 10.02.2025 according to Rule 26] In conjunction with the first aspect or the second aspect, in one possible implementation, the extended indicator matrix corresponding to the matrix 8 is:

[0039] [Corrected 10.02.2025 according to Rule 26] In combination with the first aspect or the second aspect, in one possible implementation, when the code rate of the information bit sequence is R=3 / 4, the matrix prototype of the check matrix is ​​the following matrix 9:

[0040] [Corrected 10.02.2025 according to Rule 26] In conjunction with the first aspect or the second aspect, in one possible implementation, the extended indicator matrix corresponding to the matrix 9 is:

[0041] [Corrected 10.02.2025 according to Rule 26] In combination with the first aspect or the second aspect, in one possible implementation, when the code rate of the information bit sequence is R=3 / 4, the matrix prototype of the check matrix is ​​the following matrix 10:

[0042] [Corrected 10.02.2025 according to Rule 26] In conjunction with the first aspect or the second aspect, in one possible implementation, the extended indicator matrix corresponding to the matrix 10 is:

[0043] [Corrected 10.02.2025 according to Rule 26] In combination with the first aspect or the second aspect, in one possible implementation, when the code rate of the information bit sequence is R=5 / 6, the matrix prototype of the check matrix is ​​the following matrix 11:

[0044] [Corrected 10.02.2025 according to Rule 26] In conjunction with the first aspect or the second aspect, in one possible implementation, the extended indicator matrix corresponding to the matrix 11 is:

[0045] [Corrected 10.02.2025 according to Rule 26] In combination with the first aspect or the second aspect, in one possible implementation, when the code rate of the information bit sequence is R=5 / 6, the matrix prototype of the check matrix is ​​the following matrix 12:

[0046] [Corrected 10.02.2025 according to Rule 26] In conjunction with the first aspect or the second aspect, in one possible implementation, the extended indicator matrix corresponding to the matrix 12 is:

[0047] [Corrected 10.02.2025 according to Rule 26] In combination with the first aspect or the second aspect, in one possible implementation, when the code rate R of the information bit sequence is 5 / 6, the matrix prototype of the check matrix is ​​the following matrix 13:

[0048] [Corrected 10.02.2025 according to Rule 26] In conjunction with the first aspect or the second aspect, in one possible implementation, the extended indicator matrix corresponding to the matrix 13 is:

[0049] [Corrected 10.02.2025 according to Rule 26] In combination with the first aspect or the second aspect, in one possible implementation, when the code rate R of the information bit sequence is 5 / 6, the matrix prototype of the check matrix is ​​the following matrix 14:

[0050] [Corrected 10.02.2025 according to Rule 26] In conjunction with the first aspect or the second aspect, in one possible implementation, the extended indicator matrix corresponding to the matrix 14 is:

[0051] [Corrected 10.02.2025 according to Rule 26] In combination with the first aspect or the second aspect, in one possible implementation, when the code rate R of the information bit sequence is 1 / 2, the matrix prototype of the check matrix is ​​the following matrix 15:

[0052] [Corrected 10.02.2025 according to Rule 26] In conjunction with the first aspect or the second aspect, in one possible implementation, the extended indicator matrix corresponding to the matrix 15 is:

[0053] [Corrected 10.02.2025 according to Rule 26] In combination with the first aspect or the second aspect, in one possible implementation, when the code rate R of the information bit sequence is 1 / 2, the matrix prototype of the check matrix is ​​the following matrix 16:

[0054] [Corrected 10.02.2025 according to Rule 26] In conjunction with the first aspect or the second aspect, in one possible implementation, the extended indicator matrix corresponding to the matrix 16 is:

[0055] [Corrected 10.02.2025 according to Rule 26] In combination with the first aspect or the second aspect, in one possible implementation, when the code rate R of the information bit sequence is 2 / 3, the matrix prototype of the check matrix is ​​the following matrix 17:

[0056] [Corrected 10.02.2025 according to Rule 26] In conjunction with the first aspect or the second aspect, in one possible implementation, the extended indicator matrix corresponding to the matrix 17 is:

[0057] [Corrected 10.02.2025 according to Rule 26] In combination with the first aspect or the second aspect, in one possible implementation, when the code rate R of the information bit sequence is 2 / 3, the matrix prototype of the check matrix is ​​the following matrix 18:

[0058] [Corrected 10.02.2025 according to Rule 26] In conjunction with the first aspect or the second aspect, in one possible implementation, the extended indicator matrix corresponding to the matrix 18 is:

[0059] [Corrected 10.02.2025 according to Rule 26] In combination with the first aspect or the second aspect, in one possible implementation, when the code rate of the information bit sequence is R=3 / 4, the matrix prototype of the check matrix is ​​the following matrix 19:

[0060] [Corrected 10.02.2025 according to Rule 26] In conjunction with the first aspect or the second aspect, in one possible implementation, the extended indicator matrix corresponding to the matrix 19 is:

[0061] [Corrected 10.02.2025 according to Rule 26] In combination with the first aspect or the second aspect, in one possible implementation, when the code rate of the information bit sequence is R=3 / 4, the matrix prototype of the check matrix is ​​the following matrix 20:

[0062] [Corrected 10.02.2025 according to Rule 26] In conjunction with the first aspect or the second aspect, in one possible implementation, the extended indicator matrix corresponding to the matrix 20 is:

[0063] [Corrected 10.02.2025 according to Rule 26] In combination with the first aspect or the second aspect, in one possible implementation, when the code rate of the information bit sequence is R=5 / 6, the matrix prototype of the check matrix is ​​the following matrix 21:

[0064] [Corrected 10.02.2025 according to Rule 26] In conjunction with the first aspect or the second aspect, in one possible implementation, the extended indicator matrix corresponding to the matrix 21 is:

[0065] [Corrected 10.02.2025 according to Rule 26] In combination with the first aspect or the second aspect, in one possible implementation, when the code rate of the information bit sequence is R=5 / 6, the matrix prototype of the check matrix is ​​the following matrix 22:

[0066] [Corrected 10.02.2025 according to Rule 26] In conjunction with the first aspect or the second aspect, in one possible implementation, the extended indicator matrix corresponding to the matrix 22 is:

[0067] In a third aspect, an embodiment of the present application provides a first communication device configured to execute the method in the first aspect or any possible implementation. The first communication device includes a module configured to execute the method in the first aspect or any possible implementation.

[0068] In a fourth aspect, embodiments of the present application provide a second communication device configured to execute the method in the second aspect or any possible implementation. The second communication device includes a module configured to execute the method in the second aspect or any possible implementation.

[0069] In a fifth aspect, an embodiment of the present application provides a first communication device, comprising a processor configured to execute the method described in the first aspect or any possible implementation. The processor is configured to execute a program stored in a memory, and when the program is executed, the method described in the first aspect or any possible implementation is executed.

[0070] In a possible implementation, the memory is located outside the first communication device.

[0071] In a possible implementation, the memory is located within the first communication device.

[0072] In the embodiment of the present application, the processor and the memory may also be integrated into one device, that is, the processor and the memory may also be integrated together. For example, the first communication device may be a chip.

[0073] In a possible implementation, the first communication device further includes a transceiver, where the transceiver is configured to receive information or send information.

[0074] In a sixth aspect, an embodiment of the present application provides a second communication device, comprising a processor configured to execute the method described in the second aspect or any possible implementation. The processor is configured to execute a program stored in a memory, and when the program is executed, the method described in the second aspect or any possible implementation is executed.

[0075] In a possible implementation, the memory is located outside the second communication device.

[0076] In a possible implementation, the memory is located within the second communication device.

[0077] In the embodiment of the present application, the processor and the memory may also be integrated into one device, that is, the processor and the memory may also be integrated together. Exemplarily, the second communication device may be a chip.

[0078] In a possible implementation, the second communication device further includes a transceiver, where the transceiver is configured to receive information or send information.

[0079] In the seventh aspect, an embodiment of the present application provides a first communication device, which includes a logic circuit and an interface, and the logic circuit and the interface are coupled; the interface is used to input and / or output information, and the logic circuit is used to execute the method described in the first aspect or any possible implementation method.

[0080] In an eighth aspect, an embodiment of the present application provides a second communication device, which includes a logic circuit and an interface, and the logic circuit and the interface are coupled; the interface is used to input and / or output information, and the logic circuit is used to execute the method described in the second aspect or any possible implementation method.

[0081] In the ninth aspect, an embodiment of the present application provides a computer-readable storage medium, which is used to store a computer program. When the computer-readable storage medium is run on a computer, the method shown in any one of the above-mentioned first to second aspects or any possible implementation method is executed.

[0082] In a tenth aspect, an embodiment of the present application provides a computer program product, which, when executed on a computer, enables the method shown in any one of the first to second aspects or any possible implementation thereof to be executed.

[0083] In an eleventh aspect, an embodiment of the present application provides a computer program. When the computer program is run on a computer, the method shown in any one of the first to second aspects or any possible implementation is executed.

[0084] In the twelfth aspect, an embodiment of the present application provides a communication system, which includes a first communication device and / or a second communication device, the first communication device is used to execute the method shown in the above-mentioned first aspect or any possible implementation of the first aspect, and the second communication device is used to execute the method shown in the above-mentioned second aspect or any possible implementation of the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0085] FIG1a is a schematic diagram of a matrix prototype of a reference check matrix provided in an embodiment of the present application;

[0086] FIG1b is a schematic diagram of a CPM provided in an embodiment of the present application;

[0087] FIG2a is a schematic diagram of the architecture of a communication system provided in an embodiment of the present application;

[0088] FIG2b is a schematic diagram of the architecture of a communication system provided in an embodiment of the present application;

[0089] FIG2c is a schematic diagram of the architecture of a communication system provided in an embodiment of the present application;

[0090] FIG3 is a flow chart of an encoding method and a decoding method provided in an embodiment of the present application;

[0091] FIG4a is a schematic diagram of a matrix prototype of a check matrix provided in an embodiment of the present application;

[0092] FIG4b is a schematic diagram of an extended indicator matrix corresponding to FIG4a provided in an embodiment of the present application;

[0093] FIG5a is a schematic diagram of a matrix prototype of a check matrix provided in an embodiment of the present application;

[0094] FIG5b is a schematic diagram of an extended indicator matrix corresponding to FIG5a provided in an embodiment of the present application;

[0095] FIG6a is a schematic diagram of a matrix prototype of a check matrix provided in an embodiment of the present application;

[0096] FIG6b is a schematic diagram of an extended indicator matrix corresponding to FIG6a provided in an embodiment of the present application;

[0097] FIG7a is a schematic diagram of a matrix prototype of a check matrix provided in an embodiment of the present application;

[0098] FIG7b is a schematic diagram of an extended indicator matrix corresponding to FIG7a provided in an embodiment of the present application;

[0099] FIG8a is a schematic diagram of a matrix prototype of a check matrix provided in an embodiment of the present application;

[0100] FIG8b is a schematic diagram of an extended indicator matrix corresponding to FIG8a provided in an embodiment of the present application;

[0101] FIG9a is a schematic diagram of a matrix prototype of a check matrix provided in an embodiment of the present application;

[0102] FIG9b is a schematic diagram of an extended indicator matrix corresponding to FIG9a provided in an embodiment of the present application;

[0103] FIG10a is a schematic diagram of a matrix prototype of a check matrix provided in an embodiment of the present application;

[0104] FIG10b is a schematic diagram of an extended indicator matrix corresponding to FIG10a provided in an embodiment of the present application;

[0105] FIG11a is a schematic diagram of a matrix prototype of a check matrix provided in an embodiment of the present application;

[0106] FIG11b is a schematic diagram of an extended indicator matrix corresponding to FIG11a provided in an embodiment of the present application;

[0107] FIG12a is a schematic diagram of a matrix prototype of a check matrix provided in an embodiment of the present application;

[0108] FIG12b is a schematic diagram of an extended indicator matrix corresponding to FIG12a provided in an embodiment of the present application;

[0109] FIG13a is a schematic diagram of a matrix prototype of a check matrix provided in an embodiment of the present application;

[0110] FIG13b is a schematic diagram of an extended indicator matrix corresponding to FIG13a provided in an embodiment of the present application;

[0111] FIG13c is a schematic diagram of an extended indicator matrix corresponding to FIG13a provided in an embodiment of the present application;

[0112] FIG14a is a schematic diagram of a matrix prototype of a check matrix provided in an embodiment of the present application;

[0113] FIG14b is a schematic diagram of an extended indicator matrix corresponding to FIG14a provided in an embodiment of the present application;

[0114] FIG15a is a schematic diagram of a matrix prototype of a check matrix provided in an embodiment of the present application;

[0115] FIG15b is a schematic diagram of an extended indicator matrix corresponding to FIG15a provided in an embodiment of the present application;

[0116] FIG16a is a schematic diagram of a matrix prototype of a check matrix provided in an embodiment of the present application;

[0117] FIG16b is a schematic diagram of an extended indicator matrix corresponding to FIG16a provided in an embodiment of the present application;

[0118] FIG17a is a schematic diagram of a matrix prototype of a check matrix provided in an embodiment of the present application;

[0119] FIG17b is a schematic diagram of an extended indicator matrix corresponding to FIG17a provided in an embodiment of the present application;

[0120] FIG18 is a partial schematic diagram of a shortening operation in an LDPC encoding provided in an embodiment of the present application;

[0121] FIG19a is a schematic diagram of an embodiment of the present application showing a diagonal expansion of an element i;

[0122] FIG19b is a schematic diagram of anti-diagonal expansion of element i according to an embodiment of the present application;

[0123] FIG20 a is a schematic diagram of two options of diagonal expansion and anti-diagonal expansion provided in an embodiment of the present application;

[0124] FIG20 b is a schematic diagram of a tree expansion provided by an embodiment of the present application;

[0125] FIG21a is a schematic diagram of a simulation result provided by an embodiment of the present application;

[0126] FIG21 b is a schematic diagram of a simulation result provided by an embodiment of the present application;

[0127] FIG21c is a schematic diagram of a simulation result provided by an embodiment of the present application;

[0128] FIG21 d is a schematic diagram of a simulation result provided by an embodiment of the present application;

[0129] FIG22 is a schematic structural diagram of a communication device provided in an embodiment of the present application;

[0130] FIG23 is a schematic structural diagram of a communication device provided in an embodiment of the present application;

[0131] FIG24 is a schematic structural diagram of a communication device provided in an embodiment of the present application;

[0132] FIG25 is a schematic diagram of a matrix prototype grouping design for a basic check matrix provided in an embodiment of the present application;

[0133] FIG26a and FIG26b are schematic diagrams of an extended indicator matrix provided in an embodiment of the present application;

[0134] FIG27a is a schematic diagram of a matrix prototype of a check matrix provided in an embodiment of the present application;

[0135] FIG27b is a schematic diagram of an extended indicator matrix corresponding to FIG27a provided in an embodiment of the present application;

[0136] FIG28a is a schematic diagram of a matrix prototype of a check matrix provided in an embodiment of the present application;

[0137] FIG28b is a schematic diagram of an extended indicator matrix corresponding to FIG28a provided in an embodiment of the present application;

[0138] FIG29a is a schematic diagram of a matrix prototype of a check matrix provided in an embodiment of the present application;

[0139] FIG29b is a schematic diagram of an extended indicator matrix corresponding to FIG29a provided in an embodiment of the present application;

[0140] FIG30 a is a schematic diagram of a matrix prototype of a check matrix provided in an embodiment of the present application;

[0141] FIG30 b is a schematic diagram of an extended indicator matrix corresponding to FIG30 a provided in an embodiment of the present application;

[0142] FIG31a is a schematic diagram of a matrix prototype of a check matrix provided in an embodiment of the present application;

[0143] FIG31 b is a schematic diagram of an extended indicator matrix corresponding to FIG31 a provided in an embodiment of the present application;

[0144] FIG32a is a schematic diagram of a matrix prototype of a check matrix provided in an embodiment of the present application;

[0145] FIG32b is a schematic diagram of an extended indicator matrix corresponding to FIG32a provided in an embodiment of the present application;

[0146] FIG33a is a schematic diagram of a matrix prototype of a check matrix provided in an embodiment of the present application;

[0147] FIG33b is a schematic diagram of an extended indicator matrix corresponding to FIG33a provided in an embodiment of the present application;

[0148] FIG34a is a schematic diagram of a matrix prototype of a check matrix provided in an embodiment of the present application;

[0149] FIG34b is a schematic diagram of an extended indicator matrix corresponding to FIG34a provided in an embodiment of the present application;

[0150] FIG35a is a schematic diagram of a matrix prototype of a check matrix provided in an embodiment of the present application;

[0151] FIG35 b is a schematic diagram of an extended indicator matrix corresponding to FIG35 a provided in an embodiment of the present application;

[0152] FIG36a is a schematic diagram of a matrix prototype of a check matrix provided in an embodiment of the present application;

[0153] FIG36b is a schematic diagram of an extended indicator matrix corresponding to FIG36a provided in an embodiment of the present application;

[0154] FIG37a is a schematic diagram of a matrix prototype of a check matrix provided in an embodiment of the present application;

[0155] Figure 37b is a schematic diagram of the extended indication matrix corresponding to Figure 31a provided in an embodiment of the present application. DETAILED DESCRIPTION

[0156] To facilitate understanding of the technical solution of the present application, the present application will be further described below with reference to the accompanying drawings.

[0157] The terms "first" and "second" in the specification, claims, and drawings of this application are used only to distinguish different objects and are not used to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to the process, method, product, or device.

[0158] References to "embodiments" herein mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it refer to independent or alternative embodiments that are mutually exclusive of other embodiments. It will be understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0159] In this application, "at least one (item)" means one or more, "more than one" means two or more, "at least two (items)" means two or three and more than three, and "and / or" is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. "Or" means that two relationships can exist, such as only A exists, only B exists; when A and B are not mutually exclusive, it can also mean that three relationships exist, such as only A exists, only B exists, and A and B exist at the same time. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c".

[0160] The LDPC codes used in standards such as IEEE 802.11ac / ax are quasi-cyclic (QC) LDPC (QC-LDPC) codes. QC-LDPC codes are a widely used type of structured LDPC code. Due to the unique structure of their parity check matrix, they can be encoded using a simple feedback shift register, effectively alleviating the coding complexity issues of LDPC codes.

[0161] The current standard adopts 12 LDPC code parity check matrices, with three code lengths N: N = 648, N = 1296, or N = 1944. Each code length can support four different coding rates: 1 / 2, 2 / 3, 3 / 4, and 5 / 6. The matrix prototypes of the parity check matrices for each code length and coding rate are different. The parity check bit portion (the matrix corresponding to the parity bits, or parity matrix, shown below) in the matrix prototypes of the 12 parity check matrices for different code lengths and coding rates has the same structure. For example, the code rate selection can be determined by the modulation and coding scheme (MCS) selected by the transmission system based on link adaptation. Therefore, a communication device in a wireless local area network (WLAN) can select a parity check matrix from the 12 parity check matrices based on a given code length and coding rate. The aforementioned identical structure can be understood as meaning that the parity bit portion of the matrix prototypes of the different parity check matrices in Figure 1a has the first row and first column elements all set to 1, and the last row and first column elements all set to 1. As shown in the first matrix in Figure 1a, the first column of the parity bit portion is the 13th column in the matrix prototype of the parity check matrix, and the last column of the parity bit portion is the 24th column in the matrix prototype of the parity check matrix. In the second matrix in Figure 1a, the first column of the parity bit portion is the 17th column in the matrix prototype of the parity check matrix, and the last column of the parity bit portion is the 24th column in the matrix prototype of the parity check matrix. In the third matrix in Figure 1a, the first column of the parity bit portion is the 19th column in the matrix prototype of the parity check matrix, and the last column of the parity bit portion is the 24th column in the matrix prototype of the parity check matrix. In the second matrix in Figure 1a, the first column of the parity bit portion is the 21st column in the matrix prototype of the parity check matrix, and the last column of the parity bit portion is the 24th column in the matrix prototype of the parity check matrix.

[0162] Figure 1a shows the matrix prototype of the LDPC code check matrix with code length N=1944 and different code rates. The “-” in Figure 1a represents a Z*Z all-zero matrix, the “0” in Figure 1a represents a Z*Z unit matrix, and the non-zero elements in Figure 1a represent the circulant permutation matrix (CPM) of the Z*Z unit matrix. For example, CPM uses P iIndicates that i represents the cyclic shift value or the number of bits of the unit matrix cyclically shifted to the right or the CPM coefficient or the element greater than or equal to 0 in the matrix prototype of the check matrix, etc. The specific name of i is not limited in the embodiments of the present application. i is a non-negative integer, such as 0≤i≤Z-1. When i=0, CPM can be understood as a Z*Z unit matrix, or a CPM with a cyclic shift value of 0. For example, in Figure 1a, Z=N / 24. The aforementioned "24" can be the same as the number of columns of the matrix prototype of the check matrix in the IEEE802.11ac / ax standard. For IEEE 801.11ac / ax, regardless of the code length N=648, N=1296, or N=1944, the number of columns of the matrix prototype of the check matrix is ​​24 columns.

[0163] For example, taking element "1" (i.e., i=1) in FIG1a as an example, the element 1 can be expanded to a CPM of 81*81 (1944 / 24=81). The CPM can be expanded by cyclically shifting the unit matrix right by 1 bit, as shown below:

[0164] For example, taking the 4*4 CPM as an example, FIG1b shows the CPM when i=0, the CPM when i=1, the CPM when i=2, and the CPM when i=3. The CPM shown in FIG1b is only an example. The CPM of other Z*Z unit matrices in the embodiments of the present application can refer to the principle shown in FIG1a or FIG1b to obtain the final P i , which will not be elaborated below.

[0165] Because LDPC codes can improve the transmission reliability of wireless transmission systems, they have been widely used in WLAN standards. To further improve the data transmission reliability of Wi-Fi systems, current and next-generation standards may consider LDPC codes with longer code lengths, thereby achieving stronger error control performance in the encoding module and improving the decoding performance of the decoding module.

[0166] In view of this, the embodiments of the present application provide an encoding method, a decoding method, and an apparatus, which involve a new LDPC code that can support a longer code length. The check matrix provided in the embodiments of the present application can be applied to a longer code length, such as the check matrix can be applied to a code length of n times 1944, where n is an integer greater than or equal to 2, and the check matrix can also improve decoding performance. For example, based on the existing WLAN LDPC long code (such as a code length of 1944 bits), the LDPC code (or LDPC long code) provided in the embodiments of the present application (such as a code length of 3888 bits) can achieve excellent performance. Furthermore, the new LDPC long code provided in the embodiments of the present application can reuse the encoding and decoding architecture of the original WLAN LDPC code as much as possible, such as with minimal changes to the existing LDPC encoding module and LDPC decoding module, which can reduce the implementation complexity of the LDPC encoding and decoding.

[0167] In the embodiment of the present application, the various matrices shown below can be called prototypes of check matrices, or matrix prototypes of check matrices (matrix prototypes for parity-matrices), or matrix prototypes for codeword block length N (matrix prototypes for codeword block length N) or mother matrices, etc. The specific names of the matrices involved in the embodiments of the present application are not limited in the embodiments of the present application. Generally speaking, a matrix including element 0 and element 1 after expansion based on Z and cyclic shift value i is called a check matrix, so the various matrices shown below can also be called matrices before CPM expansion, etc. The various matrices shown in Examples 1 to 14 below can be called matrix prototypes of check matrices, and the matrices after expansion based on the elements in the various matrices shown in Examples 1 to 14 can be called check matrices. For the specific method of expansion, please refer to the above description of Figures 1a and 1b. For the specific content of the expanded check matrix, the embodiments of the present application will no longer list them one by one.

[0168] In the embodiments of the present application, the code length may also be referred to as a codeword block length (acodewordblocklength), etc., and the specific name of the code length is not limited in the embodiments of the present application. In the embodiments of the present application, Z may be referred to as a subblock size (subblocksize), an expansion factor, or a lift factor, etc., and the specific name of Z is not limited in the embodiments of the present application. For ease of description, the following description uses Z as an example of an expansion factor.

[0169] In the embodiments of the present application, Z = N / 48. However, as standards progress, the subsequent method for calculating Z may also change, and the embodiments of the present application do not limit this. For ease of understanding, different letter parameters are used in the embodiments of the present application to represent different meanings, such as N for code length, Z for expansion factor, R for code rate, K for the number of information bits, and E for the number of check bits. However, the various letter parameters shown in the embodiments of the present application are only examples and should not be understood as limiting the embodiments of the present application.

[0170] The following introduces the communication system involved in the embodiments of the present application.

[0171] The technical solutions provided in the embodiments of the present application can be applied to wireless local area network (WLAN) systems, such as Wi-Fi, etc. The methods provided in the embodiments of the present application can be applied to the Institute of Electrical and Electronics Engineers IEEE 802.11 series protocols, such as the 802.11be protocol, the 802.11bn protocol, or the next generation protocol of the 802.11bn protocol or the protocol that supports ambient power (AMP), etc., which are not listed one by one. The technical solutions provided in the embodiments of the present application can also be applied to wireless personal area networks (WPANs) based on millimeter wave (MMW) and ultra wideband (UWB) technologies, etc. The methods provided in the embodiments of the present application can be applied to the IEEE802.15 series protocols, such as the 802.15.4a protocol, the 802.15.4z protocol, or the 802.15.4ab protocol, or a future generation of UWB WPAN protocols, etc., which are not listed one by one. The technical solutions provided in the embodiments of the present application can also be applied to the following communication systems, for example, the Internet of Things (IoT) system, vehicle-to-everything (V2X, where X can represent anything), device-to-device (D2D), narrowband Internet of Things (NB-IoT) system, long-term evolution (LTE) system, fifth-generation (5G) communication system, and new communication systems that will emerge in future communication developments. For example, the V2X may include vehicle-to-vehicle (V2V), vehicle-to-infrastructure (V2I), vehicle-to-pedestrian (V2P) or vehicle-to-network (V2N) communication.

[0172] WLAN systems can provide high-speed and low-latency transmission. As WLAN application scenarios continue to evolve, WLAN systems will be applied to more scenarios or industries, such as the Internet of Things industry, the Internet of Vehicles industry, the banking industry, corporate offices, sports stadiums and exhibition halls, concert halls, hotel rooms, dormitories, wards, classrooms, supermarkets, squares, streets, production workshops and warehouses, etc. Of course, devices that support WLAN communication or perception (such as access points or stations) can be sensor nodes in smart cities (such as smart water meters, smart electricity meters, and smart air detection nodes), smart devices in smart homes (such as smart cameras, projectors, displays, TVs, speakers, refrigerators, washing machines, etc.), nodes in the Internet of Things, entertainment terminals (such as wearable devices such as augmented reality (AR) and virtual reality (VR)), smart devices in smart offices (such as printers, projectors, loudspeakers, speakers, etc.), Internet of Vehicles devices, infrastructure in daily life scenarios (such as vending machines, self-service navigation counters in supermarkets, self-service checkout equipment, self-service ordering machines, etc.), and equipment in large sports and music venues.

[0173] Although the embodiments of the present application mainly take WLAN as an example, especially the network applied to the IEEE 802.11 series of standards. The embodiments of the present application can also support Wi-Fi 8, which can also be called ultra high reliability (UHR) or ultra high reliability and throughput (UHRT), etc., which are not listed here one by one. The various aspects involved in the embodiments of the present application can be extended to other networks that adopt various standards or protocols. For example, Bluetooth, high performance radio LAN (HIPERLAN) (a wireless standard similar to the IEEE 802.11 standard) and wide area network (WAN) or other networks now known or developed later.

[0174] In one possible implementation, the method provided in the embodiment of the present application may be implemented by a communication device in a communication system. For example, the communication device may be an access point (AP) or a station (STA).

[0175] An AP is a device with wireless communication capabilities that supports communication, perception, or energy transmission using WLAN protocols. It has the ability to communicate, perceive, or transmit energy with other devices in a WLAN network (such as non-access point stations (non-AP STAs) or other access points). Of course, it can also have the ability to communicate, perceive, or transmit energy with other devices. Alternatively, an access point is equivalent to a bridge connecting a wired network and a wireless network. Its main function is to connect various wireless network clients together and then connect the wireless network to the Ethernet. In a WLAN system, an access point can be called an access point station (AP STA). The device with wireless communication capabilities can be a complete device, or it can be a chip, processing system, or functional module installed in the complete device. The device in which these chips, processing systems, or functional modules are installed can implement the methods and functions of the embodiments of the present application under the control of the chips, processing systems, or functional modules. The AP in the embodiments of the present application is a device that provides services for non-AP STAs and can support 802.11 series protocols or subsequent protocols. For example, an access point can be an access point for a terminal (such as a mobile phone) to enter a wired (or wireless) network. It is mainly deployed in homes, buildings, and campuses, with a typical coverage radius of tens to hundreds of meters. Of course, it can also be deployed outdoors. For another example, an AP can be a communication entity such as a communication server, router, switch, or bridge; an AP can include various forms of macro base stations, micro base stations, and relay stations. Of course, an AP can also be a chip, processing system, or module in any of the above-mentioned devices, thereby implementing the methods and functions of the embodiments of the present application.

[0176] A STA is a device with wireless communication capabilities that supports communication, sensing, or energy transmission using the WLAN protocol and has the ability to communicate, sense, or transmit energy with other non-AP STAs or access points in the WLAN network. In a WLAN system, a station can be referred to as a non-access point station (non-AP STA). For example, a STA is any user communication device that allows a user to communicate, sense, or transmit energy with an AP and thereby communicate with the WLAN. The device with wireless communication capabilities can be a complete device, or a chip, processing system, or functional module installed in the complete device. Devices equipped with these chips, processing systems, or functional modules can implement the methods and functions of the embodiments of the present application under the control of the chip, processing system, or functional module. For example, a STA can be a wireless communication chip, a wireless sensor, or a wireless communication terminal, and can also be referred to as a user. For another example, a STA can be a mobile phone that supports Wi-Fi communication capabilities, a tablet that supports Wi-Fi communication capabilities, a set-top box that supports Wi-Fi communication capabilities, a smart TV that supports Wi-Fi communication capabilities, a smart wearable device that supports Wi-Fi communication capabilities, an in-vehicle communication device that supports Wi-Fi communication capabilities, and a computer that supports Wi-Fi communication capabilities. Of course, STA can also be a chip, processing system, or module in the various forms of devices mentioned above, so as to implement the methods and functions of the embodiments of the present application.

[0177] Exemplarily, the communication system to which the method provided in the embodiment of the present application can be applied may include access points and stations. For example, the embodiment of the present application may be applicable to scenarios of communication or perception between AP and STA, between AP and AP, or between STA and STA in a WLAN, and the embodiment of the present application is not limited to this. Optionally, the AP may communicate or perceive with a single STA, or the AP may communicate or perceive with multiple STAs at the same time. Specifically, the communication or perception between the AP and multiple STAs can be divided into downlink transmission in which the AP sends signals to multiple STAs at the same time, and uplink transmission in which multiple STAs send signals to the AP. Among them, the WLAN communication protocol can be supported between the AP and the STA, between the AP and the AP, and between the STA and the STA. The communication protocol may include a protocol of the IEEE802.11 series, such as the 802.11bn protocol, and of course, it is also applicable to protocols after 802.11bn.

[0178] Figure 2a is a schematic diagram of the architecture of a communication system provided by an embodiment of the present application. The communication system may include one or more APs and one or more STAs. Figure 2a shows two access points such as AP1 and AP2, and three stations such as STA1, STA2, and STA3. As an example, the method provided by the embodiment of the present application can be applied to data communication or perception between an AP and one or more STAs, such as the communication between AP1 and STA1 as shown in Figure 2a, the communication between an AP and a STA as shown in Figure 2b, the communication or perception or energy transmission between AP1 and STA1 and STA2 as shown in Figure 2a, and the communication or perception or energy transmission between an AP and STA1, STA2, and STA3 as shown in Figure 2c. As another example, the method provided by the embodiment of the present application can be applied to communication between APs, such as the communication or perception between AP1 and AP2 as shown in Figure 2a. As another example, the method provided by the embodiment of the present application can be applied to communication or perception between STAs, such as the communication or perception between STA2 and STA3 as shown in Figure 2a.

[0179] In Figures 2a through 2c, STAs are mobile phones and APs are routers, respectively, as examples. This does not limit the types of APs and STAs used in the embodiments of this application. Furthermore, the number of APs and STAs shown in Figures 2a through 2c is merely exemplary. In specific implementations, the number of APs or STAs can be greater or lesser, and this is not a limitation in the embodiments of this application.

[0180] From the perspectives of sending and receiving signals, the first communication device shown below can be understood as a communication device that sends signals, and the second communication device can be understood as a communication device that receives signals. Alternatively, the first communication device can be referred to as a transmitting end, and the second communication device can be referred to as a receiving end. In the embodiments of the present application, the signal can be an encoded sequence, or a signal obtained by processing an encoded sequence.

[0181] From the perspective of different devices, as an example, the first communication device and the second communication device may be Wi-Fi chips, functional modules, or processing systems, etc., provided in different Wi-Fi devices. As another example, the first communication device may be an AP, and the second communication device may be a non-AP STA. As yet another example, the first communication device and the second communication device may both be non-AP STAs or both APs. As yet another example, the first communication device may be a non-AP STA, and the second communication device may be an AP. As yet another example, at least one of the first communication device and the second communication device may be a multi-link device (MLD), etc., which are not listed one by one in the embodiments of this application. Exemplarily, a multi-link device (MLD) refers to a device that simultaneously has multiple stations (such as APs or non-AP STAs), each operating on different frequency bands or channels. A multi-link device includes multiple subordinate stations, which may be physical or logical stations, and each station may operate on a link, a frequency band, or a channel, etc. The subordinate stations may be APs or non-AP STAs. A multi-link device (such as a non-AP MLD or an AP MLD) can be a communication device with wireless communication capabilities. The communication device can be a complete device, or it can be a chip, processing system, or module installed in the complete device. Devices installed with these chips, processing systems, or modules can implement the methods and functions of the embodiments of the present application under the control of these chips, processing systems, or modules. The multi-link device can implement wireless communication in accordance with the 802.11 series of protocols, thereby enabling communication with other devices. The other devices shown here may or may not be multi-link devices. The frequency bands in which the multi-link device operates may include, but are not limited to, sub 1 GHz, 2.4 GHz, 5 GHz, 6 GHz, etc., which are not listed here one by one.

[0182] The embodiment of the present application describes the method provided by the embodiment of the present application based on the first communication device and the second communication device. However, during the process of transmitting signals, the first communication device and the second communication device can also forward the signal through other devices, such as forwarding the signal between the first communication device and the second communication device through a forwarding device. The embodiment of the present application does not limit other devices other than the first communication device and the second communication device.

[0183] The following describes the methods involved in the embodiments of the present application.

[0184] FIG3 is a flow chart of an encoding method and a decoding method provided by an embodiment of the present application. The description of the first communication device and the second communication device, etc., can be referred to above and will not be described in detail here. As shown in FIG3 , the method includes:

[0185] 301. A first communication device obtains an information bit sequence.

[0186] The information bit sequence may be a bit sequence containing information. For example, the length of the information bit sequence is N2, or the number of bits in the information bit sequence is N2. N2 is a positive integer. The N2 bits may include K information bits, or K data bits, or K payload bits. K is a positive integer. N2 may be an integer greater than or equal to K. For example, when N2 is greater than K, the information bit sequence may also include (N2-K) 0s. For the relevant description of the "0" shown here, please refer to the description of the shortening operation in Figure 18 below, which will not be described in detail here.

[0187] The value of N2 can be related to the code length and code rate. If the length of the encoded sequence in step 302 is N1, then N2 = N1 * R, where R is the encoding code rate of the information bit sequence. N1 shown here can also be referred to as the code length corresponding to the check matrix. N1 can also be understood as the original code length of a single LDPC codeword, and N2 can be understood as the original information bits of a single LDPC codeword.

[0188] In a possible implementation, the method shown in FIG3 may further include:

[0189] The first communication device obtains the code length N1.

[0190] As an example, N1 may be m times 1296, where m is an integer greater than or equal to 2. For example, N1=1296*2=2592. Another example is N1=1296*3=3888, etc., which are not listed here one by one.

[0191] As another example, N1 may be n times 1944, where n is an integer greater than or equal to 2, such as N1=1944*2=3888, or N1=1944*3=5832, etc., which are not listed here one by one.

[0192] In a possible implementation, the method shown in FIG3 may further include:

[0193] The first communication device obtains a code rate R.

[0194] In a WLAN system, different code lengths and code rates may correspond to different parity check matrices. Therefore, before the first communication device performs LDPC encoding, it may also obtain a code rate R. After obtaining the code rate R, the first communication device may select a parity check matrix based on the code rate R and the code length N1. The code rate R may be determined based on the MCS selected by link adaptation. For example, the code rate R may be determined based on current channel information. The embodiments of the present application do not limit the specific method for determining the code rate R. As an example, the MCS may be issued by the AP. As another example, the MCS may be determined by the first communication device, etc. For example, the first communication device sends an MCS to the second communication device, the second communication device receives the MCS, and obtains the code rate R based on the MCS. For another example, the second communication device sends an MCS to the first communication device, the first communication device receives the MCS, and obtains the code rate R based on the MCS. The embodiments of the present application do not limit the specific interaction process for the MCS.

[0195] For example, R can be any of the following: 1 / 2, 2 / 3, 3 / 4, 5 / 6. Of course, as the standard progresses, the value of R can also have other values, which is not limited in the embodiments of the present application.

[0196] The embodiments of the present application do not limit the order in which the first communication device obtains the code length and code rate. After the first communication device obtains the code length and code rate, it can determine the matrix prototype of the corresponding check matrix based on the code length and code rate. Similarly, the order in which the first communication device obtains the information bit sequence and code length (or code rate) is also not limited.

[0197] 302. The first communication device performs LDPC encoding on the information bit sequence based on the check matrix to obtain an encoded sequence. The length of the encoded sequence is N1, where N1 is n times 1944, and n is an integer greater than or equal to 2.

[0198] The encoded sequence may include K information bits and E parity bits. Alternatively, the encoded sequence may consist of an information bit sequence and a parity bit sequence, where the length of the information bit sequence may be N2 and the length of the parity bit sequence may be E. N1 = N2 + E. The value of E is related to N1 and R. For example, if N1 = 3888 and R = 1 / 2, then E = 1944. For another example, if N1 = 3888 and R = 2 / 3, then E = 3888 * 1 / 3 = 1296. For another example, if N1 = 3888 and R = 3 / 4, then E = 3888 * 1 / 4 = 972. For another example, if N1 = 3888 and R = 5 / 6, then E = 3888 * 1 / 6 = 648.

[0199] The following introduces the matrix prototype of the check matrix involved in the embodiments of the present application.

[0200] The "-1" in the matrix prototype of the check matrix shown below represents a Z*Z all-zero matrix, "0" represents a Z*Z unit matrix, and a non-zero element represents the CPM of the Z*Z unit matrix. Of course, the "-1" in the matrix prototype can also be replaced by "-", which is not limited in this application. For the description of each parameter and the description of CPM, please refer to the above and will not be described in detail here. The "1" in Example 1, the "2" in Example 2, or the "3" in Example 3 below are to distinguish different examples and to facilitate subsequent references.

[0201] As an example 1, the matrix prototype of the check matrix may be shown in FIG4a. The description of FIG4b can be referred to below and will not be described in detail here.

[0202] As another example 2, the matrix prototype of the check matrix may be shown in FIG5a. For the description of FIG5b, please refer to the following text and will not be described in detail here.

[0203] As another example 3, the matrix prototype of the check matrix may be shown in FIG6a. The description of FIG6b can be referred to below and will not be described in detail here.

[0204] The R corresponding to the matrix prototype of the check matrix shown in Examples 1 to 3 above can be equal to 1 / 2. Simultaneously, the R corresponding to the check matrix is ​​also equal to 1 / 2. Exemplarily, the N1 corresponding to the matrix prototype of the check matrix shown in Examples 1 to 3 above can be equal to 3888. Simultaneously, the N1 corresponding to the check matrix is ​​also equal to 3888. Furthermore, the first communication device performs LDPC encoding using the check matrix corresponding to the matrix prototype shown in Examples 1 to 3, and the length of the obtained encoded sequence is 3888 bits.

[0205] Each non-negative integer (such as element i) in the matrix prototype of the check matrix shown in Examples 1 to 3 can be expanded to the CPM of the Z*Z unit matrix. The element i in Examples 1 to 3 can be expanded to a CPM, such as the CPM obtained by expanding the unit matrix by a circular shift of i bits to the right. For example, the element 0 in Examples 1 to 3 can be expanded to an 81*81 unit matrix, and the element i greater than 0 (such as i is greater than 0) can obtain a CPM of 81*81 based on a circular shift of i bits to the right of the unit matrix. For example, the element "57" in the matrix prototype can be expanded to the CPM of the 81*81 unit matrix, such as the CPM can be obtained by circularly shifting the 81*81 unit matrix to the right by 57 bits.

[0206] In the embodiments of the present application, the matrix prototype shown in Examples 1 to 3 includes 24 rows and 48 columns, and thus the check matrix after expansion based on the expansion factor Z may include 24*81 rows and 48*81 columns (i.e., 1944 rows and 3888 columns). Regarding how to expand the matrix prototype into a check matrix, reference may be made to the description of FIG1a or FIG1b, or to relevant standards or protocols, etc., which will not be described in detail here. The relevant description of the expansion factor Z here also applies to Examples 4 to 14 below and will not be repeated here.

[0207] For ease of description, the following text refers to the first X columns of the matrix prototype of the check matrix as the matrix corresponding to the information bits, or the information bit portion of the LDPC codeword, or the information bit portion of the matrix prototype, etc., and the last Y columns of the matrix prototype of the check matrix as the matrix corresponding to the check bits, or the check matrix, or the check bit portion of the LDPC codeword, or the check bit portion of the matrix prototype, etc. X and Y are both positive integers. For example, X = 48 * R. Y = 48 * (1-R). For the matrix prototypes shown in Examples 1 to 3, X = 24 and Y = 24.

[0208] As an example, K=3888*1 / 2=1944, that is, when the information bit sequence includes 1944 information bits, the encoded sequence may include 1944 information bits and 1944 check bits.

[0209] As another example, when K is less than 1944, that is, when the number of information bits included in the information bit sequence is less than 1944, the encoded sequence may include K information bits and 1944 check bits. Although the encoded sequence includes K information bits and 1944 check bits, the length of the encoded sequence is N1. As shown in Figure 18 below, since the number of information bits is less than 1944, the first communication device can obtain the information bit sequence by filling in a certain number of 0s before performing LDPC encoding, and then delete these 0s after completing LDPC encoding. Exemplarily, the number of 0s can be equal to 1944-K. For relevant instructions on the shortening operation, please refer to Figure 18, which will not be described in detail here.

[0210] As another example, when the number of information bits to be sent obtained before the first communication device obtains the information bit sequence is greater than 1944, the first communication device can perform codeword processing on the information bits before performing LDPC encoding. For example, after the codeword processing, multiple codewords (or blocks or segments, etc.) can be obtained, and the number of information bits carried by each codeword can be less than or equal to 1944. For the specific description of the codeword processing, reference can be made to relevant standards or protocols, etc., and the embodiments of the present application are not limited to this. Of course, after the first communication device performs the codeword processing, it can also be combined with a shortening operation, etc. The combination of the above-mentioned shortening operation and the codeword operation will not be described in detail here.

[0211] The relevant explanations here about different values ​​of K are also applicable to Examples 4 to 14 below and will not be repeated below.

[0212] As an example 4, the matrix prototype of the check matrix may be shown in FIG7a. The description of FIG7b can be referred to below and will not be described in detail here.

[0213] As another example 5, the matrix prototype of the check matrix may be shown in FIG8a. For the description of FIG8b, please refer to the following text and will not be described in detail here.

[0214] As another example 6, the matrix prototype of the check matrix may be shown in FIG9a. For the description of FIG9b, please refer to the following text and will not be described in detail here.

[0215] The R corresponding to the matrix prototype of the check matrix shown in Examples 4 to 6 above can be equal to 2 / 3. At the same time, the R corresponding to the check matrix is ​​also equal to 2 / 3. For example, the N1 corresponding to the matrix prototype of the check matrix shown in Examples 4 to 6 above can be equal to 3888. At the same time, the N1 corresponding to the check matrix is ​​also equal to 3888. The first communication device performs LDPC encoding using the check matrix corresponding to the matrix prototype shown in Examples 4 to 6, and the length of the obtained encoded sequence is 3888 bits.

[0216] For Examples 4 to 6, X = 48*2 / 3 = 32, and Y = 48*1 / 3 = 16. For the relevant description of X and Y, please refer to Examples 1 to 3 above, which will not be described in detail here.

[0217] For the description of the expansion factor, CPM, and K, please refer to Examples 1 to 3 above, which will not be described in detail here.

[0218] As an example 7, the matrix prototype of the check matrix may be shown in FIG10a. For the description of FIG10b, please refer to the following text and will not be described in detail here.

[0219] As another example 8, the matrix prototype of the check matrix may be shown in FIG11a. For the description of FIG11b, please refer to the following text and will not be described in detail here.

[0220] As another example 9, the matrix prototype of the check matrix may be shown in FIG12a. For the description of FIG12b, please refer to the following text and will not be described in detail here.

[0221] As another example 10, the matrix prototype of the check matrix may be shown in FIG13a. For the description of FIG13b, please refer to the following text and will not be described in detail here.

[0222] The R corresponding to the matrix prototype of the check matrix shown in Examples 7 to 10 above can be equal to 3 / 4. At the same time, the R corresponding to the check matrix is ​​also equal to 3 / 4. For example, the N1 corresponding to the matrix prototype of the check matrix shown in Examples 7 to 10 above can be equal to 3888. At the same time, the N1 corresponding to the check matrix is ​​also equal to 3888. The first communication device performs LDPC encoding using the check matrix corresponding to the matrix prototype shown in Examples 7 to 10, and the length of the obtained encoded sequence is 3888 bits.

[0223] For Examples 7 to 10, X = 48*3 / 4 = 36, and Y = 48*1 / 4 = 12. For the relevant descriptions of X and Y, please refer to Examples 1 to 3 above, which will not be described in detail here.

[0224] For the description of the expansion factor, CPM, and K, please refer to Examples 1 to 3 above, which will not be described in detail here.

[0225] As an example 11, the matrix prototype of the check matrix may be shown in FIG14a. For the description of FIG14b, please refer to the following text and will not be described in detail here.

[0226] As another example 12, the matrix prototype of the check matrix may be shown in FIG15a. For the description of FIG15b, please refer to the following text and will not be described in detail here.

[0227] As another example 13, the matrix prototype of the check matrix may be shown in FIG16a. For the description of FIG16b, please refer to the following text and will not be described in detail here.

[0228] As another example 14, the matrix prototype of the check matrix may be shown in FIG17a. For the description of FIG17b, please refer to the following text and will not be described in detail here.

[0229] The R corresponding to the matrix prototype of the check matrix shown in Examples 11 to 14 above can be equal to 5 / 6. At the same time, the R corresponding to the check matrix is ​​also equal to 5 / 6. For example, the N1 corresponding to the matrix prototype of the check matrix shown in Examples 11 to 14 above can be equal to 3888. At the same time, the N1 corresponding to the check matrix is ​​also equal to 3888. The first communication device performs LDPC encoding using the check matrix corresponding to the matrix prototype shown in Examples 7 to 10, and the length of the obtained encoded sequence is 3888 bits.

[0230] For Examples 11 to 14, X = 48*5 / 6 = 40, and Y = 48*1 / 6 = 8. For the relevant description of X and Y, please refer to Examples 1 to 3 above, which will not be described in detail here.

[0231] For the description of the expansion factor, CPM, and K, please refer to Examples 1 to 3 above, which will not be described in detail here.

[0232] The matrix prototypes of the check matrices shown in Examples 1 to 14 above are merely examples. The matrix prototypes of the check matrices shown in the embodiments of the present application can also be obtained by other matrix prototypes through the determination method shown below, which are not listed here one by one.

[0233] 303. The first communication device outputs the encoded sequence.

[0234] Exemplarily, the first communication device may perform LDPC encoding through an encoding module (e.g., an LDPC encoding module) to obtain an encoded sequence, and output the encoded sequence from the encoding module. For a description of the length of the encoded sequence, reference may be made to step 301 or step 302 above and will not be further described here.

[0235] In a possible implementation, the first communication device may further perform a shortening operation after outputting the encoded sequence, as illustrated below by an example.

[0236] Generally speaking, after being encoded, the information bit sequence needs to be placed into an integer number of orthogonal frequency division multiplexing (OFDM) symbols, and the encoded sequence also needs to be placed into an integer number of LDPC codewords. Therefore, before the first communication device performs LDPC encoding, the first communication device needs to first determine the minimum number of OFDM symbols N required for this transmission. SYM , then based on N SYM and the current coding and modulation scheme (such as the modulation order indicated by MCS, etc.) to calculate the total number of coded bits N that can be stored in all OFDM symbols TCB =N CBPS *N SYM , where N CBPS The number of encoded bits that can be stored in each OFDM symbol. Then, the first communication device can calculate the LDPC code length (i.e., the code length shown in the embodiment of the present application) used in the current transmission and the required number of codewords N based on the above results. CW. Exemplarily, when there are not enough information bits (such as the case where K is less than 1944 as shown in Examples 1 to 3 below) to fill the information bit part of the LDPC codeword, the first communication device can perform a shortening operation before performing LDPC encoding (also referred to as generating check bits). The shortening operation refers to filling a certain number of 0s in the information bits before generating check bits through LDPC encoding, and then deleting these 0s after encoding to generate check bits. Figure 18 is a partial schematic diagram of a shortening operation in an LDPC encoding provided by an embodiment of the present application. As shown in Figure 18, step 1801 indicates that the first communication device can obtain the payload bits (payload bits) to be encoded (such as the K information bits shown in the embodiment of the present application). Step 1802 indicates that the first communication device can calculate the LDPC code length and the number of codewords. Figure 18 exemplarily shows three LDPC codewords. The length of each LDPC codeword (i.e., code length) can be equal to the code length. Step 1803 indicates that the first communication device can perform a shortening operation on the information bits, and Figure 18 shows a codeword including payload bits and shortening zero bits. Step 1804 indicates that the first communication device can generate parity bits using payload bits and shortening bits, and Figure 18 shows a codeword including payload bits, shortening zero bits and parity bits. Step 1805 indicates that the first communication device discards these shortening zero bits, and Figure 18 shows a codeword including data bits and parity bits. The above-mentioned descriptions on shortening operations, etc. are only examples. For descriptions on shortening operations, etc., reference may also be made to relevant standards or protocols, etc., and the embodiments of the present application are not limited thereto.

[0237] 304. The first communication device sends a signal corresponding to the encoded sequence, and the second communication device receives the signal.

[0238] The signal corresponding to the encoded sequence refers to the encoded sequence output from the encoding module. The encoded sequence may be further processed to form a processed signal transmitted by the first communication device through a channel.

[0239] Exemplarily, the first communication device may perform rate matching on the encoded sequence, and the rate matching method may include puncturing, repetition, and shortening. For example, the first communication device may puncture the check bits in the encoded sequence to obtain a higher code rate or a shorter code length. Exemplarily, the first communication device may also perform at least one of the following processing on the encoded sequence: stream parsing, constellation mapping, LDPC subcarrier mapping, stream cyclic shift, space and frequency mapping, inverse discrete Fourier transform (IDFT), insertion of cyclic prefix and windowing (insertGI andwindow). Exemplarily, after receiving a signal transmitted through a channel, the second communication device may perform corresponding processing on the signal. For example, before obtaining the information to be decoded, the second communication device may perform at least one of the following processing: removal of cyclic prefix, discrete Fourier transform (DFT), space and frequency demapping, deinterleaving, and deconstellation.

[0240] For other processing of the encoded sequence by the first communication device and the corresponding processing before the second communication device obtains the information to be decoded, reference may be made to relevant standards or protocols, etc., and the embodiments of the present application do not limit this.

[0241] 305. The second communication device performs LDPC decoding on the information to be decoded based on the check matrix to obtain an information bit sequence.

[0242] The length of the information to be decoded may be N1. For example, the information to be decoded may include bits or real numbers, and the specific content of the information to be decoded is not limited in this embodiment of the present application. For example, before obtaining the information to be decoded, the second communication device may supplement shortening bits, such as by combining the code length and K to supplement shortening bits, or supplement puncturing bits, etc., which is not limited in this embodiment of the present application.

[0243] Exemplarily, the decoding method that can be adopted by the second communication device includes but is not limited to a hard decision decoding method, a soft decision decoding method, or a hybrid decoding method. The specific decoding process is not described in detail in the embodiment of the present application.

[0244] For example, the second communication device may also use a method similar to that shown in FIG18 to determine the code length N1, etc. For the relevant description of how the second communication device obtains the code length N1 and the code rate R, please refer to the above description of the first communication device and will not be described in detail here. The method for the first communication device to obtain N1 and R, and the method for the second communication device to obtain N1 and R, may refer to relevant standards or protocols, etc., and the embodiments of the present application are not limited to this.

[0245] In an embodiment of the present application, the above steps 302 to 303 can be implemented by an encoding module, and the above step 305 can be implemented by a decoding module. In a specific implementation, the method shown in Figure 3 can also be split into an encoding method or a decoding method. If the encoding method can include steps 302 to 303, or includes steps 301 to 303, the first communication device can include an encoding module. If the decoding method can include step 305, the second communication device can include a decoding module. Optionally, in addition to including the above-mentioned encoding module, the first communication device can also include an acquisition module, which can be used to obtain code length and code rate, etc. Optionally, the first communication device can also include a shortening module or a blocking module, etc. Optionally, in addition to including a decoding module, the second communication device can also include an acquisition module, which can be used to obtain information to be decoded.

[0246] In an embodiment of the present application, the check matrix can be applied to an information bit sequence whose code length is n times 1944, where n is an integer greater than or equal to 2, thereby improving the transmission reliability of the system and improving the decoding performance.

[0247] The following describes a method for determining a check matrix according to an embodiment of the present application.

[0248] The method for determining the check matrix shown in the embodiment of the present application is only an example. In a specific implementation, the determination method shown below can be defined by a standard. Alternatively, in a specific implementation, the communicating parties may not perform the determination method shown below. For example, the communicating parties may save the matrix prototype of the check matrix, or save the extended indicator matrix (or referred to as the accompanying extended indicator matrix, etc.). The matrix prototypes of the 14 check matrices shown above can be obtained by the determination method shown below. Although the matrix prototypes of 14 check matrices are shown above by way of example, the matrix prototypes of other check matrices determined according to the determination method shown in the embodiment of the present application also fall within the scope of protection of the embodiment of the present application.

[0249] The determination method shown below is illustrated by taking the basic check matrix as code length N0=1944 as an example. As shown in step 301 above, N1 can also be m times of 1296, that is, according to the determination method shown below, the check matrix with a code length greater than 1944 can also be determined based on the check matrix corresponding to the code length of 1296. According to the determination method shown below, the check matrix with a code length greater than 1944 determined by taking the check matrix corresponding to the code length of 1296 as the basic check matrix also falls within the protection scope of the embodiment of the present application. The following takes the matrix prototype of the basic check matrix as shown in Figure 1a as an example to illustrate the method for determining the matrix prototype of the check matrix shown in the embodiment of the present application. Of course, the name of the basic check matrix shown in the embodiment of the present application is only an example. For example, the basic check matrix can also be called a reference check matrix, a benchmark check matrix, or an original check matrix.

[0250] To reuse the original WLAN LDPC code encoding and decoding architecture as much as possible, the embodiments of the present application respectively expand the existing WLAN system LDPC codes with a code length of 1944 bits at different code rates as the basic matrix, thereby obtaining LDPC code check matrices with a code length of 3888 bits for the corresponding code rate. Among them, in the matrix prototypes of the four check matrices with the original code length of 1944 bits (shown in Figure 1a), the CPM size of each element is 81. The CPM size of each element in the matrix prototype of the LDPC code check matrix with a code length of 3888 bits shown in the embodiment of the present application is also 81. However, the matrix prototype size of the check matrix shown in the embodiment of the present application is twice the matrix prototype size of the basic check matrix. The following is a detailed description.

[0251] Explanation of the basic check matrix:

[0252] The code length N0 of the basic check matrix is ​​1944, and the code rates include 1 / 2, 2 / 3, 3 / 4, and 5 / 6. The expansion factor Z of the basic check matrix is ​​1944 / 24=81.

[0253] When R=1 / 2, the matrix prototype of the basic check matrix is ​​a matrix of size 12*24, that is, the matrix prototype of the basic check matrix includes 12 rows and 24 columns. The basic check matrix expanded based on this matrix prototype includes 972 rows and 1944 columns. X=12, Y=12.

[0254] When R=2 / 3, the matrix prototype of the basic check matrix is ​​a matrix of size 8*24, that is, the matrix prototype of the basic check matrix includes 8 rows and 24 columns. The basic check matrix expanded based on this matrix prototype can include 648 rows and 1944 columns. X=16, Y=8.

[0255] When R=3 / 4, the matrix prototype of the basic check matrix is ​​a 6*24 matrix, that is, the matrix prototype of the basic check matrix includes 6 rows and 24 columns. The basic check matrix expanded based on this matrix prototype can include 648 rows and 1944 columns. X=18, Y=6.

[0256] When R=5 / 6, the matrix prototype of the basic check matrix is ​​a 4*24 matrix, that is, the matrix prototype of the basic check matrix includes 4 rows and 24 columns. The basic check matrix expanded based on this matrix prototype can include 324 rows and 1944 columns. X=20, Y=4.

[0257] Explanation of the check matrix:

[0258] The code length of the check matrix is ​​N1=3888, and the code rates include: 1 / 2, 2 / 3, 3 / 4, and 5 / 6. The expansion factor of the check matrix is ​​Z=3888 / 48=81.

[0259] When R=1 / 2, the matrix prototype of the check matrix is ​​a 24*48 matrix, that is, the matrix prototype of the check matrix includes 24 rows and 48 columns. The check matrix expanded based on the matrix prototype includes 1944 rows and 3888 columns. X=24, Y=24.

[0260] When R=2 / 3, the matrix prototype of the check matrix is ​​a matrix of size 16*48, that is, the matrix prototype of the check matrix includes 16 rows and 48 columns. The check matrix expanded based on the matrix prototype includes 1296 rows and 3888 columns. X=32, Y=16.

[0261] When R=3 / 4, the matrix prototype of the check matrix is ​​a matrix of size 12*48, that is, the matrix prototype of the check matrix includes 12 rows and 48 columns. The check matrix expanded based on the matrix prototype includes 972 rows and 3888 columns. X=36, Y=12.

[0262] When R=5 / 6, the matrix prototype of the check matrix is ​​a matrix of size 8*48, that is, the matrix prototype of the check matrix includes 8 rows and 48 columns. The check matrix expanded based on the matrix prototype includes 648 rows and 3888 columns. X=40, Y=8.

[0263] In an embodiment of the present application, the check matrix can be obtained by performing diagonal expansion or anti-diagonal expansion on the elements of the xth row and yth column in the matrix prototype of the basic check matrix. The code length N0 corresponding to the basic check matrix is ​​less than or equal to 1944, and the code rate corresponding to the basic check matrix is ​​the same as the code rate corresponding to the check matrix. The xth row and yth column element is greater than or equal to 0. By performing diagonal expansion or anti-diagonal expansion on each item in the basic check matrix to obtain the check matrix, various modules in the LDPC coding architecture with a code length of 1944 bits can be effectively reused. The following is a detailed description.

[0264] For example, if the element i in the matrix prototype of the basic check matrix is ​​row x and column y, then diagonally expanding i yields the matrix shown in Figure 19a, and anti-diagonally expanding i yields the matrix shown in Figure 19b. i can be an integer greater than or equal to 0. For another example, if the element in row x and column j of the matrix prototype of the basic check matrix is ​​"-1" or "-", the element at the corresponding position in the check matrix can still be "-1" or "-". Thus, element i in the matrix prototype of the basic check matrix can be diagonally expanded or anti-diagonally expanded, such that each element can be expanded into a 2*2 square matrix. The non-negative elements in the square matrix can represent the CPM of the Z*Z identity matrix (e.g., 0 in the square matrix can represent the Z*Z identity matrix, and elements greater than 0 can represent the CPM of the Z*Z identity matrix). The blank spaces in Figures 19a and 19b do not show "-1" (or "-"). "-1" in the square matrix can represent a Z*Z all-zero square matrix.

[0265] Taking (d) R=5 / 6 in Figure 1a as an example, the Z of the basic check matrix is ​​81, and the matrix prototype size of the basic check matrix is ​​4 rows and 24 columns. After diagonally or anti-diagonally expanding element i in the basic check matrix, the Z of the check matrix remains equal to 81, that is, the expansion factor of the basic check matrix remains unchanged. If element i is expanded to a 2*2 square matrix, the matrix prototype size of the check matrix is ​​8 rows and 48 columns, and the code rate of the check matrix is ​​still equal to 5 / 6, so the code length can be equal to 1944*2=3888. Of course, the expansion of element i in the matrix prototype of the basic check matrix shown in the embodiment of the present application to a 2*2 square matrix is ​​only an example. For example, element i can also be expanded to a 3*3 square matrix, or to a 4*4 square matrix, etc., which are not listed here one by one. In this case, the code length of the expanded check matrix can be longer. For example, when element i in the matrix prototype of the basic check matrix is ​​expanded to a 3*3 square matrix, the corresponding code length of the check matrix can be 24*3*81=5382. For example, when the element i in the matrix prototype of the basic check matrix is ​​expanded to a 4*4 square matrix, the code length corresponding to the check matrix can be 24*4*81=7776. These are not listed here one by one.

[0266] In the embodiment of the present application, element i in the matrix prototype of the basic check matrix can be diagonally expanded or anti-diagonally expanded. This does not mean that every element in the matrix prototype of the basic check matrix is ​​diagonally expanded or anti-diagonally expanded. Instead, the first part of the elements in the matrix prototype of the basic check matrix that are greater than or equal to 0 are diagonally expanded, and the second part of the elements that are greater than or equal to 0 are anti-diagonally expanded. The matrix corresponding to the information bits in the matrix prototype of the check matrix is ​​obtained by diagonally expanding or anti-diagonally expanding the elements in the xth row and yth column of the matrix corresponding to the information bits in the matrix prototype of the basic check matrix. That is, the information bit portion of the matrix prototype of the check matrix can be obtained by diagonally expanding the first part of the elements in the information bit portion of the matrix prototype of the basic check matrix that are greater than or equal to 0 and anti-diagonally expanding the second part of the elements that are greater than or equal to 0.

[0267] Furthermore, the first and second columns of the matrix corresponding to the check bits in the matrix prototype of the check matrix are obtained by diagonally expanding or anti-diagonally expanding the first and last elements of the first column of the matrix corresponding to the check bits in the matrix prototype of the basic check matrix. In other words, the first and second columns of the check bit portion of the matrix prototype of the check matrix can be obtained by diagonally expanding or anti-diagonally expanding the first element (e.g., element 1) or the last element (e.g., element 1) in the first column of the check bit portion of the matrix prototype of the basic check matrix. That is, the first and last elements of the first column of the last Y columns of the matrix prototype of the basic check matrix are expanded in the same manner.

[0268] For example, after the first row and first row elements of the last Y columns and the last row elements of the first column in the matrix prototype of the basic check matrix are both diagonally expanded (or anti-diagonally expanded), the first row and first row elements of the first column, the second row elements of the first column, the first row elements of the second column, the second row elements of the second column, as well as the last row elements of the first column, the second-to-last row elements of the first column, the last row elements of the second column, and the second-to-last row elements of the second column in the matrix prototype of the check matrix are obtained. For example, the first row and first row elements of the last Y columns in the extended indicator matrix are the same as the last row elements of the first column. Taking Figure 13b as an example, Y=6, that is, the first row and first row elements of the last 6 columns in the extended indicator matrix are 0, and the last row elements of the first column are also 0, as shown in Figure 13c. Similarly, in Figure 14b, the first row and first row elements of the last columns in the extended indicator matrix are 1, and the last row elements of the first column are also 1. And so on, I will not go into details here.

[0269] Illustratively, the element 0 in the first column of the check bit part in the matrix prototype of the basic check matrix can be diagonally expanded or anti-diagonally expanded to obtain the element at the corresponding position in the matrix prototype of the check matrix.

[0270] Generally speaking, the first column of the parity bit portion of the matrix prototype of the basic parity check matrix has a "1-0-1" structure, that is, the first and last rows of the column from top to bottom are both 1, and the remaining rows are all 0. Therefore, to maintain the original WLAN LDPC fast and efficient coding algorithm, the embodiment of the present application maintains a similar structure of the parity bit portion, such as the first row and the last row of elements in the last Y columns of the extended indicator matrix are both 0 or both 1. This ensures a fast and efficient LDPC code coding algorithm.

[0271] Furthermore, the elements in the matrix prototype of the check matrix corresponding to the check bits, except for the first and second columns, are obtained by diagonally expanding all the elements 0 in the matrix prototype of the basic check matrix corresponding to the check bits, except for the first column. The elements (such as 0) in the check bit portion of the matrix prototype of the basic check matrix, except for "-1" (or "-"), can all be diagonally expanded. For example, the elements 0 in the check bit portion of the matrix prototype in FIG1a are diagonally expanded, and the elements 1 in the first column of the check bit portion are all diagonally expanded (or anti-diagonally expanded), thereby obtaining the check bit portion of the matrix prototype of the check matrix.

[0272] That is to say, the first and second columns of the check bit portion in the matrix prototype of the check matrix can be obtained by diagonally expanding or anti-diagonally expanding the first and last elements in the first column of the check bit portion in the matrix prototype of the basic check matrix, and the remaining columns of the check bit portion in the matrix prototype of the check matrix can be obtained by diagonally expanding the elements 0 in the check bit portion of the matrix prototype of the basic check matrix except the first column. Thus, as an example, the expansion method of the elements in the check bit portion in the matrix prototype of the basic check matrix may be the same. As shown in Figure 4a, the check bit portion in the matrix prototype of the check matrix can be obtained by diagonally expanding the elements of the check bit portion in the matrix prototype of the basic check matrix. As another example, the expansion method of the elements in the check bit portion in the matrix prototype of the basic check matrix may not be exactly the same. As shown in FIG8b , the parity bit portion of the matrix prototype of the parity check matrix can be obtained by anti-diagonally extending the first and last elements in the first column of the parity bit portion of the matrix prototype of the basic parity check matrix, and diagonally extending all elements 0 in the parity bit portion except the first and last elements in the first column. A detailed description is omitted here.

[0273] The matrix prototype of the check matrix shown above can be obtained by correspondingly expanding the elements in the matrix prototype of the basic check matrix. The expansion mode of each element shown above can also be represented by an expansion indicator matrix. Exemplarily, the matrix prototype of the check matrix can be determined based on the matrix prototype of the basic check matrix and the expansion indicator matrix. Alternatively, the relationship between the matrix prototype of the basic check matrix and the matrix prototype of the check matrix can be represented by the expansion indicator matrix.

[0274] The size of the extended indicator matrix is ​​the same as the size of the matrix prototype of the basic check matrix. For example, the element in the xth row and yth column of the extended indicator matrix is ​​used to indicate that the square matrix at the corresponding position in the matrix prototype of the check matrix is ​​obtained by performing diagonal expansion or anti-diagonal expansion on the element in the xth row and yth column of the matrix prototype of the basic check matrix. For another example, the element in the xth row and yth column of the extended indicator matrix can be used to indicate that the element at the corresponding position in the matrix prototype of the check matrix is ​​obtained by performing the following operations on the xth row and jth column of the matrix prototype of the basic check matrix: diagonal expansion, anti-diagonal expansion, and remaining unchanged.

[0275] For example, if the element in the extended indicator matrix at row x and column j is element j, then the element j can be equal to 0, 1, or "-1" (or can be replaced by "-"). Among them, j=0 can indicate that the element at the corresponding position in the matrix prototype of the check matrix is ​​obtained by diagonally extending the element in row x and column j of the matrix prototype of the basic check matrix. j=1 can indicate that the element at the corresponding position in the matrix prototype of the check matrix is ​​obtained by anti-diagonally extending the element in row x and column j of the matrix prototype of the basic check matrix. j=-1 can indicate that the element in row x and column j of the matrix prototype of the basic check matrix (i.e., "-1" or "-") is expanded to a 2*2 all-zero square matrix, or j=-1 can indicate that the element in the matrix prototype of the check matrix is ​​still the same as the element in row x and column j of the matrix prototype of the basic check matrix, i.e., "-1" (or understood as not being expanded, or understood as remaining unchanged). The relationship between the value of j and its meaning shown here is only an example. In specific implementations, other numerical values ​​can also be used to express the above meanings, which are not listed here one by one.

[0276] For the code rate R = 1 / 2, the following description is given:

[0277] As an example, the matrix prototype of the check matrix shown in FIG4a may be determined based on the extended indicator matrix shown in FIG4b and the matrix (a) shown in FIG1a (ie, R=1 / 2).

[0278] For example, if the element in row 1 and column 1 of matrix (a) shown in FIG1a is 57, and the element in row 1 and column 1 of the extended indicator matrix shown in FIG4b is 1, then the elements in row 1 and column 1, row 1 and column 2, row 2 and column 1, and row 2 and column 2 of the matrix prototype of the check matrix are obtained by anti-diagonal expansion of element 57. That is, the element in row 1 and column 1 of the matrix prototype of the check matrix is ​​"-1", the element in row 1 and column 2 is 57, the element in row 2 and column 1 is 57, and the element in row 2 and column 2 is "-1".

[0279] For another example, if the element in the 1st row and 2nd column of the matrix (a) shown in Figure 1a is "-1", then the element in the 1st row and 2nd column of the extended indicator matrix shown in Figure 4b is still "-1", and the element in the 1st row and 3rd column, the element in the 1st row and 4th column, the element in the 2nd row and 3rd column, and the element in the 2nd row and 4th column of the matrix prototype of the check matrix remain unchanged, that is, they are still "-1".

[0280] For another example, if the element in the 3rd row and 1st column of the matrix (a) shown in FIG1a is 30, and the element in the 3rd row and 1st column of the extended indicator matrix shown in FIG4b is 0, then the element in the 5th row and 1st column, the element in the 5th row and 2nd column, the element in the 6th row and 1st column, and the element in the 6th row and 2nd column of the matrix prototype of the check matrix are obtained by diagonally extending the element 30. That is, the element in the 5th row and 1st column of the matrix prototype of the check matrix is ​​30, the element in the 5th row and 2nd column is "-1", the element in the 6th row and 1st column is "-1", and the element in the 6th row and 2nd column is 30.

[0281] Descriptions of other elements in the matrix prototype of the basic check matrix, other elements in the extended indicator matrix, and elements in the matrix prototype of the check matrix are not listed here one by one.

[0282] As another example, the matrix prototype of the check matrix shown in FIG5a may be determined based on the extended indicator matrix shown in FIG5b and the matrix (a) shown in FIG1a (ie, R=1 / 2).

[0283] As another example, the matrix prototype of the check matrix shown in FIG6a may be determined based on the extended indicator matrix shown in FIG6b and the matrix (a) shown in FIG1a (ie, R=1 / 2).

[0284] For the bit rate R = 2 / 3, the following description is given:

[0285] As an example, the matrix prototype of the check matrix shown in FIG7a may be determined based on the extended indicator matrix shown in FIG7b and the matrix (b) shown in FIG1a (ie, R=2 / 3).

[0286] As another example, the matrix prototype of the check matrix shown in FIG8a may be determined based on the extended indicator matrix shown in FIG8b and the matrix (b) shown in FIG1a (ie, R=2 / 3).

[0287] As yet another example, the matrix prototype of the check matrix shown in FIG9a may be determined based on the extended indicator matrix shown in FIG9b and the matrix (b) shown in FIG1a (ie, R=2 / 3).

[0288] For the bit rate R = 3 / 4, the following description is given:

[0289] As an example, the matrix prototype of the check matrix shown in FIG10a may be determined based on the extended indicator matrix shown in FIG10b and the matrix (c) shown in FIG1a (ie, R=3 / 4).

[0290] As another example, the matrix prototype of the check matrix shown in FIG. 11 a may be determined based on the extended indicator matrix shown in FIG. 11 b and the matrix (c) shown in FIG. 1 a (ie, R=3 / 4).

[0291] As yet another example, the matrix prototype of the check matrix shown in FIG12a may be determined based on the extended indicator matrix shown in FIG12b and the matrix (c) shown in FIG1a (ie, R=3 / 4).

[0292] As yet another example, the matrix prototype of the check matrix shown in FIG13a may be determined based on the extended indicator matrix shown in FIG13b and the matrix (c) shown in FIG1a (ie, R=3 / 4).

[0293] For the bit rate R = 5 / 6, the following description is given:

[0294] As an example, the matrix prototype of the check matrix shown in FIG14a may be determined based on the extended indicator matrix shown in FIG14b and the matrix (d) shown in FIG1a (ie, R=5 / 6).

[0295] As another example, the matrix prototype of the check matrix shown in FIG15a may be determined based on the extended indicator matrix shown in FIG15b and the matrix (d) shown in FIG1a (ie, R=5 / 6).

[0296] As yet another example, the matrix prototype of the check matrix shown in FIG16a may be determined based on the extended indicator matrix shown in FIG16b and the matrix (d) shown in FIG1a (ie, R=5 / 6).

[0297] As yet another example, the matrix prototype of the check matrix shown in FIG17a may be determined based on the extended indicator matrix shown in FIG17b and the matrix (d) shown in FIG1a (ie, R=5 / 6).

[0298] As an example, both communicating parties (e.g., a first communication device and a second communication device) store the elements of a matrix prototype of a check matrix. For example, by storing the elements of the matrix prototype of the check matrix, when the code length is 3888 bits, both communicating parties can directly obtain the check matrix based on the stored elements and the expansion factor. For another example, by storing the elements of the matrix prototype of the check matrix, when the code length is 1944 bits, both communicating parties can obtain the basic check matrix based on the above-described expansion method. In other words, by storing the elements of the matrix prototype of the check matrix (or referred to as the CPM coefficients or cyclic shift values, etc.), both communicating parties can obtain LDPC codes of two code lengths, saving storage space. As another example, both communicating parties can also store the basic check matrix and the extended indicator matrix. For example, when the code length is 3888 bits, both communicating parties can obtain the matrix prototype of the check matrix based on the matrix prototype of the basic check matrix and the extended indicator matrix.

[0299] The above description uses a matrix format to indicate the expansion method of each element in the matrix prototype of the basic check matrix. However, the matrix format shown above is only an example. In specific implementations, other variations of the expansion indicator matrix can also be made. For example, a bitmap format can be used to indicate the expansion method of each element in the matrix prototype of the basic check matrix. For example, the length of the bitmap can be equal to the number of elements greater than or equal to 0 in the matrix prototype of the basic check matrix. Another example is a table format to indicate the expansion method of each element in the matrix prototype of the basic check matrix, and so on. These are not listed here one by one.

[0300] The matrix prototype (or check matrix) of the check matrix obtained based on the above determination method falls within the protection scope of the embodiments of this application. In addition, combining the above method and the tree structure can also effectively screen out check matrices with better decoding performance, further improving the decoding performance of the check matrix.

[0301] Each element in the matrix prototype of the basic check matrix can be expanded in either diagonal or anti-diagonal ways, i.e., diagonal (Opt A) or anti-diagonal (Opt B). The small squares in Figure 20a represent element values ​​in the matrix prototype of the basic check matrix. Option A (Opt A) represents the square matrix after diagonal expansion of the element value, and Option B (Opt B) represents the square matrix after anti-diagonal expansion of the element value.

[0302] The above-mentioned element values ​​specifically select OptA or OptB to expand the nodes to be selected according to the number, and select the expansion method with deeper depth. The specific tree expansion schematic diagram is shown in Figure 20b, where the circle represents the variable node and the square represents the check node. The deeper the depth of the expanded tree, the fewer short rings the corresponding matrix obtained contains, and the short rings have a negative impact on decoding performance. For each variable node, the corresponding depth of each Opt A or Opt B in the corresponding matrix may be different, and the ring structure caused by it in the corresponding factor graph (tanner graph) of the overall check matrix will also be different. Therefore, the embodiment of the present application comprehensively considers the local and overall ring structure of the matrix, and designs all non-zero elements according to the tree expansion to ensure that the factor graph corresponding to the check matrix has a better ring structure.

[0303] Combined with the determination method and tree structure shown above, it can be effectively ensured that the check matrix provided in the embodiment of the present application can maintain the fast and efficient encoding method of the original WLAN LDPC code and improve the decoding performance.

[0304] The following describes the simulation results of the check matrix provided in the embodiments of the present application.

[0305] The following is a performance comparison of the above-mentioned check matrix and the basic check matrix. In Figures 21a to 21d, the horizontal axis represents the signal-to-noise ratio (SNR) in dB, and the vertical axis represents the block error rate (BLER). The decoding method used is a soft decision decoding method, such as the brief propagation (BP) algorithm, and the number of decoding iterations is 8. The serial numbers 1 to 4 in Figures 21a to 21d are set to facilitate the distinction between different curves and should not be understood as limiting the embodiments of the present application.

[0306] FIG21a shows a performance comparison between a parity check matrix with a code length of 3888 and a basic parity check matrix with a code length of 1944. R=1 / 2.

[0307] FIG21 b shows the performance comparison of the parity check matrix of code length 3888 and the basic parity check matrix of code length 1944. R=2 / 3.

[0308] Figure 21c shows the performance comparison between the parity check matrix of code length 3888 and the basic parity check matrix of code length 1944.

[0309] FIG21d shows the performance comparison between the parity check matrix of code length 3888 and the basic parity check matrix of code length 1944. R=5 / 6.

[0310] From the above, it can be seen that under the same SNR, the BLER corresponding to the check matrix is ​​lower, so the decoding performance of the check matrix is ​​better. Therefore, the various check matrices provided in the embodiments of the present application can achieve significant decoding performance improvements, while achieving a good compromise between decoding performance and complexity.

[0311] In an embodiment of the present application, in the matrix prototype of the check matrix of the designed LDPC code, the influence of columns of different column weights participating in small rings (or also called short rings) on the final performance is different. For example, if a small ring is formed between columns of small column weight (for example, a column weight of 2 or 3), the deterioration of performance is more serious than the deterioration of performance caused by the small ring formed between columns of large column weight. Small column weight and large column weight are relative. For example, small column weight refers to a column weight less than or equal to a first value, and large column weight refers to a column weight greater than or equal to a second value. The first value may be equal to the second value, or the first value may be less than the second value. The embodiment of the present application does not limit the specific values ​​of the first value and the second value.

[0312] Therefore, it is possible to prioritize avoiding the presence of small rings between columns with small column weights. In the embodiment of the present application, the basic check matrix can be extended and designed according to different column weights; or, the basic check matrix can be extended and designed according to different column weight groups. In other words, the regions with the same column weight in the basic check matrix can be preferentially extended and designed, that is, the extended indicator matrix corresponding to the regions with the same column weight can be preferentially designed. The extended indicator matrix designed in the embodiment of the present application can be designed according to different column weights, or designed according to different column weight groups.

[0313] Figure 25 is a schematic diagram of the matrix prototype group design of the basic check matrix provided by an embodiment of the present application. Figure 25 exemplarily shows a schematic diagram of the matrix prototype group design of the basic check matrix when the code rate R = 5 / 6 and N = 1944. As shown in Figure 25, the design of the matrix prototype of the LDPC basic check matrix when the code rate R = 5 / 6 and N = 1944 can be divided into 3 groups according to the column weight, and then each group is optimized and designed in turn according to the priority. For example, first, for the area corresponding to the highest priority short loop optimization, the extended indicator matrix corresponding to the area can be designed first (such as the column weight is 2), and the performance of the area is given priority. Secondly, for the area corresponding to the second highest priority short loop optimization, the extended indicator matrix corresponding to the area can be optimized (such as the column weight is 3). Finally, the area corresponding to the low priority short loop optimization (such as the column weight is 4) is optimized. Figure 25 exemplarily shows the case of R = 5 / 6. For other code rates, the extended indicator matrix can also be designed according to the column weight. The optimization method for regrouping by column or by region is similar to the above example. Each grouping region can also be designed according to the optimization priority of the small ring. It will not be listed here one by one. The above column regrouping is shown as an example based on the number of non-"-1" in a column.

[0314] In the method for designing an LDPC check matrix or an extended indicator matrix shown above, the extended indicator matrix corresponding to the columns of the same column weight can fall within the scope of protection of the embodiments of the present application. That is, according to the above design method, the extended indicator matrix corresponding to one or more grouping regions also falls within the scope of protection of the embodiments of the present application, and this principle applies to all embodiments of the present application. The extended indicator matrix shown in the embodiments of the present application can also be called an extended pattern. For example, taking Figure 25 as an example, the extended indicator matrix (or called the first part extended indicator matrix) corresponding to the above-mentioned highest priority short loop optimization and the matrix prototype of the check matrix (or called the first part matrix prototype) can fall within the scope of protection of the embodiments of the present application. The extended indicator matrix (or called the second part extended indicator matrix) and the matrix prototype of the check matrix (or called the second part matrix prototype) corresponding to the above-mentioned second-highest priority short loop optimization also fall within the scope of protection of the embodiments of the present application. The extended indicator matrix (or called the third part extended indicator matrix) and the matrix prototype of the check matrix (or called the third part matrix prototype) corresponding to the above-mentioned low priority short loop optimization also fall within the scope of protection of the embodiments of the present application. Similarly, the matrix prototypes of the extended indicator matrix and the check matrix corresponding to all the areas shown in Figure 25 also fall within the protection scope of the embodiments of the present application.

[0315] In the extended indicator matrix, inverting all or some of the columns of the remaining matrices, excluding the matrix corresponding to the check matrix, also falls within the scope of protection of the embodiments of the present application. That is, in the extended indicator matrix, inverting all or some of the columns of the matrix corresponding to the information bit portion also falls within the scope of protection of the embodiments of the present application. For ease of description, the remaining matrix region of the extended indicator matrix, excluding the matrix corresponding to the check matrix, is referred to as the information portion matrix or the system portion matrix. Due to the structural characteristics of the matrix prototype of the 11n LDPC check matrix, the structure of its check matrix is ​​fixed and includes a dual diagonal structure. Therefore, to achieve fast coding, the matrix corresponding to the check matrix in the extended indicator matrix does not need to be inverted. The embodiments of the present application do not limit whether the matrix corresponding to the check matrix is ​​inverted.

[0316] In the embodiment of the present application, the matrix obtained by performing column permutation or row permutation on the matrix prototype of the check matrix also falls within the protection scope of the embodiment of the present application. That is, after performing column permutation or row permutation on the matrix prototype of each check matrix shown in the present application, or after performing row permutation and column permutation at the same time, the matrix prototype of the check matrix can also be obtained. The performance of the matrix prototype before permutation is the same as that of the matrix prototype after permutation. The method for determining the extended indicator matrix or the method for determining the matrix prototype of the check matrix shown in the embodiment of the present application also falls within the protection scope of the embodiment of the present application. Since the matrix prototype of the check matrix has the changes as described above, each matrix prototype is listed one by one in the embodiment of the present application, so the deformation of all or part of the matrix of the various LDPC matrices as described above is also within the protection scope of the present application.

[0317] Figures 26a and 26b are schematic diagrams of an extended indicator matrix provided by an embodiment of the present application. For the matrix prototype of the LDPC check matrix with code rate R=5 / 6 and N=1944 shown in Figure 25, an embodiment of the present application shows an extended indicator matrix.

[0318] The extended indicator matrix shown in Figure 26b is obtained by inverting the information part matrix of the extended indicator matrix shown in Figure 26a. The specific inversion method is: the "1" in the information part matrix of the extended indicator matrix is ​​inverted to "0", the "0" is inverted to "1", and the "-1" remains unchanged. At the same time, the 4x4 check matrix on the far right remains unchanged. Since the ring length distribution of each variable node corresponding to the check matrix obtained by inverting the information part matrix according to the above method is the same as the check matrix obtained by the expansion before inversion, these two expansion methods can be considered equivalent under the principle of optimizing the ring length distribution.

[0319] That is to say, the matrix prototypes or check matrices of all extended indicator matrices or check matrices given in the embodiments of the present application, the extended indicator matrix obtained after the corresponding information part matrix is ​​inverted (such as "1" is inverted to "0", "0" is inverted to "1", and "-1" remains unchanged), and the matrix prototype of the check matrix obtained based on the extended indicator matrix, and the check matrix obtained based on the extended indicator matrix all fall within the protection scope of the embodiments of the present application.

[0320] In addition to the matrix prototypes and extended indicator matrices for each check matrix shown above, embodiments of the present application also provide the following matrices. The R corresponding to the matrix prototypes of the check matrix shown below is the same as the R corresponding to the check matrix. For example, the N1 corresponding to the matrix prototypes of the check matrix shown below can be equal to 3888. At the same time, the N1 corresponding to the check matrix is ​​also equal to 3888. For explanations of R and N1, etc., please refer to the above and will not be detailed here.

[0321] For the code rate R = 1 / 2, the following description is given:

[0322] As an example, the matrix prototype of the check matrix may be as shown in Figure 27a. The matrix prototype of the check matrix shown in Figure 27a may be determined based on the extended indicator matrix shown in Figure 27b and the matrix (a) shown in Figure 1a (ie, R=1 / 2).

[0323] As another example, the matrix prototype of the check matrix may be as shown in Figure 28a. The matrix prototype of the check matrix shown in Figure 28a may be determined based on the extended indicator matrix shown in Figure 28b and the matrix (a) shown in Figure 1a (ie, R=1 / 2).

[0324] The extended indicator matrix shown in Figure 28b is obtained by negating the information part matrix in the extended indicator matrix shown in Figure 27b. Figures 27b and 28b exemplarily illustrate the extended indicator matrix after negating the information part matrix in the extended indicator matrix, and Figures 27a and 28a exemplarily illustrate the matrix prototype of the check matrix corresponding to the negated extended indicator matrix. For the sake of brevity, the extended indicator matrix after negating the information part matrix in the extended indicator matrix is ​​not shown below.

[0325] As another example, the matrix prototype of the check matrix may be as shown in Figure 29a. The matrix prototype of the check matrix shown in Figure 29a may be determined based on the extended indicator matrix shown in Figure 29b and the matrix (a) shown in Figure 1a (ie, R=1 / 2).

[0326] For the bit rate R = 2 / 3, the following description is given:

[0327] As an example, the matrix prototype of the check matrix can be shown in Figure 30a. The matrix prototype of the check matrix shown in Figure 30a can be determined based on the extended indicator matrix shown in Figure 30b and the matrix (b) shown in Figure 1a (i.e., R = 2 / 3). As another example, the matrix prototype of the check matrix can be shown in Figure 31a. The matrix prototype of the check matrix shown in Figure 31a can be determined based on the extended indicator matrix shown in Figure 31b and the matrix (b) shown in Figure 1a (i.e., R = 2 / 3).

[0328] As another example, the matrix prototype of the check matrix may be as shown in Figure 32a. The matrix prototype of the check matrix shown in Figure 32a may be determined based on the extended indicator matrix shown in Figure 32b and the matrix (b) shown in Figure 1a (ie, R=2 / 3).

[0329] For the bit rate R = 3 / 4, the following description is given:

[0330] As an example, the matrix prototype of the check matrix may be as shown in Figure 33a. The matrix prototype of the check matrix shown in Figure 33a may be determined based on the extended indicator matrix shown in Figure 33b and the matrix (c) shown in Figure 1a (ie, R=3 / 4).

[0331] As another example, the matrix prototype of the check matrix may be as shown in Figure 34a. The matrix prototype of the check matrix shown in Figure 34a may be determined based on the extended indicator matrix shown in Figure 34b and the matrix (c) shown in Figure 1a (ie, R=3 / 4).

[0332] As another example, the matrix prototype of the check matrix may be as shown in Figure 35a. The matrix prototype of the check matrix shown in Figure 35a may be determined based on the extended indicator matrix shown in Figure 35b and the matrix (c) shown in Figure 1a (ie, R=3 / 4).

[0333] For the bit rate R = 5 / 6, the following description is given:

[0334] As an example, the matrix prototype of the check matrix may be as shown in Figure 36a. The matrix prototype of the check matrix shown in Figure 36a may be determined based on the extended indicator matrix shown in Figure 36b and the matrix (d) shown in Figure 1a (ie, R=5 / 6).

[0335] As another example, the matrix prototype of the check matrix may be as shown in Figure 37a. The matrix prototype of the check matrix shown in Figure 37a may be determined based on the extended indicator matrix shown in Figure 37b and the matrix (d) shown in Figure 1a (ie, R=5 / 6).

[0336] The following describes a communication device according to an embodiment of the present application.

[0337] The present application divides the functional modules of the communication device according to the above-mentioned method embodiment. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above-mentioned integrated modules can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in this application is schematic and is only a logical functional division. There may be other division methods in actual implementation. The communication device of the embodiment of the present application will be described in detail below with reference to Figures 22 to 24.

[0338] Figure 22 is a schematic diagram of the structure of a communication device provided in an embodiment of the present application. As shown in Figure 22, the communication device includes a processing module 2201 and a transceiver module 2202. The transceiver module 2202 can implement corresponding communication functions, and the processing module 2201 is used to implement corresponding processing functions. For example, the transceiver module 2202 can also be referred to as an interface, a communication interface, or a communication module.

[0339] In some embodiments of the present application, the communication device may be used to perform the actions performed by the first communication device in the above method embodiments. In this case, the first communication device may be the Wi-Fi device itself, or a chip or functional module configurable in the device. The transceiver module 2202 is used to perform the transceiver-related operations of the first communication device in the above method embodiments, and the processing module 2201 is used to perform the processing-related operations of the first communication device in the above method embodiments.

[0340] Exemplarily, the processing module 2201 may be configured to obtain an information bit sequence, and perform LDPC encoding on the information bit sequence based on a check matrix to obtain an encoded sequence; the transceiver module 2202 may be configured to output the encoded sequence.

[0341] Exemplarily, the processing module 2201 may also be used to perform other processing on the encoded sequence; the transceiver module 2202 may also be used to send or output the signal after other processing.

[0342] Exemplarily, the processing module 2201 may include an encoding module. For example, the processing module 2201 may also include an acquisition module, a shortening module, or a blocking module. Exemplarily, the processing module 2201 may also include at least one of the following modules: a constellation mapping module, a stream cyclic shift module, a space and frequency mapping module, an IDFT module, a cyclic prefix insertion module, and a windowing module. Exemplarily, the transceiver module 2202 may include a radio frequency module, an antenna module, etc. Exemplarily, the transceiver module 2202 may include a pin module, etc.

[0343] Using Figure 22, in some other embodiments of the present application, the communication device can be used to perform the actions performed by the second communication device in the above method embodiments. In this case, the communication device can be the Wi-Fi device itself, or a chip or functional module configurable in the device. The transceiver module 2202 is used to perform the transceiver-related operations of the second communication device in the above method embodiments, and the processing module 2201 is used to perform the processing-related operations of the second communication device in the above method embodiments.

[0344] Exemplarily, the transceiver module 2202 may be used to receive or input a signal transmitted through a channel; the processing module 2201 may be used to process the signal to obtain information to be decoded.

[0345] Exemplarily, the transceiver module 2202 may be used to input information to be decoded; the processing module 2201 may perform LDPC decoding on the information to be decoded based on a check matrix to obtain an information bit sequence.

[0346] Illustratively, the processing module 2201 may include a decoding module. For example, the processing module 2201 may also include an acquisition module, etc. Illustratively, the processing module 2201 may also include at least one of the following components: a cyclic prefix removal module, a DFT module, a deinterleaving module, a constellation deconstruction module, and a descrambling module. Illustratively, the transceiver module 2202 may include a radio frequency module, an antenna module, etc. Illustratively, the transceiver module 2202 may include a pin module, etc.

[0347] Optionally, in each of the above embodiments, the communication device may further include a storage module, which may be used to store instructions and / or data, and the processing module 2201 may read the instructions and / or data in the storage module to enable the communication device to implement the above method embodiments. Exemplarily, the storage module may store the matrix prototype of the check matrix shown above, or the storage module may be used to store the CPM coefficients or extended indicator matrix in the matrix prototype of the check matrix shown above.

[0348] In the above embodiments, the specific descriptions of terms or steps such as reference check matrix, check matrix, prototype of check matrix, prototype of reference check matrix, CPM, number of cyclic shift bits, expansion factor, code length, code rate, etc. can be referred to the introduction in the above method embodiments, and will not be described in detail here.

[0349] The specific descriptions of the transceiver module and the processing module shown in the above embodiments are only examples. For the specific functions or execution steps of the transceiver module and the processing module, please refer to the above method embodiments and will not be described in detail here.

[0350] The above describes the communication device according to the embodiment of the present application. The following describes possible product forms of the communication device. Any product that possesses the functions of the communication device described in FIG. 22 falls within the scope of protection of the embodiment of the present application. The following description is for illustrative purposes only and does not limit the product forms of the communication device according to the embodiment of the present application to these examples.

[0351] In one possible implementation, in the communication device shown in Figure 22, the processing module 2201 can be one or more processors, the transceiver module 2202 can be a transceiver, or the transceiver module 2202 can also be a sending module and a receiving module, the sending module can be a transmitter, and the receiving module can be a receiver, and the sending module and the receiving module are integrated into a single device, such as a transceiver. In the embodiment of the present application, the processor and the transceiver can be coupled, etc., and the embodiment of the present application does not limit the connection method between the processor and the transceiver. During the execution of the above method, the process of sending information in the above method can be the process of the processor outputting the above information. When outputting the above information, the processor outputs the above information to the transceiver so that the transceiver can transmit it. After being output by the processor, the above information may also need to undergo other processing before reaching the transceiver. Similarly, the process of receiving information in the above method can be the process of the processor receiving the input information. When the processor receives the input information, the transceiver receives the above information and inputs it into the processor. Furthermore, after the transceiver receives the above information, the above information may need to be processed further before being input into the processor.

[0352] As shown in FIG. 23 , the communication device 230 includes one or more processors 2320 and a transceiver 2310 .

[0353] In some embodiments of the present application, the communication device may be configured to execute the steps, methods, or functions performed by the first communication device described above. For example, the processor 2320 may be configured to execute the functions or steps implemented by the processing module 2201 shown in FIG22 , and the transceiver 2310 may be configured to execute the functions or steps implemented by the transceiver module 2202 shown in FIG22 . For a detailed description of the processor 2320 and the transceiver 2310, reference may be made to FIG22 or the method embodiment shown above and will not be described in detail here.

[0354] In other embodiments of the present application, the communication device is used to execute the steps, methods, or functions performed by the second communication device described above. For example, the processor 2320 can be used to execute the functions or steps implemented by the processing module 2201 shown in Figure 22, and the transceiver 2310 can be used to execute the functions or steps implemented by the transceiver module 2202 shown in Figure 22. For detailed descriptions of the processor 2320 and the transceiver 2310, please refer to Figure 22 or the method embodiment shown above and will not be described in detail here.

[0355] In various implementations of the communication device shown in FIG23 , the transceiver may include a receiver and a transmitter, wherein the receiver is configured to perform a receiving function (or operation) and the transmitter is configured to perform a transmitting function (or operation). The transceiver is configured to communicate with other devices / apparatuses via a transmission medium.

[0356] Optionally, the communication device 230 may further include one or more memories 2330 for storing program instructions and / or data. The memory 2330 is coupled to the processor 2320. The coupling in the embodiment of the present application is an indirect coupling or communication connection between the communication devices, units or modules, which may be electrical, mechanical or other forms, and is used for information exchange between the communication devices, units or modules. The processor 2320 may operate in conjunction with the memory 2330. The processor 2320 may execute program instructions stored in the memory 2330. Optionally, at least one of the one or more memories may be included in the processor.

[0357] The specific connection medium between the transceiver 2310, processor 2320, and memory 2330 is not limited in the embodiments of the present application. In Figure 23, the memory 2330, processor 2320, and transceiver 2310 are connected via bus 2340. The bus is represented by a bold line in Figure 23. The connection methods between other components are merely schematic and are not limiting. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, Figure 23 only uses a single bold line, but this does not mean that there is only one bus or only one type of bus.

[0358] In the embodiments of the present application, the processor may be a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, etc., and may implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the methods disclosed in the embodiments of the present application may be directly implemented as being executed by a hardware processor, or may be executed by a combination of hardware and software modules in the processor, etc.

[0359] In the embodiment of the present application, memory may include but is not limited to non-volatile memories such as hard disk drive (HDD) or solid-state drive (SSD), random access memory (RAM), erasable programmable read-only memory (EPROM), read-only memory (ROM) or portable read-only memory (CD-ROM), etc. Memory is any storage medium that can be used to carry or store program code in the form of instructions or data structures, and can be read and / or written by a computer (such as the communication device shown in the present application), but is not limited thereto. The memory in the embodiment of the present application can also be a circuit or other arbitrarily capable of realizing a storage function, for storing program instructions and / or data.

[0360] The processor 2320 is primarily used to process communication protocols and communication data, control the entire communication device, execute software programs, and process software program data. The memory 2330 is primarily used to store software programs and data. The transceiver 2310 may include a control circuit and an antenna. The control circuit is primarily used to convert baseband signals into radio frequency signals and process radio frequency signals. The antenna is primarily used to transmit and receive radio frequency signals in the form of electromagnetic waves. Input and output devices, such as a touch screen, display, and keyboard, are primarily used to receive user input and output data to the user.

[0361] When the communication device is powered on, the processor 2320 can read the software program in the memory 2330, interpret and execute the instructions of the software program, and process the data of the software program. When data needs to be sent wirelessly, the processor 2320 performs baseband processing on the data to be sent and outputs the baseband signal to the radio frequency circuit. The radio frequency circuit performs radio frequency processing on the baseband signal and then transmits the radio frequency signal to the outside in the form of electromagnetic waves through the antenna. When data is sent to the communication device, the radio frequency circuit receives the radio frequency signal through the antenna, converts the radio frequency signal into a baseband signal, and outputs the baseband signal to the processor 2320. The processor 2320 converts the baseband signal into data and processes the data.

[0362] In another implementation, the RF circuit and antenna may be provided independently of the processor performing baseband processing. For example, in a distributed scenario, the RF circuit and antenna may be remotely arranged independent of the communication device.

[0363] The communication device shown in the embodiment of the present application may also have more components than those in Figure 23, and the embodiment of the present application is not limited to this. The method performed by the processor and transceiver shown above is only an example. For the specific steps performed by the processor and transceiver, please refer to the method described above.

[0364] In another possible implementation, in the communication device shown in Figure 22, the processing module 2201 can be one or more logic circuits, and the transceiver module 2202 can be an input / output interface, or also called a communication interface, or an interface circuit, or an interface, etc. Alternatively, the transceiver module 2202 can also be a sending module and a receiving module, the sending module can be an output interface, and the receiving module can be an input interface, and the sending module and the receiving module are integrated into one module, such as an input / output interface. As shown in Figure 24, the communication device shown in Figure 24 includes a logic circuit 2401 and an interface 2402. That is, the above-mentioned processing module 2201 can be implemented with a logic circuit 2401, and the transceiver module 2202 can be implemented with an interface 2402. Among them, the logic circuit 2401 can be a chip, a processing circuit, an integrated circuit or a system on chip (SoC) chip, etc., and the interface 2402 can be a communication interface, an input / output interface, a pin, etc. For example, Figure 24 is illustrated using the above-mentioned communication device as a chip, and the chip includes a logic circuit 2401 and an interface 2402.

[0365] In the embodiment of the present application, the logic circuit and the interface can also be coupled to each other. The embodiment of the present application does not limit the specific connection method of the logic circuit and the interface. For example, the logic circuit 2401 can be used to perform the functions or steps implemented by the processing module 2201 shown in Figure 22, and the interface 2402 can be used to perform the functions or steps implemented by the transceiver module 2202 shown in Figure 22. For a specific description of the logic circuit 2401 and the interface 2402, please refer to Figure 22 or the method embodiment shown above, and will not be described in detail here.

[0366] The communication device shown in the embodiment of the present application can implement the method provided in the embodiment of the present application in the form of hardware, or can implement the method provided in the embodiment of the present application in the form of software, etc., and the embodiment of the present application is not limited to this.

[0367] An embodiment of the present application further provides a communication system, which includes a first communication device and a second communication device. The first communication device and the second communication device can be used to execute the method in any of the aforementioned embodiments.

[0368] In addition, the present application also provides a computer program, which is used to implement the operations and / or processing performed by each communication device in the method provided by the present application.

[0369] The present application also provides a computer-readable storage medium having computer code stored therein. When the computer code is run on a computer, the computer executes the operations and / or processing performed by each communication device in the method provided by the present application.

[0370] The present application also provides a computer program product, which includes computer code or computer program. When the computer code or computer program is run on a computer, the operations and / or processes performed by the method provided in the present application are executed.

[0371] In the several embodiments provided in this application, it should be understood that the disclosed systems, communication devices, and methods can be implemented in other ways. For example, the communication device embodiments described above are only schematic. For example, the division of the modules is only a logical function division. In actual implementation, there may be other division methods, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, communication devices or modules, or can be electrical, mechanical or other forms of connection.

[0372] The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the technical effects of the solutions provided in the embodiments of the present application.

[0373] In addition, the functional modules in the various embodiments of the present application may be integrated into a processing module, or each module may exist physically separately, or two or more modules may be integrated into a single module. The above-mentioned integrated modules may be implemented in the form of hardware or software functional modules.

[0374] If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a readable storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned readable storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0375] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A coding method, characterized in that, The method includes: Obtain an information bit sequence; Perform low-density parity-check (LDPC) encoding on the information bit sequence based on a parity-check matrix to obtain an encoded sequence, where the length of the encoded sequence is N1, N1 is n times of 1944, n is an integer greater than or equal to 2, and the expansion factor Z of the parity-check matrix is 81; Output the encoded sequence.

2. A decoding method, characterized in that, The method includes: Obtain information to be decoded, where the length of the information to be decoded is N1, N1 is n times of 1944, n is an integer greater than or equal to 2; Perform low-density parity-check (LDPC) decoding on the information to be decoded based on a parity-check matrix to obtain an information bit sequence, where the expansion factor Z of the parity-check matrix is 81.

3. The method according to claim 1 or 2, characterized in that, In the matrix prototype of the parity-check matrix, the first column and the second column in the matrix corresponding to the parity-check bits are obtained by performing positive diagonal expansion or anti-diagonal expansion on both the first element and the last element in the first column of the matrix corresponding to the parity-check bits in the matrix prototype of the basic parity-check matrix, and the code rate corresponding to the basic parity-check matrix is the same as the code rate corresponding to the parity-check matrix.

4. The method according to any one of claims 1 to 3, characterized in that, In the matrix prototype of the parity-check matrix, the elements other than the first column and the second column in the matrix corresponding to the parity-check bits are obtained by performing positive diagonal expansion on the element 0 other than the first column in the matrix corresponding to the parity-check bits in the matrix prototype of the basic parity-check matrix, and the code rate corresponding to the basic parity-check matrix is the same as the code rate corresponding to the parity-check matrix.

5. The method according to any one of claims 1-4, characterized in that, In the matrix prototype of the parity-check matrix, the matrix corresponding to the information bits is obtained by performing positive diagonal expansion or anti-diagonal expansion on the element in the x-th row and the y-th column in the matrix corresponding to the information bits in the matrix prototype of the basic parity-check matrix, the element in the x-th row and the j-th column is greater than or equal to 0, and both x and y are positive integers, and the code rate corresponding to the basic parity-check matrix is the same as the code rate corresponding to the parity-check matrix.

6. [Corrected according to Rule 26 on 10.02.2025] The method according to any one of claims 1-5, characterized in that, When the code rate R of the information bit sequence is 1 / 2, the matrix prototype of the parity-check matrix is any one of the following matrices: Or, Or, Where, -1 represents the all-zero matrix of Z*Z, 0 represents the identity matrix of Z*Z, and the element greater than 0 represents the cyclic permutation matrix (CPM) of the identity matrix of Z*Z.

7. [Corrected according to Rule 26 on 10.02.2025] The method according to any one of claims 1-5, characterized in that, When the code rate R of the information bit sequence is 2 / 3, the matrix prototype of the parity-check matrix is any one of the following matrices: Or, Or, Where, -1 represents the all-zero matrix of Z*Z, 0 represents the identity matrix of Z*Z, and the element greater than 0 represents the cyclic permutation matrix (CPM) of the identity matrix of Z*Z.

8. [Corrected according to Rule 26 on 10.02.2025] The method according to any one of claims 1-5, characterized in that, When the code rate R of the information bit sequence is 3 / 4, the matrix prototype of the parity-check matrix is any one of the following matrices: Or, Or, Or, Where, -1 represents the all-zero matrix of Z*Z, 0 represents the identity matrix of Z*Z, and the element greater than 0 represents the cyclic permutation matrix (CPM) of the identity matrix of Z*Z.

9. [Corrected according to Rule 26 on 10.02.2025] The method according to any one of claims 1-5, characterized in that, When the code rate R of the information bit sequence is 5 / 6, the matrix prototype of the parity check matrix is any one of the following matrices: Or, Or, Or, Where, -1 represents the all-zero matrix of Z*Z, 0 represents the identity matrix of Z*Z, and the element greater than 0 represents the cyclic permutation matrix (CPM) of the identity matrix of Z*Z.

10. [Corrected according to Rule 26 on 10.02.2025] The method according to any one of claims 1-5, characterized in that, When the code rate R of the information bit sequence is 1 / 2, the matrix prototype of the parity-check matrix is any one of the following matrices: Or, Where, -1 represents the all-zero matrix of Z*Z, 0 represents the identity matrix of Z*Z, and the element greater than 0 represents the cyclic permutation matrix (CPM) of the identity matrix of Z*Z.

11. [Corrected according to Rule 26 on 10.02.2025] The method according to any one of claims 1 to 5, characterized in that, When the code rate R of the information bit sequence is 2 / 3, the matrix prototype of the parity-check matrix is any one of the following matrices: Or, Where, -1 represents the all-zero matrix of Z*Z, 0 represents the identity matrix of Z*Z, and the element greater than 0 represents the cyclic permutation matrix (CPM) of the identity matrix of Z*Z.

12. [Corrected according to Rule 26 on 10.02.2025] The method according to any one of claims 1-5, characterized in that, When the code rate R of the information bit sequence is 3 / 4, the matrix prototype of the parity-check matrix is any one of the following matrices: Or, Where, -1 represents the all-zero matrix of Z*Z, 0 represents the identity matrix of Z*Z, and the element greater than 0 represents the cyclic permutation matrix (CPM) of the identity matrix of Z*Z.

13. [Corrected according to Rule 26 on 10.02.2025] The method according to any one of claims 1-5, characterized in that, When the code rate R of the information bit sequence is 5 / 6, the matrix prototype of the parity check matrix is any one of the following matrices: Or, Among them, -1 represents the all-zero matrix of Z*Z, 0 represents the identity matrix of Z*Z, and elements greater than 0 represent the cyclic permutation matrix CPM of the identity matrix of Z*Z.

14. A communication device, characterized in that, It includes a module for performing the method according to any one of claims 1-13.

15. A communication device, characterized in that, It includes a processor for performing the method according to any one of claims 1-13.

16. A communication device, characterized in that, It includes a logic circuit and an interface, and the logic circuit and the interface are coupled; The interface is used for inputting and / or outputting information, and the logic circuit is used for performing the method according to any one of claims 1-13.

17. A computer-readable storage medium, characterized in that, The computer-readable storage medium is used for storing a computer program, and when the computer program is executed, the method according to any one of claims 1-13 is executed.

18. A computer program product, characterized in that, When the computer program product is executed, the method according to any one of claims 1-13 is executed.

19. A communication system, characterized in that, The communication system includes a first communication device and a second communication device. The first communication device is used for performing the method according to any one of claims 1, 3-13, and the second communication device is used for performing the method according to any one of claims 2-13.

Images