Follower with controllable on / off function

Abstract

A follower with a controllable ON / OFF function (referred to as a follower switch). Two modules for controlling ON / OFF are added to a basic follower, wherein one module is a control module 13 for controlling output transistors T1&T2 to be set to an ON / OFF state, and the other module is a short-circuit control module 15 for controlling a short-circuit branch 14 to be set to an ON / OFF state. When J=0, K1&K2 are set to OFF and KF is set to ON, wherein K1&K2 being set to OFF can be regarded as if K1&K2 are not present, and a controllable operational amplifier is made to return to the state of a basic operational amplifier, and KF being set to ON is to set the controllable short-circuit branch 14 to a short-circuited state, and the two states are combined, such that the follower switch is in an ON state. When J=1, K1&K2 are set to ON and KF is set to OFF, wherein K1 being set to ON makes a base electrode of T1 communicate with a power source -VCC, and cuts off T1, K2 being set to ON makes a base electrode of T2 communicate with a power source +VCC, and cuts off T2, and KF being set to OFF is to set the controllable short-circuit branch 14 to an open circuit, such that the follower switch is in an OFF state.

Description

A follower with controllable ON / OFF

[0001] Technical field: The present invention is a controllable ON / OFF follower, referred to as a follower switch, belonging to the field of electronic circuits. Technical background:

[0002] A voltage follower, also known as a voltage follower, can increase the load capacity of a signal source. Ideally, the voltage at the follower's output will follow and equal the voltage at its input. This is a key application of integrated operational amplifiers (op amps). The basic structure of an op amp consists of an input stage 10, an intermediate stage 11, and an output stage 12. This is represented by the solid rectangle 1 in Figure 1, minus the dashed rectangle 13, which represents the output transistor control module.

[0003] Because in the amplification state, the op amp's non-inverting input and inverting input are "virtually shorted", if the op amp's output u O With the inverting input u N Short circuit, then it is equivalent to the output terminal u O With the non-inverting input u P Virtual short, u O and u P On this basis, let the in-phase input end serve as the input end of the follower, then the output end u O The voltage at the input terminal u P The voltage of the follower is a voltage follower. The follower does not have a shutdown function. If a controllable shutdown function is added to the follower, it becomes a controllable ON / OFF follower, referred to as a follower switch.

[0004] To avoid confusion, this article calls the current op amp a basic op amp, and the basic op amp with the output tube control module 13 added is called a controllable op amp; the current follower is called a basic follower, and the follower with controllable ON / OFF in this article is called a follower switch. Summary of the invention:

[0005] The present invention is an improvement on the basic follower, which adds a shutdown function to the basic follower, and becomes a follower with ON / OFF function, which is called a follower switch. That is, when it is in the ON state, the output terminal u o With input u P Virtual short, zero voltage loss; when it is in the OFF state, its output terminal u o With input u P disconnect.

[0006] To avoid confusion, some definitions, conventions, and explanations are given first.

[0007] ●A / B means A or B; A&B means A and B;

[0008] The pair of transistors in the output stage, NPN transistor T1 and PNP transistor T2, are collectively referred to as output transistors T1 & T2. The control transistors K1 & K2 that perform on / off control on output transistors T1 & T2 are called output control transistors, and the module containing the output control transistors is called the output transistor control module.

[0009] ●Control tube K X :K X (The subscript X is a wildcard.) This is a controlled switching device consisting of a control pin and two channel pins that form the main ON / OFF control channel. The control word J controls the main channel's ON / OFF state via the control pin. Device types for control transistors include, but are not limited to, transistors, field-effect transistors, analog switches, and transmission gates. The control pin of a transistor is the base, and the channel pins are the emitter and collector. The control stage of a field-effect transistor is the gate, and the channel pins are the source and drain. The control stage of an analog switch or transmission gate is CONTROL, and their channel pins are IN and OUT.

[0010] The working types of control tubes include output control tubes and short-circuit control tubes. Their icons are based on the contact icons of the borrowed switch with an additional control pin.

[0011] ●ON definition: For control tube K X For the output tubes T1 and T2, ON means that T1 and T2 are in the amplification state.

[0012] The current op amp is called a basic op amp, and the basic op amp with the output tube control module 13 added is called a controllable op amp; the current follower is called a basic follower, and the follower with controllable on / off function in this article is called a follower switch;

[0013] The present invention is a follower with controllable ON / OFF (Figure 1), referred to as a follower switch, and its symbol is S. S is a basic follower with an expanded controllable ON / OFF function.

[0014] Technical feature 1: The present invention is a controllable ON / OFF follower, referred to as a follower switch, which is a basic follower with two additional ON / OFF control modules.

[0015] One is a control module 13 for controlling the output tubes T1 & T2 to be on / off, referred to as the output tube control module 13, and the other is a short circuit control module 15 for controlling the short circuit branch 14 to be on / off, referred to as the short circuit control module 15.

[0016] One is the structure of the output tube control module 13: an output tube control module 13 is added to the basic operational amplifier structure (input stage 10 + intermediate stage 11 + output stage 12) in the basic follower to control the output tubes T1 and T2 in the output stage 12 to turn on / off, so that the basic operational amplifier is upgraded to a controllable ON / OFF operational amplifier (the structure of the solid rectangular box 1 in Figure 1), which is referred to as a controllable operational amplifier. The output tube control module 13 includes two control tubes K1 and K2 for controlling the output tubes T1 and T2 to turn on / off. K1 is used to control the ON / OFF of T1 and is called the first control tube, and K2 is used to control the ON / OFF of T2 and is called the second control tube. K1 and K2 are collectively referred to as output control tubes. The control pins of the two output control tubes K1 and K2 are controlled by the same control word J. The two channel pins of the first control tube K1 are respectively connected to the power supply -V CC and the base of the NPN output transistor T1 to control the ON / OFF of the output transistor T1; the two channel pins of the second control tube K2 are respectively connected to the power supply +V CC and the base of the PNP output transistor T2 to control the ON / OFF of the output transistor T2;

[0017] The second is the structure of the short-circuit control module 15: the short-circuit branch 14 is used to short-circuit the output terminal u o and the inverting input u N A short circuit control module 15 is connected to the short circuit branch 14 to control the ON / OFF of the short circuit branch 14; the simplest structure of the short circuit control module 15 is a short circuit control tube K F ; Short-circuit control tube K F The ON / OFF state of the output control tube K1 & K2 is opposite to each other, that is, when K1 & K2 are OFF, K F Must be set to ON; otherwise, when K1 & K2 are set to ON, K F Must be set to OFF; if K F If the ON / OFF state of K1 & K2 is the same, use an inverter to adjust them to be mutually inverted;

[0018] J=0 or J=1 agreement: the control word J can be high or low, so that K1 & K2 are turned on and K F The OFF level is agreed to be "J=1", so that K1 & K2 are OFF and K F The ON level is designated as "J=0" (the state shown in FIG1).

[0019] Working principle of follower switch:

[0020] One is the principle of following the switch to ON: the necessary and sufficient condition for following the switch to ON is that the output control tubes K1 & K2 are OFF and the control tube K is short-circuited. FSet to ON;

[0021] When J=0, K1&K2 are turned OFF and K F Set to ON; K1 & K2 set to OFF can be regarded as K1 & K2 do not exist, so that the controllable op amp returns to the basic op amp state; at the same time, K F Setting ON means setting the controllable short-circuit branch 14 to a short-circuit state. The combination of these two states causes the follower switch to return to a basic follower state, that is, the follower switch is in the ON state;

[0022] The second is the principle of following the switch to OFF: the necessary and sufficient condition for following the switch to OFF is that the output control tubes K1 & K2 are turned ON (making the output tubes T1 & T2 turned OFF) and the control tube K is short-circuited. F Set OFF;

[0023] When J=1, K1&K2 are turned ON and K F Set OFF;

[0024] Because the main channel of K1 is connected across the base of the output transistor T1 and the power supply -V CC , so K1 is turned ON so that the base of T1 is connected to the power supply -V CC Connected, so that T1 is cut off; similarly, because the main channel of K2 is connected across the base of the output transistor T2 and the power supply +V CC , so K2 is turned ON so that the base of T2 is connected to the power supply +V CC Connected, so that T2 is cut off; that is, K1 & K2 are turned ON, so that T1 & T2 are both OFF, so that the output terminal u o Cut off with controllable op amp;

[0025] At the same time, K F Setting OFF means setting the controllable short-circuit branch 14 to an open circuit, so that the output terminal u o With the inverting input u N The short-circuit connection is cut off;

[0026] Output terminal u o The controllable operational amplifier is cut off and connected to the inverting input terminal u N Truncation, that is, the output u o All the previous circuits are cut off, so that the follower switch is in the OFF state;

[0027] Technical Feature 2: A controllable ON / OFF follower according to Technical Feature 1, characterized in that:

[0028] The output control tubes K1 & K2 use triodes and corresponding base resistors, short-circuiting the control tube K F Adopt bidirectional analog switch; it can meet the requirements of follower switch;

[0029] Experiments show that, under the premise that the offset voltage of the basic operational amplifier is at the μV level, a resistor less than 10KΩ can be used as the K F , its following accuracy can reach 10 6 ~10 7 , and the ON resistance of the bidirectional analog switch is less than 100Ω; from an engineering point of view, it can be regarded as zero loss, so the follower switch can also be called a follower switch.

[0030] If K1&K2 and K F If the ON / OFF states of the two transistors are consistent, an inverter is used to make their ON / OFF states opposite.

[0031] Technical Feature 3: A controllable ON / OFF follower according to Technical Feature 1, characterized in that:

[0032] Based on the follower switch, a bidirectional follower switch is constructed. Specifically,

[0033] Connect the follower switch S1 and the follower switch S2 in parallel in forward and reverse directions (Figure 2.1), and connect the control words of the two to form a bidirectional follower switch;

[0034] Technical Feature 4: A controllable ON / OFF follower according to Technical Feature 1, characterized in that the sample-and-hold device is constructed based on a follower switch, specifically

[0035] The switches in the existing sample-and-hold device are replaced with follower switches to form a follower switch type sample-and-hold device, including a follower switch type feedback type sample-and-hold device (Figure 3.1) and a follower switch type series type sample-and-hold device (Figure 3.2).

[0036] Technical Feature 5: A controllable ON / OFF follower according to Technical Feature 1, characterized in that a plurality of follower switches are used to construct a multi-way follower switch, specifically, the input pins of the plurality of follower switches are connected to form a common input pin type multi-way follower switch, the output pins of the plurality of follower switches are connected to form a common output pin type multi-way follower switch (MS dotted box in Figure 4), and the control pins of the plurality of follower switches are connected to form a common control pin type multi-way follower switch

[0037] Additional notes on the following technical features

[0038] ●Stage-ADC is referred to as StADC, SUB-ADC is referred to as SADC, and SUB-DAC is referred to as SDAC; ADC and DAC (hereinafter referred to as ADC & DAC) will generate many symbols, including (V λe 、R λe 、J λe 、PS λe 、S λe), the first subscript in these symbols is the stage subscript (Stage-subscript), its λ is the stage subscript wildcard, wildcard (α, β, γ, ..., m), representing the first stage, the second stage, the third stage, ..., the last stage, (α, β, γ, ..., m) is (1, 2, 3, ..., m); the second subscript is the step subscript (Step-subscript), its e is the step subscript wildcard, wildcard (0, 1, 2, ..., Q λ -1), indicating the 0th, 1st, 2nd, ..., Q-1th order of the device chain.

[0039] ● The subscript of a superscript or the subscript of a subscript (secondary subscript) cannot be written. There are two ways to express it. The first is the equal method, that is, the secondary subscript is the same size as its primary superscript or subscript. qβ In the example, the subscript β of the first-level superscript q is equal to q. Similar examples include: subscript (Q λ 、E λ ) is represented by (Qλ, Eλ); the second is the omission method, that is, when it is known that it is at the λ level, the secondary subscript λ is omitted by default, such as, (d λ(qλ-1) 、J λ(Qλ-1) 、S λEλ 、J λEλ ) is written as (d λ(q-1) 、J λ(Q-1) 、S λE 、J λE );

[0040] ●The λth level SADC & SDAC has q λ bit, forming Q λ =2^q λ Order (0, 1, 2, ..., Q λ -1), because the subscript of the subscript or the subscript of the superscript cannot be written, the subscript Qλ is used to represent the subscript Q λ , such as V λ(Qλ-1) Qλ in is represented by Q λ , use superscript qλ to represent superscript q λ , such as Q β =2^q β =2 qβ , when it is known that it is at the λth level, λ can be omitted and written as V λ(Q-1) , Q λ =2 q , V λE The subscript E is actually E λ , because the subscript of the subscript cannot be written, we have to default to E when it is known that it is at level λ λ Indicated by E.

[0041] Let Q = 2 q =2^q,Qλ =2 qλ =2^q λ .

[0042] ●The single letter D acts as a noun prefix, and D means "digital signal", such as "digital signal input terminal" is abbreviated as "D input terminal"; similarly, the single letter A acts as a noun prefix, and A means "analog signal", such as "analog signal input terminal" is abbreviated as "A input terminal"; the default "input terminal" without a prefix is ​​"A input terminal".

[0043] ●At a certain moment, when the analog signal U λZ Among the reference potentials, there must be one that is closest to U λZ The potential, V λE , the reference potential V λE It is defined as ADCB λ The bridge potential at this moment, V λE λZ <V λ(E+1) , the bridge potential V can be obtained by rounding λE , V λE =INT(U λZ / ΔV)*ΔV, that is, based on the quantization unit ΔV, V λE Is the analog quantity U λZ The integer part of the mantissa voltage U λX It is the analog quantity U λZ The decimal part, U λX <ΔV, mantissa voltage U λX =Analog voltage U λZ - Bridge potential V λE ;

[0044] Technical Feature 6: A controllable ON / OFF follower according to Technical Feature 1, characterized in that a bridge potential DAC (Figure 5) is constructed based on a common output multi-channel follower switch (MS), specifically

[0045] An n-bit DAC consists of m SUB-DACs and a weight summing op amp (WAΣ). The SUB-DAC is referred to as SDAC in the following sections.

[0046] (α level, β level, γ level, ..., m level) m SDACs are respectively (SDAC α 、SDAC β 、SDAC γ ,…,SDAC m ), their digits are (q α ,q β ,q γ ,…,q m ), where m is the final stage, n = q​α +q β +q γ +…+q m ;

[0047] Use the λth sub-level SDAC λ Wildcard all sub-levels, SDAC λ The number of digits is q λ , SDAC λ Contains a q λ Bit multiplexer follower switch MS λ (multiway switch) and a q λ Bit reference resistor chain RC λ (R-chain);

[0048] The reference potential chain RC λ The resistors are equal and connected across (-V REF ~V REF ), 2 qλ A reference resistor (R λ0 、R λ1 、R λ2 ,…,R λ(Qλ-1) ) will (-V REF ~V REF ) is divided into 2 qλ To simplify the analysis, let -V REF =0, each divided voltage ΔV is ΔV=V REF / 2 qλ ; Form 2 qλ +1 potential point (V λ0 ~V λQλ ), of which 2 qλ Reference potential point (V λ0 ~V λ(Qλ-1) ), namely V λ0 =0, V λ1 =ΔV, V λ2 =2ΔV,…,V λ(Qλ-1) =(Q λ -1)ΔV,(V λQλ =Q λ ΔV=V REF , does not serve as a reference potential point), called V λe is the λth order e-th order reference potential;

[0049] The λth stage multi-way follower switch MS λ Including a q λ Bit decoder YM λ and a q λ Follower switch chain SC λ =(S λ0 、Sλ1 、S λ2 ,…,S λ(Qλ-1) ); Multi-channel follower switch MS λ It has three groups of ports, one of which is the control port - the control word of each follower switch (J λ0 、J λ1 ,…,J λ(Qλ-1) ); one group is A input terminal - each follower switch (S λ0 、S λ1 ,…,S λ(Qλ-1) )'s A input terminal, one group is the A output terminal - the A output terminal of each follower switch;

[0050] The q-bit decoder includes a D input terminal (d λ(q-1) …d λ1 d λ0 ) and Q λ =2 qλ Decoded output words (J λ0 、J λ1 ,…,J λ(Qλ-1) ), the decoded output word is the same as the 2 qλ The control word of the follower switch (J λ0 、J λ1 ,…,J λ(Qλ-1) ) are connected according to the corresponding relationship of equal subscripts;

[0051] Said 2 qλ Follower switch (S λ0 、S λ1 ,…,S λ(Qλ-1) ) are connected to the reference potential point (V λ0 、V λ1 ,…,V λ(Qλ-1) ), the A output of all follower switches is connected to the λth level common output BUS λ (Figure 5);

[0052] When SDAC λ D input terminal (d λ(q-1) …d λ1 d λ0 ) After receiving the digital signal, it converts it into 2 qλ Base E λ , determine E λ After that, it will be in 2 qλ A selected word J is generated from the decoded output words λE (Note: Under the premise of knowing that it is at the λ level, the default subscript E λ Indicated by E), J λE Sent to the corresponding follower switch S λE Control word JλE , so that the follower switch S λE Set to ON, and the rest of the follow switches to OFF; S λE After turning ON, take out the corresponding reference potential point V λE =E*ΔV, completing the DA conversion of the lambda stage;

[0053] V λE It is both an analog potential and corresponds to a digital signal (d λ(q-1) …d λ1 d λ0 ) value, is the bridge between analog signal and digital signal, so V λE Named "bridge potential"; get each level of SDAC in turn λ The bridge potential (V αE 、V βE 、V γE ,……,V mE );

[0054] For example, when the 3-bit SDAC λ D input terminal (d λ2 d λ1 d λ0 ) receives the digital signal (011), converts it into an octal number 3, and generates a selected word J among the 8 decoded output words. λ3 , J λ3 Sent to the corresponding follower switch S λ3 Control word J λ3 , so that the follower switch S λ3 Set to ON, and the rest of the follow switches to OFF; S λ3 After turning ON, take out the corresponding reference potential point V λ3 =3ΔV; the DA conversion obtained by this pulse is (011)→3ΔV;

[0055] Each bridge potential V λE With different weights λ , so the bridge potential V λE Multiply by the weight WA λ Get the weight bridge potential WV λE , that is, WV λE =WA λE *V λE To this end, it is necessary to pass the bridge potential of each level through the BUS line (BUS α 、BUS β 、BUS γ 、……、BUS m ) is sent to the Weight-ALU (WA α , WA β , WAγ ,…,WA m ) to perform weight calculation; WA λ The corresponding weight is WA λ ; Let WA α =1, the weight of the first level (λ+1) is 2 smaller than that of the first level λ qλ times, that is, WA (λ+1) =WA λ / 2 qλ ; with WA α As a benchmark, we get WA α =1, WA β =1 / 2 qα , WA γ =WA β / 2 qβ =1 / 2 (qα+qβ) ,…,WA m =WA (m-1) / 2 q(m-1) =1 / 2(qα+qβ+…+q(m-1))

[0056] (Note: Here, (α, β, …, (m-1)) in 2(qα+qβ+…+q(m-1)) is the subscript of q)

[0057] The potential of each level of weight bridge is passed through the summator Σ λ After summing, the total DAC output voltage V out , that is, V out =WV αE +WV βE +WV γE +…+WV λm =WA αE *V αE +V αE +WA β *V βE +WA γ *V γE +…+WA m *V λm =V αE +V βE / 2 qα +V γE / 2 qα+qβ +…+ V λm / 2qα+qβ+…+q(m-1);

[0058] Technical Feature 7: A controllable ON / OFF follower according to Technical Feature 6, characterized in that an MS-type bridge potential pipeline ADC1 is constructed by replacing the SDAC in the pipeline ADC with a common output multi-channel follower switch (MS), referred to as bridge potential ADC1. Specifically,

[0059] The bridge potential ADC1 is the same as the traditional pipeline ADC, which is composed of multi-stage Stage-ADC λ In order to distinguish the two, the following will be the Stage-ADC of the Type 1 bridge potential ADC1. λ Abbreviated as StADC1 λ , the traditional pipeline ADC Stage-ADC λ Referred to as StaADC λ ;StaADC λ Includes a SUB-ADC λ (SADC λ ), a SUB-DAC λ (abbreviated as SDAC λ ) and an interstage module ISM λ (Interstage module); while StADC1 λ Just StaADC λ SDAC λ Replace it with a multi-way follower switch; that is, the StADC1 λ (Figure 6.1) includes a SADC λ , a multi-channel follower switch MS λ and an interstage module ISM λ ,

[0060] The StADC1 λ SADC λ Includes a reference resistor chain RC λ , a comparator chain CC λ , an encoder ENC λ ;

[0061] The reference potential chain RC λ The resistors are equal and connected across (-V REF ~V REF ), 2 qλ A reference resistor (R λ0 、R λ1 、R λ2 ,…,R λ(Qλ -1)) will (-V REF ~V REF ) is divided into 2 qλ Divide equally, and the voltage of each equal division is ΔV = V REF / 2 qλ ; To simplify the analysis, let -V REF =0, so that the reference resistor chain RC λ Formation (2 qλ +1) potential point (Vλ0 ~V λQλ ), of which 2 qλ Reference potential point (V λ0 ~V λ(Qλ -1)), that is, V λ0 =0, V λ1 =ΔV, V λ2 =2ΔV,…,V λ(Qλ -1)=(Q λ -1)ΔV,(V λQλ =Q λ ΔV=V REF , does not serve as a reference potential point), called V λe is the λth order e-th order reference potential;

[0062] The comparator chain CC λ By (2 qλ -1) comparator (C λ0 、C λ1 、R λ2 ,…,C λ(Qλ -1)) across (-V REF ~V REF ), C λ0 For virtual;

[0063] Resistor chain and comparator chain CC λ There are two types of connection relationships. The first is the input signal U λy After passing through the sample-and-hold circuit, it is connected to the non-inverting input of each comparator. The reference potential point (V λ1 ~V λ(Qλ-1) ) is connected to the corresponding comparator (C λ1 ~C λ(Qλ-1) ) inverting input terminal; the second is just the opposite, the input signal U λy After passing through the sample and hold circuit, it is connected to the inverting input of each comparator. The reference potential point (V λ1 ~V λ(Qλ-1) ) is connected to the corresponding comparator (C λ1 ~C λ(Qλ-1) )’s non-inverting input terminal; the two have the same principle, and this article uses the first connection relationship for analysis;

[0064] The λth stage multi-way follower switch MS λ Including a q λ Bit decoder YM λ and a q λ Follower switch chain SC λ =(S λ0 、S λ1 ,…,S λ(Qλ-1) );

[0065] The q λ The bit decoder includes a D input terminal (d λ(q-1) …d λ1 d λ0 ) and Q λ =2 qλ Decoded output words (J λ0 、J λ1 ,…,J λ(Qλ-1) );

[0066] The follower switch chain 2 qλ Follower switch (S λ0 、S λ1 ,…,S λ(Qλ-1) ), its A input terminal is correspondingly connected to 2 qλ Reference potential point (V λ0 、V λ1 ,…,V λ(Qλ-1) ), all A output terminals are connected to the λth level common output terminal BUS λ , its control word (J λ0 、J λ1 ,…,J λ(Qλ-1) ) is connected to the decoder YM λ Output word (J λ0 、J λ1 ,…,J λ(Qλ-1) );

[0067] The q-bit decoder includes a D input terminal (d λ(q-1) …d λ1 d λ0 ) and 2 qλ Decoded output words (J λ0 、J λ1 ,…,J λ(Qλ-1) ), the decoded output word is the same as the 2 qλ The control word of the follower switch (J λ0 、J λ1 ,…,J λ(Qλ-1) ) are connected accordingly;

[0068] Said 2 qλ The A input of each follower switch is connected to the reference potential point according to the corresponding subscript, and the output of all follower switches is connected to the λth level common output terminal BUS λ ;

[0069] When SDAC λ D input terminal (d λ(q-1) …d λ1 d λ0 ) After receiving the digital signal, it converts it into 2 qλ Base Eλ , determine E λ After that, it will be in 2 qλ A selected word J is generated from the decoded output words λE (Note: Under the premise of knowing that it is at the λ level, the default subscript E λ Indicated by E), J λE Sent to the corresponding follower switch S λE Control word J λE , so that the follower switch S λE Set to ON, and the rest of the follow switches to OFF; S λE After turning ON, take out the corresponding reference potential point V λE =E*ΔV, completing the DA conversion of the lambda stage;

[0070] The q-bit decoder includes a D input terminal (d λ(q-1) …d λ1 d λ0 ) and 2 qλ Decoded output words (J λ0 、J λ1 ,…,J λ(Qλ-1) ), the decoded output word is the same as the 2 qλ The control word of the follower switch (J λ0 、J λ1 ,…,J λ(Qλ-1) ) are connected accordingly;

[0071] Said 2 qλ The A input of each follower switch is connected to the reference potential point according to the corresponding subscript, and the output of all follower switches is connected to the λth level common output terminal BUS λ ;

[0072] The interstage module ISM λ Including summer Σ λ , AM amplifier λ (The two are collectively called the summing amplifier Σ&AM λ ) and a sample-and-hold unit T / H;

[0073] When SDAC λ D input terminal (d λ(q-1) …d λ1 d λ0 ) After receiving the digital signal, it converts it into 2 qλ Base E λ , determine E λ After that, it will be in 2 qλ A selected word J is generated from the decoded output words λE (Note: Under the premise of knowing that it is at the λ level, the default subscript E λ Indicated by E), J λESent to the corresponding follower switch S λE Control word J λE , so that the follower switch S λE Set to ON, and the rest of the follow switches to OFF; S λE After turning ON, take out the corresponding reference potential point V λE =E*ΔV, completing the DA conversion of the λth level;

[0074] (The inter-stage module includes a sample-hold device T / H, a summer Σ λ , AM amplifier λ );

[0075] The bridge potential V λE The extraction module includes a q λ bit multiplexer follower switch; the q λ The bit multiplexer follower switch includes a q λ bit decoder, a follower switch chain (S λ0 、S λ1 、S λ2 ,…,S λ(Qλ-1) ), each follower switch output is connected to the common output terminal BUS λ ;

[0076] The A input terminals of the follower switches of the follower switch chain, the inverting input terminals of the comparators of the comparator chain, and the reference potential points of the reference resistor chain are connected according to the corresponding relationship of the subscripts;

[0077] Technical Feature 8: A controllable ON / OFF follower according to Technical Feature 1, characterized in that a logic operator is used to perform logic operations on multiple logic signals, including a combinational logic operator and a sequential logic operator, to obtain a control word J for controlling the ON / OFF of the follower switch;

[0078] Technical Feature 9: A controllable ON / OFF follower according to Technical Feature 8, characterized in that an AND gate is used to operate two control signals to obtain a dual-control follower switch PS λe Specifically

[0079] The dual-control follower switch PS λe There are two control signals (j λ(e+1) ) and (j λe ), using an AND gate, only when PS λe The control word below (j λe )=1 and the upper control word (j λ(e+1) )=0, the obtained control word J makes the state of the follower switch ON; because (j λe ) and PS λeThe order is the same, so it is also named (j λe ) is the main control word, (j λ(e+1) ) is the slave control word.

[0080] Technical Feature 10: A controllable ON / OFF follower according to Technical Feature 9, characterized in that the bridge potential ADC based on the dual-control follower switch chain (PSC) design is called a PSC-type bridge potential ADC, referred to as bridge potential ADC2; specifically,

[0081] An n-bit dual-control follower switch bridge potential ADC includes m sub-stages StADC, m sub-stages (StADC α 、StADC β 、StADC γ ,…,StADC m ) are (q α ,q β ,q γ ,…,q m ), where m is the final stage, n = q α +q β +q γ +…+q m ;

[0082] The λth sub-stage StADC is a q λ StADC λ , including a q λ Bit-parallel ADCB λ , a bridge potential V λE An extraction module, an inter-level module,

[0083] The interstage module includes a sample-hold device T / H, a summer Σ λ , AM amplifier λ ;

[0084] The λth level analog signal voltage U λy After being connected to the sample-and-hold device T / H, it becomes a stable signal voltage U λZ , U λZ Two branches, one of which is sent to the summator Σ λ The minuend terminal is sent to the comparator chain as the non-inverting input terminal signal of each comparator, and compared with the reference potential connected to the inverting input terminal of each comparator; (the subscript Q λ Can't write, here below, subscript Q λ Written Qλ )

[0085] The q λ Bit-parallel ADCB λ Including a q λThe bit reference resistor chain (R λ0 、R λ1 、R λ2 ,…,R λ(Qλ-1) ), a q λ Bit comparator chain (C λ0 、C λ1 、C λ2 ,…,C λ(Qλ-1) , where comparator C λ0 Can be omitted), a q λ Bit encoder, the reference potential chain resistors are equal to form Q λ Reference potential points (V λ0 、V λ1 、V λ2 ,…,V λ(Qλ-1) );

[0086] The bridge potential V λE The extraction module consists of a λ A double-control follower switch (PS λ0 、PS λ1 、PS λ2 ,…,PS λ(Qλ-1) ) λ bit dual-control follower switch chain, the bridge potential V λE The mathematical expression is: V λE =INT(U λZ / ΔV)*ΔV

[0087] The inverting input terminals of each comparator in the comparator chain, the input terminals of each dual-control follower switch in the dual-control follower switch chain, and the reference potential points of the reference resistor chain are connected according to the corresponding relationship of the subscripts;

[0088] The dual-control follower switch PS λe Below is J λe , J on top λe , by PS λ0 of - J λ0 Connect to PS λ1 of + J λ1 、PS λ1 of - J λ1 Connect to PS λ2 of + J λ2 、PS λ2 of - J λ2 Connect to PS λ3 of + J λ3, ..., and so on, (PS λ0 、PS λ1 、PS λ2 ,…,PS λ(Qλ-1) ) forms Q λ -1 connection point, each connection point is J λe Marked, forming a double control follower switch PS λe Control word chain (J λ1 、J λ2 ,…,J λ(Qλ-1) ) and PS λ0 J λ0 Fixed connection 1, PS λ(Qλ-1) J λ(Qλ-1) Fixed to 0; that is, let j λ0 ≡1, j λQ ≡0;

[0089] The control word of the comparison word output terminal of the comparator chain (J λ1 、J λ2 ,…,J λ(Qλ-1) ) has two output directions, one output direction is the encoder, and the encoder gets the λth level ADCB λ Q λ The other output direction is connected to the corresponding subscript of the dual-control follower switch control word ( + J λ1 、 + J λ2 、…、 + J λ(Qλ-1) ), each output end of the dual-control follower switch is connected to the common output end BUS λ Then connected to the summer Σ λ The minuend end;

[0090] When the q λ Bit-parallel ADCB λ Get the analog signal voltage U λZ When U λZ The value must be between two reference potentials, where the following reference potential is defined as the bridge potential V λE , bridge potential V λE is not greater than and closest to U λZ The reference potential is expressed as: V λE =INT(U λZ / ΔV)*ΔV;

[0091] Bridge potential V λE The comparator output value corresponding to the subscript of the reference potential point below is equal to 1, which is greater than the bridge potential V λEThe comparator output value corresponding to the reference potential point of the value is equal to 0, that is, V λE The dividing point, V λE The output value of the comparator below is a string of 1s, V λE The output value of the comparator above is a string of 0s; only PS λE At the critical point where a string of 1s turns into a string of 0s, the dual-control follower switch PS λe The ON condition is: J λe =1 and J λ(e+1) =0; that is, only PS λE Meet J λE =1 and J λ(E+1) =0, the ON condition of other dual-control follower switches is that either the upper and lower control words are all 1 or the upper and lower control words are all 0, which does not meet the conduction condition; PS λE Turn ON the bridge potential V λE Take it out and send it to the common output terminal BUS λ , and then sent to the summator Σ λ Subtrahend terminal, summator Σ λ Conduct U λZ -V λE After the operation, a value smaller than ΔV is obtained, which is named as the mantissa voltage U λX , then through the AM amplifier λ Amplify 2^q λ times, U λX Expand to (-V REF ~V REF ) voltage range, becomes the next level StADC λ+1 The input signal U (λ+1)y ;

[0092] In this way, starting from level α, the conversion is performed one level after another, and finally an n-bit digital signal is obtained. BRIEF DESCRIPTION OF THE DRAWINGS

[0093] Objects are marked with symbols and symbol diagrams known in the industry. No specific description is required unless otherwise specified. Symbols include: resistor (R * ), potential (V * )、Signal voltage(u * ), diode (D * ), transistor (T * ), op amp (A * ), switch (S * ), control word (J * ); where “*” is a subscript wildcard.

[0094] Following the above naming rules, the symbols added in this article are: follower switch is named (S); dual control word follower switch is named (PS),

[0095] Symbols that have been explained before will not be explained again unless there is a special need.

[0096] All symbols can have subscripts and superscripts, which do not change the nature of the symbol; for example, J λe 、V λe 、S λe 、 & S λe Symbols such as J, V, S are still used to express the subscript λ and e are wildcard characters, indicating λ The e-th order of the level.

[0097] Figure 1 - Follower switch principle block diagram; including: S - follower switch block diagram; 1 - controllable operational amplifier block diagram (the basic operational amplifier is the one after removing the dotted box 13 from the controllable operational amplifier); 10 - input stage; 11 - intermediate stage; 12 - output stage; 13 - output tube control module (control module 13 that controls the ON / OFF state of output tubes T1 & T2); 14 - short-circuit branch (connect the inverting input terminal u N and the output end are short-circuited); 15-short-circuit control module (controls the ON / OFF state of the short-circuit branch 14); T1-NPN output tube; T2-PNP output tube; D1-bias diode of T1; D2-bias diode of T2; R1-bias resistor of T1; R2-bias resistor of T2; K1-first output control tube (controls ON / OFF of T1); K2-second output control tube (controls ON / OFF of T2); K F - short-circuit control tube (controls the ON / OFF of short-circuit branch 14); J- control word (control word that follows the ON / OFF of switch); V1- base potential of T1; V2- base potential of T2; u N -Inverting input terminal; u P -Non-inverting input terminal; u0-output terminal; +V CC -Power supply positive pole; -V CC ;-negative pole of power supply;

[0098] Figure 1.1 - Logic operation module; including: 16-logic operator; j1~j k -Logic signals

[0099] Figure 1.2 - Symbol diagram of follower switch; including: S - follower switch; u i -Following switch input terminal; u0-following switch output terminal;

[0100] Figure 2.1 - Schematic diagram of a bidirectional follower switch; including: u i / u o - Bidirectional follower switch input / output; u o / u i-Bidirectional follower switch output / input;.

[0101] Figure 2.2 - Bidirectional follower switch symbol diagram: including: & S-bidirectional follower switch;

[0102] ;

[0103] Figure 3.1 - Feedback sample-and-hold circuit; including: S1 - follower switch; A0 - input op amp; A1 - output op amp; C1 - sample-and-hold capacitor; CLK - clock pulse signal; V in - sampling input terminal; V out - Sample and hold output terminal;

[0104] Figure 3.2 - Series sample-and-hold circuit; including: S2 - follower switch; A2 - voltage follower; C2 - sample-and-hold capacitor;

[0105] Figure 3.3 - Sample-and-hold T / H symbol diagram;

[0106] Figure 4 - Lambda-level SDAC (sub-level DAC) constructed using multiple follower switches; including: dashed-line SDAC λ -λth level SDAC; dotted box MS λ -λth level multi-channel follower switch; dotted box SC λ -λth stage multi-way follower switch chain; dotted box RC λ - Lambda level reference resistor chain; YM λ -λth level decoder; (d λ2 d λ1 d λ0 )-digital input signal; (J λ7 ~J λ0 )-the control word output by the λth level decoder; (S λ7 ~S λ0 )-Follow switch, forming a follow switch chain; BUS λ - Common output terminal of the λth stage multi-way follower switch; d α2 d α1 d α0 -Input signal; (R λ7 ~R λ0 )-λth level reference resistor chain; (V λ7 ~V λ0 )-λth level reference voltage chain; V λE ~λth level bridge potential;

[0107] Figure 5 - Bridge Potential DAC; symbols are the same as those in Figure 4, with the addition of: WA λ -λth level weight operator;Σ-summator;V Σ -Summed voltage;

[0108] Figure 5.1 - One of the structures of the weighted operator. The structure of the circuit is too numerous to mention; this structure uses an inverse proportional op amp which is a good choice. λ -The sign and magnification of the weight operator; U out -Output signal; U in -Input signal; R F - Feedback resistor; R X - Inverting input resistance; WA λ =U out / U in =-R F / R X =-1 / 2 (λ-1)q , determine the resistance value according to needs;

[0109] Figure 5.2 - Symbolic diagram of the weight operator; symbols are the same as above;

[0110] Figure 6.1-MS type m*3bit bridge potential ADC block diagram (λth level); including: Symbols not previously shown: StADC1 λ -λth-level MS type m*3bit bridge potential ADC; SADC λ -λth stage fully parallel SUB-ADC module; CC λ (C λ7 ~C λ1 )-λ-stage comparator chain; ENC λ -λth level encoder; U λy -λth level input analog signal; U λ(y+1) -The λth level outputs analog signals; U λz -Analog signal after sampling and holding; V λE -bridge potential; U λX - Mantissa voltage after extracting the bridge potential.

[0111] Figure 6.2-PSC type m*3-bit bridge potential ADC block diagram (λth stage); including: Symbols not previously shown: StADC2 λ -λth level PSC type m*3bit bridge potential ADC; PSC λ -Level λ dual-control follower switch chain; (PS λ7 ~PS λ0 )-λth level double control follower switch.

[0112] Figure 6.3-PSC type m*3bit bridge potential ADC dual control follower switch PS; using an AND gate, when PS λe The control word below (j λe )=1 and the upper control word (j λ(e+1))=0, the obtained control word J makes the state of the follower switch ON; because (j λe ) and PS λe The order is the same, so it is also named (j λe ) is the main control word, (j λ(e+1) ) is the slave control word. Example

[0113] Example 1: Output control tubes K1 & K2 are composed of NPN transistors and short-circuit control tube K is composed of a bidirectional analog switch F Follow switch.

[0114] The first control tube K1 is used to control the ON / OFF of T1, and the second control tube K2 is used to control the ON / OFF of T2. K1 & K2 are collectively referred to as output control tubes. The bases of the two output control tubes K1 & K2 are controlled by the same control word J (the bases are connected to current limiting resistors as needed); the emitter of the first control tube K1 is connected to the power supply -V CC The collector is connected to the base of the NPN output transistor T1 to control the ON / OFF of the output transistor T1; the collector of the second control tube K2 is connected to the power supply +V CC The emitter is connected to the base of the PNP output transistor T2 to control the ON / OFF of the output transistor T2;

[0115] The second is the structure of the short-circuit control module 15: the short-circuit branch 14 is used to short-circuit the output terminal u o and the inverting input u N A short circuit control module 15 is connected to the short circuit branch 14 to control the ON / OFF of the short circuit branch 14; the short circuit control module 15 uses a bidirectional analog switch as a short circuit control tube K F ; Short-circuit control tube K F The ON / OFF state of the output control tube K1 & K2 is opposite to each other, that is, when K1 & K2 are OFF, K F Must be set to ON; otherwise, when K1 & K2 are set to ON, K F Must be set to OFF; if K F If the ON / OFF state of K1 & K2 is the same, use an inverter to adjust them to be mutually inverted;

[0116] J=0 or J=1 agreement: the control word J can be high or low, so that K1 & K2 are turned on and K F The OFF level is agreed to be "J=1", so that K1 & K2 are OFF and K F The ON level is designated as "J=0" (the state shown in FIG1).

[0117] Working principle of follower switch:

[0118] One is the principle of following the switch to ON: the necessary and sufficient condition for following the switch to ON is that the output control tubes K1 & K2 are OFF and the control tube K is short-circuited. F Set to ON;

[0119] When J = low level, K1 & K2 are turned OFF and K F Set to ON; K1 & K2 set to OFF can be regarded as K1 & K2 do not exist, so that the controllable op amp returns to the basic op amp state; at the same time, K F Setting ON means setting the controllable short-circuit branch 14 to a short-circuit state. The combination of these two states causes the follower switch to return to a basic follower state, that is, the follower switch is in the ON state;

[0120] The second is the principle of following the switch to OFF: the necessary and sufficient condition for following the switch to OFF is that the output control tubes K1 & K2 are turned ON (making the output tubes T1 & T2 turned OFF) and the control tube K is short-circuited. F Set OFF;

[0121] When J = high level, K1 & K2 are turned ON and K F Set OFF;

[0122] Because the main channel of K1 is connected across the base of the output transistor T1 and the power supply -V CC , so K1 is turned ON so that the base of T1 is connected to the power supply -V CC Connected, so that T1 is cut off; similarly, because the main channel of K2 is connected across the base of the output transistor T2 and the power supply +V CC , so K2 is turned ON so that the base of T2 is connected to the power supply +V CC Connected, so that T2 is cut off; that is, K1 & K2 are turned ON, so that T1 & T2 are both OFF, so that the output terminal u o Cut off with controllable op amp;

[0123] At the same time, K F Setting OFF means setting the controllable short-circuit branch 14 to an open circuit, so that the output terminal u o With the inverting input u N The short-circuit connection is cut off;

[0124] Output terminal u o The controllable operational amplifier is cut off and connected to the inverting input terminal u N Truncation, that is, the output u o All the previous circuits are cut off, so that the follower switch is in the OFF state;

[0125] Experiments show that, under the premise that the offset voltage of the basic operational amplifier is at the μV level, a resistor less than 10KΩ can be used as the K F , its following accuracy can reach 106 ~10 7 , and the ON resistance of the bidirectional analog switch is less than 100Ω; from an engineering point of view, it can be regarded as zero loss, so the follower switch can also be called a follower switch.

[0126] If K1&K2 and K F If the ON / OFF states of the two transistors are consistent, an inverter is used to make their ON / OFF states opposite.

[0127] This paper proposes several applications of follower switches: lossless sample-and-hold, multi-channel follower switches, bridge potential DACs, and bridge potential ADCs.

[0128] Example 2: A follower switch type sample-and-hold device constructed by a follower switch.

[0129] There are many types of sample-and-holds, the mainstream ones are feedback sample-and-hold and series sample-and-hold;

[0130] Some switching op amps are on when J = 0, and some switching op amps are on when J = 1. It is agreed here that no matter whether J = 0 or J = 1, the control word signal that puts the switching op amp in the ON state is named "ON signal", and the control word signal that puts the switching op amp in the OFF state is named "OFF signal";

[0131] Feedback sample-and-hold (Figure 3.1), the switching op amp SA1 acts as a sampling switch and input amplifier, and the non-inverting input of the switching op amp SA1 acts as the signal input terminal V in Its inverting input is connected to the output of the output amplifier A1 to form a large closed loop circuit. The feedback sampling and holding capacitor C1 is connected between the inverting terminal and the output of A1 to increase the charging and discharging speed. The clock pulse is connected to the control word of the switching amplifier. When the "ON signal" of the clock pulse CLK arrives, the switching amplifier SA1 is turned on, and the feedback sampling and holding capacitor C1 is connected to the input signal V in Sampling is performed. When the clock pulse CLK "OFF signal" arrives, the switching amplifier is turned off, and the feedback sampling and holding capacitor C1 holds the sampled signal and outputs the output signal V of the output amplifier A1. out Equal to the hold signal of C1;

[0132] Series sample-and-hold (Figure 3.2), follower switch S2 acts as a sampling switch, and its input signal is V in , the output amplifier A2 is connected as a voltage follower, the sampling and holding capacitor C2 is connected between the output terminal of S2 and the ground, the clock pulse is connected to the control word of S2, when the "ON signal" of the clock pulse CLK arrives, S2 is turned on, and the sampling and holding capacitor C2 is connected to the input signal V inSampling is performed. When the clock pulse CLK "OFF signal" arrives, S2 is turned off, and the sampling and holding capacitor C2 holds the sampled signal. The output signal Vout of the output amplifier A2 is equal to the holding signal of C2.

[0133] The following are the multi-channel follower switch, bridge potential DAC and bridge potential ADC. For the sake of simplicity, the following conventions are used:

[0134] (1) The multi-channel follower switch, bridge potential DAC and bridge potential ADC are collectively named "total device", and the total device is composed of multiple stages of "sub-stage devices";

[0135] (2) Imagine an m-level by 3-bit total device, consisting of m sub-level devices, with the subscripts α, β, γ, ..., m, representing the first, second, third, ..., and last levels. In principle, each sub-level device can have different bits, but for the sake of simplicity, it is agreed that the bit of each sub-level device is equal to 3.

[0136] ⑶Use λ to match all subscripts;

[0137] ⑷ The number system is bracketed with subscripts. Let the binary subscript be "2" and the octal subscript be "8". The default analog signal uses the octal system, that is, the analog signal without a subscript defaults to the octal number, such as 5 defaults to (5)8;

[0138] ⑸Digital signals are encoded according to natural codes;

[0139] Example 3: Multiway-Switch (MS) constructed by follower switches

[0140] q bit multiplexer MS, which consists of q bit decoder YM λ and q bit rail body switch chain SC λ That is, MS = YM + SC; if q = 3, it constitutes the dotted box MS in Figure 4 λ circuit; the decoder selects a follower switch in the switch chain according to the control word.

[0141] Example 4: A bridge potential DAC constructed on the basis of a multi-way switch; the bridge potential DAC consists of m SDACs λ constitute;

[0142] SDAC λ Contains three modules: decoder YM λ , S follows the switch chain SC λ (S Chain) and resistor chain RC λ (R Chain); among them, the decoder YM λ , S follows the switch chain SC λConstitutes a multi-way switch MS λ ;

[0143] For simplicity, let's first describe each SDAC as 3 bits, and let: Q = 2 q =2 3 =8;

[0144] Set the 3-bit multiplexer MS λ Then connect a 3-bit resistor chain RC λ , we can form (Figure 5) SDAC λ ;

[0145] Use 8 resistors of equal resistance in series to form a resistor chain RC λ , resistor chain RC λ Connect to voltage V REF and ground potential, V REF Divided into 8 equal parts, the voltage of each part ΔV is ΔV=V REF / 8; forming 8 reference potential points (V λ7 ~V λ0 ), that is, V0=0, V λ1 =ΔV, V λ2 =2ΔV,…,V λ7 =7ΔV, (V λ8 =V REF , does not serve as a reference potential point), called V λe is the λth level eth order reference potential; the multi-way switch MS λ (S λ7 ~S λ0 ) are connected to the corresponding reference potential point (V λ7 ~V λ0 ), (S λ7 ~S λ0 ) output terminal is connected to the output common terminal BUS λ , thus forming a 3-bit SDAC λ ;

[0146] m SDACs λ It can form a bridge potential DAC with a resolution of m*3 bits (Figure 5). The bridge potential DAC includes SDAC α 、SDAC β 、SDAC γ ,…,SDAC m Sub-level, when the bridge potential DAC receives an m*3bit digital signal, it sends the signal to each SDAC at the same time λ , when the λth stage receives the input signal (d λ2 d λ1 d λ0)=(E λ )8, S λE Channel ON, other channels S λe OFF, S λE V λE Transmit to the public BUS λ , (SDAC α 、SDAC β 、SDAC γ ,…,SDAC m )The common terminal potentials are: (V αE 、V βE 、V γE ,……,V mE ), V λE It has dual properties. On the one hand, it is an analog potential, and on the other hand, it corresponds to a digital signal. λ2 d λ1 d λ0 =(E λ )8, that is, V λE It is the bridge between analog signals and digital signals, so it is named "bridge potential"; bridge potential V λE After being extracted, it is provided to the next link:

[0147] To build a bridge potential DAC, you need to establish the "right bridge potential V λEW "The concept of the first level weight operator WA λ =1 / 2 (λ-1)*3 , although V αE ~V mE They are all bridge potentials, but it should be noted that the weights of the bridge potentials are different. It is necessary to λE Perform weight operation, the symbol of the λth level "weight operator" is WA λ , WA λ It is also the symbol of its magnification, WA λ =1 / 2 (λ-1)3 , we get the bridge potential V λEW :(V αE 、V βE / 2 3 、V γE / 2 6 ,……,V mE / 2 (m-1)3 ), the m weighted bridge potentials are summed up by the summator Σ to obtain the total output signal V Σ ;

[0148] Total output signal V Σ =(V αE +V βE / 2 3 +V γE / 2 6 +…+V mE / 2 (m-1)*3 ),

[0149] Thus, m 3-bit resolution SDACs are used. λ It forms a high-resolution bridge potential DAC with a resolution bit value of 3*m.

[0150] The same principle can be used to construct an m-level bridge potential DAC with different bit levels.

[0151] Compared with the 3-bit bridge potential DAC above, its construction principle is the same, except that the 3 bits of each level are changed to q λ bit( λ is the subscript of q), let: Q λ =2^q λ , multi-way switch MS λ and resistor chain RC λ All are q λ bit, multiplexer MS λ The A input terminal is connected to the resistor chain RC λ When the bridge potential DAC receives a digital signal of m levels with different bits, it sends the signal to each SDAC at the same time. λ , when the λth stage receives the input signal (d λ(q-1) …d λ1 d λ0 )=(E) Q When (the subscripts of q and Q are λ Can't write, didn't write), S λE Channel ON, other channels S λe OFF, S λE V λE Transmit to the public BUS λ , (SDAC α 、SDAC β 、SDAC γ ,…,SDAC m )The common terminal potentials are: (V αE 、V βE 、V γE ,……,V mE ), we can know that the bridge potential V λE The method is the same as before, except that the weight operator is WA λ =1 / 2^(q α +q β +…+q (λ-1) ), weight bridge potential V λEW =V λE *WAλ ,

[0152] Total output signal V Σ =(V αE +V βE *WA β +V γE *WA γ +…+V mE *WA m ),

[0153] The resolution of the bridge potential DAC is equal to the sum of the resolutions of each SDAC;

[0154] About 3bit*m-level bridge potential DAC weight operator WA λ =1 / 2 (λ-1)*3 Analysis: V αE The weight of is 1, because the α level has 3 bits before the β level, so V βE The weight is only 1 / 2 3 , using proportional op amps to connect into a "weight operator" WA β , magnification WA β =1 / 2 3 , for V βE The weight calculation results in the β-level weight bridge potential being V βEW ,V βEW =V βE / 2 3 Similarly, the γth level already has α and β levels 6 bits before it, so V γE The weight operator is WA γ =1 / 2 6 , the γth level weight bridge potential is V γEW =V γE / 2 6 ; There are already (λ-1)3 bits before the λth level, so V λE The weight operator is WA λ =1 / 2 (λ-1)3 ,

[0155] About the bridge potential DAC weight operator WA of m levels with different bits λ Analysis: V αE The weight of is 1, because there is already a q of level α before the β level. α bit, so V βE The weight is only 1 / 2^q α , using proportional op amps to connect into a "weight operator" WA β , magnification WA β =1 / 2^q α , for V βEThe weight calculation results in the β-level weight bridge potential being V βEW ,V βEW =V βE *WA β ; Similarly, the γth level is already preceded by the αth level q α bit and beta level q β bit, so V γE The weight operator is WA γ =1 / 2^(q α +q β ), the γth level weight bridge potential is V γEW =V γE / 2^(q α +q β ); Similarly, the WA of the λth level λ =1 / 2^(q α +q β +…+q (λ-1) ), weight bridge potential V λEW =V λE *WA λ .

[0156] Example 9: An MS-type bridge potential ADC constructed by combining a multi-way switch MS with a parallel ADC;

[0157] MS type m*q bit bridge potential ADC,

[0158] Architecture: It consists of m q bit StADC1 λ Composition, StADC1 λ =SADC λ +MS λ ;

[0159] If q=3, q bit StADC1 λ This constitutes the 3-bit StADC1 in Figure 6.1 λ Circuit;

[0160] Set the sign of the parallel SUB-ADC to SADC λ , SADC λ Q reference resistors of equal resistance are connected in series to form a resistor chain RC λ , V REF Divided into Q equal parts, each part voltage ΔV is ΔV=V REF / Q; forming Q reference potential points (V λ(Qλ-1) ~V λ0 ), that is, V0=0, V λ1 =ΔV, V λ2 =2ΔV,…,V λ(Qλ-1) =(Q λ-1)ΔV,(V λQλ =V REF , does not serve as a reference potential point), multi-way switch MS λ (S λ(Qλ-1) ~S λ0 ) are connected to the reference potential point (V λ(Qλ-1) ~V λ0 ), thus forming a q bit StADC λ ;

[0161] Working principle:

[0162] Step 1: Receive data from the previous level StADC λ-1 The transmitted analog signal U λy , after passing through the sample-and-hold device T / H, it is stabilized into an analog signal U λz , enter (parallel ADC) SADC λ Perform AD conversion; U λz is a (0V~V REF ) potential, there must be a reference potential V λE (E=0~(Q λ -1)), so that V λE λz <V λ(E+1) , based on the quantitative unit ΔV, V λE It is the sampling signal U λZ The integer part of V λE It is the bridge potential, the mantissa voltage U λX It is the sampling signal U λZ The decimal part, U λX <ΔV; mantissa voltage U λX , sampling signal U λZ and bridge potential V λE The relationship is: U λX =U λZ -V λE

[0163] Step 2: SADC λ V λE Converted into digital signal D (qλ-1) ...D0, D (qλ-1) ...D0 goes to two paths, one is used as AD conversion value, and the other is passed to the multiplexer MS λ , as a switch MS λ D input terminal d (q -1)…d0 input signal, the bridge potential V λE take out;

[0164] Step3: Change U​λZ and V λE Feed into the summator Σ λ , conduct U λX =U λZ -V λE Operation, get the mantissa voltage U λX , then through the AM amplifier λ Amplified Q times, it is still a (0V~V REF ) potential, becomes the next level StADC λ+1 The input signal U (λ+1)y ;

[0165] By converting one level at a time, m q-bit StADCs form an m*q-bit bridge potential ADC.

[0166] Example 10: A PSC-type bridge potential ADC constructed by combining an off / on chain PSC with a parallel ADC;

[0167] PSC type m*q bit bridge potential ADC, if q = 3, it forms the m*3bit bridge potential ADC of Figure 6.2;

[0168] Architecture: Set the sign of the parallel ADC to SADC λ , SADC λ Q reference resistors of equal resistance are connected in series to form a resistor chain RC λ , V REF Divided into Q equal parts, each part voltage ΔV is ΔV=V REF / Q; forming Q reference potential points (V λ(Q-1) ~V λ0 ), that is, V0=0, V λ1 =ΔV, V λ2 =2ΔV,…,V λ(Q -1)=(Q-1)ΔV,(V λQ =V REF , does not serve as a reference potential point), off / on chain PSC λ (PS λ(Q-1) ~PS λ0 ) are connected to the reference potential point (V λ(Q-1) ~V λ0 ), thus forming a 3-bit StADC λ ;PS λe The lower control word (J λe ) is a high ON word ( + J), upper control word (J λ(e+1) ) is low ON word ( - J), because (J λe ) and PSλe The order is the same, so it is also named (J λe ) is the main control word, (J λ(e+1) ) is the slave control word; in addition, let J λ0 ≡1, J λQ ≡0;

[0169] Working principle:

[0170] Step 1: Receive data from the upper level SADC (λ-1) The transmitted analog signal U λy , after passing through the sample-and-hold device T / H, it is stabilized into an analog signal U λz , enter (parallel ADC) SADC λ Perform AD conversion; U λz is a (0V~V REF ) potential, there must be a reference potential V λE (E=0~(Q-1)), so that V λE λz <V λ(E+1) , based on the quantitative unit ΔV, V λE It is the sampling signal U λZ The integer part of V λE It is the bridge potential, the mantissa voltage U λX It is the sampling signal U λZ The decimal part, U λX <ΔV; mantissa voltage U λX , sampling signal U λZ and bridge potential V λE The relationship is: U λX =U λZ -V λE

[0171] Step 2: SADC λ The comparator chain in the control word group (J λ(Q-1) ~J λ0 ) Get V λE ; It is particularly important to note that this control word group is different from the control word group of the decoder. In the control word group of the decoder, only the selected control word is equal to 0. In Figure 6.2, because the non-inverting input of the comparator is connected to U λZ The inverting input terminal is connected to the reference potential, so the control word group output by the comparator is (J λ0 ~J λE )=1,(J λ(E+1) ~J λQ )=0; It can be seen that J λ0 ~J λQ The point where 1...1 is about to change to 0...0 is the flip point J λE ​, the potential point it corresponds to is the bridge potential point V λE Of course, if the opposite is true, the inverting input of the comparator is connected to U λZ The non-inverting input terminal is connected to the reference potential, and the control word group output by the comparator is (J λ0 ~J λE )=0,(J λ(E+1) ~J λQ )=1, in this case, it needs to be adjusted to PS λe The upper control word (J λe ) is a high ON word ( + J), the control word below (J λ(e+1) ) is low ON word ( - J); control word group (J λ(Q-1) ~J λ0 ) is divided into two paths, one to the encoder ENC to form a digital signal, and the other to the switch chain. Note that PS λe The lower control word (J λe ) is a high ON word ( + J), upper control word (J λ(e+1) ) is low ON word ( - J); Referring to the previous analysis, it is known that the low ON word must be at a low level ( - J=0) and the high ON word is at high level ( + J=1), that is, + J / - J=1 / 0 (down 1 up 0), turn PS off / on λe It will be in the ON state, and this PS λe The A input terminal is connected to the bridge potential point, this PS λe It happens to be PS λE ;PS λE Set the bridge potential V λE Take it out and send it to the next link;

[0172] Step3: Change U λZ and V λE Feed into the summator Σ λ , conduct U λX =U λZ -V λE Operation, get the mantissa voltage U λX , then through the AM amplifier λ Amplified Q times, it is still a (0V~V REF ) potential, becomes the next level StADC (λ+1) The input signal U (λ+1)y ;

[0173] By converting one level at a time, m 3-bit StADCs constitute an m*3-bit bridge potential ADC.

Claims

1. The present invention is a follower with controllable ON / OFF, abbreviated as a follow switch, which adds two modules for controlling ON / OFF to a basic follower. One is the control module 13 for setting the ON / OFF state of output transistors T1&T2, abbreviated as the output transistor control module 13, and the other is the short-circuit control module 15 for setting the ON / OFF state of the short-circuit branch 14, abbreviated as the short-circuit control module 15. Specifically, One is the structure of the output transistor control module 13: An output transistor control module 13 is added to the structure of the basic operational amplifier in the basic follower (input stage 10 + intermediate stage 11 + output stage 12) to control the output transistors T1 & T2 in the output stage 12 to be turned ON / OFF, upgrading the basic operational amplifier to a controllable ON / OFF operational amplifier (the architecture of the solid rectangle 1 in Figure 1), simply referred to as a controllable operational amplifier; the output transistor control module 13 includes two control transistors K1 & K2 for controlling the output transistors T1 & T2 to be turned ON / OFF, where K1 is used to control the ON / OFF of T1 and is called the first control transistor, K2 controls the ON / OFF of T2 and is called the second control transistor, and K1 & K2 are collectively called the output control transistors. The control pins of the two output control transistors K1 & K2 are controlled by the same control word J; the two channel pins of the first control transistor K1 are respectively connected to the power supply -V CC and the base of the NPN output transistor T1 to control the ON / OFF of the output transistor T1; the two channel pins of the second control transistor K2 are respectively connected to the power supply +V CC and the base of the PNP output transistor T2 to control the ON / OFF of the output transistor T2; Second, it is the structure of the short - circuit control module 15: The short - circuit branch 14 is used to short - circuit the output terminal u o and the inverting input terminal u N . A short - circuit control module 15 is connected in the short - circuit branch 14 to control the ON / OFF of the short - circuit branch 14; The simplest structure of the short - circuit control module 15 is a short - circuit control transistor K F ; The ON / OFF states of the short - circuit control transistor K F and the output control transistors K1&K2 are opposite, that is, when K1&K2 are set to OFF, K F must be set to ON; conversely, when K1&K2 are set to ON, K F must be set to OFF; If the ON / OFF states of K F and K1&K2 are the same, an inverter is used to adjust them to be opposite; Convention for J = 0 or J = 1: The control word J can be at a high level or a low level, such that K1&K2 is set ON and K F The level convention for setting OFF is "J = 1", such that K1&K2 is set OFF and K F The level convention for setting ON is "J = 0" (the state shown in Figure 1). The working principle of the follow switch: One is the principle of following the switch being turned ON: The necessary and sufficient condition for the following switch to be turned ON is that the output control transistors K1 & K2 are turned OFF and the short-circuit control transistor K F is turned ON; When J = 0, turn K1&K2 OFF and turn K F ON; Turning K1&K2 OFF can be regarded as the non - existence of K1&K2, making the controllable operational amplifier return to the basic operational amplifier state; At the same time, turning K F ON means setting the controllable short - circuit branch 14 to the short - circuit state. The combination of these two states makes the follower switch return to the basic follower state, that is, makes the follower switch in the ON state; Second is the principle of the follower switch being turned OFF: The necessary and sufficient condition for the follower switch to be turned OFF is that the output control transistors K1&K2 are turned ON (causing the output transistors T1&T2 to be turned OFF) and the short-circuit control transistor K F is turned OFF; When J = 1, turn K1&K2 ON and turn K F OFF; Since the main channel of K1 is connected across the base of the output triode T1 and the power supply -V CC , turning K1 to ON connects the base of T1 to the power supply -V CC , rendering T1 cut off. Similarly, since the main channel of K2 is connected across the base of the output triode T2 and the power supply +V CC , turning K2 to ON connects the base of T2 to the power supply +V CC , rendering T2 cut off. That is, when K1 & K2 are turned to ON, both T1 & T2 are turned OFF, disconnecting the output terminal u o from the controllable operational amplifier; At the same time, K F Setting OFF means setting the controllable short - circuit branch 14 to an open circuit, so that the output terminal u o and the short - circuit connection line of the inverting input terminal u N is cut off; Output terminal u o Is truncated from the controllable operational amplifier and from the inverting input terminal u N That is, the output terminal u o Is truncated from all the previous circuits, so that the follower switch is in the OFF state; 2. A follower with controllable ON / OFF according to claim 1, characterized in that The output control transistors K1&K2 use triodes and corresponding base resistors, and short-circuit the control transistor K F Adopt bilateral analog switches; if the ON / OFF states of K1&K2 and K F are the same, then use an inverter to make their ON / OFF states opposite.

3. A follower with controllable ON / OFF according to claim 1, characterized in that Construct a bidirectional follow switch based on the follow switch. Specifically, Connect the follow switch S1 and the follow switch S2 in parallel forward and backward, and at the same time connect their control words to form a bidirectional follow switch; 4. A follower with controllable ON / OFF according to claim 1, characterized in that A sample and hold circuit constructed based on the follow switch. Specifically, Replace the switch in the existing sample and hold circuit with a follow switch to become a follow switch type sample and hold circuit, including a follow switch type feedback sample and hold circuit and a follow switch type series sample and hold circuit.

5. A follower with controllable ON / OFF according to claim 1, characterized in that Construct a multi-channel follow switch with multiple follow switches. Specifically, connect the input pins of multiple follow switches to form a common input pin type multi-channel follow switch, connect the output pins of multiple follow switches to form a common output pin type multi-channel follow switch MS, and connect the control pins of multiple follow switches to form a common control pin type multi-channel follow switch 6. A follower with controllable ON / OFF according to claim 1, characterized in that A bridge potential type DAC constructed based on the common output terminal multi-channel follow switch MS. Specifically, An n-bit DAC is composed of m SUB-DACs and a weighted sum amplifier (WAΣ), and SUB-DAC is abbreviated as SDAC; m SDACs of (Level α, Level β, Level γ, …, Level m) are respectively (SDAC α , SDAC β , SDAC γ , …, SDAC m ), and their bit numbers are respectively (q α , q β , q γ , …, q m ), where m is the last level, and n = q α + q β + q γ + … + q m ; Using the λ-th level SDAC λ Wildcard each level, the SDAC λ has a bit number of q λ , the SDAC λ includes a q λ -bit multiway switch MS λ (multiway switch) and a q λ -bit reference resistor chain RC λ (R-chain); The reference potential chain RC λ Each resistor is equal and is connected across (-V REF ~V REF ). Two qλ reference resistors (R λ0 , R λ1 , R λ2 , …, R λ(Qλ-1) ) divide (-V REF ~V REF ) into two qλ equal parts. For simplicity of analysis, let -V REF = 0, and the voltage ΔV of each equal part is ΔV = V REF / 2 qλ ; forming two qλ +1 potential points (V λ0 ~V λQλ ), among which there are two qλ reference potential points (V λ0 ~V λ(Qλ-1) ), that is, V λ0 = 0, V λ1 = ΔV, V λ2 = 2ΔV, …, V λ(Qλ-1) = (Q λ -1)ΔV, (V λQλ = Q λ ΔV = V REF , which does not act as a reference potential point), and V λe is called the reference potential of the λ-th level and the e-th order; The λ-th level multi-path follower switch MS λ includes a q λ -bit decoder YM λ and a q λ -bit follower switch chain SC λ =(S λ0 , S λ1 , S λ2 , …, S λ(Qλ-1) ); The multi-path follower switch MS λ has three groups of ports. One group is the control end - the control words (J λ0 , J λ1 , …, J λ(Qλ-1) ) of each follower switch; One group is the A input end - the A input ends of each follower switch (S λ0 , S λ1 , …, S λ(Qλ-1) ), and one group is the A output end - the A output ends of each follower switch; The q-bit decoder includes a D input terminal (d λ(q-1) …d λ1 d λ0 ), and Q λ = 2 qλ decoder output words (J λ0 , J λ1 , …, J λ(Qλ-1) ). The decoder output words are connected to the 2 qλ control words (J λ0 , J λ1 , …, J λ(Qλ-1) ) of the following switches according to the corresponding relationship with equal subscripts; The said 2 qλ following switches (S λ0 , S λ1 , …, S λ(Qλ-1) ) each A input terminal is connected to the said reference potential point (V λ0 , V λ1 , …, V λ(Qλ-1) ), and the A output terminals of all the following switches are connected to the λ-th stage common output terminal BUS λ (Figure 5); When SDAC λ The D input terminal (d λ(q-1) …d λ1 d λ0 ) After receiving the digital signal, it converts it into 2 qλ Base E λ , determine E λ After that, it will be in 2 qλ A selected word J is generated from the decoded output words λE , J λE Sent to the corresponding follower switch S λE Control word J λE , so that the follower switch S λE Set to ON, and the rest of the follow switches to OFF; S λE After turning ON, take out the corresponding reference potential point V λE =E*ΔV, completing the DA conversion of the λth level; V λE is both an analog potential and corresponds to a digital signal (d λ(q-1) …d λ1 d λ0 ), and is the bridge between the analog signal and the digital signal. Therefore, V λE is specifically named the "bridge potential"; successively obtain the bridge potentials (V λ , V αE , V βE , V γE , ……, V mE ) of each stage of SDAC; Bridge potential V at all levels λE has different weights WA λ , so it is necessary to multiply the bridge potential V λE by the weight WA λ to obtain the weighted bridge potential WV λE , that is, WV λE = WA λE * V λE ; for this purpose, it is necessary to send the bridge potential at all levels through the BUS lines (BUS α , BUS β , BUS γ , ……, BUS m ) to the weight arithmetic unit (Weight-ALU), that is, (WA α , WA β , WA γ , …, WA m ) for weight operation; the weight corresponding to WA λ is WA λ ; let WA α = 1, the weight of the (λ + 1)th stage is 2 qλ times smaller than that of the λth stage, that is, WA (λ+1) = WA λ / 2 qλ ; taking WA α as the reference, we get WA α = 1, WA β = 1 / 2 qα , WA γ = WA β / 2 qβ = 1 / 2 (qα+qβ) , …, WA m = WA (m-1) / 2 q(m-1) = 1 / 2 (qα+qβ+…+q(m-1)) (Note, 2 here (qα+qβ+…+q(m-1)) in which (α, β, …, (m - 1)) are the subscripts of q) The bridge potentials at all levels are summed by the summer Σ λ After summation, the total DAC output voltage V out is obtained, that is, V out = WV αE + WV βE + WV γE +…+ WV λm = WA αE * V αE + V αE + WA β * V βE + WA γ * V γE +…+ WA m * V λm = V αE + V βE / 2 qα + V γE / 2 qα+qβ +…+ V λm / 2 qα+qβ+…+q(m-1) ； 7. A follower with controllable ON / OFF according to claim 6, characterized in that An MS type bridge potential pipelined ADC1, abbreviated as bridge potential ADC1, is formed by replacing the SDAC in the pipelined ADC with a common output terminal multi-channel follow switch (MS). Specifically, The bridge-potential ADC1, like the traditional pipelined ADC, is composed of multiple stages of Stage-ADCs λ connected stage by stage. To distinguish between the two, hereinafter, the Stage-ADC of the type-1 bridge-potential ADC1 λ will be abbreviated as StADC1 λ , and the Stage-ADC of the traditional pipelined ADC λ will be abbreviated as StaADC λ ; StaADC λ includes a SUB-ADC λ (abbreviated as SADC λ ), a SUB-DAC λ (abbreviated as SDAC λ ) and an interstage module ISM λ (Interstage module); while StADC1 λ only replaces the SDAC in StaADC λ with a multiplexed follower switch; that is, the said StADC1 λ (Fig. 6.1) includes a SADC λ , a multiplexed follower switch MS λ and an interstage module ISM λ , λ ​ The StADC1 λ SADC λ includes a reference resistor chain RC λ , a comparator chain CC λ , an encoder ENC λ ; The reference potential chain RC λ Each resistor is equal and is connected across (-V REF ~V REF ). Two qλ reference resistors (R λ0 , R λ1 , R λ2 , …, R λ(Qλ-1) ) divide (-V REF ~V REF ) into two qλ equal parts, and the voltage ΔV of each part is ΔV = V REF / 2 qλ ; for simplicity of analysis, hereinafter, by translation, -V REF = 0 is set, so that the reference resistor chain RC λ forms (2 qλ +1) potential points (V λ0 ~V λQλ ), among which there are two qλ reference potential points (V λ0 ~V λ(Qλ-1) ), that is, V λ0 = 0, V λ1 = ΔV, V λ2 = 2ΔV, …, V λ(Qλ-1) = (Q λ -1)ΔV, (V λQλ = Q λ ΔV = V REF , which does not act as a reference potential point), and V λe is called the reference potential of the λ-th level and the e-th order; The comparator chain CC λ consists of (2 qλ - 1) comparators (C λ0 , C λ1 , R λ2 , …, C λ(Qλ-1) ) connected across (-V REF ~V REF ), where C λ0 is virtual; Resistance chain and comparator chain CC λ There are two connection relationships. The first one is that the input signal U λy is connected to the non-inverting input terminals of each comparator after passing through the sample and hold circuit. The reference potential points (V λ1 ~V λ(Qλ-1) ) are connected to the inverting input terminals of the corresponding comparators (C λ1 ~C λ(Qλ-1) ). The second one is just the opposite. The input signal U λy is connected to the inverting input terminals of each comparator after passing through the sample and hold circuit. The reference potential points (V λ1 ~V λ(Qλ-1) ) are connected to the non-inverting input terminals of the corresponding comparators (C λ1 ~C λ(Qλ-1) ). The principles of the two are the same. In this article, the first connection relationship is adopted for analysis; The λ-th level multi-path follower switch MS λ includes a q λ -bit decoder YM λ and a q λ -bit follower switch chain SC λ =(S λ0 , S λ1 , …, S λ(Qλ-1) ); The said q λ -bit decoder includes a D input terminal (d λ(q-1) … d λ1 d λ0 ) and Q λ = 2 qλ decoded output words (J λ0 、J λ1 、…、J λ(Qλ-1) ); The 2 in the following switch chain qλ following switches (S λ0 , S λ1 , …, S λ(Qλ-1) ), whose A inputs are correspondingly connected to 2 qλ reference potential points (V λ0 , V λ1 , …, V λ(Qλ-1) ), all of whose A outputs are connected to the common output terminal BUS λ of the λ-th stage, and whose control words (J λ0 , J λ1 , …, J λ(Qλ-1) ) are correspondingly connected to the output words (J λ , J λ0 , …, J λ1 , …, J λ(Qλ-1) ) of the decoder YM λ ; The q-bit decoder includes a D input terminal (d λ(q-1) …d λ1 d λ0 ) and 2 qλ decoded output words (J λ0 、J λ1 、…、J λ(Qλ-1) ), and the decoded output words are correspondingly connected to the 2 qλ control words (J λ0 、J λ1 、…、J λ(Qλ-1) ) following the switches; The said 2 qλ The A input terminals of the following switches are connected to the said reference potential point according to the corresponding subscripts, and the output terminals of all the following switches are connected to the λ-th stage common output terminal BUS λ ; When SDAC λ The D input terminal (d λ(q-1) …d λ1 d λ0 ) After receiving the digital signal, it converts it into 2 qλ Base E λ , determine E λ After that, it will be in 2 qλ A selected word J is generated from the decoded output words λE (Note: Under the premise of knowing that it is at the λ level, the subscript E is used by default. λ Indicated by E), J λE Sent to the corresponding follower switch S λE Control word J λE , so that the follower switch S λE Set to ON, and the rest of the follow switches to OFF; S λE After turning ON, take out the corresponding reference potential point V λE =E*ΔV, completing the DA conversion of the λth level; The q-bit decoder includes a D input terminal (d λ(q-1) …d λ1 d λ0 ) and 2 qλ decoded output words (J λ0 、J λ1 、…、J λ(Qλ-1) ), and the decoded output words are correspondingly connected to the 2 qλ control words (J λ0 、J λ1 、…、J λ(Qλ-1) ) following the switches; The said 2 qλ The A input terminals of the following switches are connected to the said reference potential point according to the corresponding subscripts, and the output terminals of all the following switches are connected to the λ-th stage common output terminal BUS λ ; The inter-stage module ISM λ includes a summer Σ λ , an amplifier AM λ (collectively referred to as the summer and amplifier Σ&AM λ ) and a sample-and-hold circuit T / H; When SDAC λ The D input terminal (d λ(q-1) …d λ1 d λ0 ) After receiving the digital signal, it converts it into 2 qλ Base E λ , determine E λ After that, it will be in 2 qλ A selected word J is generated from the decoded output words λE (Note: Under the premise of knowing that it is at the λ level, the subscript E is used by default. λ Indicated by E), J λE Sent to the corresponding follower switch S λE Control word J λE , so that the follower switch S λE Set to ON, and the rest of the follow switches to OFF; S λE After turning ON, take out the corresponding reference potential point V λE =E*ΔV, completing the DA conversion of the λth level; The inter-stage module includes a sample-and-hold circuit T / H and a summer Σ λ and an amplifier AM λ ; The extraction module of the bridge potential V λE includes a q λ -bit multiplexed follower switch; the q λ -bit multiplexed follower switch includes a q λ -bit decoder, a follower switch chain (S λ0 , S λ1 , S λ2 , …, S λ(Qλ-1) ), and the output terminals of its respective follower switches are connected to the common output terminal BUS λ ; The Α input terminals of the respective follow switches in the follow switch chain, the inverting input terminals of the respective comparators in the comparator chain, and the respective reference potential points of the reference resistor chain are connected according to the corresponding relationship of the subscripts; 8. A follower with controllable ON / OFF according to claim 1, characterized in that Perform logical operations on multiple logical signals with a logical operation unit, including a combinational logic operation unit and a sequential logic operation unit, to obtain a control word J for controlling the ON / OFF of the follow switch; 9. The follower with controllable ON / OFF according to claim 8, characterized in that An AND gate is used to operate on two control signals to obtain the dual-control follow switch PS λe ; Specifically The dual-control follow switch PS λe has two control signals (j λ(e+1) ) and (j λe ). Using an AND gate, only when the lower control word (j λe ) of PS λe ) = 1 and the upper control word (j λ(e+1) ) = 0, the obtained control word J makes the state of the follow switch ON; 10. A follower with controllable ON / OFF according to claim 9, characterized in that, A bridge potential ADC designed based on a dual-control follow switch chain (PSC), called a PSC type bridge potential ADC, abbreviated as bridge potential ADC2; specifically, An n-bit dual-control following-switch bridge potentiometric ADC includes m sub-stage StADCs. The number of bits of the m sub-stages (StADC α , StADC β , StADC γ , …, StADC m ) are respectively (q α , q β , q γ , …, q m ), where m is the last stage, and n = q α + q β + q γ + … + q m ; The λ-th level sub-StADC is a q λ -bit StADC λ , including a q λ -bit parallel ADCB λ , a bridge potential V λE extraction module, and an inter-stage module. The inter-stage module includes a sample and hold circuit T / H and a summer Σ λ , an amplifier AM λ ; The λ-th level analog signal voltage U λy After being processed by the sample and hold circuit T / H, it becomes a stable signal voltage U λZ , U λZ Branches into two paths. One path is sent to the minuend terminal of the summer Σ λ , and the other path is sent to the in-phase input terminal signal of each comparator in the comparator chain to be compared with the reference potential connected to the inverting input terminal of each comparator; (The subscript of subscript Q λ Can't be written. Hereinafter, subscript Q λ Is written as Qλ ) The said q λ bit parallel ADCB λ includes a q λ bit reference resistor chain (R λ0 , R λ1 , R λ2 , …, R λ(Qλ-1) ), a q λ bit comparator chain (C λ0 , C λ1 , C λ2 , …, C λ(Qλ-1) , where the comparator C λ0 can be omitted), a q λ bit encoder. The resistors of the reference potential chain are equal, forming Q λ equally spaced reference potential points (V λ0 , V λ1 , V λ2 , …, V λ(Qλ-1) ); The bridge potential V λE extraction module includes a q λ -bit dual-control follower switch chain composed of Q λ0 dual-control follower switches (PS λ1 , PS λ2 , PS λ(Qλ-1) ), …, PS λ . The mathematical expression of the bridge potential V λE is: V λE = INT(U λZ / ΔV)*ΔV The inverting input terminals of the respective comparators in the comparator chain, the input terminals of the respective dual-control follow switches in the dual-control follow switch chain, and the respective reference potential points of the reference resistor chain are connected according to the corresponding relationship of the subscripts; The dual-control follower switch PS λe Below is J λe , J on top λe , by P.S. λ0 of - J λ0 Connect to PS λ1 of + J λ1 ,PS λ1 of - J λ1 Connect to PS λ2 of + J λ2 ,PS λ2 of - J λ2 Connect to PS λ3 of + J λ3 , ..., and so on, (PS λ0 ,PS λ1 ,PS λ2 , …, PS λ(Qλ-1) ) forms Q λ -1 connection point, each connection point is J λe Mark out to form a double-control follower switch PS λe Control word chain (J λ1 , J λ2 , …, J λ(Qλ-1) ), and PS λ0 J λ0 Fixed connection 1, PS λ(Qλ-1) J λ(Qλ-1) Fixed to 0; that is, let j λ0 ≡1, j λQ ≡0; The comparison word output terminals of the comparator chain control word (J λ1 、J λ2 、…、J λ(Qλ-1) ) have two output directions. One output direction is to the encoder, and through the encoder, the q λ -bit digital signal of the λ-th level ADCB λ is obtained to implement the AD conversion of the λ-th level; the other output direction is to be connected as a control word to the dual-control follow switch control word of the corresponding subscript ( + J λ1 、 + J λ2 、…、 + J λ(Qλ-1) ). Each output terminal of the dual-control follow switch is connected to the common output terminal BUS λ and then connected to the minuend terminal of the summator Σ λ ; When the q λ -bit parallel ADCB λ obtains the analog signal voltage U λZ , the value of U λZ must be between two reference potentials. Among them, the following reference potential is defined as the bridge potential V λE , and the bridge potential V λE is the reference potential that is not greater than and closest to U λZ , and its mathematical expression is: V λE = INT(U λZ / ΔV)*ΔV; Bridge potential V λE and the comparator output values corresponding to the subscripts of the reference potential points below are equal to 1, greater than the bridge potential V λE The comparator output values corresponding to the subscripts of the reference potential points greater than the value are equal to 0, that is, with V λE as the demarcation point, V λE and the following comparator output values are a string of 1s, V λE The above comparator output values are a string of 0s; only when PS λE is at the critical point where a string of 1s becomes a string of 0s, the dual-control follower switch PS λe is set to ON with the condition: J λe = 1 and J λ(e+1) = 0; that is, only when PS λE meets the ON condition of J λE = 1 and J λ(E+1) = 0, for other dual-control follower switches, either the upper and lower control words are all 1 or the upper and lower control words are all 0, not meeting the conduction condition; when PS λE is set to ON, the bridge potential V λE is taken out and sent to the common output terminal BUS λ , and then sent to the summing amplifier Σ λ subtraction terminal. The summing amplifier Σ λ performs U λZ - V λE operation to obtain a value less than ΔV, named the mantissa voltage U λX , and then amplified by 2^q λ times by the amplifier AM λ , expanding U λX to the voltage range of (-V REF ~V REF ), becoming the input signal U λ+1 of the next-stage StADC (λ+1)y ; In this way, starting from the α level, it is converted level by level backward, and finally an n-bit digital signal is obtained.

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