Half-integer frequency division system and frequency divider

Abstract

The present application discloses a half-integer frequency division system and a frequency divider. The frequency division system comprises: a countdown unit, configured to perform down counting on a set frequency division ratio n, and perform OR operation on a count value generated in real time so as to generate a first signal; a frequency division delay unit, configured to perform first frequency division on the first signal, perform XNOR operation on the frequency-divided first signal and an input clock to generate a second signal, and use the second signal as a counting clock of a counter in the countdown unit, so as to adjust the frequency division ratio of the first signal; and a frequency division output unit, configured to perform second frequency division on the first signal after the frequency division ratio is adjusted, so as to output an output signal having a required frequency division ratio. The half-integer frequency division system provided by the present application avoids the additional increase of the number of timers and the number of registers in a clock phase inversion mode, has a simple circuit structure, can achieve three frequency division modes of 2n, 2n+0.5, and 2n+1, supports the maximum frequency of 17 GHz, and satisfies the requirements of various application scenarios.

Description

Half-integer frequency division system and divider

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority and the benefit of patent application No. 202311853260.9 filed with the State Intellectual Property Office of China on December 28, 2023, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] The present application belongs to the field of digital circuit technology, and specifically relates to a half-integer frequency division system and a frequency divider. Background Art

[0004] Frequency dividers are a crucial component of digital circuit systems, placing high demands on clock signal properties in digital circuit design. With the increasing integration density and complexity of digital circuits, clock signal generation in synchronous circuit systems is becoming increasingly complex. This often places high demands on both area and performance for very large-scale integrated circuit systems like field programmable gate arrays (FPGAs). To meet the requirements of the FPGA fabric (FPGA soft logic), a serializer / deserializer (SerDes) is required to internally divide the parallel clock and output it to the fabric. Due to the wide range of protocols and rates required, the frequency divider must support division ratios of 2n, 2n+1, and 2n+0.5, and a maximum input frequency of 17 GHz.

[0005] Traditional frequency dividers require additional counters and registers to implement 2n+1 and 2n+0.5, which complicates the circuit structure, increases design difficulty, and wastes layout space. Furthermore, the duty cycle in the 2n+1 frequency division mode may not be 50%, and the duty cycle in the 2n+0.5 frequency division mode may be too small. Therefore, finding a frequency divider with simple logic, configurable frequency division, and the ability to achieve a 50% duty cycle in the 2n+1 frequency division mode is an urgent problem to be solved. Summary of the Invention

[0006] The present application provides a half-integer frequency division system and a frequency divider, which are used to solve the problem that the existing frequency divider has complex logic and cannot achieve a 50% duty cycle in a 2n+1 frequency division mode.

[0007] In order to solve the above technical problems, the present application provides a half-integer frequency division system, which includes:

[0008] A down-counting unit, configured to perform a down-count on the configured frequency division ratio n and generate a first signal by performing an OR operation on the count value generated in real time;

[0009] a frequency division delay unit, configured to perform a first frequency division on the first signal, perform an XOR operation on the divided first signal and an input clock to generate a second signal, and use the second signal as a counting clock for a counter in the down-counting unit to adjust a frequency division ratio of the first signal;

[0010] The frequency division output unit is used to perform a second frequency division on the first signal after the frequency division ratio is adjusted, so as to output an output signal with a required frequency division ratio.

[0011] As a further improvement of the present application, the frequency division ratio n configured is a decimal positive integer, and the frequency division ratio n is converted into a corresponding binary number (q x … q1 q0), the first signal generated at this time Among them, q x Indicates the xth bit of the binary number corresponding to the division ratio n.

[0012] As a further improvement of the present application, the down-counting unit is also used to trigger the first signal load to pull down the level when the real-time generated count value is reduced to 1, so that the down-counting unit completes the resetting of the count value when the next clock edge of the input clock clk_in arrives.

[0013] As a further improvement of the present application, the frequency division delay unit is provided with a delay sub-unit for delaying the first signal load and the first signal load_div after frequency division, so that when the first signal load_div after frequency division is subjected to an exclusive OR operation with the input clock clk_in, the time when it arrives at the input end of the exclusive OR gate is aligned with the clock edge of the input clock clk_in.

[0014] As a further improvement of the present application, the delay subunit includes a first delay subunit and a second delay subunit;

[0015] The frequency division delay unit is used to delay the generated first signal load through the first delay sub-unit, and to time synchronize the divided first signal load_div through the input clock clk_in, and then delay the time-synchronized first signal load_div through the second delay sub-unit, so that the time when the delayed first signal load_div arrives at the input end of the exclusive-OR gate is aligned with the clock edge of the input clock clk_in.

[0016] As a further improvement of the present application, the second signal clk_xnor_o is a signal generated by performing an exclusive OR operation on the divided first signal load_div and the input clock clk_in, and the generated second signal clk_xnor_o is used as the counting clock of the counter in the down counting unit to adjust the division ratio of the first signal load.

[0017] As a further improvement of the present application, two frequency division sub-units are provided in the frequency division delay unit, each of the frequency division sub-units adopts two-division, and the frequency division ratio of the first signal load is adjusted by adjusting the access status of the two frequency division sub-units.

[0018] As a further improvement of the present application, the second frequency division is to divide the first signal load_out after the frequency division ratio is adjusted by two, so as to output the output signal clk_out with the required frequency division ratio of 2n, 2n+1, and 2n+0.5;

[0019] When the first signal load_out with the division ratio of n is divided into two, the division ratio of the output signal clk_out is 2n; when the first signal load_out with the division ratio adjusted to n+0.5 is divided into two, the division ratio of the output signal clk_out is 2n+1; when the first signal load_out with the division ratio adjusted to n+0.25 is divided into two, the division ratio of the output signal clk_out is 2n+0.5.

[0020] The present application also provides a half-integer frequency divider, which includes any of the above-mentioned half-integer frequency division systems.

[0021] The present application provides a half-integer frequency division system and a frequency divider, which have the following beneficial effects:

[0022] The present application generates a first signal by performing a countdown count of the configured frequency division ratio through a down counter, performs a first frequency division on the first signal, performs an XOR operation on the divided first signal and the input clock to generate a second signal, and uses the second signal as the counting clock of the counter. At the same time, the first signal after the frequency division ratio is adjusted is subjected to a second frequency division, so as to avoid adding an additional timer and a number of registers by means of clock inversion. The circuit structure is simple, the occupied area of ​​the layout is reduced, and the power consumption is reduced. It can realize three frequency division modes of 2n, 2n+0.5, and 2n+1, so that the duty cycle of the 2n+1 frequency division clock is controlled at 50%, and the duty cycle of the 2n+0.5 frequency division clock is increased to be close to 50%. The maximum frequency supports 17GHz, which can meet the needs of various application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only part of the embodiments of the present application, rather than all the embodiments. For ordinary technicians in this field, without paying any creative work, other drawings obtained based on these drawings are all within the scope of protection of this application.

[0024] FIG1 is a schematic structural diagram of a half-integer frequency division system provided in an embodiment of the present application;

[0025] FIG2 is a schematic structural diagram of the first-stage frequency division in a half-integer frequency division system provided in an embodiment of the present application;

[0026] FIG3 is a timing diagram generated when n=2 in a half-integer frequency division system provided by an embodiment of the present application;

[0027] FIG4 is a timing diagram of a conventional frequency divider provided in the prior art at 2n+1;

[0028] FIG5 is a timing diagram of a conventional frequency divider provided in the prior art when 2n+0.5 is used;

[0029] FIG6 is a diagram showing a specific embodiment of a half-integer frequency division system provided in an embodiment of the present application;

[0030] FIG7 is a waveform simulation diagram of a half-integer frequency division system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solutions and advantages of this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0032] In order to make the description of the contents of this disclosure more detailed and complete, the following is an illustrative description of the implementation methods and specific examples of this application; however, this is not the only form of implementing or using the specific embodiments of this application. The implementation methods cover the features of multiple specific embodiments and the method steps and their sequence for constructing and operating these specific embodiments. However, other specific embodiments can also be used to achieve the same or equal functions and step sequences. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0033] It should be noted that the terms "first," "second," and the like in the specification and claims of this application and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, such that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0034] In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in the text is merely a description of the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, "multiple" refers to two or more than two, and other quantifiers should be understood similarly. The preferred embodiments described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In addition, the embodiments of the present application and the features in the embodiments may be combined with each other unless there is a conflict.

[0035] Referring to Figures 1-7, embodiments of the present application provide a half-integer frequency division system to address the issue of complex logic in existing frequency dividers and the inability to achieve a 50% duty cycle in the 2n+1 frequency division mode. Referring to Figure 1, a schematic diagram of the structure of the half-integer frequency division system provided by the present application is shown. The half-integer frequency division system includes a down-counting unit, a frequency division delay unit, and a frequency division output unit.

[0036] The above-mentioned down-counting unit is used to count down the configured division ratio n, and generate the first signal load through an OR operation on the count value generated in real time. The above-mentioned division delay unit is used to perform a first division on the first signal load, perform an exclusive OR operation on the divided first signal load_div and the input clock clk_in to generate the second signal clk_xnor_o, and use the second signal clk_xnor_o as the counting clock of the counter in the down-counting unit to adjust the division ratio of the first signal load. The above-mentioned division output unit is used to perform a second division on the first signal load_out after the adjustment of the division ratio to output the output signal clk_out with the required division ratio.

[0037] As an optional embodiment, the counter used in the subtraction counting unit of the present application is a subtraction counter, which is used to count down the configured frequency division ratio n. Here, n is a decimal positive integer. When counting down, the subtraction counter converts the frequency division ratio n into a corresponding binary number (q x … q1 q0), the output of the counter is used as the output signal of the down-counting unit after OR operation, that is, as the first signal load. The first signal generated at this time Among them, q x Indicates the xth bit of the binary number corresponding to the division ratio n.

[0038] Furthermore, the down-counting unit is further configured to trigger the first signal load to be pulled down when the real-time count value is reduced to 1, so that the down-counting unit completes resetting the count value when the next clock edge of the input clock clk_in arrives.

[0039] In an embodiment of the present application, please refer to Figure 6, which is a specific embodiment diagram of a half-integer frequency division system provided in an embodiment of the present application. In this application, the above-mentioned down-counting unit and the frequency division delay unit are used as the first-level frequency division, and the above-mentioned frequency division output unit is used as the second-level frequency division. At this time, the first signal load generated is used as both the output signal load_out of the first-level frequency division and the set signal load for setting the counter. At the same time, the above-mentioned first signal load is transmitted to the frequency division delay unit to divide the frequency to generate the load_div signal and perform an exclusive OR operation with the input clock clk_in.

[0040] Specifically, when the frequency division ratio n is configured to be 5, the down-counting unit converts the frequency division ratio 5 into the corresponding binary number (101), and the first signal generated at this time is When the count value generated in real time is reduced to 1 (001), the first signal load generated is triggered to be 0 as a set signal to set the down counter, so that the down counter completes the reset of the count value when the next clock edge of the input clock clk_in arrives, and sets (001) to (101) to count down again, and repeats in sequence.

[0041] As an optional implementation, please continue to refer to Figure 1. The frequency division delay unit provided in the present application is provided with a delay sub-unit for delaying the first signal load and the divided first signal load_div. The purpose of setting the delay sub-unit here is to make the time when the divided first signal load_div reaches the input end of the XOR gate when performing the XOR operation with the input clock clk_in is aligned with the clock edge of the input clock clk_in.

[0042] In an embodiment of the present application, the above-mentioned delay subunit includes a first delay subunit and a second delay subunit. Please refer to Figure 2, which is a structural diagram of the first-level frequency division in the half-integer frequency division system provided in an embodiment of the present application. It can be observed that the above-mentioned first delay subunit and the second delay subunit correspond to delay1 and delay2 in Figure 2, respectively. The frequency division delay unit provided in the present application is used to delay the generated first signal load through the first delay subunit, and to time synchronize the divided first signal load_div through the input clock clk_in, and then delay the time-synchronized first signal load_div through the second delay subunit, so that the time when the delayed first signal load_div arrives at the input end of the exclusive-OR gate is aligned with the clock edge of the input clock clk_in.

[0043] It should be noted that the above-mentioned first delay sub-unit is used to delay the first signal load based on one clock cycle of the input clock clk_in, and the above-mentioned second delay sub-unit is used to delay the first signal load_div after time synchronization based on two clock cycles of the input clock clk_in. Of course, it is also feasible to use other clocks as the reference for delay. As long as the time when the delayed first signal load_div arrives at the input end of the XOR gate can be aligned with the clock edge of the input clock clk_in, other delay references selected are feasible, and this application does not impose further restrictions on this.

[0044] Specifically, please refer to Figure 3, which is a timing diagram generated when n=2 in the half-integer division system provided in an embodiment of the present application. The figure shows the waveforms of each signal when the division ratio is 2. It can be observed that the first signal load undergoes a clock phase flip after being delayed by delay1, and then generates load_div after the first division. The time when it arrives at the input of the XOR gate after being delayed by delay2 is exactly aligned with the clock edge of the input clock clk_in, and the clock phase flip is also achieved. At this time, load_out also has a half-integer period, achieving a 2.5-divided clock, but the load_out duty cycle is obviously less than 50% at this time.

[0045] Please refer to Figure 4, which shows the timing diagram of a conventional divider in the prior art for the 2n+1 case. Conventional dividers use a counter to count on the rising or falling edges of the input clock. The counter starts at 0 and flips at counts n-1 and 2n-1, respectively, to produce a clock with a 2n frequency division. Conventional 2n+1 frequency division also uses a 2n frequency division method, flipping at n and 2n, but the resulting duty cycle is n / (2n+1), which is not 50%. To achieve a 2n+1 frequency division with a 50% duty cycle, an additional set of counters triggered by the falling edge of the input clock is required. These two sets of clocks are then ORed together to produce a 2n+1 frequency division clock with a 50% duty cycle. However, this method requires an additional set of counters. When n is large, the number of required registers doubles, which takes up more board space and increases power consumption.

[0046] Please refer to Figure 5, which is a timing diagram generated when 2n+0.5 is used in a traditional divider provided in the prior art. The traditional method of 2n+0.5 division is the same as n+1 division. Two clocks are generated by the rising edge and the falling edge respectively. The high level of out_up lasts for 2n+1 input clock cycles, and the low level of out_down lasts for 2n input clock cycles. The phase difference between the two is n cycles. Finally, the two clocks are ANDed to obtain a 2n+0.5 divided clock. However, this method has the same disadvantages as 2n+1, namely, requiring an additional set of counters and a very small duty cycle. In addition, generating the two sets of out_up / down clocks also consumes more resources.

[0047] Therefore, the present application sets the divided first signal load_div to perform an XOR operation with the input clock clk_in to generate a second signal clk_xnor_o. Please continue to refer to Figure 5. The present application uses the generated second signal clk_xnor_o as the counting clock of the counter in the down-counting unit to adjust the division ratio of the first signal load; that is, at this time, when the down-counter in the down-counting unit performs countdown, it uses the generated second signal clk_xnor_o as the counting clock, thereby cleverly adjusting the division ratio of the first signal load in this way, avoiding the need to add an additional set of timers and a number of registers, reducing the occupied area of ​​the layout, and reducing power consumption.

[0048] Specifically, how to adjust the division ratio of the first signal load is now explained in detail. The division delay unit provided in the present application is provided with two division sub-units, and each division sub-unit is composed of a two-division circuit. As long as the two-division circuit structure can achieve the output of one cycle for every two cycles of the clock triggered, it is feasible. Therefore, the present application does not impose further restrictions on the specific structure of the division sub-unit.

[0049] In an embodiment of the present application, the frequency division ratio of the first signal load can be adaptively adjusted by adjusting the access status of the above-mentioned two frequency division sub-units. Please continue to refer to Figure 6. When one of the frequency division sub-units is connected, the first frequency division performed by the frequency division delay unit corresponds to dividing the first signal load by two. At this time, the frequency division ratio of the first signal load is adjusted to n+0.5 division. When two frequency division sub-units are connected, the first frequency division performed by the frequency division delay unit corresponds to dividing the first signal load by four. At this time, the frequency division ratio of the first signal load is adjusted to n+0.25 division. When both frequency division sub-units are not connected, the first frequency division performed by the frequency division delay unit corresponds to not dividing the first signal load. At this time, the frequency division ratio of the first signal load remains at n division.

[0050] Taking the configuration of the division ratio n=2 as an example, when one of the division sub-units is connected, the first division performed by the division delay unit corresponds to dividing the first signal load by two, corresponding to Figure 3, at this time the division ratio of the first signal load is adjusted to 2+0.5=2.5 division, when two division sub-units are connected, the first division performed by the division delay unit corresponds to dividing the first signal load by four, at this time the division ratio of the first signal load is adjusted to 2+0.25=2.25 division, when both division sub-units are not connected, the first division performed by the division delay unit corresponds to not dividing the first signal load, at this time the division ratio of the first signal load remains at 2 division.

[0051] Since the present application uses the down-counting unit and the frequency division delay unit as the first-level frequency division and the frequency division output unit as the second-level frequency division, the first signal load_out generated after adjusting the frequency division ratio is also used as the output signal of the first-level frequency division to enter the second-level frequency division. The frequency division output unit performs a second frequency division on the first signal load_out after adjusting the frequency division ratio to output the output signal clk_out of the required frequency division ratio.

[0052] In an embodiment of the present application, the frequency division output unit is used to adjust the first signal load_out after the division ratio to perform two-way frequency division. As long as the two-way frequency division circuit structure can achieve one cycle of circuit output every two cycles of the clock triggered, it is feasible. The present application does not impose any restrictions on the specific circuit structure of the frequency division output unit that can achieve two-way frequency division output.

[0053] Furthermore, when the first signal load_out with a division ratio of n is divided into two, the division ratio of the output signal clk_out generated by the division output unit is 2n; when the first signal load_out with a division ratio adjusted to n+0.5 is divided into two, the division ratio of the output signal clk_out generated by the division output unit is 2n+1; when the first signal load_out with a division ratio adjusted to n+0.25 is divided into two, the division ratio of the output signal clk_out generated by the division output unit is 2n+0.5. That is, through the half-integer division system provided in the present application, three modes of division ratio output of 2n, 2n+1, and 2n+0.5 can be achieved by setting only one down counter.

[0054] It should be added that please continue to refer to Figure 2, which corresponds to the division ratio of the above-mentioned 2n+1 mode. It can be observed that after the first level of division, load_out has a half-integer period, realizing a 2.5-division clock, but at this time the load_out duty cycle obviously does not reach 50%. However, after the first signal load_out with a division ratio of 2.5 is divided into two by the division output unit in the second level of division, the division ratio of the output signal clk_out becomes 5, and a duty cycle of 50% is also realized; similarly, when a division ratio of 2n is selected, a 4-division clock can be obtained, and when a division ratio of 2n+0.5 is selected, a 4.5-division clock can be obtained, which can increase the duty cycle achieved by the 2n+0.5 division ratio to close to 50%. Of course, different division ratio n values ​​can also be configured to achieve different division clocks, and this application will not go into too much detail about this.

[0055] Please continue to refer to Figure 6. In this specific embodiment, the present application sets the counter to a 7-bit down counter in the first level of frequency division. The load signal adjusts the access status of the two frequency division sub-units in the frequency division delay unit to achieve three frequency division modes, wherein the three frequency division modules can be switched by configuring sel<1:0>, 00 is the 2n frequency division mode, 01 is the 2n+1 frequency division mode, and 11 is the 2n+0.5 frequency division mode.

[0056] Furthermore, in order to ensure that the edges of load_div and clk_in are aligned, the load_div signal after frequency division is sent to the XNOR gate after passing through the delay2 delay unit. The second-stage frequency divider can be implemented using a common divide-by-two circuit.

[0057] Please refer to Figure 7, which is a waveform simulation diagram of the half-integer frequency division system provided in an embodiment of the present application. The waveform simulation diagram corresponds to the simulation result generated in the simulation software of the specific embodiment shown in Figure 6, wherein the first line clk_in is the input clock to be divided, with an average period of 58.8ps, that is, the clock frequency is 17GHz, the second line clk_xnor is the second signal generated after the XOR gate, the third line load is the set signal sent to the down counter, which is a 2.5-frequency division clock with a duty cycle of 60%, the fourth line load_out is the output clock of the first stage frequency division, and it can be observed that there is a time difference with the load, the last line clk_out is the output clock of the second stage frequency division, which is a 5-frequency division clock with a duty cycle of 50%. Through simulation, it can be seen that the frequency division function corresponding to this specific embodiment is normal and correct.

[0058] Therefore, the half-integer frequency division system provided by the present application can achieve a maximum input frequency of 17 GHz, a maximum frequency division ratio of 127, and supports frequency division ratios of 2n, 2n+1, and 2n+0.5 modes, achieving a 2n+1 frequency division clock with a 50% duty cycle, and increasing the duty cycle of the 2n+0.5 frequency division clock to close to 50%. The circuit structure is simple and the operation flexibility is high.

[0059] Based on the above-mentioned half-integer frequency division system, the present application also provides a half-integer frequency divider, which can realize three frequency division modes: 2n, 2n+0.5, and 2n+1, realize a 2n+1 frequency division clock with a duty cycle of 50%, and increase the duty cycle of the 2n+0.5 frequency division clock to close to 50%. The maximum frequency supports 17GHz and can be applied to a variety of application scenarios.

[0060] For other details about how the above-mentioned half-integer frequency divider implements the above-mentioned technical solution, please refer to the description of the half-integer frequency division system provided in the above-mentioned application embodiment, which will not be repeated here.

[0061] In the several embodiments provided in this application, it should be understood that the disclosed devices, apparatuses and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of modules is merely a logical function division. In actual implementation, there may be other division methods, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, device or module, which can be electrical, mechanical or other forms.

[0062] In addition, the functional modules in the various embodiments of the present application may be integrated into a processing module, or each module may exist physically separately, or two or more modules may be integrated into a single module. The above-mentioned integrated modules may be implemented in the form of hardware or software functional modules.

[0063] The half-integer frequency division system and frequency divider provided in the present application use a down counter to perform a countdown count of the configured frequency division ratio to generate a first signal, perform a first frequency division on the first signal, perform an XOR operation on the divided first signal and the input clock to generate a second signal, and use the second signal as the counting clock of the counter. At the same time, the first signal after the frequency division ratio is adjusted is subjected to a second frequency division, so as to avoid the additional addition of timers and a number of registers by means of clock inversion. The circuit structure is simple, the occupied area of ​​the layout is reduced, and the power consumption is reduced. It can realize three frequency division modes of 2n, 2n+0.5, and 2n+1, so that the duty cycle of the 2n+1 frequency division clock is controlled at 50%, and the duty cycle of the 2n+0.5 frequency division clock is increased to be close to 50%. The maximum frequency supports 17GHz, which can meet the needs of various application scenarios.

[0064] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A half-integer frequency division system, characterized in that, Including: A down-counter unit, which is used to count down the configured frequency division ratio n, and generate a first signal through an OR operation on the count value generated in real time; A frequency division delay unit, which is used to perform a first frequency division on the first signal, perform an exclusive-NOR operation on the frequency-divided first signal and the input clock to generate a second signal, and use the second signal as the counting clock of the counter in the down-counter unit to adjust the frequency division ratio of the first signal; A frequency division output unit, which is used to perform a second frequency division on the first signal after adjusting the frequency division ratio to output an output signal with the required frequency division ratio.

2. The half-integer frequency division system according to claim 1, wherein The frequency division ratio n of the said configuration is a positive decimal integer, and the frequency division ratio n is converted into the corresponding binary number (q x … q1 q0), and at this time, the generated first signal where q x represents the x-th bit of the binary number corresponding to the frequency division ratio n.

3. The half-integer frequency division system according to claim 2, wherein The down-counter unit is further configured to trigger the first signal load to be pulled low when the count value generated in real time is decremented to 1, so that the down-counter unit completes the reset of the count value when the next clock edge of the input clock clk_in arrives.

4. The half-integer frequency division system according to claim 1, wherein A delay sub-unit for delaying the first signal load and the frequency-divided first signal load_div is provided in the frequency division delay unit, so that when the frequency-divided first signal load_div performs an exclusive-NOR operation with the input clock clk_in, the time when it reaches the input terminal of the exclusive-NOR gate is aligned with the clock edge of the input clock clk_in.

5. The half-integer frequency division system according to claim 4, wherein The delay sub-unit includes a first delay sub-unit and a second delay sub-unit; The frequency division delay unit is used to delay the generated first signal load through the first delay sub-unit, and is used to synchronize the time of the frequency-divided first signal load_div through the input clock clk_in, and then delay the time-synchronized first signal load_div through the second delay sub-unit, so that the time when the delayed first signal load_div reaches the input terminal of the exclusive-NOR gate is aligned with the clock edge of the input clock clk_in.

6. The half-integer frequency division system according to claim 4, wherein The second signal clk_xnor_o is a signal generated by performing an exclusive-NOR operation on the frequency-divided first signal load_div and the input clock clk_in, and the generated second signal clk_xnor_o is used as the counting clock of the counter in the down-counter unit to adjust the frequency division ratio of the first signal load.

7. The half-integer frequency division system according to claim 1, wherein Two frequency division sub-units are provided in the frequency division delay unit, and each frequency division sub-unit uses a divide-by-two frequency division, and the access state of the two frequency division sub-units is adjusted to adjust the frequency division ratio of the first signal load.

8. The half-integer frequency division system according to claim 7, wherein When one of the frequency division sub-units is accessed, the first frequency division is to perform a divide-by-two frequency division on the first signal load, and the frequency division ratio of the first signal load is adjusted to n + 0.5 frequency division; When two of the frequency division sub-units are accessed, the first frequency division is to perform a divide-by-four frequency division on the first signal load, and the frequency division ratio of the first signal load is adjusted to n + 0.25 frequency division; when neither of the two frequency division sub-units is accessed, the first frequency division does not perform frequency division on the first signal load, and the frequency division ratio of the first signal load remains n frequency division.

9. The half-integer frequency division system according to claim 8, wherein, The second frequency division divides the first signal load_out after adjusting the frequency division ratio by two, so as to output an output signal clk_out with required frequency division ratios of 2n, 2n + 1, and 2n + 0.5; When the first signal load_out with a frequency division ratio of n is divided by two, the frequency division ratio of the output signal clk_out is 2n; when the first signal load_out with the frequency division ratio adjusted to n + 0.5 is divided by two, the frequency division ratio of the output signal clk_out is 2n + 1; when the first signal load_out with the frequency division ratio adjusted to n + 0.25 is divided by two, the frequency division ratio of the output signal clk_out is 2n + 0.

5.

10. A half-integer frequency divider, characterized in that The half-integer frequency divider includes the half-integer frequency division system according to any one of claims 1-9.

Images