Display device and display device manufacturing method

Abstract

Disclosed are a display device and a display device manufacturing method according to an embodiment. The display device according to an embodiment comprises: a substrate; a pixel electrode disposed on the substrate; a light emitting element disposed on the pixel electrode and including a first semiconductor layer, an active layer, and a second semiconductor layer; and a common electrode disposed on the light emitting element, wherein a top surface disposed farther from the active layer in the second semiconductor layer is a lens-shaped surface, and side surfaces of the active layer and the second semiconductor layer are aligned.

Description

Display device and method for manufacturing the display device

[0001] The present invention relates to a display device and a method for manufacturing the display device.

[0002] As the information society develops, demand for display devices for displaying images is increasing in various forms. Display devices can be flat panel displays such as liquid crystal displays (LCDs), field emission displays (FEDs), and light-emitting displays (LEDs).

[0003] The light-emitting display device can be implemented as an organic light-emitting display device including an organic light-emitting diode element as a light-emitting element, an inorganic light-emitting display device including an inorganic semiconductor element as a light-emitting element, or an ultra-small light-emitting diode display device including an ultra-small light-emitting diode element (or micro light-emitting diode element) as a light-emitting element. In this case, in the ultra-small light-emitting diode display device, since the ultra-small light-emitting diode element is connected to the pixel electrode, it is necessary to reduce the resistance of the pixel electrode.

[0004] The problem that the present invention seeks to solve is to provide a light-emitting element integrated with a lens structure.

[0005] The tasks of the present invention are not limited to the tasks mentioned above, and other technical tasks not mentioned will be clearly understood by those skilled in the art from the description below.

[0006] According to one embodiment of the present invention for solving the above problem, a display device includes a substrate, a pixel electrode disposed on the substrate, a light-emitting element disposed on the pixel electrode and including a first semiconductor layer, an active layer, and a second semiconductor layer, a connection electrode disposed between the pixel electrode and the light-emitting element, and a common electrode disposed on the light-emitting element, wherein the second semiconductor layer has an upper surface disposed further from the active layer as a lens-shaped surface, and side surfaces of the active layer and the second semiconductor layer can be aligned.

[0007] In one embodiment, the second semiconductor layer includes a lens portion that contacts the common electrode and has a lens-shaped upper surface, and a body portion that is disposed on a lower surface of the lens portion, and a side surface of the lens portion and a side surface of the body portion can be aligned.

[0008] In one embodiment, the lens-shaped surface may be convex downward or convex upward.

[0009] In one embodiment, the display device may further include a connecting electrode disposed between the substrate and the light-emitting element and having a diameter larger than a diameter of the light-emitting element.

[0010] In one embodiment, the diameter of the connecting electrode may be larger than the diameter of the light emitting element.

[0011] In one embodiment, the display device may further include an insulating layer partially surrounding the light emitting element.

[0012] In one embodiment, the insulating layer may be disposed on a side of the light-emitting element and a portion of the substrate on which the light-emitting element is not disposed.

[0013] In one embodiment, the display device may further include a reflective layer partially surrounding the light emitting element on the insulating layer.

[0014] In one embodiment, the display device may further include a connecting electrode disposed between the substrate and the light-emitting element, the connecting electrode having a diameter equal to a diameter of the light-emitting element and a diameter of the lens portion.

[0015] In one embodiment, the display device may further include a connection electrode disposed between the substrate and the light-emitting element and a pixel electrode disposed between the substrate and the connection electrode.

[0016] In one embodiment, the display device may further include a convex lens-shaped microlens that is convex downward and overlaps the light-emitting element and is disposed on the common electrode.

[0017] In one embodiment, the lower surface of the micro lens can be in contact with the common electrode.

[0018] In one embodiment, the second semiconductor layer may have a plurality of downwardly convex lens shapes.

[0019] According to another embodiment for solving the above problem, a method for manufacturing a display device includes the steps of: laminating a first connection electrode layer on a second substrate on which a second semiconductor layer, an active layer, and a first semiconductor layer are sequentially grown; melting and bonding the second substrate to a first substrate having a pixel circuit and the first connection electrode layer; removing the second substrate; forming a first mask pattern in the shape of a lens on an upper surface of the second semiconductor layer; etching the second semiconductor layer, the active layer, and the first semiconductor layer using the first mask pattern in the shape of a lens to form a plurality of light-emitting elements having the second semiconductor layer having a lens-shaped upper surface; forming a second mask pattern surrounding the light-emitting elements; etching the first connection electrode layer using the second mask pattern; and forming a common electrode on the light-emitting elements, wherein side surfaces of the active layer and the second semiconductor layer can be aligned.

[0020] In one embodiment, the lens-shaped upper surface may be convex downward or convex upward.

[0021] In one embodiment, the step of melting and bonding the first connection electrode layer may include the step of laminating a second connection electrode layer on a first substrate having the pixel circuit, and the step of melting and bonding the first connection electrode layer and the second connection electrode layer to form a connection electrode.

[0022] In one embodiment, prior to the step of forming the common electrode, the method may further include the step of depositing an insulating layer on the light-emitting element and a portion of the first substrate on which the light-emitting element is not disposed, the step of forming a planarization layer on a portion of the first substrate on which the insulating layer is formed, wherein the planarization layer is formed to be lower than the height of the light-emitting element, and the step of removing a portion of the insulating layer from a portion of the light-emitting element that is not covered by the planarization layer.

[0023] The method may include forming a planarization layer on the first substrate on which the insulating layer is formed, and prior to forming the planarization layer to be lower than the height of the light-emitting element, depositing a reflective material layer on the first substrate on which the insulating layer is laminated, and removing a portion of the reflective material layer from the horizontal plane of the first substrate to form a reflective layer that partially surrounds the side surface of the light-emitting element.

[0024] According to another embodiment for solving the above problem, a method for manufacturing a display device may include the steps of: laminating a connection electrode layer on a second substrate on which a second semiconductor layer, an active layer, and a first semiconductor layer are disposed; etching the active layer, the first semiconductor layer, and the connection electrode layer to form a light-emitting element; bonding the second substrate having the light-emitting element to a carrier substrate; removing the second substrate; forming a lens-shaped mask pattern on an upper surface of the second semiconductor layer; etching the upper surface of the second semiconductor layer to have a lens shape using the lens-shaped mask pattern, while forming side surfaces of the active layer and the second semiconductor layer so as to be aligned; transferring the light-emitting element on the carrier substrate onto a first substrate including a pixel electrode using an interposer substrate; and removing the interposer substrate; and forming a common electrode on the light-emitting element.

[0025] In one embodiment, the lens shape may be a downwardly convex or upwardly convex shape.

[0026] In one embodiment, the carrier substrate may include a transparent and mechanically stable support layer and an adhesive layer disposed on the support layer.

[0027] In one embodiment, the interposer substrate may include a support layer that is optically transparent and mechanically stable, and an adhesive layer disposed on the support layer.

[0028] In one embodiment, prior to the step of forming the common electrode, the method may further include the steps of depositing an insulating layer on the light-emitting element and a portion of the first substrate on which the light-emitting element is not disposed, depositing a reflective material layer on a portion of the first substrate on which the insulating layer is laminated, removing the reflective material layer from a horizontal plane on the first substrate to form a reflective layer surrounding a side surface of the light-emitting element, forming a planarization layer on the first substrate on which the insulating layer is formed, wherein the planarization layer is formed lower than a height of the light-emitting element, and removing a portion of the insulating layer on the light-emitting element that is not covered by the planarization layer.

[0029] Specific details of other embodiments are included in the detailed description and drawings.

[0030] According to the display device according to the embodiments, the amount of light emitted can be improved by adjusting the divergence angle or viewing angle of light emitted from the active layer (MQW).

[0031] In addition, the manufacturing process of the display device is simplified because there is no need to add a lens structure formed of a separate organic layer, etc.

[0032] Additionally, collimation between the light emitting element (LE) and a separate lens structure becomes unnecessary.

[0033] Additionally, it is advantageous to the process in that there is no need to consider the stability, refractive index, transmittance, etc. of the lens structure material formed separately.

[0034] The effects according to the embodiments are not limited to those exemplified above, and more diverse effects are included in this specification.

[0035] Figure 1 is a perspective view showing a display device according to one embodiment.

[0036] Figures 2 and 3 are plan views showing a display device according to one embodiment.

[0037] FIG. 4 is a circuit diagram showing a first sub-pixel of a display panel according to one embodiment.

[0038] FIG. 5 is a circuit diagram showing a first sub-pixel of a display panel according to another embodiment.

[0039] Fig. 6 is a cross-sectional view schematically showing a display area of ​​a display device according to one embodiment.

[0040] Figure 7 is an enlarged view showing in detail the common electrode and light-emitting element illustrated in Figure 6.

[0041] Fig. 8 is a cross-sectional view schematically showing a display area of ​​a display device according to another embodiment.

[0042] Figure 9 is an enlarged view showing in detail the common electrode and light-emitting element illustrated in Figure 8.

[0043] FIG. 10A is a cross-sectional view schematically showing a display area of ​​a display device according to another embodiment, and FIG. 10B is an enlarged view showing in detail the common electrode and light-emitting element shown in FIG. 10A.

[0044] FIGS. 11A and 11B are cross-sectional views schematically showing a display area of ​​a display device according to another embodiment.

[0045] Fig. 12 is a cross-sectional view schematically showing a display area of ​​a display device according to another embodiment.

[0046] Figure 13 is an enlarged view showing in detail the common electrode and light-emitting element illustrated in Figure 12.

[0047] Fig. 14 is a cross-sectional view schematically showing a display area of ​​a display device according to another embodiment.

[0048] Figure 15 is an enlarged view showing in detail the common electrode and light-emitting element illustrated in Figure 14.

[0049] FIG. 16 is a cross-sectional view schematically illustrating a display device including a wavelength conversion layer and a color filter layer according to another embodiment.

[0050] FIGS. 17 to 26 are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment.

[0051] Figures 27 to 30 are cross-sectional views illustrating a method of manufacturing a display device according to another embodiment.

[0052] Figures 31 to 43 are cross-sectional views illustrating a method of manufacturing a display device according to another embodiment.

[0053] FIG. 44 is an exemplary drawing showing a virtual reality device including a display device according to one embodiment.

[0054] FIG. 45 is an exemplary drawing showing a smart device including a display device according to one embodiment.

[0055] FIG. 46 is an exemplary drawing showing a vehicle including a display device according to one embodiment.

[0056] FIG. 47 is an exemplary drawing showing a transparent display device including a display device according to one embodiment.

[0057] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0058] When elements or layers are referred to as being "on" another element or layer, this includes both cases where the other element or layer is directly on top of the other element or layer or intervening therebetween. Like reference numerals refer to like elements throughout the specification. The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments are illustrative and therefore the present invention is not limited to the matters illustrated.

[0059] Although terms like "first" and "second" are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it should be understood that a "first" component referred to below may also be a "second" component within the technical scope of the present invention.

[0060] The individual features of the various embodiments of the present invention can be partially or wholly combined or combined with each other, and various technical linkages and operations are possible, and each embodiment can be implemented independently of each other or implemented together in a related relationship.

[0061] Specific embodiments are described below with reference to the attached drawings.

[0062] Figure 1 is a perspective view showing a display device according to one embodiment.

[0063] Referring to FIG. 1, the display device (10) is a device that displays a moving image or a still image, and can be used as a display screen for various products such as a mobile phone, a smart phone, a tablet personal computer, a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation system, an Ultra Mobile PC (UMPC), etc., as well as a television, a laptop, a monitor, a billboard, an Internet of Things (IOT) device, etc.

[0064] The display device (10) may be a light-emitting display device such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and an ultra-small light-emitting display device using an ultra-small light-emitting diode (micro or nano light emitting diode (micro LED or nano LED)). Hereinafter, the display device (10) is described mainly as an ultra-small light-emitting display device, but the present invention is not limited thereto. Meanwhile, for the convenience of explanation, the ultra-small light-emitting diode is described as a micro light-emitting diode below.

[0065] The display device (10) includes a display panel (100), a display driving circuit (200), and a circuit board (300).

[0066] The display panel (100) may be formed as a rectangular plane having a short side in a first direction (DR1) and a long side in a second direction (DR2) intersecting the first direction (DR1). The corner where the short side in the first direction (DR1) and the long side in the second direction (DR2) meet may be formed to be rounded to have a predetermined curvature or formed at a right angle. The plane shape of the display panel (100) is not limited to a square, and may be formed in another polygonal, circular, or oval shape. The display panel (100) may be formed flat, but is not limited thereto. For example, the display panel (100) may include a curved portion formed at the left and right ends and having a constant curvature or a varying curvature. In addition, the display panel (100) may be formed flexibly so as to be bent, curved, folded, or rolled.

[0067] The substrate (SUB) of the display panel (100) may include a main area (MA) and a sub area (SBA).

[0068] The main area (MA) may include a display area (DA) that displays an image and a non-display area (NDA) surrounding the display area (DA). The display area (DA) may include a plurality of pixels that display an image. For example, the pixels may include a first sub-pixel that emits a first light, a second sub-pixel that emits a second light, and a third sub-pixel that emits a third light.

[0069] The sub-area (SBA) may protrude in a second direction (DR2) from one side of the main area (MA). In FIG. 1, the sub-area (SBA) is illustrated as being unfolded, but the sub-area (SBA) may be bent, in which case it may be disposed on the lower surface of the display panel (100). When the sub-area (SBA) is bent, it may overlap with the main area (MA) in the third direction (DR3), which is the thickness direction of the display panel (100). A display driving circuit (200) may be disposed in the sub-area (SBA).

[0070] The display driving circuit (200) can generate signals and voltages for driving the display panel (100). The display driving circuit (200) can be formed as an integrated circuit (IC) and attached to the display panel (100) using a chip-on-glass (COG) method, a chip-on-plastic (COP) method, or an ultrasonic bonding method, but is not limited thereto. For example, the display driving circuit (200) can be attached to a circuit board (300) using a chip-on-film (COF) method.

[0071] The circuit board (300) may be attached to one end of the sub-area (SBA) of the display panel (100). As a result, the circuit board (300) may be electrically connected to the display panel (100) and the display driving circuit (200). The display panel (100) and the display driving circuit (200) may receive digital video data, timing signals, and driving voltages through the circuit board (300). The circuit board (300) may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0072] Figures 2 and 3 are plan views illustrating a display device according to one embodiment. Figure 2 illustrates an example in which the sub-area (SBA) is unfolded rather than bent. Figure 3 illustrates an example in which the sub-area (SBA) is bent.

[0073] Referring to FIGS. 2 and 3, the display panel (100) may include a main area (MA) and a sub area (SBA).

[0074] The main area (MA) may include a display area (DA) that displays an image and a non-display area (NDA) surrounding the display area (DA). The display area (DA) may occupy most of the area of ​​the main area (MA). The display area (DA) may be positioned at the center of the main area (MA).

[0075] A non-display area (NDA) may be positioned adjacent to a display area (DA). The non-display area (NDA) may be an area outside the display area (DA). The non-display area (NDA) may be positioned to surround the display area (DA). The non-display area (NDA) may be an edge area of ​​the display panel (100).

[0076] The first scan driver (SDC1) and the second scan driver (SDC2) may be disposed in a non-display area (NDA). The first scan driver (SDC1) may be disposed on one side (for example, the left side) of the display panel (100), and the second scan driver (SDC2) may be disposed on the other side (for example, the right side) of the display panel, but is not limited thereto. Each of the first scan driver (SDC1) and the second scan driver (SDC2) may be electrically connected to the display driver circuit (200) through scan fan-out wires. Each of the first scan driver (SDC1) and the second scan driver (SDC2) may receive a scan control signal from the display driver circuit (200), generate scan signals according to the scan control signal, and output the scan signals to the scan wires.

[0077] The sub-area (SBA) may protrude from one side of the main area (MA) in a second direction (DR2). The length of the sub-area (SBA) in the second direction (DR2) may be shorter than the length of the main area (MA) in the second direction (DR2). The length of the sub-area (SBA) in the first direction (DR1) may be shorter than the length of the main area (MA) in the first direction (DR1) or may be substantially the same as the length of the main area (MA) in the first direction (DR1). The sub-area (SBA) may be curved and may be disposed at a lower portion of the display panel (100). In this case, the sub-area (SBA) may overlap the main area (MA) in the third direction (DR3).

[0078] The sub-area (SBA) may include a connection area (CA), a pad area (PA), and a bending area (BA).

[0079] The connection area (CA) is an area that protrudes in the second direction (DR2) from one side of the main area (MA). One side of the connection area (CA) may be in contact with the non-display area (NDA) of the main area (MA), and the other side of the connection area (CA) may be in contact with the bending area (BA).

[0080] The pad area (PA) is an area where pads (PD) and a display driving circuit (200) are arranged. The display driving circuit (200) can be attached to the driving pads of the pad area (PA) using a conductive adhesive such as an anisotropic conductive film. The circuit board (300) can be attached to the pads (PD) of the pad area (PA) using a conductive adhesive such as an anisotropic conductive film. One side of the pad area (PA) can be in contact with the bending area (BA).

[0081] The bending area (BA) is a bending area. When the bending area (BA) is bent, the pad area (PA) can be positioned below the connection area (CA) and below the main area (MA). The bending area (BA) can be positioned between the connection area (CA) and the pad area (PA). One side of the bending area (BA) can be in contact with the connection area (CA), and the other side of the bending area (BA) can be in contact with the pad area (PA).

[0082] FIG. 4 is a circuit diagram showing a first sub-pixel of a display panel according to one embodiment.

[0083] Referring to FIG. 4, a first sub-pixel (SPX1) according to one embodiment may be connected to scan lines (GWL, GIL, GCL, GBL), a light-emitting line (EL), and a data line (DL). For example, the first sub-pixel (SPX1) may be connected to a write scan line (GWL), an initialization scan line (GIL), a control scan line (GCL), a bias scan line (GBL), an light-emitting line (EL), and a data line (DL).

[0084] A first sub-pixel (SPX1) according to one embodiment includes a driving transistor (DT), switch elements, a capacitor (C1), and a first light-emitting element (LE1). The switch elements include first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6).

[0085] A driving transistor (DT) includes a gate electrode, a first electrode, and a second electrode. The driving transistor (DT) controls a drain-source current (hereinafter referred to as “driving current”) flowing between the first electrode and the second electrode according to a data voltage applied to the gate electrode.

[0086] The first light-emitting element (LE1) emits light according to the driving current. The amount of light emitted by the first light-emitting element (LE1) may be proportional to the driving current (Ids). The anode electrode of the first light-emitting element (LE1) may be connected to the first electrode of the fourth transistor (ST4) and the second electrode of the sixth transistor (ST6), and the cathode electrode may be connected to the second power line (VSL) to which the second power voltage is applied.

[0087] A capacitor (C1) is formed between the second electrode of the driving transistor (DT) and the first power line (VDL) to which a first power voltage is applied. The first power voltage may be a voltage of a higher level than the second power voltage. One electrode of the capacitor (C1) may be connected to the second electrode of the driving transistor (DT), and the other electrode may be connected to the first power line (VDL).

[0088] As shown in Fig. 4, the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) can all be formed as p-type MOSFETs. In this case, the active layers of each of the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) can be formed of polysilicon or oxide semiconductor.

[0089] The gate electrode of the second transistor (ST2) may be connected to a write scan line (GWL), and the gate electrode of the first transistor (ST1) may be connected to a control scan line (GCL). The gate electrode of the third transistor (ST3) may be connected to an initialization scan line (GIL), and the gate electrode of the fourth transistor (ST4) may be connected to a bias scan line (GBL). Since the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, and ST6) are formed of p-type MOSFETs, they may be turned on when a scan signal of a gate low voltage and an emission signal are applied to the control scan line (GCL), the initialization scan line (GIL), the write scan line (GWL), the bias scan line (GBL), and the emission line (EL), respectively. One electrode of the third transistor (ST3) and one electrode of the fourth transistor (ST4) may be connected to an initialization voltage line (VIL).

[0090] FIG. 5 is a circuit diagram showing a first sub-pixel of a display panel according to another embodiment.

[0091] Referring to FIG. 5, the driving transistor (DT), the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) may be formed as p-type MOSFETs, and the first transistor (ST1) and the third transistor (ST3) may be formed as n-type MOSFETs. The active layers of each of the driving transistor (DT), the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6), which are formed as p-type MOSFETs, may be formed of polysilicon, and the active layers of each of the first transistor (ST1) and the third transistor (ST3), which are formed as n-type MOSFETs, may be formed of oxide semiconductors. In this case, the transistors formed of polysilicon and the transistors formed of oxide semiconductors may be arranged on different layers.

[0092] Since the first transistor (ST1) and the third transistor (ST3) are formed as n-type MOSFETs, the first transistor (ST1) can be turned on when a control scan signal of a gate high voltage is applied to the control scan line (GCL), and the third transistor (ST3) can be turned on when an initialization scan signal is applied to the initialization scan line (GIL). In contrast, the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) are formed as p-type MOSFETs, and therefore can be turned on when a scan signal of a gate low voltage and an emission signal are applied to the write scan line (GWL), the bias scan line (GBL), and the emission line (EL), respectively.

[0093] Alternatively, the fourth transistor (ST4) in FIG. 4 may be formed as an n-type MOSFET. In this case, the active layer of each of the fourth transistors (ST4) may be formed of an oxide semiconductor. When the fourth transistor (ST4) is formed as an n-type MOSFET, it may be turned on when a bias scan signal of a gate high voltage is applied to the bias scan line (GBL).

[0094] Alternatively, although not shown in FIGS. 4 and 5, the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) may all be formed as n-type MOSFETs.

[0095] Meanwhile, the circuit diagram of the second sub-pixel and the circuit diagram of the third sub-pixel according to one embodiment are substantially the same as the circuit diagram of the first sub-pixel (SPX1) described in conjunction with FIGS. 4 and 5, and therefore, a description thereof is omitted.

[0096] Fig. 6 is a cross-sectional view schematically illustrating a display area of ​​a display device according to one embodiment. Fig. 7 is an enlarged view showing in detail the common electrode and light-emitting element illustrated in Fig. 6.

[0097] Referring to FIGS. 6 and 7, the display panel (100) may include a semiconductor circuit board (110) and a light emitting element layer (120).

[0098] A semiconductor circuit board (110) may include a plurality of pixel circuits (PXC) and pixel electrodes (PE).

[0099] The first substrate (SUB1) may be a silicon wafer substrate. The first substrate (SUB1) may be made of single crystal silicon.

[0100] Each of the plurality of pixel circuit units (PXC) may be arranged on a first substrate (SUB1). Each of the plurality of pixel circuit units (PXC) may include a complementary metal-oxide semiconductor (CMOS) circuit formed using a semiconductor process. Each of the plurality of pixel circuit units (PXC) may include at least one transistor formed using a semiconductor process. In addition, each of the plurality of pixel circuit units (PXC) may further include at least one capacitor formed using a semiconductor process.

[0101] A plurality of pixel circuit units (PXC) can be arranged in a display area (DA). Each of the plurality of pixel circuit units (PXC) can be connected to a corresponding pixel electrode (PE). Each of the plurality of pixel circuit units (PXC) can apply a pixel voltage or an anode voltage to the pixel electrode (PE).

[0102] Each of the pixel electrodes (PE) may be disposed on a corresponding pixel circuit unit (PXC). Each of the pixel electrodes (PE) may be an exposed electrode exposed from the pixel circuit unit (PXC). That is, each of the pixel electrodes (PE) may protrude from an upper surface of the pixel circuit unit (PXC). Each of the pixel electrodes (PE) may be formed integrally with the pixel circuit unit (PXC). Each of the pixel electrodes (PE) may receive a pixel voltage or an anode voltage from the pixel circuit unit (PXC). The pixel electrodes (PE) may include copper (Cu), titanium (Ti), silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or a mixture thereof. In addition, the pixel electrodes (PE) may have a multilayer structure in which two or more metal layers are stacked. For example, the pixel electrodes (PE) may have a two-layer structure in which a copper layer is laminated on a titanium layer, but is not limited thereto.

[0103] The interlayer insulating layer (111) may be disposed on a first substrate (SUB1) on which pixel electrodes (PE) are not disposed. The interlayer insulating layer (111) is disposed between pixel electrodes (PE), and the interlayer insulating layer (111) may be formed in a multi-stage structure.

[0104] The interlayer insulating layer (111) is a silicon oxide film (SiO2), an aluminum oxide film (Al2O3), or a hafnium oxide film (HfO x ) can be formed into a film of inorganic substances.

[0105] The connecting electrode (112) may be disposed on the pixel electrode (PE). The connecting electrode (112) may serve as a bonding metal for bonding the pixel electrodes (PE) and the light emitting elements (LE) during the manufacturing process. The connecting electrode (112) may serve to apply a light emitting signal to the light emitting element (LE) by bonding with the pixel electrode (PE). The light emitting element (LE) may include at least one connecting electrode (112).

[0106] The connecting electrode (112) can reduce the resistance between the light emitting element (LE) and the contact electrode when the light emitting element (LE) is electrically connected to the pixel electrode in the display panel (100) according to one embodiment. The connecting electrode (112) can include a conductive metal. For example, the connecting electrode (112) can include at least one of gold (Au), copper (Cu), tin (Sn), titanium (Ti), aluminum (Al), and silver (Ag). For example, the connecting electrode (112) can include a 9:1 alloy, an 8:2 alloy, or a 7:3 alloy of gold and tin, or can include an alloy of copper, silver, and tin (SAC305).

[0107] Although not shown, an ohmic contact layer may be further disposed on the connection electrode (112). The ohmic contact layer may be disposed between the connection electrode (112) and the first semiconductor layer (SEM1). The ohmic contact layer may be an ohmic connection electrode. However, the present invention is not limited thereto, and may also be a Schottky connection electrode. The ohmic contact layer may include ITO. However, the present invention is not limited thereto, and may include at least one selected from gold (Au), copper (Cu), tin (Sn), titanium (Ti), aluminum (Al), and silver (Ag), and may be formed of an alloy thereof or a multilayer structure thereof.

[0108] The connecting electrode (112) may have a diameter (W2) larger than the diameter (W1) of the light emitting element (LE). For example, the connecting electrode (112) may protrude outside the light emitting element (LE) disposed on the connecting electrode (112).

[0109] The light emitting element layer (120) may include a light emitting element (LE), an insulating layer (INS), a planarization layer (113), and a common electrode (CE).

[0110] Each of the light emitting elements (LE) may be placed on a connecting electrode (112). The light emitting elements (LE) may be placed to overlap with the pixel electrode (PE).

[0111] The light emitting element (LE) may be a vertical light emitting diode element extending in a third direction (DR3). That is, the length of the light emitting element (LE) in the third direction (DR3) may be longer than the length in the horizontal direction. The length in the horizontal direction refers to the length in the first direction (DR1) or the length in the second direction (DR2). For example, the length of the light emitting element (LE) in the third direction (DR3) may be approximately 1 to 5 μm. The light emitting element (LE) may have an upper surface formed in a lens shape. The lens shape may be an upwardly convex shape.

[0112] Referring to FIG. 7, the light emitting element (LE) may be a micro light emitting diode element or a nano light emitting diode. The light emitting element (LE) includes a first semiconductor layer (SEM1), an electron blocking layer (EBL), an active layer (MQW), a superlattice layer (SLT), and a second semiconductor layer (SEM2) in a third direction (DR3). The first semiconductor layer (SEM1), the electron blocking layer (EBL), the active layer (MQW), the superlattice layer (SLT), and the second semiconductor layer (SEM2) may be sequentially stacked in the third direction (DR3). Side surfaces of the first semiconductor layer (SEM1), the electron blocking layer (EBL), the active layer (MQW), the superlattice layer (SLT), and the second semiconductor layer (SEM2) may be arranged on the same line.

[0113] The light emitting element (LE) may have a cylindrical, disk, or rod shape with a width greater than its height. However, the present invention is not limited thereto, and the light emitting element (LE) may have a rod, wire, tube, or other shape, or a polygonal prism shape such as a cube, rectangular parallelepiped, or hexagonal prism.

[0114] A first semiconductor layer (SEM1) may be disposed on a connection electrode (112). The first semiconductor layer (SEM1) may be doped with a first conductivity type dopant such as Mg, Zn, Ca, Ba, etc. For example, the first semiconductor layer (SEM1) may be p-GaN doped with p-type Mg. The thickness of the first semiconductor layer (SEM1) may be approximately 30 to 200 nm.

[0115] An electron blocking layer (EBL) may be disposed on the first semiconductor layer (SEM1). The electron blocking layer (EBL) may be a layer that suppresses or prevents too many electrons from flowing into the active layer (MQW). For example, the electron blocking layer (EBL) may be p-AlGaN doped with p-type magnesium. The thickness of the electron blocking layer (EBL) may be approximately 10 to 50 nm. The electron blocking layer (EBL) may be omitted.

[0116] The active layer (MQW) can be disposed on the electron blocking layer (EBL). The active layer (MQW) can emit light by the combination of electron-hole pairs in response to an electric signal applied through the first semiconductor layer (SEM1) and the second semiconductor layer (SEM2). The active layer (MQW) can emit first light, i.e., light in the blue wavelength band, having a center wavelength band in the range of 450 nm to 495 nm, but is not limited thereto.

[0117] The active layer (MQW) may include a material having a single or multiple quantum well structure. When the active layer (MQW) includes a material having a multiple quantum well structure, it may have a structure in which multiple well layers and barrier layers are alternately laminated. In this case, the well layers may be formed of InGaN, and the barrier layer may be formed of GaN or AlGaN, but is not limited thereto. The thickness of the well layers may be approximately 1 to 4 nm, and the thickness of the barrier layer may be 3 to 10 nm.

[0118] Alternatively, the active layer (MQW) may have a structure in which semiconductor materials with large band gap energy and semiconductor materials with small band gap energy are alternately laminated, and may include different group III to group V semiconductor materials depending on the wavelength of the light emitted. The light emitted by the active layer (MQW) is not limited to the first light (light in the blue wavelength band), and may also emit the second light (light in the green wavelength band) or the third light (light in the red wavelength band) depending on the case.

[0119] A superlattice layer (SLT) may be disposed on the active layer (MQW). The superlattice layer (SLT) may be a layer for relieving stress between the second semiconductor layer (SEM2) and the active layer (MQW). For example, the superlattice layer (SLT) may be formed of InGaN or GaN. The thickness of the superlattice layer (SLT) may be approximately 50 to 200 nm. The superlattice layer (SLT) may be omitted.

[0120] The second semiconductor layer (SEM2) may be disposed on the superlattice layer (SLT). The second semiconductor layer (SEM2) may be doped with a second conductivity type dopant, such as Si, Ge, Sn, Se, etc. For example, the second semiconductor layer (SEM2) may be n-GaN doped with n-type Si. The thickness of the second semiconductor layer (SEM2) may be approximately 500 nm to 1 μm.

[0121] The upper surface of the second semiconductor layer (SEM2) may have a lens shape. For example, the lens shape may be an upwardly convex shape. The upper surface of the second semiconductor layer (SEM2) may be a surface that contacts the common electrode (CE).

[0122] For convenience of explanation, the upper surface of the lens shape of the second semiconductor layer (SEM2) may be referred to as a lens portion (SEM2-1), and the lower surface supporting the upper surface of the lens shape may be referred to as a body portion (SEM2-2). The diameter of the lens portion (SEM2-1) may be the same as the diameter of the body portion (SEM2-2). The lens portion (SEM2-1) and the body portion (SEM2-2) may be arranged in a row in the third direction, but are not limited thereto. In addition, the material of the lens portion (SEM2-1) may be the same as the material of the body portion (SEM2-2).

[0123] The second semiconductor layer (SEM2) has a lens-shaped upper surface, thereby reducing the divergence angle or viewing angle of light emitted from the active layer (MQW).

[0124] Since the upper surface of the second semiconductor layer (SEM2) is formed in a lens shape, a separate lens structure formed from an organic layer or the like is not required. This simplifies the manufacturing process of the display device. Therefore, forming the upper surface of the second semiconductor layer (SEM2) in a lens shape offers advantages in terms of process time and cost compared to forming a separate lens structure.

[0125] In addition, since the second semiconductor layer (SEM2) has a lens-shaped upper surface, collimation between the light-emitting element (LE) and a separate lens structure becomes unnecessary.

[0126] In addition, the upper surface of the second semiconductor layer (SEM2) is formed in a lens shape, so there is no need to consider the stability, refractive index, transmittance, etc. of the lens structure material formed separately.

[0127] Referring again to FIGS. 6 and 7, the insulating layer (INS) may be disposed on the side surfaces of each of the light emitting elements (LE) and on the upper surfaces of the connecting electrodes (112) that do not overlap the light emitting elements (LE) and on the side surfaces of the connecting electrodes (112). Additionally, the insulating layer (INS) may be disposed on the interlayer insulating layer (111) on which the light emitting elements (LE) are not disposed.

[0128] Additionally, the insulating layer (INS) may be a silicon oxide film (SiO2), an aluminum oxide film (Al2O3), or a hafnium oxide film (HfO). x ) can be formed as a film, but is not limited thereto.

[0129] A planarization layer (113) may be disposed on each side of the light emitting elements (LE). The planarization layer (113) may be a layer for planarizing steps caused by the light emitting elements (LE). The upper surfaces of the light emitting elements (LE) and the upper surface of the planarization layer (113) may be connected to each other in a flat manner. The planarization layer (113) may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0130] The common electrode (CE) is disposed entirely on the first substrate (SUB1) and may include a material having low resistance since a common voltage is applied thereto. The common electrode (CE) may be disposed on the upper surface of each of the light emitting elements (LE) and the upper surface of the planarization layer (113). The common electrode (CE) may be in direct contact with the second semiconductor layer (SEM2) having a lens shape.

[0131] In addition, the common electrode (CE) may be formed to a thin thickness so as to facilitate light transmission. The common electrode (CE) may include a transparent conductive material. For example, the common electrode (CE) may include a transparent conductive oxide (TCO) such as indium tin oxide (ITO) or indium zinc oxide (IZO). The thickness of the common electrode (CE) may be approximately 10 Å to 200 Å, but is not limited thereto.

[0132] Fig. 8 is a cross-sectional view schematically showing a display area of ​​a display device according to another embodiment. Fig. 9 is an enlarged view showing in detail the common electrode and light-emitting element illustrated in Fig. 8.

[0133] FIGS. 8 and 9 differ from the embodiments of FIGS. 6 and 7 in that the light emitting element (LE) further includes a reflective layer (REF). In the following description referring to FIGS. 8 and 9, the differences from the embodiments of FIGS. 6 and 7 will be primarily explained.

[0134] A reflective layer (REF) can be disposed on the side of each of the light-emitting elements (LE) on the insulating layer (INS) and on the upper surface of the connecting electrodes (112) that do not overlap with the light-emitting elements (LE) and on the side of the connecting electrode (112).

[0135] The reflective layer (REF) reflects light emitted from the light-emitting element (LE) in the lateral directions, rather than the upward direction. The reflective layer (REF) may include a highly reflective metal material, such as aluminum (Al). The thickness of the reflective layer (REF) may be approximately 0.1 μm, but is not limited thereto.

[0136] FIG. 10A is a cross-sectional view schematically showing a display area of ​​a display device according to another embodiment, and FIG. 10B is an enlarged view showing in detail the common electrode and light-emitting element shown in FIG. 10A.

[0137] FIGS. 10A and 10B differ from the embodiments of FIGS. 6 and 7 in that the lens shape of the upper surface of the light emitting element (LE) is convex downward. In the following description referring to FIGS. 10A and 10B, the differences from the embodiments of FIGS. 6 and 7 will be mainly explained.

[0138] Referring to FIGS. 10A and 10B, the upper surface of the light-emitting element (LE) may have a lens shape. The upper surface of the light-emitting element (LE) has a convex shape toward the first substrate (SUB1). The first common electrode (CE) has a convex shape downward along the upper surface of the light-emitting element (LE).

[0139] The light emitting element (LE) may include a first semiconductor layer (SEM1), an electron blocking layer (EBL), an active layer (MQW), a superlattice layer (SLT), and a second semiconductor layer (SEM2).

[0140] The second semiconductor layer (SEM2) has a top surface in the shape of a lens that is convex downward, thereby improving the front light emission effect by focusing the light emitted from the active layer (MQW). In another modified example, a reflective layer may be arranged on the side surface of each of the light-emitting elements (LE) on the insulating layer (INS), on the top surface of the connecting electrodes (112) that do not overlap with the light-emitting elements (LE), and on the side surface of the connecting electrode (112). As described with reference to Fig. 9, the reflective layer may reflect light emitted from the light-emitting elements (LE) that propagates in the up, down, left, and right lateral directions rather than in the upward direction.

[0141] FIGS. 11A and 11B are cross-sectional views schematically showing a display area of ​​a display device according to another embodiment.

[0142] FIG. 11a differs from the embodiments of FIGS. 10a and 10b in that a micro lens (MLA) is arranged on the upper surface of the light emitting element (LE).

[0143] In the following, the description referring to Fig. 11a will focus on differences from the embodiments of Figs. 10a and 10b.

[0144] Fig. 11a The upper surface of the light emitting element (LE) may have a lens shape. The upper surface of the light emitting element (LE) has a convex shape toward the first substrate (SUB1). The first common electrode (CE) has a convex shape downward along the upper surface of the light emitting element (LE). A micro lens (MLA) may be disposed on the first common electrode (CE). The micro lens (MLA) may have a curvature corresponding to the curvature of the first common electrode (CE). The curvature of the micro lens (MLA) may be the same as the curvature of the first common electrode (CE). The micro lens (MLA) may be in direct contact with the common electrode (CE) on the first common electrode (CE). The focus of each micro lens (MLA) may be focused on a corresponding pixel (PX) by adjusting the radius of curvature and the height of each micro lens (MLA).

[0145] The microlens (MLA) can be formed to fill the concave groove of the first common electrode (CE) on the upper surface of the light emitting element (LE) and protrude convexly upward. The microlens (MLA) can have a convex lens shape that protrudes convexly on the upper surface of the light emitting element (LE).

[0146] The microlens (MLA) may include organic or inorganic materials such as polydimethylsiloxane (PDMS), polymethyl methacrylate (PMMA), photoresist, silicon dioxide (SiO2), etc.

[0147] Fig. 11b differs from Fig. 11a in that a curve is formed on the upper surface of the light emitting element (LE).

[0148] In Fig. 11b, two concave lens shapes are formed on the upper surface of the light emitting element (LE), but the present invention is not limited thereto, and the upper surface of the light emitting element (LE) may form a plurality of downwardly convex lens shapes. Each of the plurality of convex lens shapes has a curvature, and the curvature of each of the plurality of convex lens shapes may be the same, but is not limited thereto, and lens shapes having different curvatures may be formed. For example, in the case of three plurality of downwardly convex lens shapes, the curvature of the lens shape arranged in the middle may be the largest, and the curvatures of the lens shapes arranged on both sides may be arranged to be smaller.

[0149] Following the downward convex lens shape on the upper surface of the light emitting element (LE), the common electrode (CE) may also have a downward concave lens shape on the light emitting element (LE). Additionally, the microlens (MLA) may be formed to fill the concave groove on the common electrode (CE) overlapping the upper surface of the light emitting element (LE) and protrude upwardly convexly.

[0150] As shown in FIGS. 11a and 11b, by adding a separate micro lens (MLA) to the upper surface of the light emitting element (LE), the effect of controlling the direction of light emission can be achieved.

[0151] FIGS. 12 and 13 differ from the embodiments of FIGS. 8 and 9 in that the diameter of the connecting electrode (112) and the diameter of the light-emitting element (LE) are the same. In the following description referring to FIGS. 12 and 13, the differences from the embodiments of FIGS. 8 and 9 will be mainly explained.

[0152] Referring to FIGS. 12 and 13, the diameter of the light-emitting element (LE) and the diameter of the connecting electrode (112) may be the same. The light-emitting element (LE) and the connecting electrode may completely overlap in the third direction (DR3).

[0153] The light emitting element (LE) may include a first semiconductor layer (SEM1), an electron blocking layer (EBL), an active layer (MQW), a superlattice layer (SLT), and a second semiconductor layer (SEM2).

[0154] The side surfaces of the first semiconductor layer (SEM1), the electron blocking layer (EBL), the active layer (MQW), the superlattice layer (SLT), the second semiconductor layer (SEM2), and the connecting electrode (112) can be arranged on the same line.

[0155] The side surfaces of the first semiconductor layer (SEM1), the electron blocking layer (EBL), the active layer (MQW), the superlattice layer (SLT), the second semiconductor layer (SEM2), and the connecting electrode (112) can be arranged in a row in the third direction.

[0156] The second semiconductor layer (SEM2) may include a lens portion (SEM2-1) and a body portion (SEM2-2). The diameter of the lens portion (SEM2-1) may be the same as the diameter of the body portion (SEM2-2). The lens portion (SEM2-1) and the body portion (SEM2-2) may be arranged in a row in the third direction, but are not limited thereto. In addition, the side surface of the lens portion (SEM2-1) may be arranged in a row with the side surface of the connection electrode (112) in the third direction.

[0157] The height of the reflective layer (REF) may be lower than the height of the planarization layer (113). The height of the reflective layer (REF) is the distance from the upper surface of the interlayer insulating layer (111) to the upper surface of the reflective layer (REF), and the height of the planarization layer (113) may be defined as the distance from the upper surface of the interlayer insulating layer (111) to the upper surface of the planarization layer (113). Therefore, the common electrode (CE) and the reflective layer (REF) may not be in contact.

[0158] Fig. 14 is a cross-sectional view schematically illustrating a display area of ​​a display device according to another embodiment. Fig. 15 is an enlarged view showing in detail the common electrode and light-emitting element illustrated in Fig. 14.

[0159] FIGS. 14 and 15 differ from the embodiments of FIGS. 12 and 13 in that the lens shape of the upper surface of the light-emitting element (LE) is convex downward. In addition, FIGS. 14 and 15 differ from the embodiments of FIGS. 10 and 11 in that the diameter of the connecting electrode (112) and the diameter of the light-emitting element (LE) are the same.

[0160] In the following, the description with reference to FIGS. 14 and 15 will focus on differences from the embodiments of FIGS. 12 and 13.

[0161] Referring to FIGS. 14 and 15, the upper surface of the light-emitting element (LE) may have a lens shape. The upper surface of the light-emitting element (LE) has a convex shape toward the first substrate (SUB1). The upper surface of the light-emitting element (LE) has a convex shape toward the first substrate (SUB1). The first common electrode (CE) has a convex shape in a downward direction along the upper surface of the light-emitting element (LE).

[0162] The light emitting element (LE) may include a first semiconductor layer (SEM1), an electron blocking layer (EBL), an active layer (MQW), a superlattice layer (SLT), and a second semiconductor layer (SEM2).

[0163] The second semiconductor layer (SEM2) has a lens-shaped upper surface that is convex downward, thereby focusing light emitted from the active layer (MQW) to improve the front light emission effect. In another modified example, a reflective layer may be disposed on the side surface of each of the light-emitting elements (LE) on the insulating layer (INS), on the upper surface of the connecting electrodes (112) that do not overlap with the light-emitting elements (LE), and on the side surface of the connecting electrode (112). As described with reference to Fig. 13, the height of the reflective layer may be lower than the height of the planarization layer (113). Therefore, the common electrode (CE) and the reflective layer may not be in contact. Fig. 16 is a cross-sectional view schematically illustrating a display device including a wavelength conversion layer and a color filter layer according to another embodiment.

[0164] Referring to FIG. 16, the display device (10) may further include a semiconductor circuit board (110), a light emitting element layer (120), a wavelength conversion layer (QDL), and a color filter layer (CFL).

[0165] The semiconductor circuit board (110) and the light emitting element layer (120) are the same as the semiconductor circuit board (110) and the light emitting element layer (120) described in FIGS. 6 and 7, so overlapping descriptions are omitted.

[0166] The light emitting element layer (120) may include a light emitting element (LE), an insulating layer (INS), a common electrode (CE), and a wavelength conversion layer (QDL).

[0167] Each of the plurality of pixels (PX) may include a plurality of light-emitting areas (EA1, EA2, EA3) that emit light. Each of the plurality of light-emitting areas (EA1, EA2, EA3) may include a light-emitting element (LE) that emits first light.

[0168] Each of the first light-emitting areas (EA1) refers to an area that emits a first light. Each of the first light-emitting areas (EA1) can directly output the first light output from the light-emitting element (LE). The first light may be light in the blue wavelength band. The blue wavelength band may be approximately 370 nm to 460 nm, but the embodiments of the present specification are not limited thereto.

[0169] Each of the first light-emitting areas (EA1) may include a light-emitting element (LE), a light-transmitting layer (TPL), and a first color filter (CF1). The light-emitting element (LE), the light-transmitting layer (TPL), and the first color filter (CF1) may overlap in a third direction (DR3). The light-transmitting layer (TPL) directly transmits the first light output from the light-emitting element (LE), and the first color filter (CF1) may transmit the first light. Therefore, each of the first light-emitting areas (EA1) may emit the first light.

[0170] Each of the second light-emitting areas (EA2) may include a light-emitting element (LE), a wavelength conversion layer (QDL), and a second color filter (CF2). The light-emitting element (LE), the wavelength conversion layer (QDL), and the second color filter (CF2) may overlap in a third direction (DR3). The wavelength conversion layer (QDL) may convert a portion of the first light output from the light-emitting element (LE) into fourth light and emit the converted light. For example, the fourth light may be light in a yellow wavelength band. The fourth light may be light including both a green wavelength band and a red wavelength band. In other words, the fourth light may be light that mixes the second light and the third light. The second color filter (CF2) may transmit the second light. Therefore, each of the second light-emitting areas (EA2) may emit the second light.

[0171] Each of the third light-emitting areas (EA3) may include a light-emitting element (LE), a wavelength conversion layer (QDL), and a third color filter (CF3). The light-emitting element (LE), the wavelength conversion layer (QDL), and the third color filter (CF3) may overlap in a third direction (DR3). The wavelength conversion layer (QDL) may convert a portion of the first light output from the light-emitting element (LE) into a fourth light and emit the converted light. The third color filter (CF3) may transmit the third light. Therefore, each of the second light-emitting areas (EA3) may emit the third light.

[0172] The area of ​​the light transmitting layer (TPL) and the area of ​​the wavelength conversion layer (QDL) may each be larger than the area of ​​the light emitting element (LE). The areas of each of the first color filter (CF1), the second color filter (CF2), and the third color filter (CF3) may each be larger than the area of ​​the light emitting element (LE). In addition, the areas of each of the first color filter (CF1), the second color filter (CF2), and the third color filter (CF3) may each be larger than the area of ​​the light transmitting layer (TPL) and the area of ​​the wavelength conversion layer (QDL).

[0173] In the first light-emitting area (EA1), the light-emitting element (LE) may be completely covered by the light-transmitting layer (TPL), and the light-transmitting layer (TPL) may be completely covered by the first color filter (CF1). In addition, in the second light-emitting area (EA2), the light-emitting element (LE) may be completely covered by the wavelength conversion layer (QDL), and the wavelength conversion layer (QDL) may be completely covered by the second color filter (CF2). Furthermore, in the third light-emitting area (EA3), the light-emitting element (LE) may be completely covered by the wavelength conversion layer (QDL), and the wavelength conversion layer (QDL) may be completely covered by the third color filter (CF3).

[0174] It is exemplified that the planar shape of the light transmitting layer (TPL), the planar shape of the wavelength conversion layer (QDL), the planar shape of the first color filter (CF1), the planar shape of the second color filter (CF2), and the planar shape of the third color filter (CF3) follow the planar shape of the light emitting element (LE). For example, when the light emitting element (LE) has a rectangular planar shape, each of the light transmitting layer (TPL), the wavelength conversion layer (QDL), the first color filter (CF1), the second color filter (CF2), and the third color filter (CF3) may have a rectangular planar shape. Alternatively, the light emitting element (LE) may have a polygonal, circular, elliptical, or irregular shape other than a square, and in this case, the light transmitting layer (TPL), the wavelength conversion layer (QDL), the first color filter (CF1), the second color filter (CF2), and the third color filter (CF3) may also have a polygonal, circular, elliptical, or irregular shape other than a square.

[0175] Alternatively, the planar shape of the light transmitting layer (TPL), the planar shape of the wavelength conversion layer (QDL), the planar shape of the first color filter (CF1), the planar shape of the second color filter (CF2), and the planar shape of the third color filter (CF3) may not follow the planar shape of the light emitting element (LE). In this case, each of the planar shape of the light transmitting layer (TPL), the planar shape of the wavelength conversion layer (QDL), the planar shape of the first color filter (CF1), the planar shape of the second color filter (CF2), and the planar shape of the third color filter (CF3) may be different from the planar shape of the light emitting element (LE). In addition, each of the planar shape of the light transmitting layer (TPL) and the planar shape of the wavelength conversion layer (QDL) may be different from each of the planar shape of the first color filter (CF1), the planar shape of the second color filter (CF2), and the planar shape of the third color filter (CF3).

[0176] The light transmitting layer (TPL) may include a light transmitting organic material. For example, the light transmitting layer (TPL) may include an epoxy resin, an acrylic resin, a cardo resin, or an imide resin.

[0177] The wavelength conversion layer (QDL) can be arranged to completely cover the light emitting element (LE) in each of the second light emitting areas (EA2) and the third light emitting areas (EA3).

[0178] A wavelength conversion layer (QDL) may include a base resin (BRS) and wavelength conversion particles (WCPs). The wavelength conversion particles (WCPs) may convert first light emitted from a light emitting element (LE) into fourth light. For example, the first wavelength conversion particles may convert light in a blue wavelength band into light in a yellow wavelength band. The first wavelength conversion particles may be quantum dots (QDs), quantum rods, fluorescent materials, or phosphorescent materials. The quantum dots may include group IV nanocrystals, group II-VI compound nanocrystals, group III-V compound nanocrystals, group IV-VI nanocrystals, or a combination thereof.

[0179] A quantum dot may include a core and a shell overcoating the core. The core may be, for example, but not limited to, at least one of CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InP, InAs, InSb, SiC, Ca, Se, In, P, Fe, Pt, Ni, Co, Al, Ag, Au, Cu, FePt, Fe2O3, Fe3O4, Si, and Ge. The shell may include, but is not limited to, at least one of ZnS, ZnSe, ZnTe, CdS, CdSe, CdTe, HgS, HgSe, HgTe, AlN, AlP, AlAs, AlSb, GaN, GaP, GaAs, GaSb, GaSe, InN, InP, InAs, InSb, TlN, TlP, TlAs, TlSb, PbS, PbSe and PbTe.

[0180] The wavelength conversion layer (QDL) may further include a scatterer for scattering light from the light emitting element (LE) in a random direction. In this case, the scatterer may include metal oxide particles or organic particles. For example, the metal oxide may be titanium oxide (TiO2), zirconium oxide (ZrO2), silicon dioxide (SiO2), aluminum oxide (Al2O3), indium oxide (In2O3), zinc oxide (ZnO), or tin oxide (SnO2). In addition, the organic particles may include an acrylic resin or a urethane resin. The diameter of the scatterer may be several to several tens of nanometers.

[0181] A partition wall (PW) is arranged on a common electrode (CE) of a display area (DPA) and can divide a plurality of light-emitting areas (EA1, EA2, EA2) and a non-light-emitting area. The partition wall (PW) is arranged to extend in a first direction (DR1) and a second direction (DR2) and can be formed in a grid-like pattern throughout the display area (DPA). In addition, the partition wall (PW) does not overlap with the plurality of light-emitting areas (EA1, EA2, EA3) and can overlap with the non-light-emitting area (NEA).

[0182] The partition wall (PW) may include a plurality of openings (OP1, OP2, OP3) defining light emitting areas. The plurality of openings (OP1, OP2, OP3) may include a first opening (OP1) overlapping a first light emitting area (EA1), a second opening (OP2) overlapping a second light emitting area (EA2), and a third opening (OP3) overlapping a third light emitting area (EA3). Here, the plurality of openings (OP1, OP2, OP3) may correspond to the plurality of light emitting areas (EA1, EA2, EA3). That is, the first opening (OP1) may correspond to the first light emitting area (EA1), the second opening (OP2) may correspond to the second light emitting area (EA2), and the third opening (OP3) may correspond to the third light emitting area (EA3).

[0183] The barrier rib (PW) may serve to provide a space for forming a wavelength conversion layer (QDL). To this end, the barrier rib (PW) may have a predetermined thickness, for example, the thickness of the barrier rib (PW) may be in the range of 1 μm to 10 μm. To enable the barrier rib (PW) to have a predetermined thickness, the barrier rib (PW) may include an organic insulating material. The organic insulating material may include, for example, an epoxy resin, an acrylic resin, a cardo resin, or an imide resin.

[0184] A reflective layer (RF) may be placed inside the space formed by the partition wall (PW). The reflective layer (RF) may be referred to as a partition wall reflective layer (RF) to distinguish it from the reflective layer (REF) placed on the side of the light emitting element (LE) with reference to FIGS. 8 and 9.

[0185] The barrier rib reflective layer (RF) may be in direct contact with the barrier rib (PW) and the wavelength conversion layer (QDL). The barrier rib reflective layer (RF) serves to reflect light emitted from the light emitting element (LE) that propagates in a lateral direction rather than an upward direction. The barrier rib reflective layer (RF) may include a metal material having a high reflectivity, such as aluminum (Al). A plurality of color filters (CF1, CF2, CF3) may be disposed on the barrier rib (PW), the light transmitting layer (TPL), and the wavelength conversion layer (QDL). The plurality of color filters (CF1, CF2, CF3) may be disposed to overlap a plurality of pixel circuit units (PXC) and the wavelength conversion layer (QDL). The plurality of color filters (CF1, CF2, CF3) may include a first color filter (CF1), a second color filter (CF2), and a third color filter (CF3).

[0186] The plurality of color filters (CF1, CF2, CF3) may include first color filters (CF1), second color filters (CF2), and third color filters (CF3).

[0187] Each of the first color filters (CF1) may be disposed on the light transmitting layer (TPL) in the first light emitting area (EA1). Each of the first color filters (CF1) may transmit the first light and absorb or block the second light and the third light. For example, each of the first color filters (CF1) may transmit the light in the blue wavelength band and absorb or block the light in the green and red wavelength bands. Therefore, each of the first color filters (CF1) may transmit the first light emitted from the light emitting element (LE). That is, the first light emitted from the light emitting element (LE) in the first light emitting area (EA1) is not converted by a separate wavelength conversion layer and may transmit the first color filter (CF1) through the light transmitting layer (TPL). Therefore, each of the first light emitting areas (EA1) may emit the first light.

[0188] Each of the second color filters (CF2) may be disposed on the wavelength conversion layer (QDL) in the second light-emitting area (EA2). Each of the second color filters (CF2) may transmit second light and absorb or block first light and third light. For example, each of the second color filters (CF2) may transmit light in a green wavelength band and absorb or block light in blue and red wavelength bands. Therefore, each of the second color filters (CF2) may absorb or block first light that is not converted by the wavelength conversion layer (QDL) among the first light emitted from the light-emitting element (LE). In addition, each of the second color filters (CF2) may transmit second light corresponding to a green wavelength band among the fourth light converted by the wavelength conversion layer (QDL) and absorb or block third light corresponding to a blue wavelength band. Therefore, each of the second light-emitting areas (EA1) may emit second light.

[0189] Each of the third color filters (CF3) may be disposed on the wavelength conversion layer (QDL) in the third light-emitting area (EA3). Each of the third color filters (CF3) may transmit third light and absorb or block first light and second light. For example, each of the third color filters (CF3) may transmit light in a red wavelength band and absorb or block light in blue and green wavelength bands. Therefore, each of the third color filters (CF3) may absorb or block first light that is not converted by the wavelength conversion layer (QDL) among the first light emitted from the light-emitting element (LE). In addition, each of the third color filters (CF3) may transmit third light corresponding to a red wavelength band among the fourth light converted by the wavelength conversion layer (QDL) and absorb or block second light corresponding to a green wavelength band. Therefore, each of the third light-emitting areas (EA3) may emit third light.

[0190] A black matrix (or light-blocking member) (BM) may be arranged between a plurality of color filters (CF1, CF2, CF3). For example, the black matrix (BM) may be arranged between the first color filter (CF1) and the second color filter (CF2), between the second color filter (CF2) and the third color filter (CF3), and between the first color filter (CF1) and the third color filter (CF3). The black matrix (BM) may include an inorganic black pigment such as carbon black or an organic black pigment.

[0191] In addition, the plurality of color filters (CF1, CF2, CF3) may partially overlap with neighboring color filters. For example, the first color filter (CF1) may have a region that partially overlaps with the neighboring second color filter (CF2), the second color filter (CF2) may have a region that partially overlaps with the neighboring first color filter (CF1) or the third color filter (CF3), and the third color filter (CF3) may have a region that partially overlaps with the neighboring first color filter (CF1) or the second color filter (CF2). In this way, the region formed by the plurality of color filters (CF1, CF2, CF3) overlapping each other may function as a black matrix (BM) that blocks light leakage due to the overlap, and thus the black matrix (BM) may be omitted.

[0192] A shading member (BM) may be arranged on the partition wall (PW). The shading member (BM) may overlap the non-emission area (NEA) to block the transmission of light. The shading member (BM) may be arranged in a roughly grid shape on a plane similar to the partition wall (PW). The shading member (BM) may be arranged to overlap the partition wall (PW) and may not overlap the emitting areas (EA1, EA2, EA3).

[0193] In one embodiment, the light-shielding member (BM) may include an organic light-shielding material and may be formed through a coating process and exposure process of the organic light-shielding material. The light-shielding member (BM) may include a dye or pigment having light-shielding properties and may be a black matrix. At least a portion of the light-shielding member (BM) may overlap adjacent color filters (CF1, CF2, CF3), and the color filters (CF1, CF2, CF3) may overlap at least a portion of the light-shielding member (BM).

[0194] When a shading member (BM) is placed on a partition wall (PW), at least a portion of the external light is absorbed by the shading member (BM). Therefore, color distortion due to external light reflection can be reduced. In addition, the shading member (BM) can prevent color mixing by reducing or preventing light penetration between adjacent light-emitting areas, thereby further improving color reproducibility.

[0195] A protective layer (BF) may be disposed under a plurality of color filters (CF1, CF2, CF3) and a light-shielding member (BM). The protective layer (BF) may be disposed on a barrier rib (PW), a light-transmitting layer (TPL), and a wavelength conversion layer (QDL). One surface of the protective layer (BF), for example, an upper surface, may contact lower surfaces of the plurality of color filters (CF1, CF2, CF3) and the light-shielding member (BM), respectively. In addition, another surface, for example, a lower surface, opposite to one surface of the protective layer (BF) may contact upper surfaces of the barrier rib (PW), the light-transmitting layer (TPL), and the wavelength conversion layer (QDL), respectively. The protective layer (BF) may include an inorganic insulating material. For example, the protective layer (BF) may include, but is not limited to, silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (AlxOy), aluminum nitride (AlN), etc. The protective layer (BF) may be formed to a predetermined thickness, for example, may be formed in a range of 0.01 to 1 ㎛, but is not limited thereto.

[0196] Hereinafter, a manufacturing process of a display device (10) according to one embodiment will be described with reference to other drawings.

[0197] FIGS. 17 to 26 are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment.

[0198] Figures 17 to 26 illustrate the structure of each layer of the display device (10) according to the formation order, respectively, in cross-sectional and plan views. Figures 17 to 26 focus on the manufacturing process of the light-emitting body part (LEP), and these can generally correspond to the cross-sectional view of Figure 6.

[0199] As shown in FIG. 17 and FIG. 18, a first substrate (SUB1) having a pixel electrode (PE) and a second substrate (SUB2) having a light-emitting material layer (LEML) are bonded together with a connecting electrode layer (112L), and the second substrate (SUB2) is removed.

[0200] First, referring to FIG. 17, a first connection electrode layer (112L_1) is formed on a first substrate (SUB1) having a pixel electrode (PE), and a second connection electrode layer (112L_2) is formed on a light-emitting material layer (LEML) of a second substrate (SUB2).

[0201] For example, first, an interlayer insulating layer (111) is formed on a first substrate (SUB1) on which pixel electrodes (PE) are not arranged. The upper surface of the interlayer insulating layer (111) and the upper surfaces of each of the pixel electrodes (PE) can be flatly connected. That is, the height difference between the upper surface of the first substrate (SUB1) and the upper surface of the pixel electrode (PE) can be eliminated by the interlayer insulating layer (111). The interlayer insulating layer (111) may be formed of a silicon oxide film (SiO2), an aluminum oxide film (Al2O3), or a hafnium oxide film (HfO). x ) can be formed into a film of inorganic substances.

[0202] Then, a first connection electrode layer (112L_1) is deposited on the pixel electrodes (PE) and the interlayer insulating layer (111). The first connection electrode layer (112L_1) may include at least one of gold (Au), copper (Cu), tin (Sn), silver (Ag), aluminum (Al), and titanium (Ti). For example, the first connection electrode layer (112L_1) may include a 9:1 alloy, an 8:2 alloy, or a 7:3 alloy of gold and tin, or may include an alloy of copper, silver, and tin (SAC305).

[0203] Additionally, a buffer film (BF) may be formed on one surface of the second substrate (SUB2). The second substrate (SUB2) may be a silicon substrate or a sapphire substrate. The buffer film (BF) may be a silicon oxide film (SiO2), an aluminum oxide film (Al2O3), or a hafnium oxide film (HfO). x ) can be formed into a film of inorganic substances.

[0204] A light-emitting material layer (LEML) may be disposed on the buffer film (BF). The light-emitting material layer (LEML) may include a first semiconductor material layer (LEMD) and a second semiconductor material layer (LEMU). The second semiconductor material layer (LEMU) may be disposed on the buffer film (BF), and the first semiconductor material layer (LEMD) may be disposed on the second semiconductor material layer (LEMU).

[0205] The first semiconductor material layer (LEMD) may include a first semiconductor layer (SEM1), an electron blocking layer (EBL), an active layer (MQW), a superlattice layer (SLT), and a second semiconductor layer (SEM2), as shown in Fig. 7. The second semiconductor material layer (LEMU) may be a semiconductor layer that is not doped with a dopant, i.e., an undoped semiconductor layer. For example, the second semiconductor material layer (LEMU) may be undoped-GaN that is not doped with a dopant.

[0206] The second connection electrode layer (112L_2) may be deposited on the first semiconductor material layer (LEMD). The second connection electrode layer (112L_2) may include the same material as the first connection electrode layer (112L-1), but is not limited thereto.

[0207] The second connecting electrode layer (112L_2) may include at least one of gold (Au), copper (Cu), tin (Sn), silver (Ag), aluminum (Al), and titanium (Ti). For example, the second connecting electrode layer (112L_2) may include a 9:1 alloy, an 8:2 alloy, or a 7:3 alloy of gold and tin, or may include an alloy of copper, silver, and tin (SAC305).

[0208] As shown in the following Figure 18, the first connection electrode layer (112L_1) and the second connection electrode layer (112L_2) are bonded, and the second substrate (SUB2) is removed.

[0209] For example, a first connection electrode layer (112L_1) of a first substrate (SUB1) and a second connection electrode layer (112L_2) of a second substrate (SUB2) are brought into contact. Then, the first connection electrode layer (112L_1) and the second connection electrode layer (112L_2) are melt-bonded at a predetermined temperature to form one connection electrode layer (112L). That is, the connection electrode layer (112L) is disposed between the pixel electrodes (PE) of the first substrate (SUB1) and the light-emitting material layer (LEML) of the second substrate (SUB2), and serves as a bonding metal layer that bonds the pixel electrodes (PE) of the first substrate (SUB1) and the light-emitting material layer (LEML) of the second substrate (SUB2). In one embodiment, connection electrodes are formed on each of the first substrate (SUB1) and the second substrate (SUB2) and bonded. However, the first substrate (SUB1) and the second substrate (SUB2) may be bonded by forming a connection electrode on only one of the first substrate (SUB1) or the second substrate (SUB2).

[0210] After bonding the first connection electrode layer (112L_1) and the second connection electrode layer (112L_2), the second substrate (SUB2) and the buffer film (BF) can be removed through a polishing process such as a CMP (Chemical Mechanical Polishing) process and / or an etching process. In addition, the second semiconductor material layer (LEMU) of the light-emitting material layer (LEML) can be removed through a polishing process such as a CMP process.

[0211] As shown in FIGS. 19 and 20, a first mask pattern (MP1) in the shape of a lens is patterned on the light-emitting material layer (LEML). To this end, as shown in FIG. 19, a photosensitive polymer mask pattern (MP) is first patterned using a photolithography process. Thereafter, the first mask pattern (MP1) is formed into a lens shape using a reflow process.

[0212] The reflow process melts the patterned photosensitive polymer mask into a liquefied state by heating the polymer material to a temperature exceeding the melting point of the polymer material for a predetermined period of time. At this time, the surface tension of the liquefied material will form it into a lens-shaped pattern with a smooth, curved surface. After the reflow process, as shown in FIG. 19, the patterned photosensitive polymer mask pattern (MP) can be formed into a lens-shaped first mask pattern (MP1), as shown in FIG. 20.

[0213] Afterwards, referring to FIG. 21, a light emitting element (LE) having a lens-shaped upper surface is formed using a first mask pattern (MP1) having a lens shape.

[0214] For example, a region on which the first mask pattern (MP1) is not arranged on the first semiconductor material layer (LEMD) is first etched until the connection electrode layer (112L) is exposed. Accordingly, the upper surface of the first semiconductor material layer (LEMD) can have a lens shape with a smooth curvature surface like the first mask pattern (MP1).

[0215] Referring to the following Figures 22 and 23, a connecting electrode (112) is formed by a photolithography process and an etching process.

[0216] For example, a photosensitive polymer mask pattern (MP) surrounding a light emitting element (LE) is patterned using a photolithography process. Thereafter, a connecting electrode layer (112L) is etched until the interlayer insulating layer (111) is exposed to form a connecting electrode (112). At this time, the upper edge of the connecting electrode (112) may have a curvature.

[0217] Next, referring to FIGS. 24 and 25, an insulating layer (INS) and a planarization layer (113) are formed on the side of the light emitting element (LE).

[0218] For example, referring to FIG. 24, an insulating layer (INS) is deposited to cover the front surface of the first substrate (SUB1) on which the light emitting element (LE) is arranged. The insulating layer (INS) may be a silicon oxide film (SiO2), an aluminum oxide film (Al2O3), or a hafnium oxide film (HfO x ) can be formed as a film, but is not limited thereto.

[0219] The insulating layer (INS) is formed on the upper and side surfaces of each light emitting element (LE) and on the side interlayer insulating layer (111) of the connecting electrode (112).

[0220] As shown in Fig. 25, a planarization layer (113) is formed on a first substrate (SUB1) on which an insulating layer (INS) is formed. The planarization layer (113) may be placed in an area of ​​the light emitting element (LE) excluding an area where the insulating layer (INS) is to be opened. The planarization layer (113) may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin, but is not limited thereto.

[0221] Then, the insulating layer (INS) disposed on the upper surface of the light emitting element (LE) that is not covered by the planarization layer (113) is removed. That is, an opening (OP) is formed in the upper region of the light emitting element (LE) by etching the insulating layer (INS), so that the upper portion of the light emitting element (LE) can be exposed.

[0222] Next, as shown in Fig. 26, a common electrode (CE) is formed on the upper surface of the light emitting element (LE) exposed by the opening (OP) and the planarization layer (113).

[0223] The common electrode (CE) may include a transparent conductive oxide (TCO), such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0224] Next, FIGS. 27 to 30 are cross-sectional views for explaining a method of manufacturing a display device according to another embodiment.

[0225] Figures 27 to 30 illustrate the structure of each layer of the display device (10) according to the formation order, respectively, in cross-sectional and plan views. Figures 27 to 30 focus on manufacturing processes according to other embodiments following the manufacturing processes described in Figures 17 to 24, and these can generally correspond to the cross-sectional views of Figure 8.

[0226] As shown in FIGS. 27 and 28, a reflective material layer (REFL) is deposited to cover the first substrate (SUB1) on the insulating layer (INS).

[0227] Then, a large voltage difference is formed in the third direction (DR3) without a separate mask, and the reflective material layer (REFL) is etched by the etching material. In this case, the etching material can move in the third direction (DR3) by voltage control, that is, move from the top to the bottom, and etch the reflective material layer (REFL). As a result, the reflective material layer (REFL) arranged on the horizontal plane defined by the first direction (DR1) and the second direction (DR2) as shown in FIG. 28 is removed, whereas the reflective material layer (REFL) arranged on the vertical plane defined by the third direction (DR3) may not be removed. Therefore, the reflective material layer (REFL) arranged on the upper surface of the light-emitting element (LE) and the upper surface of the insulating layer (INS) on which the light-emitting element (LE) is not arranged can be removed. The reflective material layer (REFL) arranged on the side surfaces of the light-emitting element (LE) may not be removed. The reflective material layer (REFL) that remains on the side surfaces of the light-emitting element (LE) without being removed in this way can be referred to as a reflective layer (REF). The reflective layer (REF) can be formed to surround the side surfaces of the light-emitting element (LE) on the insulating layer (INS).

[0228] As illustrated in FIG. 29, a planarization layer (113) is formed on a first substrate (SUB1) on which an insulating layer (INS) and a reflective layer (REF) are formed. The planarization layer (113) may be disposed in an area of ​​the light emitting element (LE) except for an area where the insulating layer (INS) is to be opened. The planarization layer (113) may be formed lower than the height of the light emitting element (LE). The planarization layer (113) may be formed higher than the reflective layer (REF). Therefore, the common electrode (CE) to be formed later and the reflective layer (REF) may not be in contact. The planarization layer (113) may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin, but is not limited thereto.

[0229] Then, the insulating layer (INS) disposed on the upper surface of the light emitting element (LE) that is not covered by the planarization layer (113) is removed. That is, an opening (OP) is formed in the upper region of the light emitting element (LE) by etching the insulating layer (INS), so that the upper portion of the light emitting element (LE) can be exposed.

[0230] Next, as shown in Fig. 30, a common electrode (CE) is formed on the upper surface of the light emitting element (LE) exposed by the opening (OP) and the planarization layer (113).

[0231] The common electrode (CE) may include a transparent conductive oxide (TCO), such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0232] Figures 31 to 43 are cross-sectional views illustrating a method of manufacturing a display device according to another embodiment.

[0233] Figures 31 to 43 illustrate the structure of each layer of the display device (10) according to the formation order, respectively, in cross-sectional and plan views. Figures 31 to 43 focus on the manufacturing process of the light emitting body part (LEP), and these can generally correspond to the cross-sectional view of Figure 12.

[0234] Referring to Fig. 31, a light-emitting material layer (LEML) and a connecting electrode layer (112L) are formed on a base substrate (BSUB).

[0235] First, a second substrate (SUB2) is prepared. The second substrate (SUB2) may be a sapphire substrate (Al2O3) or a silicon wafer containing silicon. However, the present invention is not limited thereto, and in one embodiment, a case in which the second substrate (SUB2) is a sapphire substrate is exemplified and described.

[0236] A second semiconductor material layer (LEMU) and a light-emitting material layer (LEML) are sequentially formed on a second substrate (SUB2).

[0237] The first semiconductor material layer (LEMD) may include a first semiconductor layer (SEM1), an electron blocking layer (EBL), an active layer (MQW), a superlattice layer (SLT), a layer, and a second semiconductor layer (SEM2), as shown in FIG. 13.

[0238] The light-emitting material layer (LEML) grown by an epitaxial method can be formed by growing a seed crystal. Here, the method for forming the light-emitting material layer (LEML) may be electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-type thermal evaporation, sputtering, metal-organic chemical vapor deposition (MOCVD), etc., and preferably, the LEML can be formed by metal-organic chemical vapor deposition (MOCVD). However, the present invention is not limited thereto.

[0239] The precursor material for forming the light emitting material layer (LEML) is not particularly limited within a range that can be conventionally selected to form the target material. For example, the precursor material may be a metal precursor containing an alkyl group such as a methyl group or an ethyl group. Examples thereof include, but are not limited to, compounds such as trimethyl gallium (Ga(CH3)3), trimethyl aluminum (Al(CH3)3), and triethyl phosphate ((C2H5)3PO4).

[0240] Specifically, a second semiconductor material layer (LEMU) is formed on a second substrate (SUB2). Although the drawing illustrates that the second semiconductor material layer (LEMU) is laminated in one layer, the present invention is not limited thereto, and a plurality of layers may be formed. The second semiconductor material layer (LEMU) may be arranged to reduce a difference in lattice constants between the first semiconductor material layer (LEMD) and the base substrate (BSUB). For example, the second semiconductor material layer (LEMU) may include an undoped semiconductor, and may be a material that is not doped as an n-type or p-type. In an exemplary embodiment, the second semiconductor material layer (LEMU) may be at least one of undoped InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, but is not limited thereto.

[0241] A first semiconductor material layer (LEMD) is formed on a second semiconductor material layer (LEMU) using the method described above. The first semiconductor material layer (LEMD) is formed by sequentially forming a second semiconductor material layer, a superlattice material layer, an active material layer, an electron blocking material layer, and a first semiconductor material layer.

[0242] Thereafter, a connection electrode layer (112L) is formed on the first semiconductor material layer (LEMD). The connection electrode layer (112L) may include at least one of gold (Au), copper (Cu), tin (Sn), silver (Ag), aluminum (Al), and titanium (Ti). For example, the first connection electrode layer (112L_1) may include a 9:1 alloy, an 8:2 alloy, or a 7:3 alloy of gold and tin, or may include an alloy of copper, silver, and tin (SAC305).

[0243] Next, referring to FIG. 32, a portion of the connecting electrode layer (112L) and the first semiconductor material layer (LEMD) are etched. The superlattice material layer, the active material layer, the electron blocking material layer, and the first semiconductor material layer (LEMD) of the first semiconductor material layer (LEMD) can be etched.

[0244] For example, a photosensitive polymer mask pattern (MP) is formed on a first semiconductor material layer (LEMD). The photosensitive polymer mask pattern (MP) may be a hard mask including an inorganic material or a photoresist mask including an organic material. The photosensitive polymer mask pattern (MP) prevents the first semiconductor material layer (LEMD) underneath from being etched. Then, using the photosensitive polymer mask pattern (MP), the first semiconductor material layer (LEMD) is etched (1) until a second semiconductor material layer (SEM2L) among the first semiconductor material layers (LEMD) is exposed. st etch)

[0245] Semiconductor material layers can be etched by a conventional method. For example, the process for etching semiconductor material layers can be dry etching, wet etching, reactive ion etching (RIE), deep reactive ion etching (DRIE), inductively coupled plasma reactive ion etching (ICP-RIE), etc. In the case of dry etching, anisotropic etching is possible, so it can be suitable for vertical etching. When using the etching method described above, the etchant can be Cl2 or O2, etc., but is not limited thereto.

[0246] The light emitting material layer (LEML) overlapping the photosensitive polymer mask pattern (MP) is not etched.

[0247] Referring to FIG. 33, a second substrate (SUB2) is attached to a carrier substrate (CSUB). For example, an etched first semiconductor material layer (LEMD) of the second substrate (SUB2) is attached to the carrier substrate (CSUB).

[0248] The carrier substrate (CSUB) may be composed of a first support layer (CSUB-1) and a first adhesive layer (CSUB-2) disposed on the first support layer (CSUB-1). The first support layer (CSUB-1) may be made of a material that is transparent and mechanically stable so that light can pass through it. For example, the support layer may include a transparent polymer such as polyester, polyacrylic, polyepoxy, polyethylene, polystyrene, polyethylene terephthalate, etc. The first adhesive layer (CSUB-2) may include an adhesive material for adhering the light emitting element (LE). For example, the adhesive material may include urethane acrylate, epoxy acrylate, polyester acrylate, etc. The adhesive material may be a material whose adhesive strength changes when ultraviolet (UV) light or heat is applied, and thus the first adhesive layer (CSUB-2) may be easily separated from the light emitting element (LE).

[0249] Next, referring to FIG. 34, a laser (1) is applied to the second substrate (SUB2). st The light-emitting material layer (LEML) and the second substrate (SUB2) are separated by irradiating the laser.

[0250] The process of separating the second substrate (SUB2) can be separated by the laser lift-off (LLO) process. The laser lift-off process uses a laser, and a KrF excimer laser (248 nm wavelength) can be used as a source. The energy density of the excimer laser is irradiated in the range of approximately 550 mJ / cm2 to 950 mJ / cm2, and the irradiation area (incident area) is 50 x 50 ㎛. 2 The range may be 1 x 1㎠, but is not limited thereto. By irradiating the second substrate (SUB2) with a laser, the second substrate (SUB2) can be separated from the light-emitting material layer (LEML).

[0251] Afterwards, the second semiconductor material layer (LEMU) can be removed through a polishing process such as a CMP process.

[0252] Next, referring to FIGS. 35 and 36, a photosensitive polymer mask (PR) is formed on the first semiconductor material layer (LEMD) by a photolithography process, and then the photosensitive polymer mask (PR) is shaped into a lens shape using a reflow process. Since the reflow process has been described above, a description thereof is omitted.

[0253] Afterwards, referring to FIG. 37, a light-emitting element (LE) having a lens-shaped upper surface is formed using a photosensitive polymer mask (PR) having a lens shape.

[0254] For example, the second semiconductor layer (SEM2) and the adhesive layer (CSUB-2) in the area where the photosensitive polymer mask pattern (PR) is not arranged on the first semiconductor material layer (LEMD) are etched. Accordingly, the upper surface of the first semiconductor material layer (LEMD) can have a lens shape with a smooth curvature surface like the photosensitive polymer mask pattern (PR). That is, the upper surface of the second semiconductor layer (SEM2) is formed into a lens shape. A light emitting element (LE) having an upper surface in the shape of a lens is formed.

[0255] Referring to Figure 38, the carrier substrate (CSUB) is aligned on the interposer substrate (ISUB).

[0256] The interposer substrate (ISUB) may be composed of a second support layer (ISUB-1) and a second adhesive layer (ISUB-2) disposed on the second support layer (ISUB-1), similar to the carrier substrate (CSUB).

[0257] The second support layer (ISUB-1) may be formed of a material that is transparent and mechanically stable so that light can pass through it. For example, the support layer may include a transparent polymer such as polyester, polyacrylic, polyepoxy, polyethylene, polystyrene, polyethylene terephthalate, etc. The second adhesive layer (ISUB-2) may include an adhesive material for adhering the light-emitting element (LE). For example, the adhesive material may include urethane acrylate, epoxy acrylate, polyester acrylate, etc. The adhesive material may be a material whose adhesive strength changes when ultraviolet (UV) light or heat is applied, thereby allowing the second adhesive layer (ISUB-2) to be easily separated from the light-emitting element (LE).

[0258] The upper surface of the lens-shaped light-emitting element (LE) can be placed on the second adhesive layer (ISUB-2).

[0259] Thereafter, referring to FIGS. 39 and 40, a laser is irradiated onto a desired light-emitting element (LE) to selectively transfer it to an interposer substrate (ISUB), and the carrier substrate (CSUB) is separated.

[0260] For example, by irradiating the first light-emitting element (LE1) and the third light-emitting element (LE3) with a laser, only the first light-emitting element (LE1) and the third light-emitting element (LE3) can be attached to the interposer substrate (ISUB). Thereafter, by applying ultraviolet light or heat to the carrier substrate (CSUB), the adhesive strength of the adhesive layer of the carrier substrate (CSUB) can be reduced, and then the carrier substrate (CSUB) can be physically or naturally separated.

[0261] Next, referring to FIGS. 41 to 43, a light emitting element (LE) attached to an interposer substrate (ISUB) is bonded onto a first substrate (SUB1), and the interposer substrate (ISUB) is separated.

[0262] To this end, a first substrate (SUB1) is prepared. The first substrate (SUB1) may include a plurality of pixel circuit units (PXC) and pixel electrodes (PE).

[0263] For example, a pixel electrode (PE) is formed on a first substrate (SUB1) on which a plurality of pixel circuit units (PXC) are formed. Then, an interposer substrate (ISUB) is aligned on the first substrate (SUB1). Alignment keys are arranged on each of the first substrate (SUB1) and the interposer substrate (ISUB) so that alignment can be achieved. Then, the first substrate (SUB1) and the interposer substrate (ISUB) are bonded together.

[0264] Thereafter, the pixel electrode (PE) of the first substrate (SUB1) and the connection electrode (112) of each light-emitting element (LE1, LE3) are brought into contact. Then, each light-emitting element (LE1, LE3) is joined to the first substrate (SUB1) by melting and bonding the pixel electrodes (PE) and the connection electrodes (112) at a predetermined temperature.

[0265] As described with reference to FIGS. 23 to 26, an insulating layer (INS), a planarization layer (113), and a common electrode (CE) can be formed on the first substrate (SUB1). The method for forming the insulating layer (INS), the planarization layer (113), and the common electrode (CE) has been described with reference to FIGS. 23 to 26, so a redundant description will be omitted.

[0266] In another modified example, as described with reference to FIGS. 27 to 30, an insulating layer (INS), a planarization layer (113), a reflective layer (REF), and a common electrode (CE) may be formed on the first substrate (SUB1). The method for forming the insulating layer (INS), the planarization layer (113), the reflective layer (REF), and the common electrode (CE) has been described with reference to FIGS. 23 to 26, and therefore, a redundant description thereof will be omitted.

[0267] Fig. 44 is an exemplary drawing showing a virtual reality device including a display device according to one embodiment. Fig. 44 shows a virtual reality device (1) to which a display device (10) according to one embodiment is applied.

[0268] Referring to FIG. 44, a virtual reality device (1) according to one embodiment may be a device in the form of glasses. The virtual reality device (1) according to one embodiment may include a display device (10), a left-eye lens (10a), a right-eye lens (10b), a support frame (20), glasses frame legs (30a, 30b), a reflective member (40), and a display device storage unit (50).

[0269] Although FIG. 44 illustrates a virtual reality device (1) including eyeglass frame legs (30a, 30b), the virtual reality device (1) according to one embodiment may also be applied to a head-mounted display including a head-mounted band that can be mounted on the head instead of the eyeglass frame legs (30a, 30b). That is, the virtual reality device (1) according to one embodiment is not limited to that illustrated in FIG. 44, and may be applied in various forms to various other electronic devices.

[0270] The display device housing (50) may include a display device (10) and a reflective member (40). An image displayed on the display device (10) may be reflected by the reflective member (40) and provided to the user's right eye through the right eye lens (10b). As a result, the user may view a virtual reality image displayed on the display device (10) through the right eye.

[0271] In FIG. 44, the display device housing (50) is exemplified as being arranged at the right end of the support frame (20), but the embodiment of the present specification is not limited thereto. For example, the display device housing (50) may be arranged at the left end of the support frame (20), in which case the image displayed on the display device (10) may be reflected by the reflective member (40) and provided to the user's left eye through the left eye lens (10a). As a result, the user may view the virtual reality image displayed on the display device (10) through the left eye. Alternatively, the display device housing (50) may be arranged at both the left end and the right end of the support frame (20), in which case the user may view the virtual reality image displayed on the display device (10) through both the left eye and the right eye.

[0272] FIG. 45 is an exemplary drawing showing a smart device including a display device according to one embodiment.

[0273] Referring to FIG. 45, a display device (10) according to one embodiment can be applied to a smart watch (2), which is one of smart devices.

[0274] Fig. 46 is an exemplary drawing showing a vehicle including a display device according to one embodiment. Fig. 46 shows a vehicle to which a display device (10) according to one embodiment is applied.

[0275] Referring to FIG. 46, display devices (10_a, 10_b, 10_c) according to one embodiment may be applied to a dashboard of a vehicle, a center fascia of a vehicle, or a CID (Center Information Display) placed on a dashboard of a vehicle. Alternatively, they may be used as a display device (10C). In addition, display devices (10_d, 10_e) according to one embodiment may be applied to a room mirror display replacing a side mirror of a vehicle.

[0276] FIG. 47 is an exemplary drawing showing a transparent display device including a display device according to one embodiment.

[0277] Referring to FIG. 47, a display device (10) according to one embodiment can be applied to a transparent display device. The transparent display device can display an image (IM) and transmit light at the same time. Therefore, a user positioned at the front of the transparent display device can not only view the image (IM) displayed on the display device (10), but also view an object (RS) or a background positioned at the back of the transparent display device. When the display device (10) is applied to a transparent display device, the semiconductor circuit board (110) of the display device (10) illustrated in FIG. 6 may include a light-transmitting portion capable of transmitting light or may be formed of a material capable of transmitting light.

[0278] Although embodiments of the present invention have been described with reference to the attached drawings, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without altering the technical spirit or essential characteristics of the present invention. Therefore, the embodiments described above should be understood to be illustrative in all respects and not restrictive.

Claims

1. Substrate; A light-emitting element comprising a first semiconductor layer, an active layer, and a second semiconductor layer, which are arranged on the substrate; A common electrode is disposed on the light emitting element, The second semiconductor layer has a lens-shaped surface on its upper surface that is positioned further away from the active layer, A display device in which the side surfaces of the active layer and the second semiconductor layer are aligned.

2. In paragraph 1, A display device in which the above lens-shaped surface is convex downwards or convex upwards.

3. In paragraph 1, The second semiconductor layer includes a lens portion that contacts the common electrode and has a lens-shaped upper surface, and a body portion that is arranged on a lower surface of the lens portion. A display device in which the side of the lens portion and the side of the body portion are aligned.

4. In paragraph 3, A display device further comprising a connecting electrode disposed between the substrate and the light-emitting element and having a diameter larger than the diameter of the light-emitting element.

5. In paragraph 4, A display device in which the diameter of the above connecting electrode is larger than the diameter of the above lens portion.

6. In paragraph 4, A display device further comprising an insulating layer partially surrounding the light emitting element.

7. In paragraph 6, A display device in which the insulating layer is disposed on a side of the light-emitting element and a portion of the substrate on which the light-emitting element is not disposed.

8. In paragraph 6, A display device further comprising a reflective layer partially surrounding the light-emitting element on the insulating layer.

9. In paragraph 3, A display device further comprising a connecting electrode disposed between the substrate and the light-emitting element and having a diameter equal to a diameter of the light-emitting element and a diameter of the lens portion.

10. In paragraph 1, a connecting electrode disposed between the substrate and the light-emitting element; and A display device further comprising a pixel electrode disposed between the substrate and the connecting electrode.

11. In paragraph 1, A display device further comprising a convex lens-shaped micro lens that is convex downward and overlaps the light-emitting element and is disposed on the common electrode.

12. In paragraph 11, A display device in which the lower surface of the above micro lens is in contact with the above common electrode.

13. In paragraph 1, A display device in which the second semiconductor layer has a plurality of downwardly convex lens shapes.

14. A step of laminating a first connection electrode layer on a second substrate on which a second semiconductor layer, an active layer, and a first semiconductor layer are sequentially grown; A step of melting and bonding the second substrate to the first substrate having the pixel circuit and the first connection electrode layer; A step of removing the second substrate; A step of forming a first mask pattern in the shape of a lens on the upper surface of the second semiconductor layer; A step of forming a plurality of light-emitting elements having the second semiconductor layer having a lens-shaped upper surface by etching the second semiconductor layer, the active layer, and the first semiconductor layer using the first mask pattern having the lens shape; A step of forming a second mask pattern surrounding the light-emitting element; A step of etching the first connection electrode layer using the second mask pattern; and Comprising a step of forming a common electrode on the light emitting element, A method for manufacturing a display device in which the side surfaces of the active layer and the second semiconductor layer are aligned.

15. In paragraph 14, A method for manufacturing a display device in which the upper surface of the lens shape is convex downward or convex upward.

16. In paragraph 14, The step of melting and bonding the first connecting electrode layer is as follows: A step of laminating a second connection electrode layer on a first substrate having the pixel circuit; and A method for manufacturing a display device, comprising the step of forming a connection electrode by melting and bonding the first connection electrode layer and the second connection electrode layer.

17. In paragraph 14, Before the step of forming the above common electrode, A step of depositing an insulating layer on the light-emitting element and on a part of the first substrate on which the light-emitting element is not arranged; A step of forming a planarization layer on a part of the first substrate on which the insulating layer is formed, wherein the planarization layer is formed lower than the height of the light-emitting element; and A method for manufacturing a display device further comprising the step of removing a portion of an insulating layer from a portion of the light emitting element that is not covered by the flattening layer.

18. In paragraph 17, A step of depositing a reflective material layer on the first substrate on which the insulating layer is laminated; and A method for manufacturing a display device, comprising the step of removing a portion of the reflective material layer from a horizontal plane of the first substrate to form a reflective layer that partially surrounds a side surface of the light-emitting element.

19. A step of laminating a connection electrode layer on a second substrate on which a second semiconductor layer, an active layer, and a first semiconductor layer are disposed; A step of forming a light-emitting element by etching the active layer, the first semiconductor layer, and the connecting electrode layer; A step of bonding the second substrate having the light-emitting element onto a carrier substrate; A step of removing the second substrate; A step of forming a lens-shaped mask pattern on the upper surface of the second semiconductor layer; A step of etching the upper surface of the second semiconductor layer to have a lens shape using the lens-shaped mask pattern, while forming the side surfaces of the active layer and the second semiconductor layer so as to be aligned; A step of transferring a light-emitting element on the carrier substrate onto a first substrate including a pixel electrode using an interposer substrate; and A step of removing the above interposer substrate; A method for manufacturing a display device, comprising the step of forming a common electrode on the light-emitting element.

20. In paragraph 19, A method for manufacturing a display device wherein the above lens shape is a convex downward or upward shape.

21. In paragraph 20, A method for manufacturing a display device, wherein the carrier substrate comprises a support layer that is transparent and has mechanical stability, and an adhesive layer disposed on the support layer.

22. In paragraph 20, A method for manufacturing a display device, wherein the interposer substrate comprises a support layer that is transparent to light and has mechanical stability, and an adhesive layer disposed on the support layer.

23. In paragraph 20, Before the step of forming the above common electrode, A step of depositing an insulating layer on the light-emitting element and on a part of the first substrate on which the light-emitting element is not arranged; A step of depositing a reflective material layer on a part of the first substrate on which the insulating layer is laminated; A step of removing the reflective material layer from a horizontal plane on the first substrate to form a reflective layer surrounding a side surface of the light-emitting element; A step of forming a planarization layer on the first substrate on which the insulating layer is formed, wherein the planarization layer is formed lower than the height of the light-emitting element; and A method for manufacturing a display device further comprising the step of removing a portion of an insulating layer on the light-emitting element that is not covered by the flattening layer.

Images