Array substrate, display panel, and display device

Abstract

An array substrate, a display panel, and a display device. The array substrate comprises: a substrate (1); a plurality of gate lines (2) located on one side of the substrate (1) and extending in a first direction; a plurality of data lines (3) located on the same side of the substrate (1) as the gate lines (2) and extending in a second direction, the second direction intersecting with the first direction; and a plurality of sub-pixels (4) located on the same side of the substrate (1) as the gate lines (2), wherein at least one sub-pixel (4) among the plurality of sub-pixels (4) comprises: two first sub-pixels (41) sequentially arranged in the first direction, and a second sub-pixel (42) located between the two first sub-pixels (41), and the brightness of the second sub-pixel (42) is greater than the brightness of the first sub-pixels (41).

Description

Array substrate, display panel, and display device Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0002] The name UV2A comes from the multiplication of ultraviolet (UV) light and the VA method of the liquid crystal panel. This technology can precisely manipulate the alignment of liquid crystal molecules through ultraviolet light, greatly improving the light transmittance.

[0003] The key to UV2A lies in its use of a special polymer material as an alignment film, precisely controlling the tilt of liquid crystal molecules along the direction of ultraviolet light. This accuracy is measured in picometers (one trillionth of a meter). UV2A's advantage lies in its simple LCD panel structure, free of protrusions and slits. This "dream of LCD technicians" was explored as early as 30 years ago. Today, thanks to the availability of new materials, production equipment, and a refined processing process, this dream has become a reality. This simple LCD panel structure not only improves production efficiency but also offers numerous advantages in image quality.

[0004] Summary of the Invention

[0005] The present disclosure provides an array substrate, a display panel, and a display device. The array substrate includes:

[0006] substrate;

[0007] A plurality of gate lines are located on one side of the substrate and extend along a first direction;

[0008] a plurality of data lines, located on the same side of the substrate as the gate lines, extending along a second direction, the second direction intersecting the first direction;

[0009] A plurality of sub-pixels are located on the same side of the substrate as the gate line, and at least one sub-pixel among the plurality of sub-pixels includes: two first sub-pixels arranged in sequence along a first direction, and a second sub-pixel located between the two first sub-pixels; wherein the brightness of the second sub-pixel is greater than the brightness of the first sub-pixel.

[0010] In a possible implementation, the sub-pixel includes: a sub-pixel electrode; the first sub-pixel includes: a first sub-pixel electrode; the second sub-pixel includes: a second sub-pixel electrode; the sub-pixel electrodes include: the first sub-pixel electrode and the second sub-pixel electrode;

[0011] The second sub-pixel electrode includes: two second electrode portions distributed along the second direction; the orthographic projection shape of the second electrode portion on the substrate includes a V shape.

[0012] In a possible embodiment, the second electrode portion includes: a first sub-pattern portion extending along a third direction, and a second sub-pattern portion extending along a fourth direction; wherein the third direction intersects with the first direction and the second direction, and the fourth direction intersects with the first direction and the second direction.

[0013] In a possible implementation manner, a position where the first sub-pattern portion intersects the second sub-pattern portion overlaps with an edge of the sub-pixel electrode.

[0014] In a possible implementation manner, in the same second sub-pixel electrode, the opening directions of two second electrode portions are opposite.

[0015] In a possible implementation, the first sub-pixel electrode includes: a first electrode portion and a third electrode portion distributed along the second direction; the first electrode portion is located on a side facing the opening of the second electrode portion, and the third electrode portion is located on a side facing away from the opening of the second electrode portion;

[0016] The orthographic projection shape of the first electrode portion on the substrate includes a triangle, and the orthographic projection shape of the third electrode portion on the substrate includes a triangle.

[0017] In a possible implementation manner, an edge of an end portion of the second electrode portion is parallel to an edge of the sub-pixel electrode extending along the first direction.

[0018] In a possible implementation manner, the sub-pixel electrode further includes: a first connecting portion; in the same sub-pixel electrode, two first sub-pixel electrodes are electrically connected via the first connecting portion;

[0019] The first connecting portion extends along the first direction, and the first connecting portion and an end portion of the second electrode portion are arranged opposite to each other, with a first gap extending along the first direction therebetween.

[0020] In a possible implementation, a portion of the edge of the end portion of the second electrode portion is parallel to the edge of the sub-pixel electrode extending along the first direction, and another portion of the edge of the end portion of the second electrode portion is parallel to the edge of the sub-pixel electrode extending along the second direction.

[0021] In a possible implementation manner, the sub-pixel electrode further includes: a second connecting portion; in the same sub-pixel electrode, two first sub-pixel electrodes are electrically connected via the second connecting portion;

[0022] The second connecting portion is bent, and the second connecting portion and an end portion of the second electrode portion are arranged opposite to each other with a second bent gap therebetween.

[0023] In one possible embodiment, the subpixel electrode has a slit; the subpixel electrode includes: a first sub-portion, a second sub-portion, a third sub-portion, and a fourth sub-portion arranged along the second direction; an extension direction of the slit in the first sub-portion is the same as an extension direction of the slit in the fourth sub-portion; an extension direction of the slit in the second sub-portion is the same as an extension direction of the slit in the third sub-portion; and an extension direction of the slit in the first sub-portion is different from an extension direction of the slit in the second sub-portion;

[0024] In the first sub-section, the extension direction of the first sub-pattern section is parallel to the extension direction of the slit in the first sub-section; in the second sub-section, the extension direction of the second sub-pattern section is parallel to the extension direction of the slit in the second sub-section; in the third sub-section, the extension direction of the first sub-pattern section is parallel to the extension direction of the slit in the third sub-section; in the fourth sub-section, the extension direction of the second sub-pattern section is parallel to the extension direction of the slit in the fourth sub-section.

[0025] In one possible embodiment, the subpixel electrode has a slit; the subpixel electrode includes: a first sub-portion, a second sub-portion, a third sub-portion, and a fourth sub-portion arranged along the second direction; an extension direction of the slit in the first sub-portion is the same as an extension direction of the slit in the fourth sub-portion; an extension direction of the slit in the second sub-portion is the same as an extension direction of the slit in the third sub-portion; and an extension direction of the slit in the first sub-portion is different from an extension direction of the slit in the second sub-portion;

[0026] In the first sub-section, the extension direction of the first sub-pattern section is perpendicular to the extension direction of the slit in the first sub-section; in the second sub-section, the extension direction of the second sub-pattern section is perpendicular to the extension direction of the slit in the second sub-section; in the third sub-section, the extension direction of the first sub-pattern section is perpendicular to the extension direction of the slit in the third sub-section; in the fourth sub-section, the extension direction of the second sub-pattern section is perpendicular to the extension direction of the slit in the fourth sub-section.

[0027] In a possible implementation manner, the first sub-pixel electrode is a planar electrode; and the second sub-pixel electrode is a planar electrode.

[0028] In a possible implementation, the orthographic projection of the gate line on the substrate passes through a central area of ​​the orthographic projection of the sub-pixel electrode; the orthographic projections of the two second electrode portions of the same sub-pixel electrode on the substrate are respectively located on different sides of the gate line;

[0029] The sub-pixel electrode further includes a third connecting portion; and in the second sub-pixel electrode, two second electrode portions are electrically connected via the third connecting portion.

[0030] In a possible implementation, the third connection portion includes: a first sub-connection portion and a second sub-connection portion arranged along the second direction;

[0031] A width of the first sub-connection portion in the first direction is greater than a width of the second sub-connection portion in the first direction.

[0032] In a possible implementation manner, the first sub-connection portion is located in an end region of the second connection portion in the second direction, and the first sub-connection portion is formed by the second electrode portion protruding toward one side of the gate line.

[0033] In a possible implementation manner, the orthographic projection of the gate line on the substrate is located at an edge of the orthographic projection of the sub-pixel electrode on the substrate;

[0034] The sub-pixel electrode also includes: a first extension portion; the first extension portion includes: a first sub-extension portion distributed along the second direction, and a second sub-extension portion; the first sub-extension portion is located in the end area of ​​the second sub-extension portion along the second direction, and the width of the first sub-extension portion in the first direction is greater than the width of the second sub-extension portion in the first direction.

[0035] In a possible implementation, the array substrate further includes: a first common trace located on one side of the gate line, and a transfer electrode; an orthographic projection of the transfer electrode on the substrate and an orthographic projection of the first common trace on the substrate have an overlapping area;

[0036] The sub-pixel further includes: a pixel circuit; the pixel circuit includes: a first transistor, a second transistor, and a third transistor; the first transistor includes: a first transistor control electrode, a first transistor first electrode, and a first transistor second electrode; the second transistor includes: a second transistor control electrode, a second transistor first electrode, and a second transistor second electrode; the third transistor includes: a third transistor control electrode, a third transistor first electrode, and a third transistor second electrode;

[0037] The control electrode of the first transistor multiplexes with the gate line, the first electrode of the first transistor multiplexes with the data line; the second electrode of the first transistor is electrically connected to the second sub-pixel electrode;

[0038] The control electrode of the second transistor reuses the gate line, the first electrode of the second transistor reuses the first electrode of the first transistor; the second electrode of the second transistor is electrically connected to the first sub-pixel electrode;

[0039] The control electrode of the third transistor reuses the gate line, the first electrode of the third transistor reuses the second electrode of the second transistor; the second electrode of the third transistor is electrically connected to the first common wiring through the switching electrode.

[0040] An embodiment of the present disclosure further provides a display panel, which includes the array substrate provided in the embodiment of the present disclosure and also includes an opposite substrate arranged opposite to the array substrate; the opposite substrate includes: a common electrode layer.

[0041] An embodiment of the present disclosure further provides a display device, which includes the display panel provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] FIG1A is a schematic top view of an array substrate according to an embodiment of the present disclosure;

[0043] FIG1B is a schematic diagram of a single film layer of the gate line layer in FIG1A;

[0044] FIG1C is a schematic diagram of a single film layer of the data line layer in FIG1A ;

[0045] FIG1D is a schematic diagram of a single film layer of the active layer in FIG1A ;

[0046] FIG1E is a schematic diagram of a single film layer of the first insulating layer in FIG1A ;

[0047] FIG1F is a schematic diagram of a single film layer of the pixel electrode layer in FIG1A ;

[0048] FIG1G is a schematic diagram of the black matrix layer corresponding to FIG1A ;

[0049] FIG1H is a schematic diagram of the light effect corresponding to FIG1A ;

[0050] FIG2A is a second schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0051] FIG2B is a schematic diagram of a single film layer of the pixel electrode layer in FIG2A ;

[0052] FIG2C is a schematic diagram of light effects corresponding to FIG2A ;

[0053] FIG3A is a third schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0054] FIG3B is a schematic diagram of a single film layer of the pixel electrode layer in FIG3A ;

[0055] FIG3C is a schematic diagram of light effects corresponding to FIG3A ;

[0056] FIG4A is a fourth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0057] FIG4B is a schematic diagram of a single film layer of the gate line layer in FIG4A;

[0058] FIG4C is a schematic diagram of a single film layer of the data line layer in FIG4A ;

[0059] FIG4D is a schematic diagram of a single film layer of the active layer in FIG4A;

[0060] FIG4E is a schematic diagram of a single film layer of the first insulating layer in FIG4A ;

[0061] FIG4F is a schematic diagram of a single film layer of the pixel electrode layer in FIG4A ;

[0062] FIG4G is a schematic diagram of the black matrix layer corresponding to FIG4A ;

[0063] FIG4H is a schematic diagram of light effects corresponding to FIG4A ;

[0064] FIG5A is a fifth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0065] FIG5B is a schematic diagram of a single film layer of the data line layer in FIG5A ;

[0066] FIG5C is a schematic diagram of a single film layer of the pixel electrode layer in FIG5A ;

[0067] FIG6A is a sixth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0068] FIG6B is a schematic diagram of a single film layer of the pixel electrode layer in FIG6A ;

[0069] FIG6C is a schematic diagram of light effects corresponding to FIG6A ;

[0070] FIG7A is a seventh schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0071] FIG7B is a schematic diagram of a single film layer of the pixel electrode layer in FIG7A ;

[0072] FIG7C is a schematic diagram of light effects corresponding to FIG7A ;

[0073] FIG8 is a schematic diagram of sub-pixel distribution of 1P4D;

[0074] FIG9 is an equivalent circuit diagram corresponding to FIG1A ;

[0075] FIG10 is a schematic diagram of various crosstalk images. DETAILED DESCRIPTION

[0076] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0077] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0078] As used herein, "about" or "approximately the same" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "approximately the same" can mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%.

[0079] In the accompanying drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes of the figures are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Thus, the embodiments described herein should not be construed as limited to the specific shapes of the regions as shown herein, but rather include deviations in shape that result from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. Furthermore, sharp corners illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0080] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0081] Compared with the UV2A pixel design, ultra-fine photo-alignment (SUVA) is an upgraded version of UV2A, as shown in Figure 8, where Figure 8 is a 1P4D (one sub-pixel contains 4 domains) SUVA pixel design. Compared with the UV2A pixel design, the SUVA pixel design can effectively reduce the dark lines of the pixel, but the transmittance of the SUVA alignment is significantly improved for the 4-domain alignment, while the number of dark lines increases for the 8-domain alignment, and the transmittance improvement is obviously insufficient.

[0082] In view of this, an embodiment of the present disclosure provides an array substrate, as shown in FIG. 1A to FIG. 1H , FIG. 2A to FIG. 2C , FIG. 3A to FIG. 3C , FIG. 4A to FIG. 4H , FIG. 5A to FIG. 5C , FIG. 6A to FIG. 6C , and FIG. 7A to FIG. 7C , including:

[0083] Substrate 1;

[0084] A plurality of gate lines 2 are located on one side of the substrate 1 and extend along a first direction X;

[0085] A plurality of data lines 3 are located on the same side of the substrate 1 as the gate lines 2 and extend along a second direction Y, which intersects the first direction X;

[0086] Multiple sub-pixels 4 are located on the same side of the substrate 1 as the gate line 2, and at least one sub-pixel 4 among the multiple sub-pixels 4 includes: two first sub-pixels 41 arranged in sequence along the first direction X, and a second sub-pixel 42 located between the two first sub-pixels 41; wherein the brightness of the second sub-pixel 42 is greater than the brightness of the first sub-pixel 41.

[0087] In the embodiment of the present disclosure, the array substrate includes a plurality of sub-pixels 4, and the sub-pixels 4 include: a first sub-pixel 41, a second sub-pixel 42, and a first sub-pixel 41 distributed in sequence along a first direction X; wherein the brightness of the second sub-pixel 42 is greater than the brightness of the first sub-pixel 41, that is, the brighter second sub-pixel 42 is located in the middle, and the darker first sub-pixels 41 are arranged on both sides. Due to voltage suppression, longitudinal crosstalk does not occur. At the same time, the sub-pixel 4 has 8 domains, which can greatly reduce the proportion of dark lines, improve transmittance, and at the same time, improve color shift performance.

[0088] In the liquid crystal display panel, various wirings are densely arranged, and there is a large coupling capacitance, which leads to various crosstalk problems. The type of crosstalk is closely related to the row flip / column flip / dot flip of the liquid crystal display panel. As shown in Figure 10, crosstalk problems include horizontal crosstalk, vertical crosstalk, etc. Among them, horizontal crosstalk is related to the coupling capacitance between the data line and the common electrode; and vertical crosstalk, on the one hand, is related to the coupling capacitance between the data line and the pixel electrode, and on the other hand, it is also related to the transistor leakage current Ioff.

[0089] In the conventional 8Domain sub-pixel design, dark pixels are not bright at low grayscales, and only bright pixels are bright. In the disclosed embodiment, by setting the brighter second sub-pixel 42 in the middle of the sub-pixel 4, the distance between the brighter second sub-pixel 42 and the data line can be made farther, and the coupling capacitance Cpd between the sub-pixel electrode and the data line is approximately 0. Therefore, when the image changes at low grayscales, pixels of different grayscales on both sides are unlikely to be affected by the different voltages of the data lines on both sides, so it is difficult for longitudinal crosstalk (i.e., vertical crosstalk) to occur, thereby improving the problem of longitudinal crosstalk. In other words, the setting method of setting the brighter second sub-pixel 42 in the middle of the sub-pixel 4 has good longitudinal crosstalk performance at low grayscales.

[0090] It should be noted that brighter means more backlight is transmitted, and darker means less backlight is transmitted. That is, when different voltages are applied to different areas, the voltage difference formed with the common electrode of the opposite substrate is different. The greater the pressure difference, the stronger the ability to drive the liquid crystal to rotate, the more backlight is transmitted, and the brighter the area is. Conversely, the smaller the pressure difference, the weaker the ability to drive the liquid crystal to rotate, the less backlight is transmitted, and the darker the area is.

[0091] Specifically, the array substrate may further include a pixel circuit. The brightness of the second sub-pixel 42 is greater than the brightness of the first sub-pixel 41 . This can be understood as the brightness of the second sub-pixel 42 being greater than the brightness of the first sub-pixel 41 under the drive of the pixel circuit.

[0092] In a possible embodiment, referring to Figures 1A to 1H, the sub-pixel 4 includes: a sub-pixel electrode P; the first sub-pixel 41 includes: a first sub-pixel electrode P1; the second sub-pixel 42 includes: a second sub-pixel electrode P2; the sub-pixel electrode P includes: a first sub-pixel electrode P1 and a second sub-pixel electrode P2; the second sub-pixel electrode P2 includes: two second electrode portions PY distributed along the second direction Y; the positive projection shape of the second electrode portion PY on the substrate 1 includes a V shape.

[0093] In a possible implementation manner, the orthographic projection shape of the second electrode portion PY on the substrate 1 is V-shaped.

[0094] In a possible embodiment, the maximum width of the second electrode portion PY in the first direction X may be one-fifth to one-half of the width of the sub-pixel electrode P in the first direction X; for example, the maximum width of the second electrode portion PY in the first direction X may be one-third of the width of the sub-pixel electrode P in the first direction X; for another example, the maximum width of the second electrode portion PY in the first direction X may be one-half of the width of the sub-pixel electrode P in the first direction X.

[0095] In one possible embodiment, as shown in FIG1F , the second electrode portion PY includes a first sub-pattern portion PY1 extending along a third direction J1 and a second sub-pattern portion PY2 extending along a fourth direction J2. The third direction J1 intersects the first direction X and the second direction Y, and the fourth direction J2 intersects the first direction X and the second direction Y. The third direction J1 may be perpendicular to the fourth direction J2. The first sub-pattern portion PY1 and the second sub-pattern portion PY2 intersect to form a V-shape.

[0096] In one possible embodiment, the angle formed by the first sub-pattern portion PY1 and the first direction X can be in the range of 130° to 160°, specifically, for example, it can be 130°, 135°, 140°, 145°, 150°, 155° or 160°; the angle formed by the second sub-pattern portion PY2 and the first direction X can be in the range of 30° to 60°, specifically, for example, it can be 30°, 35°, 40°, 45°, 50°, 55° or 60°.

[0097] In one possible embodiment, referring to FIG1F , the intersection of the first sub-pattern portion PY1 and the second sub-pattern portion PY2 overlaps with an edge of the sub-pixel electrode P. Specifically, for example, in conjunction with FIG1F , in the second electrode portion PY above the rightmost sub-pixel electrode P, the intersection of the first sub-pattern portion PY1 and the second sub-pattern portion PY2 overlaps with the right edge of the sub-pixel electrode P. For another example, in conjunction with FIG1F , in the second electrode portion PY below the rightmost sub-pixel electrode P, the intersection of the first sub-pattern portion PY1 and the second sub-pattern portion PY2 overlaps with the left edge of the sub-pixel electrode P.

[0098] In one possible embodiment, as shown in FIG1F , the opening directions of the two second electrode portions PY in the same second subpixel electrode P2 are opposite. This aligns with the extension direction of the slit S, thereby improving the color shift problem of the array substrate. Specifically, for example, as shown in FIG1F , in the rightmost subpixel electrode P, the upper second electrode portion PY opens to the left, while the lower second electrode portion PY opens to the right.

[0099] In the SUVA structural design, the sub-pixel electrode P is located in two parts on both sides of the gate line 2. When the slit S forms a "<" shape and a ">" shape, the color deviation of the array substrate is improved. When the edge of the second sub-pixel electrode P2 is perpendicular to the extension direction of the slit S, it is beneficial to reduce dark lines and increase transmittance. Furthermore, in the embodiment of the present disclosure, in the same second sub-pixel electrode P2, the opening directions of the two second electrode parts PY are opposite, which can improve the color deviation problem of the array substrate.

[0100] In a possible embodiment, referring to FIG1A and FIG1F , the first sub-pixel electrode P1 includes: a first electrode portion PX and a third electrode portion PZ distributed along the second direction Y; the first electrode portion PX is located on a side facing the opening of the second electrode portion PY, and the third electrode portion PZ is located on a side facing away from the opening of the second electrode portion PY; the orthographic projection shape of the first electrode portion PX on the substrate 1 includes a triangle, and the orthographic projection shape of the third electrode portion PZ on the substrate includes a triangle.

[0101] In a possible embodiment, referring to FIG. 1A and FIG. 1F , the first electrode portion PX may include a triangular pattern. Specifically, the positive projection shape of the first electrode portion PX on the substrate 1 may be a right triangle, and the right angle of the right-angled triangle first electrode portion PX is opposite to the opening of the V-shaped second electrode portion PY.

[0102] In one possible embodiment, as shown in Figures 1A and 1F , the third electrode portion PZ may include two triangular patterns. Specifically, both triangular patterns in the third electrode portion PZ are right triangles. The two right triangle patterns in the third electrode portion PZ are arranged at an acute angle relative to each other, with their right-angled sides lying on a straight line in the same second direction Y, and their hypotenuses facing the V-shaped second electrode portion PY. Specifically, the two triangular patterns in the third electrode portion PZ are connected by a third electrode connecting portion PZZ extending along the second direction Y.

[0103] In one possible embodiment, as shown in FIG1F , the edge of the end of the second electrode portion PY is parallel to the edge of the sub-pixel electrode P extending along the first direction X. In this way, the dark lines at the end can be pushed into the area shielded by the black matrix, thereby reducing the dark lines at the end and increasing the transmittance of the display panel.

[0104] In one possible embodiment, as shown in FIG1F , a portion of the end portion of the second electrode portion PY is located in the middle of the edge of the sub-pixel electrode P. For example, in FIG1F , the rightmost portion of the end portion of the second electrode portion PY is located in the middle of the edge of the sub-pixel electrode P. In one possible embodiment, as shown in FIG1F , an edge of the intersection of the first sub-pattern portion PY1 and the second sub-pattern portion PY2 facing away from the outlet extends along the second direction Y.

[0105] In a possible embodiment, as shown in Figure 1F, the sub-pixel electrode P further includes: a first connecting portion L1; in the same sub-pixel electrode P, two first sub-pixel electrodes P1 are electrically connected through the first connecting portion L1; the first connecting portion L1 extends along the first direction X, and the first connecting portion L1 and the end of the second electrode portion PY are arranged opposite to each other, and a first gap F extending along the first direction X is present between the two.

[0106] In one possible embodiment, as shown in Figure 1F , the end of the second electrode portion PY is disposed opposite to the first connection portion L1 . In one possible embodiment, as shown in Figure 1F , the edge of the end of the second electrode portion PY is parallel to the first connection portion L1 .

[0107] In one possible embodiment, as shown in FIG2B , a portion of the edge of the end portion of the second electrode portion PY is parallel to the edge of the sub-pixel electrode P extending along the first direction X, and another portion of the edge of the end portion of the second electrode portion PY is parallel to the edge of the sub-pixel electrode P extending along the second direction Y. That is, the end portion of the second electrode portion PY is in the shape of a right triangle, with the right angle opposite the corner of the sub-pixel electrode P. In this way, dark streaks in the sub-pixel 4 in the first direction X (i.e., the short side of the pixel) can be reduced.

[0108] In a possible embodiment, as shown in FIG. 2B , the end of the second electrode portion PY is located at a corner of an edge of the sub-pixel electrode P, and the shape of the end of the second electrode portion PY is similar to the shape of the sub-pixel electrode P at the corner region.

[0109] In one possible embodiment, as shown in FIG2B , the subpixel electrode P further includes a second connection portion L2. Within the same subpixel electrode P, two first subpixel electrodes P1 are electrically connected via the second connection portion L2. The second connection portion L2 is bent and disposed opposite an end of the second electrode portion PY, with a second bent gap F2 defined therebetween. Specifically, the second connection portion L2 is right-angled, serving as a corner of the subpixel electrode P.

[0110] In a possible implementation, as shown in FIG. 2B , in the second electrode portion PY, the first sub-pattern portion PY1 and the second sub-pattern portion PY2 intersect at a right angle.

[0111] In one possible embodiment, as shown in FIG. 1F , the subpixel electrode P has a slit S. The subpixel electrode P includes a first sub-portion PP1, a second sub-portion PP2, a third sub-portion PP3, and a fourth sub-portion PP4 arranged along a second direction Y. The slit S in the first sub-portion PP1 extends in the same direction as the slit S in the fourth sub-portion PP4. The slit S in the second sub-portion PP2 extends in the same direction as the slit S in the third sub-portion PP3. The slit S in the first sub-portion PP1 extends in a different direction than the slit S in the second sub-portion PP2.

[0112] In the first sub-section PP1, the extension direction of the first sub-pattern section PY1 is perpendicular to the extension direction of the slits S in the first sub-section PP1. For example, as shown in FIG1F , the extension direction of the first sub-pattern section PY1 is the third direction J1, and the extension direction of the slits S in the first sub-section PP1 is the fourth direction J2. The third direction J1 may be perpendicular to the fourth direction J2. In the second sub-section PP2, the extension direction of the second sub-pattern section PP2 is perpendicular to the extension direction of the slits S in the second sub-section PP2. In the third sub-section PP3, the extension direction of the first sub-pattern section PY1 is perpendicular to the extension direction of the slits S in the third sub-section PP3. In the fourth sub-section PP4, the extension direction of the second sub-pattern section PY2 is perpendicular to the extension direction of the slits S in the fourth sub-section PP4. This enhances the edge brightness of sub-pixel 4 and reduces dark fringes, thereby increasing the transmittance of the display panel.

[0113] In a possible embodiment, referring to FIG1F and FIG3B , the angle formed by the extension direction of the slit F in the first sub-electrode portion PX11 and the first direction X may be in the range of 30° to 60°, specifically, for example, 45°; the angle formed by the extension direction of the slit F in the second sub-electrode portion PX12 and the first direction X may be in the range of 130° to 160°, specifically, for example, 145°.

[0114] Specifically, in combination with Figure 1F, the first sub-portion PP1 may include: a portion of the second electrode portion PY (e.g., it may include the first sub-pattern portion PY1 in the second electrode portion PY), and may also include a portion of the first electrode portion PX, and a portion of the third electrode portion PZ; similarly, the second sub-portion PP2 may include: a portion of the second electrode portion PY, and may also include a portion of the first electrode portion PX, and a portion of the third electrode portion PZ; similarly, the third sub-portion PP3 may include: a portion of the second electrode portion PY, and may also include a portion of the first electrode portion PX, and a portion of the third electrode portion PZ; similarly, the fourth sub-portion PP4 may include: a portion of the second electrode portion PY, and may also include a portion of the first electrode portion PX, and a portion of the third electrode portion PZ.

[0115] In one possible embodiment, referring to FIG. 3A to FIG. 3C , the subpixel electrode P has a slit S. The subpixel electrode P includes: a first sub-portion PP1, a second sub-portion PP2, a third sub-portion PP3, and a fourth sub-portion PP4 arranged along a second direction Y. The slit S in the first sub-portion PP1 extends in the same direction as the slit S in the fourth sub-portion PP4. The slit S in the second sub-portion PP2 extends in the same direction as the slit S in the third sub-portion PP3. The slit S in the first sub-portion PP1 extends in a different direction than the slit S in the second sub-portion PP2.

[0116] In the first sub-section PP1, the extension direction of the first sub-pattern section PY1 is parallel to the extension direction of the slit S in the first sub-section PP1. For example, as shown in Figure 3B, the extension direction of the first sub-pattern section PY1 is the fourth direction J2, and the extension direction of the slit S in the first sub-section PP1 is the fourth direction J2; in the second sub-section PP2, the extension direction of the second sub-pattern section PY2 is parallel to the extension direction of the slit S in the second sub-section PP2; in the third sub-section PP3, the extension direction of the first sub-pattern section PY1 is parallel to the extension direction of the slit S in the third sub-section PP3; in the fourth sub-section PP4, the extension direction of the second sub-pattern section PP2 is parallel to the extension direction of the slit S in the fourth sub-section PP4.

[0117] In one possible implementation, as shown in Figures 5A-5C, 6A-6C, and 7A-7C, the first sub-pixel electrode P1 is a planar electrode, and the second sub-pixel electrode P2 is a planar electrode. In the disclosed embodiment, when the first sub-pixel electrode P1 and the second sub-pixel electrode P2 are planar electrodes, UV2A alignment can also be used, thereby improving crosstalk issues associated with the UV2A structure.

[0118] In one possible embodiment, referring to Figures 1A-1G , the orthographic projection of the gate line 2 on the substrate 1 passes through the central area of ​​the orthographic projection of the sub-pixel electrode P; the orthographic projections of the two second electrode portions PY of the same sub-pixel electrode P on the substrate 1 are respectively located on different sides of the gate line 2; the sub-pixel electrode P further comprises: a third connection portion L3; and in the second sub-pixel electrode P2, the two second electrode portions PY are electrically connected via the third connection portion L3. That is, the first sub-pixel electrode P1 has two portions located on either side of the gate line 2, and the second sub-pixel electrode P2 also has two portions located on either side of the gate line 2; wherein the two portions of the second sub-pixel electrode P2 are electrically connected via the third connection portion L3. In the disclosed embodiment, the orthographic projections of the two second electrode portions PY of the same sub-pixel electrode P on the substrate 1 are respectively located on different sides of the gate line 2, that is, there is a gap between the two to prevent the second sub-pixel electrode P2 from overlapping with the gate line 2. The two second electrode portions PY on either side of the gate line 2 are then connected via the third connection portion L3 to achieve electrical connection between the two second electrode portions PY on different sides of the gate line 2.

[0119] In one possible embodiment, as shown in Figure 1F, the third connection portion L3 includes: a first sub-connection portion L31 arranged along the second direction Y, and a second sub-connection portion L32; the width a1 of the first sub-connection portion L31 in the first direction X is greater than the width a2 of the second sub-connection portion L32 in the first direction X. In this way, while electrically connecting the two parts of the second sub-pixel electrode P2 on different sides of the gate line 2 through the third connection portion L3, it is also possible to electrically connect to the transistor of the pixel circuit through the wider first sub-connection portion L31, so as to achieve a brighter display by driving the second sub-pixel electrode P2 through the pixel circuit.

[0120] In a possible embodiment, as shown in FIG. 1F , the first sub-connection portion L31 is located at the end region of the second connection portion L2 in the second direction Y. The first sub-connection portion L31 is formed by the second electrode portion PY protruding toward the gate line 2 .

[0121] In a possible implementation, as shown in FIG1F , the sub-pixel electrode P further includes a fourth connection portion L5 ; in the first sub-pixel electrode P1 , the first electrode portion PX and the third electrode portion PZ on different sides of the gate line 2 are electrically connected via the fourth connection portion L5 .

[0122] In a possible embodiment, referring to Figures 4A to 4H, the positive projection of the gate line 2 on the substrate 1 is located at the edge of the positive projection of the sub-pixel electrode P on the substrate 1; the sub-pixel electrode P also includes: a first extension portion L4; the first extension portion L4 includes: a first sub-extension portion L41 distributed along the second direction Y, and a second sub-extension portion L42; the first sub-extension portion L41 is located at the end area of ​​the second sub-extension portion L42 along the second direction Y, and the width c1 of the first sub-extension portion L41 in the first direction X is greater than the width c2 of the second sub-extension portion L42 in the first direction X. In this way, when the gate line 2 is located at the edge of the sub-pixel electrode P, it can be electrically connected to the transistor of the pixel circuit through the wider first sub-extension portion L41, so as to achieve a brighter display by driving the second sub-pixel electrode P2 through the pixel circuit.

[0123] In one possible embodiment, as shown in FIG. 4F , the first sub-extension L41 is located at the end region of the second sub-extension L42 along the second direction Y. The sub-pixel electrodes P in the N-1th row have a recessed portion Q at a position opposite the first sub-extension L41 of the sub-pixel electrodes P in the Nth row, where N is a positive integer greater than zero. This arrangement avoids the first extension L4, thereby preventing electrical connection between the sub-pixel electrodes P in the previous row and the first extension L4 in the next row.

[0124] It should be understood that the Nth row of sub-pixel electrodes P can be the next pixel electrode row located in the N-1th row of sub-pixel electrodes P in the direction of the gate scanning signal, that is, the gate scanning signal is first loaded on the N-1th row of sub-pixel electrodes P, and then loaded on the Nth row of sub-pixel electrodes P.

[0125] In a possible embodiment, referring to FIG. 1A to FIG. 1H and FIG. 9 , where FIG. 9 may be an equivalent circuit diagram corresponding to FIG. 1A , the array substrate further includes: a first common trace 51 located on one side of the gate line 2, and a transfer electrode PC; an orthographic projection of the transfer electrode PC on the substrate 1 has an overlapping area with an orthographic projection of the first common trace 51 on the substrate 1;

[0126] The sub-pixel 4 further includes: a pixel circuit; the pixel circuit includes: a first transistor T1, a second transistor T2, and a third transistor T3; the first transistor T1 includes: a first transistor control electrode T1A, a first transistor first electrode T1B, and a first transistor second electrode T1C; the second transistor T2 includes: a second transistor control electrode T2A, a second transistor first electrode T2B, and a second transistor second electrode T2C; the third transistor T3 includes: a third transistor control electrode T3A, a third transistor first electrode T3B, and a third transistor second electrode T3C;

[0127] The first transistor control electrode T1A is multiplexed with the gate line 2, the first transistor first electrode T1B is multiplexed with the data line 2; the first transistor second electrode T1C is electrically connected to the second sub-pixel electrode P2;

[0128] The control electrode T2A of the second transistor reuses the gate line 2, the first electrode T2B of the second transistor reuses the first electrode T1B of the first transistor; the second electrode T2C of the second transistor is electrically connected to the first sub-pixel electrode P1;

[0129] The control electrode T3A of the third transistor reuses the gate line 2 , the first electrode T3B of the third transistor reuses the second electrode T2C of the second transistor; the second electrode T3C of the third transistor is electrically connected to the first common wiring 51 through the switching electrode PC.

[0130] Specifically, the array substrate also includes: a second common wiring 52 located on the other side of the gate line 2, a first liquid crystal capacitor Cpx1, a second liquid crystal capacitor Cpx2, a first capacitor C1, and a second capacitor C2, wherein the first liquid crystal capacitor Cpx1 can be formed by the first sub-pixel electrode P1 and the common electrode layer of the opposite substrate, the second liquid crystal capacitor Cpx2 can be formed by the second sub-pixel electrode P2 and the common electrode layer of the opposite substrate, the first capacitor C1 can be formed by the first sub-pixel electrode P1 and the second common wiring 52, and the second capacitor C2 can be formed by the second sub-pixel electrode P2 and the first sub-common wiring 51.

[0131] In the embodiment of the present invention, the first sub-pixel electrode P1 can be electrically connected to the gate line 2 and the data line 3 through the first transistor T1, the second sub-pixel electrode P2 can be electrically connected to the gate line 2 and the data line 3 through the second transistor T2, and the second electrode T3C of the third transistor is electrically connected to the first common wiring 51. Part of the charge in the second capacitor C2 corresponding to the second sub-pixel electrode P2 can be released to the first common wiring 51 through the third transistor T3, thereby making the brightness of the first sub-pixel electrode P1 greater than the brightness of the second sub-pixel electrode P2, thereby achieving different light and dark pixels in the same sub-pixel electrode P, and realizing an 8-domain display effect.

[0132] In one possible embodiment, as shown in Figures 1A-1G, the orthographic projection of the transfer electrode PC on the substrate 1 overlaps with the orthographic projection of the first common trace 51 on the substrate 1, and also overlaps with the orthographic projection of the second electrode T3C of the third transistor on the substrate 1. The third via K3 can be designed as a semi-via, partially exposing the first common trace 51 and partially exposing the second electrode T3C of the third transistor. The transfer electrode PC, at the third via K3, partially contacts the first common trace 51 and partially contacts the second electrode T3C of the third transistor, thereby electrically connecting the first common trace 51 and the second electrode T3C of the third transistor via the transfer electrode PC. Specifically, the semi-via design of the third via K3 can form a stepped structure inside the third via K3, which serves to drain the alignment liquid and prevent the appearance of moiré patterns on the screen.

[0133] In a possible implementation, as shown in FIG. 1F , the first common traces 51 may be made of the same layer and material as the gate lines 2 . Thus, the first common traces 51 are formed simultaneously with the gate lines 2 , which simplifies the manufacturing process of the array substrate.

[0134] In a possible implementation, as shown in FIG. 1F , the transfer electrode PC may be made of the same layer and material as the sub-pixel electrode P. Thus, the transfer electrode PC is formed at the same time as the sub-pixel electrode P, thereby simplifying the manufacturing process of the array substrate.

[0135] In a possible embodiment, as shown in Figure 1F, the array substrate may further include: a third common routing group extending along the second direction Y, the third common routing group including: two third common routing lines 53, the two third common routing lines 53 of the same third common routing group are projected on the substrate 1, and are located on both sides of the projected data line 3 on the substrate 1.

[0136] In a possible embodiment, with reference to FIG. 1A to FIG. 1H , the array substrate may be provided with, in sequence, a gate line layer as shown in FIG. 1B , a data line layer as shown in FIG. 1C , an active layer as shown in FIG. 1D , a first insulating layer as shown in FIG. 1E , and a sub-pixel electrode layer as shown in FIG. 1F on one side of the substrate 1 ;

[0137] The active layer may include an active pattern 71 corresponding to the transistor;

[0138] The first insulating layer may have a first via hole K1, a second via hole K2, and a third via hole K3; the first insulating layer may be a first passivation layer or an organic organic layer;

[0139] Based on the same inventive concept, an embodiment of the present disclosure further provides a display panel, which includes the array substrate provided in the embodiment of the present disclosure and also includes an opposite substrate arranged opposite to the array substrate; the opposite substrate includes: a common electrode layer.

[0140] Specifically, the counter substrate may include a counter substrate and a common electrode layer located on the side of the counter substrate facing the array substrate. Specifically, the counter substrate may also include a black matrix layer as shown in FIG1G , which may include a black matrix pattern 81 and black matrix openings.

[0141] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes a display panel provided by the embodiment of the present disclosure.

[0142] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0143] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An array substrate, wherein: include: substrate; A plurality of gate lines are located on one side of the substrate and extend along a first direction; a plurality of data lines, located on the same side of the substrate as the gate lines, extending along a second direction, the second direction intersecting the first direction; A plurality of sub-pixels are located on the same side of the substrate as the gate line, and at least one sub-pixel among the plurality of sub-pixels includes: two first sub-pixels arranged in sequence along a first direction, and a second sub-pixel located between the two first sub-pixels; wherein the brightness of the second sub-pixel is greater than the brightness of the first sub-pixel.

2. The array substrate according to claim 1, wherein: The sub-pixel includes: a sub-pixel electrode; the first sub-pixel includes: a first sub-pixel electrode; the second sub-pixel includes: a second sub-pixel electrode; the sub-pixel electrodes include: the first sub-pixel electrode and the second sub-pixel electrode; The second sub-pixel electrode includes: two second electrode portions distributed along the second direction; the orthographic projection shape of the second electrode portion on the substrate includes a V shape.

3. The array substrate according to claim 2, wherein: The second electrode portion includes a first sub-pattern portion extending along a third direction and a second sub-pattern portion extending along a fourth direction; wherein the third direction intersects the first direction and the second direction, and the fourth direction intersects the first direction and the second direction.

4. The array substrate according to claim 3, wherein: A position where the first sub-pattern portion intersects the second sub-pattern portion overlaps with an edge of the sub-pixel electrode.

5. The array substrate according to any one of claims 2 to 4, wherein: In the same second sub-pixel electrode, the opening directions of the two second electrode portions are opposite to each other.

6. The array substrate according to any one of claims 2 to 5, wherein: The first sub-pixel electrode includes: a first electrode portion and a third electrode portion distributed along the second direction; the first electrode portion is located on a side facing the opening of the second electrode portion, and the third electrode portion is located on a side facing away from the opening of the second electrode portion; The orthographic projection shape of the first electrode portion on the substrate includes a triangle, and the orthographic projection shape of the third electrode portion on the substrate includes a triangle.

7. The array substrate according to any one of claims 2 to 6, wherein: An edge of an end portion of the second electrode portion is parallel to an edge of the sub-pixel electrode extending along the first direction.

8. The array substrate according to claim 7, wherein: The sub-pixel electrode further includes: a first connecting portion; in the same sub-pixel electrode, two first sub-pixel electrodes are electrically connected via the first connecting portion; The first connecting portion extends along the first direction, and the first connecting portion and an end portion of the second electrode portion are arranged opposite to each other, with a first gap extending along the first direction therebetween.

9. The array substrate according to any one of claims 2 to 6, wherein: Part of the edge of the second electrode portion is parallel to the edge of the sub-pixel electrode extending along the first direction, and another part of the edge of the second electrode portion is parallel to the edge of the sub-pixel electrode extending along the second direction.

10. The array substrate according to claim 9, wherein: The sub-pixel electrode further includes: a second connecting portion; in the same sub-pixel electrode, two first sub-pixel electrodes are electrically connected via the second connecting portion; The second connecting portion is bent, and the second connecting portion and an end portion of the second electrode portion are arranged opposite to each other with a second bent gap therebetween.

11. The array substrate according to any one of claims 3 to 10, wherein: The subpixel electrode has a slit; the subpixel electrode includes: a first sub-portion, a second sub-portion, a third sub-portion, and a fourth sub-portion arranged along the second direction; an extension direction of the slit in the first sub-portion is the same as an extension direction of the slit in the fourth sub-portion; an extension direction of the slit in the second sub-portion is the same as an extension direction of the slit in the third sub-portion; and an extension direction of the slit in the first sub-portion is different from an extension direction of the slit in the second sub-portion; In the first sub-section, the extension direction of the first sub-pattern portion is parallel to the extension direction of the slit in the first sub-section; in the second sub-section, the extension direction of the second sub-pattern portion is parallel to the extension direction of the slit in the first sub-section; The extension direction of the slit in the second sub-section is parallel; in the third sub-section, the extension direction of the first sub-pattern section is parallel to the extension direction of the slit in the third sub-section; in the fourth sub-section, the extension direction of the second sub-pattern section is parallel to the extension direction of the slit in the fourth sub-section.

12. The array substrate according to any one of claims 3 to 10, wherein: The subpixel electrode has a slit; the subpixel electrode includes: a first sub-portion, a second sub-portion, a third sub-portion, and a fourth sub-portion arranged along the second direction; an extension direction of the slit in the first sub-portion is the same as an extension direction of the slit in the fourth sub-portion; an extension direction of the slit in the second sub-portion is the same as an extension direction of the slit in the third sub-portion; and an extension direction of the slit in the first sub-portion is different from an extension direction of the slit in the second sub-portion; In the first sub-section, the extension direction of the first sub-pattern section is perpendicular to the extension direction of the slit in the first sub-section; in the second sub-section, the extension direction of the second sub-pattern section is perpendicular to the extension direction of the slit in the second sub-section; in the third sub-section, the extension direction of the first sub-pattern section is perpendicular to the extension direction of the slit in the third sub-section; in the fourth sub-section, the extension direction of the second sub-pattern section is perpendicular to the extension direction of the slit in the fourth sub-section.

13. The array substrate according to any one of claims 2 to 10, wherein: The first sub-pixel electrode is a planar electrode; the second sub-pixel electrode is a planar electrode.

14. The array substrate according to any one of claims 2 to 13, wherein: The orthographic projection of the gate line on the substrate passes through the central area of ​​the orthographic projection of the sub-pixel electrode; The orthographic projections of the two second electrode portions of the same sub-pixel electrode on the substrate are respectively located on different sides of the gate line; The sub-pixel electrode further includes a third connecting portion; and in the second sub-pixel electrode, two second electrode portions are electrically connected via the third connecting portion.

15. The array substrate according to claim 14, wherein: The third connection portion includes: a first sub-connection portion and a second sub-connection portion arranged along the second direction; The width of the first sub-connection portion in the first direction is greater than the width of the second sub-connection portion in the first direction. The width in the first direction.

16. The array substrate according to claim 14, wherein: The first sub-connection portion is located in an end region of the second connection portion in the second direction, and the first sub-connection portion is formed by the second electrode portion protruding toward one side of the gate line.

17. The array substrate according to any one of claims 2 to 16, wherein: The orthographic projection of the gate line on the substrate is located at the edge of the orthographic projection of the sub-pixel electrode on the substrate; The sub-pixel electrode also includes: a first extension portion; the first extension portion includes: a first sub-extension portion distributed along the second direction, and a second sub-extension portion; the first sub-extension portion is located in the end area of ​​the second sub-extension portion along the second direction, and the width of the first sub-extension portion in the first direction is greater than the width of the second sub-extension portion in the first direction.

18. The array substrate according to claim 16 or 17, wherein: The array substrate further includes: a first common wiring located on one side of the gate line, and a switching electrode; an orthographic projection of the switching electrode on the substrate and an orthographic projection of the first common wiring on the substrate have an overlapping area; The sub-pixel further includes: a pixel circuit; the pixel circuit includes: a first transistor, a second transistor, and a third transistor; the first transistor includes: a first transistor control electrode, a first transistor first electrode, and a first transistor second electrode; the second transistor includes: a second transistor control electrode, a second transistor first electrode, and a second transistor second electrode; the third transistor includes: a third transistor control electrode, a third transistor first electrode, and a third transistor second electrode; The control electrode of the first transistor multiplexes with the gate line, the first electrode of the first transistor multiplexes with the data line; the second electrode of the first transistor is electrically connected to the second sub-pixel electrode; The control electrode of the second transistor reuses the gate line, the first electrode of the second transistor reuses the first electrode of the first transistor; the second electrode of the second transistor is electrically connected to the first sub-pixel electrode; The control electrode of the third transistor reuses the gate line, the first electrode of the third transistor reuses the second electrode of the second transistor; the second electrode of the third transistor is electrically connected to the first common wiring through the switching electrode.

19. A display panel, wherein: comprising the array substrate according to any one of claims 1 to 18, further comprising an opposite substrate arranged opposite to the array substrate; The opposite substrate includes a common electrode layer.

20. A display device, wherein: Comprising the display panel as claimed in claim 19.

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