Circuit board, and semiconductor package comprising same

Abstract

A circuit board according to an embodiment comprises: a build-up insulation part including a plurality of insulation layers stacked vertically; a first pad disposed on a first region of the build-up insulation part; and a second pad disposed on the upper surface of the first pad, wherein the first pad includes a concave portion that is concave inward from a side surface of the first pad, and the concave portion may vertically overlap the second pad.

Description

Circuit boards and semiconductor packages including the same

[0001] The present invention relates to a circuit board and a semiconductor package including the same.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to accommodate a greater number of semiconductor devices on circuit boards of limited size. However, conventional semiconductor packages typically consist of a single semiconductor device, limiting their ability to achieve desired performance.

[0003] Accordingly, semiconductor packages that incorporate multiple semiconductor devices across multiple substrates have recently been developed. These semiconductor packages have a structure in which multiple semiconductor devices are connected horizontally and / or vertically on the circuit board. Consequently, semiconductor packages offer the advantages of efficiently utilizing the mounting area of ​​semiconductor devices and enabling high-speed signal transmission through short signal transmission paths between semiconductor devices.

[0004] Meanwhile, the circuit board includes a build-up insulating portion including an insulating layer and a build-up wiring body arranged on the build-up insulating portion. For example, the circuit board may mean that a mounting position of each semiconductor device is predetermined for mounting at least one semiconductor device, and a build-up wiring body connected to the semiconductor device is arranged on the build-up insulating portion. The build-up wiring body includes a wiring layer arranged on the surface of each insulating layer and a via electrode for vertically connecting each wiring layer. The semiconductor device is mounted on the circuit board and can transmit and receive signals through the build-up wiring body.

[0005] Meanwhile, in conventional circuit boards, a protective layer is formed to partially cover the pads for connection to external chips and solder balls and other connecting parts are connected. However, there is a problem that the adhesive strength between the pads and the protective layer is insufficient, causing the circuit board to warp or a gap to form between the protective layer and the pads due to external impact. As a result, there is a problem that the pads are damaged by external contaminants, and the solder balls connected to the pads also have a reduced fixing strength, which reduces electrical reliability.

[0006] In addition, since the pad for connection with an external chip in a conventional circuit board contains the same material as the seed layer, there is a problem that the upper part of the pad is also etched in the process of etching the seed layer exposed on the surface of the build-up insulation. As a result, a recess is formed on the surface of the pad in contact with the connection part, which causes a significant increase in electrical resistance and a problem of signal loss. In addition, there is a problem that the thickness of the pad in contact with the connection part is reduced, which causes a defect in the connection with the external chip, or a difference in the height of the pad according to the area in the horizontal direction of the circuit board occurs, which causes a defect in the chip mounting and assembly stage.

[0007] One of the technical challenges of the embodiment is to prevent damage to pads connecting to external chips on a circuit board.

[0008] Additionally, one of the technical challenges of the embodiment is to prevent delamination of the pad and protective layer connected to the external chip.

[0009] Additionally, one of the technical challenges of the embodiment is to improve the fixing strength of the pad and connection part connected to the external chip.

[0010] Additionally, one of the technical challenges of the embodiment is to prevent poor connection between the circuit board and an external chip.

[0011] The technical problems of the embodiment are not limited to those described in this article, but include those that can be understood through the description of the invention.

[0012] A circuit board according to an embodiment comprises a build-up insulating portion including a plurality of insulating layers stacked along a vertical direction; a first pad disposed on a first region of the build-up insulating portion; and a second pad disposed on an upper surface of the first pad, wherein the first pad includes a concave portion that is concave inwardly from a side surface of the first pad, and the concave portion can vertically overlap the second pad.

[0013] Additionally, in the embodiment, the horizontal width of the lower surface of the first pad may be greater than the horizontal width of the upper surface of the first pad.

[0014] Additionally, in the embodiment, the horizontal width of the second pad may be smaller than the horizontal width of the lower surface of the first pad.

[0015] Additionally, in the embodiment, the horizontal width of the upper surface of the first pad may be smaller than the horizontal width of the lower surface of the second pad.

[0016] Additionally, in an embodiment, the thickness of the first pad may be greater than the thickness of the second pad.

[0017] Additionally, in the embodiment, the roughness of the upper surface of the second pad may be smaller than the roughness of the concave portion.

[0018] Additionally, the embodiment may further include a third pad disposed on the second region of the build-up insulation and a fourth pad disposed on the third pad.

[0019] Additionally, in the embodiment, the third pad and the fourth pad may be grounded.

[0020] Additionally, in the embodiment, the fourth pad includes a fourth-1 pad and a fourth-2 pad that are spaced apart from each other, and the fourth-1 pad and the fourth-2 pad can be connected via the third pad.

[0021] Additionally, in the embodiment, the fourth pad may be provided on a side surface of the third pad and may have a second concave portion that is concave toward the lower surface from the upper surface of the third pad.

[0022] Additionally, in the embodiment, the third pad may include a plurality of third recesses disposed between the 4-1 pad and the 4-2 pad.

[0023] Additionally, in embodiments, the first pad and the second pad may comprise different materials.

[0024] The circuit board according to the embodiment has a technical effect of preventing damage to pads connected to external chips.

[0025] For example, the embodiment includes a pad portion including a first pad and a second pad, and the second pad includes a different material from the first pad, so that the second pad is not etched during the seed layer etching process, thereby preventing damage.

[0026] Additionally, the embodiment has a technical effect of preventing poor connection with an external chip.

[0027] For example, since the thickness and upper surface of the second pad connected to the external chip are not damaged, an open short problem during connection with the external chip can be prevented and a problem of increased electrical resistance can be prevented.

[0028] In addition, the embodiment has a technical effect of increasing the adhesive strength between the pad portion and the protective layer, thereby preventing peeling.

[0029] For example, referring to FIG. 2F, the embodiment includes a concave portion facing inward on the side of the first pad, and as the concave portion exposes the lower surface of the second pad, the protective layer may be disposed within the concave portion and also contact the lower surface of the second pad, thereby improving the adhesion between the pad portion and the protective layer.

[0030] In addition, the embodiment has a technical effect of improving electrical reliability by improving the fixing strength of the connection part and the pad part.

[0031] For example, referring to FIG. 2g, the embodiment has a concave portion formed inwardly on the side surface of the first pad, and a connecting portion is disposed within the concave portion so that the connecting portion contacts not only the side surface of the second pad but also the lower surface thereof, thereby improving the fixing strength of the connecting portion and the second pad.

[0032] In addition, the embodiment has a technical effect of being able to uniformly control the height according to the area of ​​the circuit board.

[0033] For example, in the embodiment, during the process of etching the first metal layer, the second pad connected to the connection portion is not etched, so that the thickness can be maintained, and the height of the second pad in the effective area and the ground area of ​​the circuit board can be maintained the same.

[0034] The technical effects of the embodiments are not limited to those described in this article, but include those that can be understood through the description of the invention.

[0035] Fig. 1 is a cross-sectional view of a circuit board (100) according to an embodiment.

[0036] Figures 2a to 2g are process diagrams showing the manufacturing process of the first area (A1) of Figure 1.

[0037] Figure 3 is a drawing showing the second area (A2) of Figure 1.

[0038] Figures 4a to 4c are electron microscope drawings of a circuit board according to an embodiment.

[0039] Figure 5 is a drawing of a semiconductor package (101) according to the second embodiment.

[0040] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0041] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0042] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by those of ordinary skill in the technical field to which the present invention pertains, unless explicitly and specifically defined and described. Commonly used terms, such as terms defined in a dictionary, may have their meanings interpreted in consideration of the contextual meaning of the relevant technology. In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention.

[0043] In this specification, singular forms may also include plural forms unless specifically stated otherwise in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C. In addition, terms such as first, second, A, B, (a), (b), etc. may be used to describe components of embodiments of the present invention.

[0044] In this specification, for the convenience of explanation, components may be described in the horizontal direction and the vertical direction. The vertical direction means the top (above) or bottom (below) of each component, and the horizontal direction means the direction perpendicular to the vertical direction. In addition, the horizontal direction may include a first horizontal direction and a second horizontal direction. Here, when the horizontal direction follows a Cartesian coordinate system, the first horizontal direction may mean the X-axis, the second horizontal direction may mean the Y-axis, and the vertical direction may mean the Z-axis. When following a cylindrical coordinate system, the first horizontal direction may mean a direction along an azimuth, and the second horizontal direction may mean a direction toward a radius, and these may be selectively used in combination. In addition, the direction along an azimuth may be referred to as a circumferential direction, and the direction toward a radius may be referred to as a centrifugal direction.

[0045] These terms are only intended to distinguish the component from other components, and are not intended to limit the nature, order, or sequence of the component by the term. In addition, when a component is described as being "connected," "coupled," or "connected" to another component, it may include not only cases where the component is directly connected, coupled, or connected to the other component, but also cases where the component is "connected," "coupled," or "connected" by another component between the component and the other component.

[0046] Additionally, the statement that component A is exposed from component B should be understood to mean that component A is exposed from component B, not that component A is exposed from the entire product. That is, when it is stated that component A is exposed from component B, it should be understood to mean that component A is at least partially covered by component C.

[0047] Additionally, when it is described that a component A is in "contact" with a component B, it may include not only cases where that component is in "contact" with the other component directly, but also cases where that component is "contacted" by another component between that component and the other component. Thus, if a component A is to be understood to be in "direct contact" with a component B, it is described as being in "direct contact."

[0048] In addition, when it is written that configuration A is 'covered' by configuration B, it should be understood that configuration A is covered by configuration B, and that the part for the function and purpose to be solved is covered, and unless there are special circumstances, it should not be understood that the entire configuration A is covered by configuration B.

[0049] In addition, when it is described that configuration A is 'fixed' to configuration B, it should be understood that configuration A is not only fixed by being directly combined with configuration B, but also indirectly fixed to configuration B through configuration C and / or configuration D, etc., unless otherwise specified, taking into account the function and purpose to be solved, and when configuration A is only understood to be 'directly fixed' to configuration B, it is described as being 'directly fixed'.

[0050] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

[0051]

[0052] (Example)

[0053] FIG. 1 is a cross-sectional view of a circuit board (100) according to an embodiment. Referring to FIG. 1, the circuit board (100) according to the embodiment may include a build-up insulating portion (120), a build-up wiring body, and a protective layer (116, 117). The build-up structure may include the build-up insulating portion (120), the build-up wiring body, and the protective layer (116, 117), but is not limited thereto. The build-up structure may function as a laminated circuit for connecting to electronic components / main boards, etc.

[0054] The build-up insulation (120) includes a single or multiple laminated insulation layers and provides insulation properties between the build-up wiring bodies. The build-up insulation (120) may be referred to as a build-up insulation. The build-up insulation (120) may include, but is not limited to, a first build-up insulation (111), a second build-up insulation (112), and a third build-up insulation (113).

[0055] One of the build-up insulation members (120) may be a core layer. The first build-up insulation member (111) located at the center of the build-up insulation member (120) may be a core layer, but is not limited thereto.

[0056] The core layer can function to ensure the overall mechanical rigidity of the circuit board, thereby suppressing warpage. Because it can suppress both warpage occurring during processing and during product operation, the core layer can improve circuit board yield and enhance its reliability.

[0057] The core layer may include a reinforcing member such as glass fiber extending horizontally and a resin covering the reinforcing member, and the mechanical rigidity may be controlled according to the density of the reinforcing member. The reinforcing members of the core layer may be laminated and spaced apart from each other in the vertical direction and provided within the resin layer. According to another embodiment, the core layer may be provided with glass. When provided with glass, there is an effect that the density of via electrodes penetrating the core layer can be increased, and the spacing between via electrodes can be easily controlled. In addition, it may have an advantage of being able to make the circuit board thinner due to higher mechanical rigidity than a resin including glass fiber. The core layer is not limited to the above-described material in consideration of yield, price, etc., and any material that can secure mechanical rigidity may be freely selected and used.

[0058] The build-up insulation (120) may include an upper build-up insulation disposed on the upper surface of the core layer and a lower build-up insulation disposed on the lower surface of the core layer. For example, the build-up insulation (120) may include a first build-up insulation (111) which is the core layer, a second build-up insulation (112) which is an upper build-up insulation disposed on the upper surface of the core layer, and a third build-up insulation (113) which is a lower build-up insulation disposed on the lower surface of the core layer.

[0059] The upper build-up insulation part and the lower build-up insulation part have the function of arranging the wiring layer or via electrode of the build-up wiring body, and the function of securing insulation between circuits and controlling impedance or insertion loss by the circuit, and include an insulation layer including at least one of a thermosetting resin, a photocurable resin, or an optically isotropic film in consideration of dielectric constant, mechanical rigidity, and processability.

[0060]

[0061] For example, the insulation layer of the build-up insulation (120) may be a thermosetting material, and may include, for example, one or more of Ajinomoto build-up film (ABF), epoxy resin, polyimide, phenolic resin, bismaleimide triazine (BT) resin, and silicone resin.

[0062] Also, for example, the insulation layer of the build-up insulation (120) may be a photocurable material, and may include, for example, one or more of a photocurable resin (PID: Photo Imageable Dielectric resin), a photosensitive polyimide, a liquid photoimageable solder resist (LPI), a photosensitive epoxy, or a photosensitive acrylic.

[0063] For example, photocurable resins can form fine patterns of through holes or openings through exposure and development processes, and can eliminate stoppers required in the cavity formation process. Meanwhile, the content of ceramic particles such as SiO2 provided in the insulating layer of the photocurable resin may be higher than the content of ceramic particles provided in the insulating layer of the thermosetting resin, and thus the interfaces of the photocurable resin and the thermosetting resin may be distinguishable. For example, when analyzing a photocurable resin by XPS (X-ray Photoelectron Spectroscopy), relatively high power peak values ​​may be detected in two of acrylic and epoxy. And when analyzing a thermosetting resin by XPS, a peak value may be detected only in epoxy.

[0064] Additionally, the insulating layer of the build-up insulation (120) may include an optically isotropic film, and may include, for example, one or more of COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA).

[0065] Additionally, the insulation layer of the build-up insulation portion (120) may include a prepreg, thereby having a strength higher than a certain level that can improve the bending characteristics of the circuit board. The prepreg constituting the insulation layer may have a structure in which a glass fiber layer in the form of a fabric sheet, such as a glass fabric, is impregnated with an epoxy resin or the like.

[0066]

[0067] Next, the build-up wiring body of the circuit board (100) includes a wiring layer (125) arranged on the surface of each insulating layer and a via electrode (126) for vertically connecting each wiring layer (125). The wiring layer (125) can have the function of transmitting signals and / or power to semiconductor elements arranged on the circuit board (100) and can have an impedance matching function. The wiring layer (125) can be referred to as a wiring pattern layer, a metal wiring, or a wiring portion.

[0068] The via electrode (126) may include a plurality of first via electrodes (127), second via electrodes (128), and third via electrodes (129) formed in through holes that penetrate the first to third build-up insulating portions (111, 112, 113), respectively. The via electrode (126) may electrically connect between wiring layers (125) arranged in different layers.

[0069] The via electrode (126) is formed in a through hole that penetrates each insulating layer, and the through hole can be formed by any one of mechanical processing, laser processing, and chemical processing. When the through hole is formed by mechanical processing, methods such as milling, drilling, and routing can be used. When formed by laser processing, a UV or CO2 laser method can be used, and for chemical processing, a chemical agent including aminosilane, ketones, etc. can be used.

[0070]

[0071] A via electrode (126) can be formed by forming a through hole penetrating the insulating layers and filling the inside of the formed through hole with a conductive material.

[0072] Once the through hole is formed, the inside of the through hole can be filled with a conductive material to form a via electrode (126). The metal material forming the via electrode (126) can be at least one material selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd). In addition, the filling of the conductive material can utilize any one of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjetting, and dispensing, or a combination thereof.

[0073]

[0074] Next, the circuit board (100) according to the embodiment includes a wiring layer (125) electrically connected to a via electrode (126). The wiring layer (125) includes pads and / or traces (or connection patterns) for connecting to the via electrode (126) and / or semiconductor elements and / or capacitors. The traces may be signal wiring lines connecting between a plurality of pads.

[0075] At this time, the pad of the wiring layer (125) includes a connection pad or a connecting pad. The connection pad may be a mounting pad on which an electronic component or semiconductor chip is mounted, or a terminal pad connected to an external substrate. The connection pad is a contact portion that comes into contact with a via electrode, and may include a lateral extension portion with a horizontal width greater than that of the trace for alignment margin.

[0076] The wiring layer (125) may include, but is not limited to, a first wiring layer (121) electrically connected to the upper surface of the first via electrode (127), a second wiring layer (122) disposed on the first build-up insulation (111) and electrically connected to the second via electrode (128), a third wiring layer (123) connected to the lower surface of the first via electrode (127), and a fourth wiring layer (124) electrically connected to the lower surface of the third via electrode (129).

[0077] The wiring layer (125) can be formed by a manufacturing process of a circuit board, such as an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP).

[0078] Any one of the above-described build-up wiring structures may have an Embedded Trace Substrate (ETS) structure. The ETS structure may also be referred to as a buried structure. The ETS structure may be advantageous for miniaturization compared to build-up wiring structures having a general protruding structure. Accordingly, the embodiment enables the formation of electrodes corresponding to the size and pitch of terminals provided in a semiconductor device. Through this, the embodiment can improve circuit integration. Furthermore, the embodiment can minimize the transmission distance of a signal transmitted through the semiconductor device, thereby minimizing signal transmission loss.

[0079] In addition, the build-up wiring body can be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), aluminum (Al), silicon (Si), and zinc (Zn). In addition, the build-up wiring body can be formed of a paste or solder paste containing at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) having excellent bonding strength.

[0080]

[0081] Next, the circuit board (100) according to the embodiment includes a protective layer (116, 117) disposed on the wiring layer of the uppermost or lowermost insulating layer. For example, the protective layer (116, 117) may include a first protective layer (116) disposed on a second build-up insulating portion (112) and a second protective layer (117) disposed under a third build-up insulating portion (113).

[0082] The protective layer (116, 117) can prevent problems such as oxidation or peeling of the build-up structure due to penetration of moisture and / or external contaminants. In addition, the protective layer is formed of a material with low solder wettability to prevent short circuits between adjacent solders when connecting the build-up structure and electronic components or a main board, thereby preventing bridging short circuits between adjacent solders.

[0083] In addition, the protective layer (116, 117) includes an insulating material, and includes various materials that can be cured by heating or light irradiation after being applied to protect the surfaces of the insulating layers and the surfaces of the wiring layers. The protective layer (116, 117) may be a resist layer, and for example, the protective layer (116, 117) may be a solder resist layer that includes an organic polymer material. As an example, the protective layer (116, 117) includes an epoxy acrylate series resin. In detail, the protective layer (116, 117) includes a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic series monomer, etc. However, the embodiment is not limited thereto, and the protective layer (116, 117) may be any one of a photosolder resist layer, a cover-lay, and a polymer material.

[0084]

[0085] Next, FIGS. 2A to 2G are process diagrams showing the manufacturing process of the first region (A1) of FIG. 1. Hereinafter, the process of forming the first pad (140) and the second pad (150) on the upper side of the build-up insulation portion (120) on the circuit board will be described.

[0086] The build-up insulation portion (120) of FIGS. 2a to 2e may include a plurality of insulation layers as shown in FIG. 1, and may include a plurality of wiring layers and via electrodes.

[0087] First, referring to FIG. 2A, a first metal layer (130) may be formed on the build-up insulation portion (120). The first metal layer (130) may refer to a copper foil layer disposed on the build-up insulation portion (120). In addition, the first metal layer (130) may be an electroless plating layer formed by performing electroless plating on the build-up insulation portion (120). For example, the first metal layer (130) may be a chemical copper plating layer. The first metal layer (130) may include both a copper foil layer and a chemical copper plating layer.

[0088] Next, a first mask (not shown) can be formed on the first metal layer (130), and the first mask can include an open area that opens an area where a first pad (140) is to be formed.

[0089] Thereafter, a first pad (140) can be formed by filling the open area of ​​the first mask with the first metal layer (130) as a seed layer. Subsequently, a process of removing the first mask can be performed.

[0090] Next, referring to FIG. 2B, the embodiment may perform a process of forming a second mask (180) on the build-up insulation portion (120). The second mask (180) may be a dry film, but is not limited thereto. The second mask (180) may be formed on the first metal layer (130) and the first pad (140). The second mask (180) may include an open area (180H). The open area (180H) of the second mask (180) may vertically overlap with the first pad (140). A portion of the upper surface of the first pad (140) may be exposed by the open area (180H) of the second mask (180).

[0091] Next, referring to FIG. 2c, a second pad (150) may be formed on the upper surface of the exposed first pad (140). The second pad (150) may be positioned on the upper surface of the first pad (140). The second pad (150) may be formed by performing electrolytic plating on the upper surface of the exposed first pad (140). The second pad (150) may include tin or an alloy containing tin. For example, the second pad (150) may include SnAg, but is not limited thereto.

[0092] The horizontal width of the second pad (150) may be smaller than the horizontal width of the first pad (140). In addition, the thickness of the second pad (150) may be formed to be smaller than the thickness of the first pad (140).

[0093] Next, referring to FIG. 2d, a process of removing the second mask (180) may be performed in the embodiment.

[0094]

[0095] Next, referring to FIG. 2e, in the embodiment, a process for removing a first metal layer (130) disposed on a build-up insulating portion (120) may be performed. A first metal layer disposed in an area of ​​the first metal layer (130) that does not vertically overlap with the first pad (140) may be removed. The process for removing the first metal layer may include organic etching. Specifically, in the embodiment, etching using a general acid or alkali may cause the problem of etching not only the first metal layer (130) but also the second pad (150), so organic etching using an organic acid may be performed.

[0096] Meanwhile, in the process of etching the first metal layer (130), the first pad (140) may also be partially etched. In detail, a concave portion (160) may be formed from the upper surface of the first pad (140) toward the lower surface. In addition, the concave portion (160) may be formed to face inward from the side surface of the first pad (140). The side surface of the first pad (140) may refer to a side surface in an area that does not vertically overlap with the second pad (150). In addition, the inward direction of the first pad (140) may refer to a direction toward the central region of the first pad (140), and may refer to a direction from one side surface of the first pad (140) to the other side surface opposite to the one side surface.

[0097] Additionally, the first pad (140) may include a protrusion (162) in an area that comes into contact with the second pad (150). The protrusion (162) may overlap the second pad (150) in a vertical direction. Additionally, the horizontal width of the protrusion (162) may be smaller than or equal to the horizontal width of the second pad (150). Additionally, the side surface of the protrusion (162) may have a concave shape facing inward.

[0098] As the concave portion (160) is formed, the horizontal width of the upper surface of the first pad (140) may be smaller than the horizontal width of the lower surface of the first pad (140). In addition, the horizontal width of the upper surface of the first pad (140) may be equal to or smaller than the horizontal width of the lower surface of the second pad (150). In addition, the horizontal width of the upper surface of the first pad (140) may be smaller than the horizontal width of the first metal layer (130). Accordingly, in the embodiment, only a portion of the first metal layer (130) and the first pad (140) are etched due to the etching process, and the second pad (150) is not subject to etching damage, so that the thickness of the second pad (150) can be maintained. Therefore, there is a technical effect of preventing a wettability issue (Non-wet) of a connection portion for connection with an external chip and preventing a connection failure.

[0099] Additionally, the concave portion (160) may vertically overlap with the second pad (150). Accordingly, the lower surface of the second pad (150) may be partially exposed by the concave portion (160).

[0100] When a connecting portion such as a solder ball is placed on the second pad (150), the connecting portion can be in contact not only with the upper and side surfaces of the second pad (150) but also with the lower surface of the second pad (150) exposed by the concave portion (160), thereby improving the electrical contact area, and there is a technical effect in that the edge area of ​​the second pad (150) exposed by the concave portion (160) can function as an anchor to fix the connecting portion.

[0101] Additionally, the first thickness (T1) of the first pad (140) may be greater than the second thickness (T2) of the second pad (150).

[0102] Additionally, the first metal layer (130) may be electrically connected to the via electrode of the build-up insulation (120). Additionally, the first pad (140) may overlap the via electrode electrically connected to the first metal layer (130) in the vertical direction.

[0103] In addition, since a part of the first pad (140) is etched and the second pad (150) is not etched, the roughness of the upper surface of the second pad (150) may be less than the roughness of the concave portion (160). Accordingly, the embodiment has a technical effect in that the upper surface of the second pad (150) in contact with the external chip and / or connection portion is not damaged, thereby preventing the problem of increased electrical resistance.

[0104]

[0105] Next, referring to FIG. 2f, a protective layer (116) may be formed on the build-up insulation (120). The protective layer (116) may be positioned to cover a portion of the first pad (140). Additionally, the protective layer (116) may be positioned to contact a side surface of the second pad (150).

[0106] Meanwhile, the protective layer (116) may be formed to fill the concave portion (160). Accordingly, the protective layer (116) may also be in contact with the lower surface of the second pad (150) exposed by the concave portion (160). The concave portion (160) may vertically overlap with the second pad (150). Accordingly, the concave portion (160) may perform an anchor function so that the protective layer (116) may be in contact with the lower surface of the second pad (150). Therefore, the embodiment has a technical effect in that the contact area between the protective layer (116) and the pad is increased by the concave portion (160) formed in the first pad (140), and the adhesive strength between the protective layer (116) and the pad can be improved by contacting not only the side surface but also the lower surface of the second pad.

[0107] Thereafter, a connection portion (190) can be placed on the second pad (150). Through the connection portion (190), the second pad (150) can be connected to an external chip or substrate.

[0108] Next, FIG. 2g is an embodiment in which the protective layer (116) in FIG. 2f is modified. Referring to FIG. 2g, the protective layer (116) may be arranged to cover a portion of the first pad (140). Meanwhile, the protective layer (116) may be arranged to be spaced apart from the second pad (150) by a predetermined distance. At this time, when the connecting portion (190) is formed on the second pad (150), the connecting portion (190) may penetrate between the second pad (150) and the protective layer (116). In addition, the connecting portion (190) may be arranged to fill the concave portion (160). Accordingly, the connecting portion (190) may contact the upper surface, side surface, and lower surface of the second pad (150). The connecting portion (190) in contact with the lower surface of the second pad (150) has a technical effect of performing an anchor function to prevent the connecting portion (190) from being separated from the second pad (150). In addition, the embodiment has a technical effect of improving the signal transmission speed as the contact area between the connecting portion (190) and the second pad (150) increases.

[0109]

[0110] Fig. 3 is a drawing showing the second area (A2) of Fig. 1. The second area (A2) of Fig. 1 may be a ground area (ground area). Referring to Fig. 3, a first metal layer (130) may be disposed on a build-up insulation portion (120). The first metal layer (130) may not be electrically connected to a via electrode or wiring layer disposed within the build-up insulation portion (120).

[0111] A third pad (140G) may be placed on the first metal layer (130). A fourth pad (150G) may be placed on the upper surface of the third pad (140G). The third pad (140G) and the fourth pad (150G) may function as ground pads.

[0112] The fourth pad (150G) may include multiple pads. For example, the fourth pad (150G) may include a fourth-first pad (150G1) and a fourth-second pad (150G2) that are spaced apart from each other. The fourth-first pad (150G1) and the fourth-second pad (150G2) may be positioned on the same third pad (140G). The fourth-first pad (150G1) and the fourth-second pad (150G2) may be connected via the third pad (140G).

[0113] Meanwhile, referring to FIG. 1 for a moment, the upper surface of the third pad (140G) of the second region (A2) may be partially etched during the process of etching the first metal layer (130) of the first region (A1). Specifically, the third pad (140G) may have a second concave portion (160G) formed so that it is concave from the upper surface to the lower surface. In addition, a plurality of third concave portions (165) may be formed between the 4-1 pad (150G1) and the 4-2 pad (150G2).

[0114]

[0115] Figures 4a and 4b are electron microscope drawings of a circuit board according to an embodiment. Referring first to Figure 4a, the circuit board according to the embodiment may include a first pad (140) and a second pad (150) on a build-up insulating portion (120).

[0116] Meanwhile, the first pad (140) on the circuit board may be formed with the first metal layer (130) as a seed layer. In addition, the second pad (150) placed on the first pad (140) may include a different material from the first pad (140).

[0117] Accordingly, a portion of the first pad (140) may be etched during the etching process of the first metal layer (130). Specifically, the first pad (140) may include a concave portion (160) that faces from the upper surface to the lower surface. The concave portion (160) may vertically overlap the second pad (150). In addition, the concave portion (160) may contact the lower surface of the second pad (150). On the other hand, the second pad (150) may not be etched. In addition, the roughness of the upper surface of the second pad (150) may be maintained during the etching process of the first metal layer (130).

[0118] Also, referring to FIG. 4B, a second pad (150) may be placed on the first pad (140). The horizontal width of the second pad (150) may be smaller than the horizontal width of the first pad (140). In addition, the first pad (140) may include a concave portion (160) that is concave inward from the side. The concave portion (160) may contact the lower surface of the second pad (150). In addition, a protective layer (116) may be placed to cover a portion of the first pad (140). The protective layer (116) may cover a portion of the side surface and the upper surface of the first pad (140) and fill the inside of the concave portion (160). Accordingly, the protective layer (116) may contact the side surface and the lower surface of the second pad (150), and the adhesion between the protective layer (116) and the pad may be improved.

[0119]

[0120] Also, referring to FIG. 4C, the circuit board of the embodiment may include a first area (A1) which is a signal area and a second area (A2) which is a ground area. In the first area (A1), the first pads (140) may be arranged to be spaced apart from each other. In addition, the second pad (150) may be arranged on the first pad (140), and the horizontal width of the second pad (150) may be smaller than the horizontal width of the first pad (140). In addition, an inwardly concave portion (160) may be formed on the side surface of the first pad (140), and the concave portion (160) may vertically overlap the second pad (150). In addition, the first pad (140) and the second pad (150) may include different materials. Accordingly, during seed layer etching, a portion of the first pad (140) may be etched to form a concave portion (160), but the second pad (150) may not be etched.

[0121] Additionally, the first region (A1) and the second region (A2) may be separated by a first pad (140). In the second region (A2), the second pad (150) may be placed on the same first pad (140). Additionally, the heights of the upper surfaces of the second pad (150) of the first region (A1) and the second pad (150) of the second region (A2) may be the same.

[0122]

[0123] Fig. 5 is a drawing of a semiconductor package (101) according to a second embodiment. The semiconductor package (101) of the second embodiment may include a circuit board (100) having the build-up structure of Fig. 1.

[0124] Referring to FIG. 5, a semiconductor package (101) according to a second embodiment may include a circuit board (100) and a chip (200) disposed on the circuit board (100). In detail, the circuit board (100) may have a second pad (150) disposed on a first pad (140) disposed on the outermost layer of a build-up insulating member (120), and a first protective layer (116) exposing an upper surface of the second pad (150) may be disposed. In addition, a connection portion (190) may be disposed on the exposed second pad (150). The connection portion (190) may have a spherical shape. In addition, a cross-section of the connection portion (190) may have a circular shape or a semicircular shape. The connection portion (190) may be a solder ball, but is not limited thereto.

[0125] In addition, the circuit board may further include a bonding portion on the first protective layer (116). The bonding portion is positioned on the upper surface of the first protective layer (116) to perform thermal compression bonding with the semiconductor element, and may be used when the pitch of the first pad (140) of the semiconductor element becomes fine and it is difficult to implement with conventional solder bonding.

[0126] In addition, a chip (200) or a component may be included on the connection portion (190) of the circuit board. The chip (200) may be a processor chip. For example, the chip (200) may be an application processor (AP) chip of any one of a central processor (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller. A terminal (210) may be included on the bottom surface of the chip (200), and a plurality of terminals (210) may be included.

[0127] The terminal (210) of the chip (200) can be electrically connected to the connection portion (190) of the circuit board.

[0128] Meanwhile, the semiconductor package (101) of the embodiment may include a plurality of chips that are horizontally spaced apart from each other and arranged on a single circuit board. For example, the chip (200) may also include a first chip and a second chip. The first chip and the second chip may be different types of application processor (AP) chips.

[0129] Additionally, the connection portion located at the bottom of the semiconductor package (101) of the embodiment may be for connecting a main board (or motherboard) of an external device.

[0130] The circuit board or semiconductor package according to the embodiment may be applied to any one of a CSP (Chip Scale Package), an FC-CSP (Flip Chip-Chip Scale Package), an FC-BGA (Flip Chip Ball Grid Array), a POP (Package On Package), and a SIP (System In Package).

[0131] Additionally, the circuit board or semiconductor package may be applied to, but is not limited to, smart phones, personal digital assistants, digital video cameras, digital still cameras, vehicles, high-performance servers, network systems, computers, monitors, tablets, laptops, netbooks, televisions, video games, smart watches, automotives, etc.

[0132] The features, structures, effects, etc. described in the above-described embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as falling within the scope of the present invention.

[0133] Although the above description focuses on examples, these are merely examples and do not limit the present invention. Those skilled in the art to which the present invention pertains will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the present invention defined in the appended claims.

Claims

1. A built-up insulation comprising a plurality of insulating layers laminated along a vertical direction; A first pad disposed on a first region of the above build-up insulation; and A second pad disposed on the upper surface of the first pad; The first pad includes a concave portion that is concave inwardly on the side of the first pad, The above concave portion is a circuit board vertically overlapped with the second pad.

2. In paragraph 1, A circuit board wherein the horizontal width of the lower surface of the first pad is greater than the horizontal width of the upper surface of the first pad.

3. In paragraph 1, A circuit board wherein the horizontal width of the second pad is smaller than the horizontal width of the lower surface of the first pad.

4. In paragraph 1, A circuit board wherein the horizontal width of the upper surface of the first pad is smaller than the horizontal width of the lower surface of the second pad.

5. In paragraph 1, A circuit board wherein the thickness of the first pad is greater than the thickness of the second pad.

6. In paragraph 1, A circuit board wherein the roughness of the upper surface of the second pad is smaller than the roughness of the concave portion.

7. In paragraph 1, A third pad disposed on the second region of the above build-up insulation; and Further comprising a fourth pad disposed on the third pad; The above third pad and the above fourth pad are grounded, The above fourth pad includes a fourth-1 pad and a fourth-2 pad which are arranged spaced apart from each other, A circuit board in which the above 4-1 pad and the 4-2 pad are connected through the above 3rd pad.

8. In paragraph 7, A circuit board, wherein the fourth pad is provided on a side surface of the third pad and has a second concave portion that is concave toward the lower surface from the upper surface of the third pad.

9. In paragraph 1, A circuit board, wherein the first pad and the second pad contain different materials.

10. A semiconductor package comprising a circuit board according to any one of claims 1 to 10.

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