Display substrate and manufacturing method therefor

Abstract

A display substrate and a manufacturing method therefor. The display substrate comprises a base substrate (110), a driving circuit layer (120), a plurality of first electrodes (E1), and a pixel defining layer (PDL); the driving circuit layer (120) is provided on the base substrate (110) and comprises a plurality of pixel driving circuits (D) for a plurality of subpixels (SP) and a protective insulating layer (PLN) covering the plurality of pixel driving circuits (D); the plurality of first electrodes (E1) are provided on the side of the driving circuit layer (120) distant from the base substrate (110), and are respectively electrically connected to output terminals (T) of the plurality of pixel driving circuits (D) through a plurality of first via holes (PLN1) of the protective insulating layer (PLN); the pixel defining layer (PDL) is at least provided on the side of the plurality of first electrodes (E1) distant from the base substrate (110), and comprises a plurality of first openings (O1) respectively exposing the plurality of first electrodes (E1) and a plurality of second openings (O2) formed between adjacent subpixels (SP) among the plurality of subpixels (SP); and the pixel defining layer (PDL) has first partition structures (P1) at the plurality of first openings (O1) and has second partition structures (P2) at the plurality of second openings (O2). The display substrate has a high color gamut and a good display effect.

Description

Display substrate and manufacturing method thereof Technical Field

[0001] Embodiments of the present disclosure relate to a display substrate and a method for manufacturing the same. Background Art

[0002] OLED (Organic Light Emitting Diode) display devices have a series of advantages such as self-luminescence, high contrast, high clarity, wide viewing angle, low power consumption, fast response speed, and low manufacturing cost. They have become one of the key development directions of the new generation of display devices and are therefore receiving increasing attention.

[0003] Summary of the Invention

[0004] At least one embodiment of the present disclosure provides a display substrate, which includes a display substrate having a plurality of sub-pixels arranged in an array, and includes a base substrate, a driving circuit layer, a plurality of first electrodes and a pixel defining layer, wherein the driving circuit layer is arranged on the base substrate, including a plurality of pixel driving circuits for the plurality of sub-pixels and a protective insulating layer covering the plurality of pixel driving circuits, wherein the protective insulating layer includes a plurality of first vias exposing the output ends of the plurality of pixel driving circuits, the plurality of first electrodes are arranged on a side of the driving circuit layer away from the base substrate, and are electrically connected to the output ends of the plurality of pixel driving circuits through the plurality of first vias respectively; the pixel defining layer is arranged at least on a side of the plurality of first electrodes away from the base substrate, including a plurality of first openings respectively exposing the plurality of first electrodes and a plurality of second openings arranged between adjacent sub-pixels in the plurality of sub-pixels, wherein the pixel defining layer has a first partition structure at the plurality of first openings and a second partition structure at the plurality of second openings.

[0005] For example, in the display substrate provided in at least one embodiment of the present disclosure, in a direction perpendicular to the base substrate, a height of the first partition structure is different from a height of the second partition structure.

[0006] For example, in the display substrate provided by at least one embodiment of the present disclosure, the height of the first partition structure is smaller than the height of the second partition structure.

[0007] For example, in the display substrate provided in at least one embodiment of the present disclosure, the pixel defining layer includes a first pixel defining layer and a second pixel defining layer arranged on a side of the first pixel defining layer away from the base substrate, the first pixel defining layer includes an inorganic material, and the second pixel defining layer includes an organic material.

[0008] For example, in the display substrate provided in at least one embodiment of the present disclosure, the organic material includes polyimide or resin.

[0009] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first pixel defining layer includes a first sub-pixel defining layer and a second sub-pixel defining layer arranged on a side of the first sub-pixel defining layer away from the base substrate, the first sub-pixel defining layer and the second sub-pixel defining layer are made of different materials, and in a direction parallel to the base substrate and at the multiple first openings, the first sub-pixel defining layer is retracted relative to the second sub-pixel defining layer so that the first partition structure includes a first undercut structure.

[0010] For example, in the display substrate provided by at least one embodiment of the present disclosure, at the plurality of first openings, the first sub-pixel defining layer is retracted relative to the second sub-pixel defining layer by a distance of 0.05 μm to 0.2 μm.

[0011] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first pixel defining layer includes a first sub-pixel defining layer and a second sub-pixel defining layer arranged on a side of the first sub-pixel defining layer away from the base substrate, the first sub-pixel defining layer and the second sub-pixel defining layer are made of different materials, and in a direction parallel to the base substrate and at the multiple second openings, the first sub-pixel defining layer is retracted relative to the second sub-pixel defining layer so that the second partition structure includes a second undercut structure.

[0012] For example, in the display substrate provided by at least one embodiment of the present disclosure, at the plurality of second openings, the first sub-pixel defining layer is retracted relative to the second sub-pixel defining layer by a distance of 0.05 μm to 0.2 μm.

[0013] For example, in the display substrate provided in at least one embodiment of the present disclosure, the materials of the first sub-pixel defining layer and the second sub-pixel defining layer are two of Al2O3, SiN, SiO, SiCN, TiO and Nb2O5 respectively.

[0014] For example, in the display substrate provided in at least one embodiment of the present disclosure, in a direction perpendicular to the base substrate, the thickness of the first sub-pixel defining layer is greater than the thickness of the second sub-pixel defining layer.

[0015] For example, in the display substrate provided in at least one embodiment of the present disclosure, the thickness of the first sub-pixel defining layer is 25 nm-50 nm, and the thickness of the second sub-pixel defining layer is 20 nm-25 nm.

[0016] For example, in the display substrate provided in at least one embodiment of the present disclosure, in a direction perpendicular to the base substrate, the thickness of the second pixel defining layer is 0.8 μm-1.5 μm.

[0017] For example, in the display substrate provided in at least one embodiment of the present disclosure, the second pixel defining layer has a first slope angle at the multiple first openings and a second slope angle at the multiple second openings, the first slope angle is 30°-70°, and the second slope angle is 30°-70°.

[0018] For example, the display substrate provided by at least one embodiment of the present disclosure also includes a passivation layer arranged between the protective insulating layer and the multiple first electrodes, the passivation layer includes multiple second vias respectively exposing the multiple first vias, and the multiple first electrodes are electrically connected to the output ends of the multiple pixel driving circuits through the multiple second vias and the multiple first vias respectively; the passivation layer includes multiple third openings respectively connected to the multiple second openings, and the orthographic projections of the multiple third openings on the base substrate at least partially overlap with the orthographic projections of the multiple second openings on the base substrate.

[0019] For example, in the display substrate provided by at least one embodiment of the present disclosure, the orthographic projections of the plurality of second via holes on the base substrate are respectively located within the orthographic projections of the plurality of first via holes on the base substrate.

[0020] For example, in the display substrate provided in at least one embodiment of the present disclosure, the passivation layer includes a first passivation layer and a second passivation layer arranged on a side of the first passivation layer away from the base substrate, the first passivation layer and the second passivation layer are made of different materials, and the second passivation layer includes the multiple third openings.

[0021] For example, in the display substrate provided in at least one embodiment of the present disclosure, in a direction perpendicular to the base substrate, the thickness of the first passivation layer is greater than the thickness of the second passivation layer.

[0022] For example, in the display substrate provided in at least one embodiment of the present disclosure, the thickness of the first passivation layer is 100 nm-200 nm, and the thickness of the second passivation layer is 40 nm-100 nm.

[0023] For example, in the display substrate provided in at least one embodiment of the present disclosure, the protective insulating layer includes a plurality of fourth openings respectively connected to the plurality of second openings, and the orthographic projections of the plurality of fourth openings on the base substrate respectively at least partially overlap with the orthographic projections of the plurality of second openings on the base substrate.

[0024] For example, in the display substrate provided in at least one embodiment of the present disclosure, in a direction parallel to the base substrate, the multiple fourth openings expand outward relative to the multiple second openings, so that the orthographic projections of the multiple second openings on the base substrate are respectively located within the orthographic projections of the multiple fourth openings on the base substrate.

[0025] For example, in the display substrate provided by at least one embodiment of the present disclosure, in a direction parallel to the base substrate, the outer extension distance of the plurality of fourth openings relative to the plurality of second openings is 0.1 μm-0.5 μm.

[0026] For example, in the display substrate provided in at least one embodiment of the present disclosure, at least one second opening is provided between every two adjacent sub-pixels in the plurality of sub-pixels.

[0027] For example, in the display substrate provided by at least one embodiment of the present disclosure, at least some of the plurality of second openings are connected to each other to form a ring-shaped opening that completely surrounds at least one sub-pixel among the plurality of sub-pixels.

[0028] For example, in the display substrate provided in at least one embodiment of the present disclosure, the plurality of second openings are respectively in a strip shape and spaced apart from each other.

[0029] For example, the display substrate provided in at least one embodiment of the present disclosure also includes a light-emitting material layer and a second electrode layer; the light-emitting material layer is arranged on the side of the pixel defining layer away from the base substrate, and the second electrode layer is arranged on the side of the light-emitting material layer away from the base substrate, wherein at least part of the light-emitting material layer is disconnected by at least one of the first partition structure and the second partition structure, and the second electrode layer is continuous at at least one of the first partition structure and the second partition structure.

[0030] For example, in the display substrate provided in at least one embodiment of the present disclosure, the light-emitting material layer includes at least one charge generation layer, and the at least one charge generation layer is disconnected by at least one of the first partition structure and the second partition structure.

[0031] At least one embodiment of the present disclosure also provides a method for preparing a display substrate, wherein the display substrate has a plurality of sub-pixels arranged in an array, the preparation method comprising: providing a base substrate, forming a driving circuit layer on the base substrate, wherein the driving circuit layer comprises a plurality of pixel driving circuits for the plurality of sub-pixels and a protective insulating layer covering the plurality of pixel driving circuits, wherein the protective insulating layer comprises a plurality of first vias exposing output ends of the plurality of pixel driving circuits, forming a plurality of first electrodes on a side of the driving circuit layer away from the base substrate, wherein the plurality of first electrodes are respectively electrically connected to the output ends of the plurality of pixel driving circuits through the plurality of first vias; and forming a pixel defining layer on at least a side of the plurality of first electrodes away from the base substrate, wherein the pixel defining layer comprises a plurality of first openings respectively exposing the plurality of first electrodes and a plurality of second openings arranged between adjacent sub-pixels in the plurality of sub-pixels, and the pixel defining layer has a first partition structure formed at the plurality of first openings and a second partition structure formed at the plurality of second openings. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0033] FIG1 is a schematic plan view of a display substrate provided by at least one embodiment of the present disclosure;

[0034] FIG2 is a partial cross-sectional schematic diagram of the display substrate along line AA in FIG1 ;

[0035] FIG3 is a schematic cross-sectional view of a light-emitting device of a display substrate provided by at least one embodiment of the present disclosure;

[0036] 4A-4B are transmission electron microscope images of a display substrate at a second partition structure according to at least one embodiment of the present disclosure;

[0037] FIG4C is a transmission electron microscope image of a display substrate at a first partition structure according to at least one embodiment of the present disclosure;

[0038] FIG5 is another partial cross-sectional schematic diagram of the display substrate along line AA in FIG1 ;

[0039] FIG6 is a schematic cross-sectional view of another portion of the display substrate along line AA in FIG1 ;

[0040] FIG7 is another partial cross-sectional schematic diagram of the display substrate along line AA in FIG1 ;

[0041] FIG8 is another partial cross-sectional schematic diagram of the display substrate along line AA in FIG1 ;

[0042] FIG9 is another partial cross-sectional schematic diagram of the display substrate along line AA in FIG1 ;

[0043] FIG10 is a planar scanning electron microscope image of a display substrate provided by at least one embodiment of the present disclosure;

[0044] 11 to 13 are schematic diagrams of different arrangements of first openings and second openings in a display substrate according to at least one embodiment of the present disclosure;

[0045] FIG14 is a partial cross-sectional schematic diagram of the display substrate in FIG2 during the preparation process;

[0046] FIG15 is a partial cross-sectional schematic diagram of the display substrate in FIG6 during the preparation process;

[0047] FIG16 is a partial cross-sectional schematic diagram of the display substrate in FIG7 during the preparation process; and

[0048] FIG17 is a partial cross-sectional schematic diagram of the display substrate in FIG8 during the preparation process. DETAILED DESCRIPTION

[0049] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0050] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0051] In OLED displays, to increase the brightness of the OLED device, a charge generation layer (CGL) is introduced into the luminescent material layer of the OLED device to connect multiple luminescent layers in series. However, the charge generation layer is a high-mobility film layer whose function is to transfer electrons and holes to adjacent luminescent layers. Due to the presence of the CGL, there will be lateral current transmission between adjacent sub-pixels, causing sub-pixels that should not emit light to emit light, resulting in a reduction in the color gamut of the display device.

[0052] At least one embodiment of the present disclosure provides a display substrate and a preparation method thereof, wherein the display substrate has a plurality of sub-pixels arranged in an array, and includes a base substrate, a driving circuit layer, a plurality of first electrodes and a pixel defining layer; the driving circuit layer is arranged on the base substrate, including a plurality of pixel driving circuits for the plurality of sub-pixels and a protective insulating layer covering the plurality of pixel driving circuits, wherein the protective insulating layer includes a plurality of first vias exposing the output ends of the plurality of pixel driving circuits, the plurality of first electrodes are arranged on a side of the driving circuit layer away from the base substrate, and are electrically connected to the output ends of the plurality of pixel driving circuits through the plurality of first vias respectively; the pixel defining layer is arranged on at least a side of the plurality of first electrodes away from the base substrate, including a plurality of first openings respectively exposing the plurality of first electrodes and a plurality of second openings arranged between adjacent sub-pixels in the plurality of sub-pixels, the pixel defining layer has a first partition structure at the plurality of first openings and a second partition structure at the plurality of second openings.

[0053] In the above-mentioned display substrate provided in the embodiment of the present disclosure, by respectively arranging the first partition structure and the second partition structure at different positions of the pixel defining layer, the isolation effect of the light-emitting material layer can be fully realized in each sub-pixel and between adjacent sub-pixels, thereby effectively avoiding electrical crosstalk between different sub-pixels and improving the color gamut of the display substrate.

[0054] The display substrate and the preparation method thereof according to some embodiments of the present disclosure are described below through several specific examples.

[0055] At least one embodiment of the present disclosure provides a display substrate, FIG1 shows a planar schematic diagram of the display substrate, FIG2 shows a partial cross-sectional schematic diagram of the display substrate along line AA in FIG1 , and FIG3 shows a cross-sectional schematic diagram of a light-emitting device. As shown in FIG1 and FIG2 , the display substrate has a plurality of sub-pixels SP arranged in an array, and includes a base substrate 110, a driving circuit layer 120, a plurality of first electrodes E1, and a pixel defining layer PDL.

[0056] As shown in Figure 2, the driving circuit layer 120 is provided on the base substrate 110, and includes a plurality of pixel driving circuits D for a plurality of sub-pixels SP and a protective insulating layer PLN covering the plurality of pixel driving circuits D. For example, each sub-pixel SP includes a pixel driving circuit D and a light-emitting device EM, and the pixel driving circuit D is used to drive the light-emitting device EM to emit light. For example, each pixel driving circuit D includes a plurality of thin film transistors and storage capacitors and other structures, for example, formed into a 2T1C (i.e., including two thin film transistors and a storage capacitor), a 3T1C (i.e., including three thin film transistors and a storage capacitor), a 7T1C (i.e., including seven thin film transistors and a storage capacitor), an 8T2C (i.e., including eight thin film transistors and two storage capacitors) and other structures. The embodiments of the present disclosure do not limit the specific form of the pixel driving circuit D.

[0057] For example, the protective insulating layer PLN can be an organic planar layer, including organic insulating materials such as polyimide and resin. The protective insulating layer PLN is set above multiple pixel driving circuits D to achieve the protection and planarization of multiple pixel driving circuits D.

[0058] For example, each pixel driving circuit D has an output terminal T for connecting to a light-emitting device EM to drive the light-emitting device EM. For example, as shown in FIG3 , each light-emitting device EM includes a first electrode E1, a light-emitting material layer E2, and a second electrode layer E3, which are sequentially arranged in a direction away from the base substrate 110. The protective insulating layer PLN includes a plurality of first vias PLN1 that expose the output terminals T of the plurality of pixel driving circuits D. The plurality of first electrodes E1 are arranged on a side of the driving circuit layer 120 away from the base substrate 110 and are electrically connected to the output terminals T of the plurality of pixel driving circuits D through the plurality of first vias PLN1, thereby achieving a connection between the light-emitting device EM and the pixel driving circuit D in each sub-pixel SP.

[0059] As shown in FIG2 , the pixel defining layer (PDL) is disposed at least on a side of the plurality of first electrodes E1 away from the base substrate 110 and includes a plurality of first openings O1 that expose the plurality of first electrodes E1, and a plurality of second openings O2 disposed between adjacent sub-pixels SP. The plurality of first openings O1 may serve as sub-pixel openings for defining locations for forming the light-emitting devices EM. The pixel defining layer (PDL) includes a first partition structure P1 at the plurality of first openings O1 and a second partition structure P2 at the plurality of second openings O2.

[0060] For example, in the embodiments of the present disclosure, the light-emitting material layer E2 is disposed on a side of the pixel defining layer PDL away from the base substrate 110, and the second electrode layer E3 is disposed on a side of the light-emitting material layer E2 away from the base substrate 110. For example, the first electrode E1 serves as the anode of the light-emitting device EL, and the second electrode layer E3 serves as the cathode of the light-emitting device EL. For example, the second electrode layer E3 is typically disposed continuously on the display substrate, that is, the second electrode layers E3 of multiple sub-pixels SP are disposed continuously. This reduces the resistance of the second electrode layer E3 and ensures that the electrical signals received by the second electrode layers E3 of the multiple sub-pixels SP are substantially the same.

[0061] In the embodiments of the present disclosure, the first partition structure P1 and the second partition structure P2 can isolate the light-emitting material layer E2 of the light-emitting device EM. For example, at least a portion of the light-emitting material layer E2 is disconnected by at least one of the first partition structure P1 and the second partition structure P2. That is, the light-emitting material layer E2 is discontinuous at at least one of the first partition structure P1 and the second partition structure P2, while the second electrode layer E3 is continuous at at least one of the first partition structure P1 and the second partition structure P2. This effectively prevents electrical crosstalk between different sub-pixels and improves the color gamut of the display substrate.

[0062] For example, in some examples, the light-emitting material layer E2 includes at least one charge generation layer E21. The charge generation layer E21 has high electron mobility. This charge generation layer E21 is disconnected by at least one of the first partition structure P1 and the second partition structure P2, thereby preventing crosstalk between adjacent sub-pixels SP. For example, the light-emitting material layer E2 may further include functional layers such as an organic light-emitting layer, a hole injection layer, a hole transport layer, an electron blocking layer, and an electron transport layer, although these are not specifically limited in the embodiments of the present disclosure.

[0063] For example, the plurality of sub-pixels SP may include sub-pixels of three colors: red, green, and blue. The first partition structure P1 and the second partition structure P2 may prevent crosstalk between sub-pixels of different colors.

[0064] For example, in some embodiments, the height H1 of the first partition structure P1 is different from the height H2 of the second partition structure P2 in a direction perpendicular to the base substrate 110. Thus, the first partition structure P1 and the second partition structure P2 achieve different degrees of isolation at different locations, thereby achieving the technical effect of fully and effectively isolating the light-emitting material layer E2.

[0065] For example, in some embodiments, the height of the first partition structure P1 is smaller than the height of the second partition structure P2 , thereby achieving a more effective partitioning effect at the second partition structure P2 .

[0066] For example, in some embodiments, as shown in Figure 2, the pixel defining layer PDL includes a first pixel defining layer PDL1 and a second pixel defining layer PDL2 arranged on the side of the first pixel defining layer PDL1 away from the base substrate 110, the first pixel defining layer PDL1 includes an inorganic material, and the second pixel defining layer PDL2 includes an organic material, such as polyimide, resin and other organic insulating materials.

[0067] For example, in some embodiments, the first pixel defining layer PDL1 includes a multi-layer structure. For example, as shown in Figure 2, the first pixel defining layer PDL1 includes a first sub-pixel defining layer PDL11 and a second sub-pixel defining layer PDL12 arranged on the side of the first sub-pixel defining layer PDL11 away from the base substrate 110. The materials of the first sub-pixel defining layer PDL11 and the second sub-pixel defining layer PDL12 are different. For example, during the preparation process, the materials of the first sub-pixel defining layer PDL11 and the second sub-pixel defining layer PDL12 have different etching rates relative to the etchant used to form a partition structure.

[0068] For example, in a direction parallel to the base substrate 110 and at the plurality of first openings O1, the first sub-pixel defining layer PDL11 is retracted relative to the second sub-pixel defining layer PDL12, so that the first partition structure P1 includes a first undercut structure. That is, the first sub-pixel defining layer PDL11 at the bottom layer occupies a smaller area, while the second sub-pixel defining layer PDL12 at the top layer occupies a larger area. For example, the orthographic projection of the first sub-pixel defining layer PDL11 on the base substrate 110 is smaller than the orthographic projection of the second sub-pixel defining layer PDL12 on the base substrate 110. Therefore, when the light-emitting material layer is formed above the second sub-pixel defining layer PDL12, it is easily disconnected at the first undercut structure.

[0069] For example, in some embodiments, as shown in FIG2 , at a plurality of first openings O1 , the first sub-pixel defining layer PDL11 is retracted by a distance L1 of 0.05 μm to 0.2 μm relative to the second sub-pixel defining layer PDL12 , for example, 0.05 μm, 0.07 μm, 0.09 μm, 0.12 μm, 0.15 μm, 0.18 μm or 0.20 μm, etc., so that the first undercut structure of the first partition structure P1 has sufficient partitioning effect.

[0070] For example, as shown in FIG2 , in a direction parallel to the base substrate 110 and at the plurality of second openings O2, the first sub-pixel defining layer PDL11 is retracted relative to the second sub-pixel defining layer PDL12, so that the second partition structure P2 includes a second undercut structure. Similar to the first undercut structure, at the plurality of second openings O2, the first sub-pixel defining layer PDL11 at the bottom layer occupies a smaller area, while the second sub-pixel defining layer PDL12 at the top layer occupies a larger area. For example, the orthographic projection of the first sub-pixel defining layer PDL11 on the base substrate 110 is smaller than the orthographic projection of the second sub-pixel defining layer PDL12 on the base substrate 110. Consequently, when the light-emitting material layer is formed above the second sub-pixel defining layer PDL12, it is easily disconnected at the second undercut structure.

[0071] For example, at the plurality of second openings O2 , the first sub-pixel defining layer PDL11 is retracted relative to the second sub-pixel defining layer PDL12 by a distance L2 of 0.05 μm-0.2 μm, such as 0.05 μm, 0.07 μm, 0.09 μm, 0.12 μm, 0.15 μm, 0.18 μm or 0.20 μm.

[0072] For example, in some embodiments, the first sub-pixel defining layer PDL11 may be retracted relative to the second sub-pixel defining layer PDL12 at the plurality of first openings O1 by a different distance L1 than the first sub-pixel defining layer PDL11 may be retracted relative to the second sub-pixel defining layer PDL12 at the plurality of second openings O2, thereby forming different degrees of isolation. For example, in some examples, the retracted distance L2 is greater than the retracted distance L1 to form a stronger isolation effect between adjacent sub-pixels SO, thereby preventing crosstalk between adjacent sub-pixels SP.

[0073] For example, in some embodiments, the materials of the first sub-pixel defining layer PDL11 and the second sub-pixel defining layer PDL12 are respectively two of Al2O3, SiN, SiO, SiCN, TiO, and Nb2O5, for example, materials having different etching rates relative to the same etchant. For example, in some examples, the first sub-pixel defining layer PDL11 can be made of SiN, and the second sub-pixel defining layer PDL12 can be made of SiO; in other examples, the first sub-pixel defining layer PDL11 can be made of Al2O3, and the second sub-pixel defining layer PDL12 can be made of SiO or SiN.

[0074] For example, in some embodiments, as shown in FIG2 , in a direction perpendicular to the base substrate 110 , that is, in the vertical direction in the figure, the thickness of the first sub-pixel defining layer PDL11 is greater than the thickness of the second sub-pixel defining layer PDL12 to form a sufficiently high bottom cut structure to fully and effectively realize the isolation effect.

[0075] For example, in some examples, the thickness of the first sub-pixel defining layer PDL11 is 25nm-50nm, such as 25nm, 30nm, 35nm, 40nm, 45nm or 50nm, and the thickness of the second sub-pixel defining layer PDL12 is 20nm-25nm, such as 20nm, 21nm, 22nm, 23nm or 24nm.

[0076] For example, in a direction perpendicular to the base substrate 110 , the thickness of the second pixel defining layer PDL2 is 0.8 μm-1.5 μm, such as 0.9 μm, 1.0 μm, 1.1 μm, 1.2 μm, 1.3 μm or 1.4 μm.

[0077] For example, in some embodiments, as shown in FIG2 , the second pixel defining layer PDL2 has a first slope angle a at the plurality of first openings O1 and a second slope angle b at the plurality of second openings O2. The first slope angle a is 30°-70°, for example, 35°, 40°, 45°, 50°, 55°, 60°, 65°, etc., and the second slope angle b is 30°-70°, for example, 35°, 40°, 45°, 50°, 55°, 60°, 65°, or 70°, etc. The second pixel defining layer PDL2 is made of an organic material and can be formed by coating or other methods during preparation. The organic material has a certain fluidity, which facilitates the formation of the aforementioned slope angles.

[0078] For example, in some embodiments, because the first slope angle a and the second slope angle b of the second pixel defining layer PDL2 located above are more gradual, when the second electrode layer E3 is formed thereon, it is difficult for the second electrode layer E3 to be disconnected at the first slope angle a and the second slope angle b. In other words, it is difficult for the second electrode layer E3 to be disconnected at the plurality of first openings O1 and the plurality of second openings O2. As a result, a continuous second electrode layer E3 is formed, such as a second electrode layer E3 formed over the entire surface. The continuously arranged second electrode layer E3 has a lower resistance and can provide a more balanced electrode voltage to each sub-pixel SP, thereby improving the display uniformity of the display substrate.

[0079] For example, in some embodiments, as shown in FIG2 , the display substrate may further include a passivation layer PVX disposed between the protective insulating layer PLN and the plurality of first electrodes E1, the passivation layer PVX including a plurality of second vias PVX0 that respectively expose the plurality of first vias PLN1, and the plurality of first electrodes E1 are electrically connected to the output terminals T of the plurality of pixel driving circuits D through the plurality of second vias PVX0 and the plurality of first vias PLN1. For example, the passivation layer PVX includes a plurality of third openings O3 that are respectively connected to the plurality of second openings O2, and the orthographic projections of the plurality of third openings O3 on the base substrate 110 at least partially overlap with the orthographic projections of the plurality of second openings O2 on the base substrate 110. Thus, the passivation layer PVX also participates in forming the second partition structure P2, and the provision of the plurality of third openings O3 in the passivation layer PVX makes the height of the second partition structure P2 higher.

[0080] For example, as shown in FIG2 , the plurality of second vias PVX0 are respectively formed in the plurality of first vias PLN1. In this case, the orthographic projections of the plurality of second vias PVX0 on the base substrate 110 are respectively located within the orthographic projections of the plurality of first vias PLN1 on the base substrate 110. Thus, the plurality of first vias PLN1 and the plurality of second vias PVX0 form a nested hole form, facilitating effective connection of the plurality of first electrodes E1 with the output terminals T of the plurality of pixel driving circuits D.

[0081] For example, in some embodiments, as shown in Figure 2, the passivation layer PVX includes a first passivation layer PVX1 and a second passivation layer PVX2 arranged on the side of the first passivation layer PVX1 away from the base substrate 110, the materials of the first passivation layer PVX1 and the second passivation layer PVX2 are different, and the second passivation layer PVX2 includes a plurality of third openings O3.

[0082] For example, during the preparation process, the etching rates of the first passivation layer PVX1 and the second passivation layer PVX2 relative to the same etchant are different. For example, the etching rate of the etchant on the second passivation layer PVX2 is greater than the etching rate on the first passivation layer PVX1, thereby facilitating the formation of multiple third openings O3 in the second passivation layer PVX2.

[0083] For example, in some embodiments, the passivation layer PVX is made of an inorganic material, such as SiO, SiN, Al2O3, etc. For example, in some examples, the first passivation layer PVX1 can be made of SiO, and the second passivation layer PVX2 can be made of SiN. For example, in other embodiments, the first passivation layer PVX1 can be made of Al2O3, and the second passivation layer PVX2 can be made of SiO or SiN.

[0084] For example, the thickness of the first passivation layer PVX1 is greater than the thickness of the second passivation layer PVX2 in a direction perpendicular to the base substrate 110. Therefore, during the preparation process, the first passivation layer PVX1 can play a sufficient blocking role to accurately form the corresponding structure.

[0085] For example, in some examples, the thickness of the first passivation layer PVX1 is 100nm-200nm, such as 110nm, 130nm, 150nm, 170nm, 180nm or 190nm, etc., and the thickness of the second passivation layer PVX2 is 40nm-100nm, such as 40nm, 45nm, 50nm, 60nm, 70nm, 80nm or 90nm, etc.

[0086] For example, Figures 4A and 4B respectively show transmission electron microscope schematic diagrams of the second partition structure P2. As shown in Figure 4A, the position indicated by the box is the undercut structure, and the position indicated by the circle is the position where the light-emitting material layer E2 is disconnected. Figure 4B shows the undercut structure on the left side of Figure 4A and the position where the light-emitting material layer E2 is disconnected. As shown in Figures 4A and 4B, on the left and right sides of the second partition structure P2, the light-emitting material layer E2 is disconnected, and the second electrode layer E3 is continuous. As a result, the second partition structure P2 effectively achieves the isolation effect on the light-emitting material layer E2, but still maintains the continuous setting of the second electrode layer E3. Figure 4C shows a transmission electron microscope schematic diagram of the first partition structure P1. As shown in Figure 4C, the position indicated by the box is the undercut structure, and the position indicated by the circle is the position where the light-emitting material layer E2 is disconnected. As shown in Figure 4C, on the left and right sides of the first partition structure P1, the light-emitting material layer E2 is disconnected, and the second electrode layer E3 is continuous. Thus, the first partition structure P1 effectively realizes the partitioning effect on the light-emitting material layer E2, while still maintaining the continuous arrangement of the second electrode layer E3.

[0087] By conducting optical tests on the display substrate shown in FIG2 , it can be concluded that the degree of crosstalk is reduced for sub-pixels of different colors. For example, for a red sub-pixel, the ratio of its crosstalk light intensity to the luminous intensity of the sub-pixel (hereinafter referred to as the crosstalk rate) is reduced from 6% (corresponding to the control embodiment without the first partition structure and the second partition structure) to 1.5%; for a green sub-pixel, the ratio of its crosstalk light intensity to the luminous intensity of the sub-pixel is reduced from 8.5% (corresponding to the control embodiment without the first partition structure and the second partition structure) to 2%; for a blue sub-pixel, the ratio of its crosstalk light intensity to the luminous intensity of the sub-pixel is reduced from 8.5% (corresponding to the control embodiment without the first partition structure and the second partition structure) to 0% (basically no crosstalk light is detected). Thus, the isolation effect of the first partition structure and the second partition structure is effectively verified.

[0088] For example, in other embodiments, as shown in FIG5 , even if the passivation layer PVX is provided, the passivation layer PVX may not be used to form the second partition structure P2 , and only the pixel definition layer PDL may be used to form the second partition structure P2 . This embodiment can also achieve the above-mentioned partition effect.

[0089] For example, in some further embodiments, as shown in FIG6 , the protective insulating layer PLN includes a plurality of fourth openings O4 that are respectively connected to the plurality of second openings O2, and the orthographic projections of the plurality of fourth openings O4 on the base substrate 110 at least partially overlap with the orthographic projections of the plurality of second openings O2 on the base substrate 110. Thus, the protective insulating layer PLN participates in forming the second partition structure, thereby increasing the height of the second partition structure.

[0090] For example, as shown in FIG6 , in a direction parallel to the base substrate 110 , the plurality of fourth openings O4 are respectively expanded relative to the plurality of second openings O2 , so that the orthographic projections of the plurality of second openings O2 on the base substrate 110 are respectively located within the orthographic projections of the plurality of fourth openings O4 on the base substrate 110 .

[0091] For example, as shown in FIG6 , in a direction parallel to the base substrate 110 , the outward expansion distance L3 of the plurality of fourth openings O4 relative to the plurality of second openings O2 is 0.1 μm-0.5 μm, such as 0.2 μm, 0.3 μm, 0.4 μm or 0.5 μm, thereby forming a second undercut structure with a stepped cross-section.

[0092] Through testing, it is found that the display substrate shown in FIG. 6 can also effectively isolate the light-emitting material layer E2 while still ensuring the continuity of the second electrode layer E3 .

[0093] For example, in other embodiments, as shown in FIG7 , the first pixel defining layer PDL1 may also have a single-layer structure. In this case, the structure of the first pixel defining layer PDL1 is slightly different from that of the embodiment of FIG6 , while the other structures are substantially the same. The embodiment of FIG7 can be used in the case of white sub-pixels, that is, multiple sub-pixels SP are configured to emit white light. For example, full-color display can be achieved by using color filters on the display substrate.

[0094] Through testing, the first partition structure P1 and the second partition structure P2 in this embodiment can reduce the crosstalk rate of sub-pixels to below 2%, and no crosstalk is detected in some sub-pixels.

[0095] For example, in some further embodiments, as shown in Figure 8, based on the embodiment of Figure 7, the display substrate also includes a passivation layer PVX, the passivation layer PVX includes a first passivation layer PVX1 and a second passivation layer PVX2 arranged on the side of the first passivation layer PVX1 away from the base substrate 110, the first passivation layer PVX1 and the second passivation layer PVX2 are made of different materials, the second passivation layer PVX2 includes a plurality of third openings O3, so that the second passivation layer PVX2 participates in the formation of the second partition structure P2, and the protective insulation layer PLN does not participate in the formation of the second partition structure P2.

[0096] For example, during the preparation process, the etching rates of the first passivation layer PVX1 and the second passivation layer PVX2 relative to the same etchant are different. For example, the etching rate of the etchant on the second passivation layer PVX2 is greater than the etching rate on the first passivation layer PVX1, thereby facilitating the formation of multiple third openings O3 in the second passivation layer PVX2.

[0097] Through testing, the first partition structure P1 and the second partition structure P2 in this embodiment can reduce the crosstalk rate of sub-pixels to below 2%, and no crosstalk is detected in some sub-pixels.

[0098] For example, in some embodiments, at least one second opening O2 is provided between every two adjacent sub-pixels SP in the plurality of sub-pixels SP. For example, in the embodiments of FIG. 2 and FIG. 5 to FIG. 8 , one second opening O2 is provided between adjacent sub-pixels SP, and one second partition structure P2 is provided accordingly. In the embodiment of FIG. 9 , multiple second openings O2, for example, three second openings O2, are provided between adjacent sub-pixels SP, and three second partition structures P2 are provided between adjacent sub-pixels SP accordingly.

[0099] For example, Figure 10 shows a scanning electron microscope image of a display substrate provided in at least one embodiment of the present disclosure, which schematically illustrates the arrangement of a plurality of first openings O1 and a plurality of second openings O2. As shown in Figure 10, in this embodiment, two second openings O2 are provided between adjacent sub-pixels SP, and correspondingly, two second partition structures P2 are provided. The two second openings O2 are arranged side by side and in parallel, and each second opening O2 is provided on one side of a first opening O1. Second openings O2 located on different sides of a first opening O1 are not connected.

[0100] For example, in other embodiments, the number of the second openings O2 and the second partition structures P2 between adjacent sub-pixels SP may also be other numbers, such as four, five, etc., which is not specifically limited in the embodiments of the present disclosure.

[0101] For example, Figures 11-13 illustrate different arrangements of the plurality of first openings O1 and the plurality of second openings O2. In some embodiments, the plurality of second openings O2 are strip-shaped and spaced apart from one another. For example, the second openings O2 located on different sides of the sub-pixel SP are strip-shaped and spaced apart from one another.

[0102] For example, as shown in FIG11 , in some examples, a second opening O2 is provided between adjacent sub-pixels SP. The second opening O2 is strip-shaped, and the second openings O2 located on different sides of the first opening O1 are not connected, that is, spaced apart from each other. As shown in FIG12 , in some examples, multiple second openings O2 are provided between adjacent sub-pixels SP. The multiple second openings O2 are strip-shaped. The multiple second openings O2 located on the same side of the sub-pixel SP extend along the same straight line. Each second opening O2 is provided on one side of the first opening O1. The second openings O2 located on different sides of the first opening O1 are not connected, that is, spaced apart from each other.

[0103] For example, as shown in FIG13 , in some other examples, a second opening O2 is provided between adjacent sub-pixels SP, and the second openings O2 located on different sides of the first opening O1 are connected to form a ring-shaped opening R1 completely surrounding at least one sub-pixel SP.

[0104] For example, corresponding to the embodiment of FIG. 13 , at least some of the plurality of second openings O2 are interconnected to form a ring-shaped opening R1 completely surrounding at least one sub-pixel SP, so as to fully and effectively achieve a partitioning effect between adjacent sub-pixels SP.

[0105] For example, in other embodiments, corresponding to the embodiment of Figure 10, multiple second openings O2 may also be set between adjacent sub-pixels SP, and the multiple second openings O2 located on different sides of the sub-pixel SP are correspondingly connected to form a multi-layer annular opening surrounding at least one sub-pixel SP to further enhance the isolation effect between adjacent sub-pixels SP.

[0106] In summary, in the embodiments of the present disclosure, by adding a first partition structure and a second partition structure to the display substrate, and in some embodiments, setting the heights of the first partition structure and the second partition structure to different levels, the light-emitting material layer can be accurately isolated, thereby avoiding the continuity of the light-emitting material layers of different sub-pixels, and solving the problems of severe electrical crosstalk and low color gamut between sub-pixels; in addition, by introducing a multi-layer pixel defining layer structure, the organic material used in the second pixel defining layer located on the top layer has the advantage of a gentle slope angle, and the second electrode layer (i.e., the cathode) will not be isolated to cause cathode penetration and other phenomena, thereby avoiding the problem of increased cathode resistance.

[0107] At least one embodiment of the present disclosure further provides a method for preparing a display substrate, wherein the display substrate has a plurality of sub-pixels SP arranged in an array, and the preparation method comprises: providing a base substrate 110, forming a driving circuit layer 120 on the base substrate 110, wherein the driving circuit layer 120 comprises a plurality of pixel driving circuits D for the plurality of sub-pixels SP and a protective insulating layer PLN covering the plurality of pixel driving circuits D, wherein the protective insulating layer PLN comprises a plurality of first vias PLN1 exposing output terminals T of the plurality of pixel driving circuits D, and forming a plurality of first vias PLN1 on a side of the driving circuit layer 120 away from the base substrate 110. electrode E1, wherein the plurality of first electrodes E1 are electrically connected to the output terminals T of the plurality of pixel driving circuits D through the plurality of first via holes PLN1 respectively; and a pixel defining layer PDL is formed on at least one side of the plurality of first electrodes E1 away from the base substrate 110, wherein the pixel defining layer PDL includes a plurality of first openings O1 respectively exposing the plurality of first electrodes E1 and a plurality of second openings O2 arranged between adjacent sub-pixels SP in the plurality of sub-pixels SP, and the pixel defining layer PDL has a first partition structure P1 formed at the plurality of first openings O1 and a second partition structure P2 formed at the plurality of second openings O2.

[0108] 14 and FIG. 2 , a method for preparing the display substrate shown in FIG. 2 provided by an embodiment of the present disclosure will be described in detail.

[0109] As shown in FIG14 , a base substrate 110 is first prepared. The base substrate 110 may be a rigid substrate such as a glass substrate or a flexible substrate such as polyimide. A driving circuit layer 120 is fabricated on the base substrate 110. For example, a patterning process is used to sequentially form various structural layers of the driving circuit layer on the base substrate 110. For example, a pixel driving circuit D is first formed, thereby forming a driving backplane such as an a-Si TFT substrate, an LTPS TFT substrate, or an oxide TFT substrate.

[0110] A patterning process is used to form a protective insulating layer PLN on the pixel driving circuit D. For example, a coating process is first used to form a protective insulating layer on the pixel driving circuit D, with a thickness of, for example, 1.5 μm to 2 μm. The protective insulating layer PLN is then patterned to form a protective insulating layer PLN having a first via hole PLN1. For example, a single patterning process includes steps such as forming a photoresist, exposing, developing, and etching. For details, please refer to the relevant art.

[0111] A passivation layer PVX is formed on the protective insulating layer PLN by deposition or sputtering. The passivation layer PVX uses an inorganic material such as SiO, SiN, or Al2O3. For example, the passivation layer PVX includes multiple sublayers, such as a first passivation layer PVX1 and a second passivation layer PVX2. The first passivation layer PVX1 at the bottom layer uses SiO, and the second passivation layer PVX2 at the top layer uses SiN. The first passivation layer PVX1 has a thickness of 100nm-200nm, and the second passivation layer PVX2 has a thickness of 40nm-100nm. For example, the passivation layer PVX is patterned to form a second via hole PVX0.

[0112] A plurality of first electrodes E1 are formed on the passivation layer PVX through a patterning process. The plurality of first electrodes E1, for example, serve as anodes of the light-emitting device EM. For example, in the patterning process, a first electrode material layer is first formed on the passivation layer PVX by deposition or sputtering. For example, three metal sublayers of ITO / Ag / ITO are sequentially formed. In a direction away from the base substrate 110, the thicknesses of the ITO layer, the Ag layer, and the ITO layer can be formed to be 8 nm, 100 nm, and 8 nm, or 8 nm, 100 nm, and 12 nm, respectively. The three metal sublayers of ITO / Ag / ITO are then patterned to form the plurality of first electrodes E1. The plurality of first electrodes E1 are electrically connected to the output terminal T of the pixel drive circuit D through the second via PVX0 and the first via PLN1, respectively.

[0113] Subsequently, a pixel definition layer PLD is formed on the plurality of first electrodes E1. The pixel definition layer PLD includes a first pixel definition layer PDL1 and a second pixel definition layer PDL2. The first pixel definition layer PDL1 is made of an inorganic material, while the second pixel definition layer PDL2 is made of an organic material. For example, the first pixel definition layer PDL1 may include multiple sublayers, such as a first sub-pixel definition layer PDL11 and a second sub-pixel definition layer PDL12. The first sub-pixel definition layer PDL11 and the second sub-pixel definition layer PDL12 may be made of two materials with relatively high etching selectivity, such as Al2O3 and SiN / SiO, or SiO and SiCN, or TiO, Nb2O5, etc., although this is not specifically limited in the embodiments of the present disclosure. For example, in one example, the first sub-pixel defining layer PDL11 uses SiN, and the second sub-pixel defining layer PDL12 uses SiO. The first sub-pixel defining layer PDL11 and the second sub-pixel defining layer PDL12 can be formed on multiple first electrodes E1 through a composition process. The formation thickness of the first sub-pixel defining layer PDL11 is, for example, 25nm-50nm, and the formation thickness of the second sub-pixel defining layer PDL12 is, for example, 20nm-25nm.

[0114] For example, the second pixel defining layer PDL2 is made of a resin material such as polyimide and has a thickness of 0.8 μm-1.5 μm. The second pixel defining layer PDL2 is then patterned through a composition process to form a structure as shown in FIG. 14 .

[0115] Subsequently, the first pixel defining layer PDL1 is etched using the second pixel defining layer PDL2 as a mask, thereby forming multiple first openings O1 corresponding to multiple sub-pixels and multiple second openings O2 between adjacent sub-pixels, and forming a first partition structure P1 at the multiple first openings O1, and a second partition structure P2 at the multiple second openings O2, as shown in Figure 2.

[0116] For example, during the etching process of the first pixel defining layer PDL1, for the first partition structure P1, the film layers etched are the first sub-pixel defining layer PDL11 and the second sub-pixel defining layer PDL12, and the etching stop layer is a plurality of first electrodes E1. By adjusting the etchant to increase the etching selectivity of the etchant to the first sub-pixel defining layer PDL11 and the second sub-pixel defining layer PDL12, the first sub-pixel defining layer PDL11 at the bottom is etched more, and the second sub-pixel defining layer PDL12 at the top is etched less, thereby forming a first undercut structure of the first partition structure P1. For the second partition structure P2, the film layers etched at the second opening O2 are the first sub-pixel defining layer PDL11 and the second sub-pixel defining layer PDL12, and the second passivation layer PVX2 included in the passivation layer PVX. The first passivation layer PVX1 is, for example, an etching stop layer. The etching solution has a relatively high etching selectivity to the first passivation layer PVX1 and the second passivation layer PVX2, thereby forming the second partition structure P2 as shown in FIG.

[0117] Afterwards, a light-emitting material layer E2 is formed on the pixel definition layer PDL by inkjet printing or the like, and a second electrode layer E3 is formed by deposition or sputtering or the like. The prepared substrate is then packaged to complete the preparation of the entire display substrate.

[0118] For the display substrate shown in FIG6 , the preparation process thereof may include the following steps.

[0119] As shown in FIG15 , a base substrate 110 is first prepared. The base substrate 110 may be a rigid substrate such as a glass substrate or a flexible substrate such as polyimide. A driving circuit layer is fabricated on the base substrate 110. For example, a patterning process is used to sequentially form various structural layers of the driving circuit layer on the base substrate 110. For example, a pixel driving circuit D is first formed, thereby forming a driving backplane such as an a-Si TFT substrate, an LTPS TFT substrate, or an oxide TFT substrate.

[0120] A patterning process is used to form a protective insulating layer PLN on the pixel driving circuit D. For example, a coating process is first used to form a protective insulating layer on the pixel driving circuit D, with a thickness of, for example, 1.5 μm to 2 μm. The protective insulating layer PLN is then patterned to form a protective insulating layer PLN having a first via hole PLN1. For example, a single patterning process includes steps such as forming a photoresist, exposing, developing, and etching. For details, please refer to the relevant art.

[0121] A plurality of first electrodes E1 are formed on the protective insulating layer PLN through a patterning process. The plurality of first electrodes E1, for example, serve as anodes of the light-emitting device EM. For example, in the patterning process, a first electrode material layer is first formed on the protective insulating layer PLN by deposition or sputtering. For example, three metal sub-layers of ITO / Ag / ITO are sequentially formed. In a direction away from the base substrate 110, the thicknesses of the ITO layer, the Ag layer, and the ITO layer can be formed to be 8 nm, 100 nm, and 8 nm, or 8 nm, 100 nm, and 12 nm, respectively. The three metal sub-layers of ITO / Ag / ITO are then patterned to form the plurality of first electrodes E1.

[0122] Subsequently, a pixel definition layer PLD is formed on the plurality of first electrodes E1. The pixel definition layer PLD includes a first pixel definition layer PDL1 and a second pixel definition layer PDL2. The first pixel definition layer PDL1 is made of an inorganic material, while the second pixel definition layer PDL2 is made of an organic material. For example, the first pixel definition layer PDL1 may include multiple sublayers, such as a first sub-pixel definition layer PDL11 and a second sub-pixel definition layer PDL12. The first sub-pixel definition layer PDL11 and the second sub-pixel definition layer PDL12 may be made of two materials with relatively high etching selectivity, such as Al2O3 and SiN / SiO, or SiO and SiCN, or TiO, Nb2O5, etc., although this is not specifically limited in the embodiments of the present disclosure. For example, in one example, the first sub-pixel defining layer PDL11 uses SiN, and the second sub-pixel defining layer PDL12 uses SiO. The first sub-pixel defining layer PDL11 and the second sub-pixel defining layer PDL12 can be formed on multiple first electrodes E1 through a composition process. The formation thickness of the first sub-pixel defining layer PDL11 is, for example, 25nm-50nm, and the formation thickness of the second sub-pixel defining layer PDL12 is, for example, 20nm-25nm.

[0123] For example, the second pixel defining layer PDL2 is made of a resin material such as polyimide and has a thickness of 0.8 μm-1.5 μm. The second pixel defining layer PDL2 is then patterned through a composition process to form a structure as shown in FIG. 15 .

[0124] The first pixel defining layer PDL1 is then etched using the second pixel defining layer PDL2 as a mask, thereby forming multiple first openings O1 corresponding to multiple sub-pixels and multiple second openings O2 between adjacent sub-pixels, and forming a first partition structure P1 at the multiple first openings O1 and a second partition structure P2 at the multiple second openings O2.

[0125] For example, during the etching process of the first pixel defining layer PDL1, for the first partition structure P1, the film layers etched are the first sub-pixel defining layer PDL11 and the second sub-pixel defining layer PDL12, and the etching stop layer is a plurality of first electrodes E1. By adjusting the etchant to improve the etching selectivity of the etchant to the first sub-pixel defining layer PDL11 and the second sub-pixel defining layer PDL12, the first sub-pixel defining layer PDL11 at the bottom is etched more, and the second sub-pixel defining layer PDL12 at the top is etched less, thereby forming a first undercut structure of the first partition structure P1. For the second partition structure P2, the second film layer etched at the second opening O2 is the first sub-pixel defining layer PDL11, the second sub-pixel defining layer PDL12, and a portion of the protective insulating layer PLN, for example, with an etching depth of 40nm-100nm, thereby forming the second partition structure P2, as shown in FIG6.

[0126] Afterwards, a light-emitting material layer is formed on the pixel definition layer PDL by inkjet printing or other methods, and a second electrode layer E3 is formed by deposition or sputtering or other methods. Then, the prepared substrate is packaged to complete the preparation of the entire display substrate.

[0127] For example, the manufacturing process of the embodiment of FIG. 7 differs from that of FIG. 6 in that the first pixel defining layer PDL1 is replaced with a single layer of inorganic material. As shown in FIG. 16 , during the manufacturing process, the first pixel defining layer PDL1 comprises only a single layer. When subsequently forming the partition structure, the first pixel defining layer PDL1 is etched using the second pixel defining layer PDL2 as a mask, thereby forming a plurality of first openings O1 corresponding to the plurality of sub-pixels and a plurality of second openings O2 between adjacent sub-pixels. Furthermore, a first partition structure P1 is formed at the plurality of first openings O1, and a second partition structure P2 is formed at the plurality of second openings O2.

[0128] For example, during the etching process of the first pixel defining layer PDL1, for the first partition structure P1, the film layer etched is the first pixel defining layer PDL1, and the etch stop layer is the plurality of first electrodes E1. For the second partition structure P2, the film layers etched at the second opening O2 are the first pixel defining layer PDL1 and the protective insulating layer PLN, thereby forming the second partition structure P2, as shown in FIG7 .

[0129] For example, in the embodiment of FIG8 , the preparation process thereof is compared with the embodiment of FIG7 , in which a passivation layer PVX is fabricated. The passivation layer PVX includes a first passivation layer PVX1 and a second passivation layer PVX2. The first passivation layer PVX1 and the second passivation layer PVX2 are made of two materials having different etching rates relative to the same etchant. For example, the first passivation layer PVX1 at the bottom layer is made of SiO, and the second passivation layer PVX2 at the top layer is made of SiN. Subsequently, in an etching process, the first pixel defining layer PDL1 is etched using the second pixel defining layer PDL2 as a mask, thereby forming a plurality of first openings O1 corresponding to the plurality of sub-pixels and a plurality of second openings O2 between adjacent sub-pixels, and forming a first partition structure P1 at the plurality of first openings O1, and a second partition structure P2 at the plurality of second openings O2.

[0130] For example, during the etching process of the first pixel defining layer PDL1, for the first partition structure P1, the film layer etched is the first pixel defining layer PDL1, and the etch stop layer is the plurality of first electrodes E1. For the second partition structure P2, the film layers etched at the second opening O2 are the first pixel defining layer PDL1 and the second passivation layer PVX2, and the etch stop layer is the first passivation layer PVX1, thereby forming the second partition structure P2, as shown in Figure 8.

[0131] For example, for other structures on the display substrate, their preparation processes may refer to related technologies, and the embodiments of the present disclosure do not specifically limit this.

[0132] There are a few points to note:

[0133] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0134] (2) For the sake of clarity, the thickness of layers or regions in the drawings used to describe the embodiments of the present disclosure are exaggerated or reduced, i.e., these drawings are not drawn to scale. It is understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element or intervening elements may be present.

[0135] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0136] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A display substrate having a plurality of sub-pixels arranged in an array, comprising: substrate, a driving circuit layer, disposed on the base substrate, comprising a plurality of pixel driving circuits for the plurality of sub-pixels and a protective insulating layer covering the plurality of pixel driving circuits, wherein the protective insulating layer comprises a plurality of first vias exposing output terminals of the plurality of pixel driving circuits; a plurality of first electrodes, disposed on a side of the driving circuit layer away from the base substrate, and electrically connected to output terminals of the plurality of pixel driving circuits through the plurality of first via holes; and a pixel defining layer, disposed at least on a side of the plurality of first electrodes away from the base substrate, comprising a plurality of first openings respectively exposing the plurality of first electrodes and a plurality of second openings disposed between adjacent sub-pixels in the plurality of sub-pixels; The pixel definition layer has a first partition structure at the plurality of first openings and a second partition structure at the plurality of second openings.

2. The display substrate according to claim 1, wherein In a direction perpendicular to the base substrate, a height of the first partition structure is different from a height of the second partition structure.

3. The display substrate according to claim 2, wherein: The height of the first partition structure is smaller than the height of the second partition structure.

4. The display substrate according to any one of claims 1 to 3, wherein: The pixel defining layer includes a first pixel defining layer and a second pixel defining layer disposed on a side of the first pixel defining layer away from the base substrate. The first pixel defining layer includes an inorganic material, and the second pixel defining layer includes an organic material.

5. The display substrate according to claim 4, wherein: The organic material includes polyimide or resin.

6. The display substrate according to claim 4, wherein: The first pixel defining layer includes a first sub-pixel defining layer and a second sub-pixel defining layer disposed on a side of the first sub-pixel defining layer away from the base substrate. The first sub-pixel defining layer and the second sub-pixel defining layer are made of different materials. In a direction parallel to the base substrate, and at the plurality of first openings, The first sub-pixel defining layer is retracted relative to the second sub-pixel defining layer, so that the first partition structure includes a first undercut structure.

7. The display substrate according to claim 6, wherein: At the plurality of first openings, the first sub-pixel defining layer is retracted relative to the second sub-pixel defining layer by a distance of 0.05 μm to 0.2 μm.

8. The display substrate according to claim 4, wherein: The first pixel defining layer includes a first sub-pixel defining layer and a second sub-pixel defining layer disposed on a side of the first sub-pixel defining layer away from the base substrate. The first sub-pixel defining layer and the second sub-pixel defining layer are made of different materials. In a direction parallel to the base substrate and at the plurality of second openings, the first sub-pixel defining layer is retracted relative to the second sub-pixel defining layer, so that the second partition structure includes a second undercut structure.

9. The display substrate according to claim 8, wherein: At the plurality of second openings, the first sub-pixel defining layer is retracted relative to the second sub-pixel defining layer by a distance of 0.05 μm to 0.2 μm.

10. The display substrate according to any one of claims 6 to 9, wherein: Materials of the first sub-pixel defining layer and the second sub-pixel defining layer are respectively two of Al2O3, SiN, SiO, SiCN, TiO and Nb2O5.

11. The display substrate according to any one of claims 6 to 10, wherein: In a direction perpendicular to the base substrate, a thickness of the first sub-pixel defining layer is greater than a thickness of the second sub-pixel defining layer.

12. The display substrate according to claim 11, wherein: The thickness of the first sub-pixel defining layer is 25 nm-50 nm, and the thickness of the second sub-pixel defining layer is 20 nm-25 nm.

13. The display substrate according to any one of claims 4 to 12, wherein: In a direction perpendicular to the base substrate, the thickness of the second pixel defining layer is 0.8 μm-1.5 μm.

14. The display substrate according to any one of claims 4 to 13, wherein: The second pixel defining layer has a first slope angle at the plurality of first openings and a second slope angle at the plurality of second openings. The first slope angle is 30°-70°, and the second slope angle is 30°-70°.

15. The display substrate according to any one of claims 1 to 14, further comprising a passivation layer disposed between the protective insulating layer and the plurality of first electrodes, the passivation layer comprising a plurality of second via holes respectively exposing the plurality of first via holes, the plurality of first electrodes being electrically connected to output terminals of the plurality of pixel driving circuits through the plurality of second via holes and the plurality of first via holes, respectively; The passivation layer includes a plurality of third openings respectively connected to the plurality of second openings, and orthographic projections of the plurality of third openings on the base substrate at least partially overlap with orthographic projections of the plurality of second openings on the base substrate.

16. The display substrate according to claim 15, wherein: The orthographic projections of the plurality of second via holes on the base substrate are respectively located within the orthographic projections of the plurality of first via holes on the base substrate.

17. The display substrate according to claim 15, wherein: The passivation layer includes a first passivation layer and a second passivation layer arranged on a side of the first passivation layer away from the substrate. The first passivation layer and the second passivation layer are made of different materials, and the second passivation layer includes the plurality of third openings.

18. The display substrate according to claim 17, wherein: In a direction perpendicular to the base substrate, a thickness of the first passivation layer is greater than a thickness of the second passivation layer.

19. The display substrate according to claim 18, wherein: The thickness of the first passivation layer is 100 nm-200 nm, and the thickness of the second passivation layer is 40 nm-100 nm.

20. The display substrate according to any one of claims 1 to 13, wherein: The protective insulating layer includes a plurality of fourth openings respectively connected to the plurality of second openings, and orthographic projections of the plurality of fourth openings on the base substrate at least partially overlap with orthographic projections of the plurality of second openings on the base substrate.

21. The display substrate according to claim 20, wherein: In a direction parallel to the base substrate, the plurality of fourth openings expand outward relative to the plurality of second openings, so that the orthographic projections of the plurality of second openings on the base substrate are respectively located within the orthographic projections of the plurality of fourth openings on the base substrate.

22. The display substrate according to claim 21, wherein In a direction parallel to the base substrate, the fourth openings have an outward extension distance of 0.1 μm-0.5 μm relative to the second openings.

23. The display substrate according to any one of claims 1 to 22, wherein: There is at least one second opening between every two adjacent sub-pixels in the plurality of sub-pixels.

24. The display substrate according to any one of claims 1 to 23, wherein: At least some of the plurality of second openings are connected to each other to form a ring-shaped opening that completely surrounds at least one sub-pixel among the plurality of sub-pixels.

25. The display substrate according to any one of claims 1 to 23, wherein: The plurality of second openings are respectively in a strip shape and spaced apart from each other.

26. The display substrate according to any one of claims 1 to 25, further comprising: a light-emitting material layer, disposed on a side of the pixel defining layer away from the base substrate, and The second electrode layer is arranged on a side of the light emitting material layer away from the base substrate. At least part of the light-emitting material layer is disconnected by at least one of the first partition structure and the second partition structure, and the second electrode layer is continuous at at least one of the first partition structure and the second partition structure.

27. The display substrate according to claim 26, wherein: The light emitting material layer includes at least one charge generation layer, and the at least one charge generation layer is interrupted by at least one of the first partition structure and the second partition structure.

28. A method for preparing a display substrate, the display substrate having a plurality of sub-pixels arranged in an array, the method comprising: providing a substrate substrate, forming a driving circuit layer on the base substrate, wherein the driving circuit layer includes a plurality of pixel driving circuits for the plurality of sub-pixels and a protective insulating layer covering the plurality of pixel driving circuits, wherein the protective insulating layer includes a plurality of first vias exposing output terminals of the plurality of pixel driving circuits; forming a plurality of first electrodes on a side of the driving circuit layer away from the base substrate, wherein the plurality of first electrodes are electrically connected to output terminals of the plurality of pixel driving circuits through the plurality of first via holes; and forming a pixel defining layer at least on one side of the plurality of first electrodes away from the base substrate, wherein the pixel defining layer comprises a plurality of first openings respectively exposing the plurality of first electrodes and a plurality of second openings disposed between adjacent sub-pixels among the plurality of sub-pixels; The pixel definition layer has a first partition structure formed at the plurality of first openings and a second partition structure formed at the plurality of second openings.

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