Display panel and display apparatus

Abstract

The present disclosure relates to the technical field of display. Provided are a display panel and a display apparatus. The display panel comprises a pixel driving circuit, which comprises a driving transistor, a first transistor and a second transistor, wherein a first electrode of the second transistor is connected to a gate electrode of the driving transistor, a second electrode of the second transistor is connected to a second electrode of the driving transistor, a first electrode of the first transistor is connected to a first initial signal line, and a second electrode of the first transistor is connected to the second electrode of the driving transistor. The display panel further comprises: a base substrate, a first gate line, a first conductive portion, a first bridging portion and a ninth bridging portion, wherein an orthographic projection of the first gate line on the base substrate extends in a first direction, and part of the structure of the first gate line is used for forming a gate electrode of the second transistor; the first conductive portion is used for forming the gate electrode of the driving transistor; the first bridging portion is connected to the second electrode of the first transistor, the second electrode of the driving transistor and the second electrode of the second transistor by means of via holes; the ninth bridging portion is connected to the first conductive portion and the first electrode of the second transistor by means of through holes; and the area of overlap between an orthographic projection of the first bridging portion on the base substrate and the orthographic projection of the first gate line on the base substrate is a first overlap area, and the area of overlap between an orthographic projection of the ninth bridging portion on the base substrate and the orthographic projection of the first gate line on the base substrate is a second overlap area, the first overlap area being less than or equal to the second overlap area. The display panel can improve a display effect.

Description

Display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In related technologies, the display panel includes a first bridge portion connecting the second electrode of the driving transistor and the second electrode of the second transistor. There is a large parasitic capacitance between the first bridge portion and the gate line of the second transistor, which will amplify the impact of the change in the characteristics of the second transistor on the display effect.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0004] Summary of the Invention

[0005] According to one aspect of the present disclosure, a display panel is provided, the display panel including a pixel driving circuit, the pixel driving circuit including a driving transistor, a first transistor, and a second transistor, wherein a first electrode of the second transistor is connected to a gate of the driving transistor, a second electrode of the second transistor is connected to a second electrode of the driving transistor, a first electrode of the first transistor is connected to a first initial signal line, and a second electrode of the first transistor is connected to the second electrode of the driving transistor;

[0006] The display panel further includes:

[0007] substrate;

[0008] a first gate line, an orthographic projection of the first gate line on the substrate extending along a first direction, and a portion of the first gate line being used to form a gate of the second transistor;

[0009] a first conductive portion, wherein the first conductive portion is used to form a gate of the driving transistor;

[0010] a first bridge portion, the first bridge portion being connected to the second electrode of the first transistor, the second electrode of the driving transistor, and the second electrode of the second transistor through via holes;

[0011] a ninth bridge portion, the ninth bridge portion being connected to the first conductive portion and the first electrode of the second transistor through a through hole;

[0012] An overlapping area of ​​an orthographic projection of the first bridging portion on the base substrate and an orthographic projection of the first gate line on the base substrate is a first overlapping area, an overlapping area of ​​an orthographic projection of the ninth bridging portion on the base substrate and an orthographic projection of the first gate line on the base substrate is a second overlapping area, and the first overlapping area is less than or equal to the second overlapping area.

[0013] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0014] a first reset signal line, wherein an orthographic projection of the first reset signal line on the substrate extends along the first direction, and a portion of the first reset signal line is used to form a gate of the first transistor;

[0015] In the same pixel driving circuit, an orthographic projection of the first conductive portion on the base substrate is located between an orthographic projection of the first gate line on the base substrate and an orthographic projection of the first reset signal line on the base substrate;

[0016] An orthographic projection of the first bridge portion on the base substrate is located between an orthographic projection of the first gate line on the base substrate and an orthographic projection of the first reset signal line on the base substrate.

[0017] In an exemplary embodiment of the present disclosure, the display panel further includes a light-emitting unit, and the pixel driving circuit is used to drive the light-emitting unit to emit light;

[0018] The pixel driving circuit further includes: a sixth transistor and a seventh transistor, wherein a first electrode of the sixth transistor is connected to the second electrode of the driving transistor, a second electrode of the sixth transistor is connected to the first electrode of the light-emitting unit, a first electrode of the seventh transistor is connected to the second initial signal line, and a second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit;

[0019] The display panel further includes:

[0020] a second reset signal line, an orthographic projection of the second reset signal line on the substrate extending along the first direction, and a portion of the second reset signal line forming a gate of the seventh transistor;

[0021] an enable signal line, an orthographic projection of the enable signal line on the substrate extending along the first direction, and a partial structure of the enable signal line being used to form a gate of the sixth transistor;

[0022] In the same pixel driving circuit, an orthographic projection of the second reset signal line on the base substrate and an orthographic projection of the enable signal line on the base substrate are located between an orthographic projection of the first conductive portion on the base substrate and an orthographic projection of the first reset signal line on the base substrate;

[0023] The orthographic projection of the first bridge portion on the base substrate overlaps with the orthographic projection of the second reset signal line on the base substrate and the orthographic projection of the enable signal line on the base substrate.

[0024] In an exemplary embodiment of the present disclosure, the second reset signal line includes a first extending portion and a second extending portion, wherein the width of an orthographic projection of the first extending portion on the base substrate is smaller than the width of an orthographic projection of the second extending portion on the base substrate;

[0025] The orthographic projection of the first bridging portion on the base substrate extends along a second direction and intersects with the orthographic projection of the first extending portion on the base substrate, and the second direction intersects with the first direction.

[0026] In an exemplary embodiment of the present disclosure, an orthographic projection of the second reset signal line on the base substrate is located between an orthographic projection of the first reset signal line on the base substrate and an orthographic projection of the enable signal line on the base substrate.

[0027] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes: a fifth transistor, a first electrode of the fifth transistor being connected to a power line, and a second electrode of the fifth transistor being connected to a first electrode of the driving transistor;

[0028] The display panel further includes:

[0029] a first active layer located on one side of the base substrate, the first active layer comprising a first active portion, a third active portion, and a fifth active portion, the first active portion being used to form a channel region of the first transistor, the third active portion being used to form a channel region of the driving transistor, and the fifth active portion being used to form a channel region of the fifth transistor;

[0030] In the same pixel driving circuit, in the first direction, the orthographic projection of the third active portion on the base substrate is located between the orthographic projection of the first active portion on the base substrate and the orthographic projection of the fifth active portion on the base substrate.

[0031] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes: a fifth transistor, a first electrode of the fifth transistor being connected to a power line, and a second electrode of the fifth transistor being connected to a first electrode of the driving transistor;

[0032] The display panel further includes:

[0033] a first active layer located on one side of the base substrate, the first active layer comprising a third active portion and a fifth active portion, the third active portion being used to form a channel region of the driving transistor, and the fifth active portion being used to form a channel region of the fifth transistor;

[0034] a second active layer, located on a side of the first active layer facing away from the base substrate, the second active layer comprising a second active portion, and the second active portion is used to form a channel region of the second transistor;

[0035] In the same pixel driving circuit, in the first direction, the orthographic projection of the third active portion on the base substrate is located between the orthographic projection of the second active portion on the base substrate and the orthographic projection of the fifth active portion on the base substrate.

[0036] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0037] a fourth conductive layer, located on one side of the base substrate, the fourth conductive layer comprising a ninth bridge portion, the ninth bridge portion being connected to the first conductive portion and the first electrode of the second transistor through a through hole;

[0038] A fifth conductive layer is located on a side of the fourth conductive layer away from the base substrate, and at least a portion of the structure of the first bridging portion is located on the fifth conductive layer.

[0039] In an exemplary embodiment of the present disclosure, the first bridging portion includes:

[0040] a first sub-bridge portion, located in the fifth conductive layer;

[0041] a second sub-bridging portion, located in the fourth conductive layer;

[0042] a third sub-bridging portion, located in the fourth conductive layer;

[0043] Among them, the second sub-bridge portion is connected to the second electrode of the second transistor and the second electrode of the driving transistor through vias, the third sub-bridge portion is connected to the second electrode of the first transistor through a via, and the first sub-bridge portion is connected to the second sub-bridge portion and the third sub-bridge portion through vias.

[0044] In an exemplary embodiment of the present disclosure, the fifth conductive layer further includes:

[0045] a first fan-out line, wherein an orthographic projection of the first fan-out line on the substrate extends along the first direction;

[0046] The display panel further includes:

[0047] a sixth conductive layer, located on a side of the fifth conductive layer facing away from the base substrate, the sixth conductive layer comprising a second fan-out line, an orthographic projection of the second fan-out line on the base substrate extending along a second direction, and the second direction intersecting the first direction;

[0048] A data line is used to provide a data signal to the pixel driving circuit, the data line is connected to the first fan-out line, and the second fan-out line is connected to the first fan-out line.

[0049] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0050] a fourth conductive layer, located on one side of the base substrate, the fourth conductive layer comprising a ninth bridge portion, the ninth bridge portion being connected to the first conductive portion and the first electrode of the second transistor through a through hole;

[0051] The first bridge portion is located in the fourth conductive layer, and the first bridge portion is connected to the second electrode of the second transistor, the second electrode of the driving transistor, and the second electrode of the first transistor through via holes.

[0052] In an exemplary embodiment of the present disclosure, the fourth conductive layer further includes:

[0053] a first fan-out line, wherein an orthographic projection of the first fan-out line on the substrate extends along the first direction;

[0054] The display panel further includes:

[0055] a fifth conductive layer, located on a side of the fourth conductive layer facing away from the base substrate, the fifth conductive layer comprising a second fan-out line, an orthographic projection of the second fan-out line on the base substrate extending along a second direction, and the second direction intersecting the first direction;

[0056] A data line is used to provide a data signal to the pixel driving circuit, the data line is connected to the first fan-out line, and the second fan-out line is connected to the first fan-out line.

[0057] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0058] a second active layer located on one side of the base substrate, the second active layer comprising a second active portion, the second active portion being used to form a channel region of the second transistor;

[0059] The first gate line includes any one of a first sub-gate line and a second sub-gate line, the first sub-gate line is located on the side of the second active portion facing away from the substrate, and a partial structure of the first sub-gate line is used to form the top gate of the second transistor, and the second sub-gate line is located between the second active portion and the substrate, and a partial structure of the second sub-gate line is used to form the bottom gate of the second transistor.

[0060] In an exemplary embodiment of the present disclosure, the first reset signal line and the first initial signal line are located in different conductive layers. In the same pixel driving circuit, the orthographic projection of the first reset signal line on the base substrate and the orthographic projection of the first initial signal line on the base substrate at least partially overlap.

[0061] In an exemplary embodiment of the present disclosure, the display panel further includes a light-emitting unit, and the pixel driving circuit is used to drive the light-emitting unit to emit light;

[0062] The pixel driving circuit further includes: a sixth transistor, a seventh transistor, and an eighth transistor, wherein a first electrode of the sixth transistor is connected to the second electrode of the driving transistor, a second electrode of the sixth transistor is connected to the first electrode of the light-emitting unit, a first electrode of the seventh transistor is connected to the second initial signal line, a second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit, a first electrode of the eighth transistor is connected to the third initial signal line, and a second electrode of the eighth transistor is connected to the first electrode of the driving transistor;

[0063] The display panel further includes:

[0064] a second reset signal line, an orthographic projection of the second reset signal line on the substrate extending along the first direction, and a portion of the second reset signal line forming a gate of the eighth transistor;

[0065] an enable signal line, an orthographic projection of the enable signal line on the substrate extending along the first direction, and a partial structure of the enable signal line being used to form a gate of the sixth transistor;

[0066] Wherein, the third initial signal line and the second reset signal line are located in different conductive layers, and the second initial signal line and the enable signal line are located in different conductive layers;

[0067] In the same pixel driving circuit, the orthographic projection of the third initial signal line on the base substrate and the orthographic projection of the second reset signal line on the base substrate at least partially overlap, and the orthographic projection of the second initial signal line on the base substrate and the orthographic projection of the enable signal line on the base substrate at least partially overlap.

[0068] In an exemplary embodiment of the present disclosure, the display panel further includes a light-emitting unit, and the pixel driving circuit is used to drive the light-emitting unit to emit light;

[0069] The pixel driving circuit further includes: a sixth transistor, a seventh transistor, and an eighth transistor, wherein a first electrode of the sixth transistor is connected to the second electrode of the driving transistor, a second electrode of the sixth transistor is connected to the first electrode of the light-emitting unit, a first electrode of the seventh transistor is connected to the second initial signal line, a second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit, a first electrode of the eighth transistor is connected to the third initial signal line, and a second electrode of the eighth transistor is connected to the first electrode of the driving transistor;

[0070] The display panel further includes:

[0071] a second reset signal line, an orthographic projection of the second reset signal line on the substrate extending along the first direction, and a portion of the second reset signal line forming a gate of the eighth transistor;

[0072] an enable signal line, an orthographic projection of the enable signal line on the substrate extending along the first direction, and a partial structure of the enable signal line being used to form a gate of the sixth transistor;

[0073] Wherein, the second initial signal line and the first reset signal line are located in different conductive layers, and the third initial signal line and the second reset signal line are located in different conductive layers;

[0074] In the same pixel driving circuit, the orthographic projection of the first reset signal line on the substrate is located between the orthographic projection of the first initial signal line on the substrate and the orthographic projection of the first conductive portion on the substrate, the orthographic projection of the second initial signal line on the substrate and the orthographic projection of the first reset signal line on the substrate at least partially overlap, and the orthographic projection of the third initial signal line on the substrate and the orthographic projection of the second reset signal line on the substrate at least partially overlap.

[0075] In an exemplary embodiment of the present disclosure, the display panel further includes a light-emitting unit, the pixel driving circuit is used to drive the light-emitting unit to emit light, and the pixel driving circuit further includes:

[0076] a fourth transistor, a first electrode of which is connected to the data line, and a second electrode of which is connected to the first electrode of the driving transistor;

[0077] a fifth transistor, a first electrode connected to the first power line, and a second electrode connected to the first electrode of the driving transistor;

[0078] a sixth transistor, a first electrode of which is connected to the second electrode of the driving transistor, and a second electrode of which is connected to the first electrode of the light-emitting unit;

[0079] a seventh transistor, a first electrode connected to the second initial signal line, and a second electrode connected to the first electrode of the light-emitting unit;

[0080] an eighth transistor, a first electrode of which is connected to the third initial signal line, and a second electrode of which is connected to the first electrode of the driving transistor;

[0081] a capacitor, a first electrode of which is connected to the gate of the driving transistor, and a second electrode of which is connected to the first power line;

[0082] The first transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are P-type transistors, and the second transistor is an N-type transistor.

[0083] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes a P-type transistor and an N-type transistor, and the display panel further includes:

[0084] a first active layer, located on one side of the base substrate, wherein a portion of the first active layer is used to form a channel region of a P-type transistor in the pixel driving circuit;

[0085] a first conductive layer, located on a side of the first active layer facing away from the base substrate, wherein a portion of the first conductive layer is used to form a gate of a P-type transistor in the pixel driving circuit;

[0086] a second conductive layer, located on a side of the first conductive layer away from the base substrate, wherein a portion of the second conductive layer is used to form a bottom gate of an N-type transistor in the pixel driving circuit;

[0087] a second active layer, located on a side of the second conductive layer facing away from the base substrate, wherein a portion of the second active layer is used to form a channel region of an N-type transistor in the pixel driving circuit;

[0088] a third conductive layer, located on a side of the second active layer facing away from the substrate, wherein a portion of the third conductive layer is used to form a top gate of an N-type transistor in the pixel driving circuit;

[0089] The fourth conductive layer is located on a side of the third conductive layer away from the base substrate, and a portion of the structure of the fourth conductive layer is used to form a bridge portion connecting different transistors.

[0090] According to one aspect of the present disclosure, a display device is provided, wherein the display device includes the above-mentioned display panel.

[0091] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0092] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0093] FIG1 is a schematic structural diagram of an exemplary embodiment of a pixel driving circuit disclosed herein;

[0094] FIG2 is a timing diagram of some nodes in an exemplary embodiment of the pixel driving circuit shown in FIG1 ;

[0095] FIG3 is a structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0096] FIG4 is a structural diagram of the shielding layer in FIG3 ;

[0097] FIG5 is a structural diagram of the first active layer in FIG3;

[0098] FIG6 is a structural diagram of the first conductive layer in FIG3 ;

[0099] FIG7 is a structural diagram of the second conductive layer in FIG3 ;

[0100] FIG8 is a structural diagram of the second active layer in FIG3;

[0101] FIG9 is a structural diagram of the third conductive layer in FIG3 ;

[0102] FIG10 is a structural diagram of the fourth conductive layer in FIG3 ;

[0103] FIG11 is a structural diagram of the fifth conductive layer in FIG3 ;

[0104] FIG12 is a structural diagram of the sixth conductive layer in FIG3;

[0105] FIG13 is a structural diagram of the shielding layer and the first active layer in FIG3;

[0106] FIG14 is a structural layout diagram of the shielding layer, the first active layer, and the first conductive layer in FIG3;

[0107] FIG15 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, and the second conductive layer in FIG3;

[0108] FIG16 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer in FIG3 ;

[0109] FIG17 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in FIG3 ;

[0110] FIG18 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in FIG3 ;

[0111] FIG19 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer in FIG3 ;

[0112] FIG20 is a partial cross-sectional view of the display panel shown in FIG3 taken along dotted line AA;

[0113] FIG21 is a structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0114] FIG22 is a structural diagram of the shielding layer in FIG21;

[0115] FIG23 is a structural layout diagram of the first active layer in FIG21;

[0116] FIG24 is a structural diagram of the first conductive layer in FIG21;

[0117] FIG25 is a structural diagram of the second conductive layer in FIG21;

[0118] FIG26 is a structural diagram of the second active layer in FIG21;

[0119] FIG27 is a structural diagram of the third conductive layer in FIG21;

[0120] FIG28 is a structural layout diagram of the fourth conductive layer in FIG21;

[0121] FIG29 is a structural layout diagram of the fifth conductive layer in FIG21;

[0122] FIG30 is a structural layout diagram of the shielding layer and the first active layer in FIG21;

[0123] FIG31 is a structural layout diagram of the shielding layer, the first active layer, and the first conductive layer in FIG21;

[0124] FIG32 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, and the second conductive layer in FIG21;

[0125] FIG33 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer in FIG21 ;

[0126] FIG34 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in FIG21 ;

[0127] FIG35 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in FIG21 ;

[0128] FIG36 is a partial cross-sectional view of the display panel shown in FIG21 taken along dotted line BB;

[0129] FIG37 is a partial structural diagram of another exemplary embodiment of a display panel disclosed herein;

[0130] FIG38 is a partial structural diagram of another exemplary embodiment of a display panel disclosed herein;

[0131] FIG39 is a partial structural diagram of another exemplary embodiment of a display panel disclosed herein;

[0132] FIG40 is a partial structural diagram of another exemplary embodiment of the display panel disclosed herein. DETAILED DESCRIPTION

[0133] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent like or similar structures, and thus their detailed description will be omitted.

[0134] The terms "a", "an", and "said" are used to indicate that there are one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.

[0135] This exemplary embodiment first provides a pixel driving circuit, as shown in Figures 1 and 2. Figure 1 is a structural diagram of an exemplary embodiment of the pixel driving circuit disclosed in the present invention, and Figure 2 is a timing diagram of some nodes in an exemplary embodiment of the pixel driving circuit shown in Figure 1.

[0136] The pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a capacitor C. A first electrode of the fourth transistor T4 is connected to the data signal terminal Da, a second electrode of the fourth transistor T4 is connected to the first electrode of the driving transistor T3, and a gate of the fourth transistor T4 is connected to the second gate driving signal terminal G2; a first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, a second electrode of the fifth transistor T5 is connected to the first electrode of the driving transistor T3, and a gate of the fifth transistor T5 is connected to the enable signal terminal EM; a gate of the driving transistor T3 is connected to the first node N1; a first electrode of the second transistor T2 is connected to the first node N1, a second electrode of the second transistor T2 is connected to the second electrode (third node N3) of the driving transistor T3, and a gate of the second transistor T2 is connected to the first gate driving signal terminal G1; a first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, and a second electrode of the sixth transistor T6 is connected to the enable signal terminal EM. The second electrode of the seventh transistor T7 is connected to the second electrode of the seventh transistor T7, the gate of the sixth transistor T6 is connected to the enable signal terminal EM, the first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and the gate of the seventh transistor T7 is connected to the second reset signal terminal Re2; the first electrode of the first transistor T1 is connected to the first initial signal terminal Vinit1, the second electrode of the first transistor T1 is connected to the second electrode of the driving transistor T3, and the gate of the first transistor T1 is connected to the first reset signal terminal Re1; the first electrode of the eighth transistor T8 is connected to the third initial signal terminal Vinit3, the second electrode of the eighth transistor T8 is connected to the first electrode of the driving transistor T3, and the gate of the eighth transistor T8 is connected to the second reset signal terminal Re2; the first electrode of the capacitor C is connected to the first node N1, and the second electrode of the capacitor C is connected to the first power supply terminal VDD. This pixel driving circuit can be used to drive a light-emitting unit OLED. The first electrode of the light-emitting unit OLED can be connected to the second electrode of the sixth transistor T6, and the second electrode of the light-emitting unit can be connected to the second power supply terminal VSS. The first electrode of the light-emitting unit can be the anode of the light-emitting unit, and the second electrode of the light-emitting unit can be the cathode of the light-emitting unit. The second transistor T2 may be an N-type transistor, for example, an N-type metal oxide transistor. The N-type transistor has a small leakage current, thereby preventing the first node N1 from leaking through the second transistor T2 during the light emitting stage.At the same time, the first transistor T1, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be P-type transistors. For example, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be P-type low-temperature polysilicon transistors. P-type transistors have high carrier mobility, which is conducive to realizing a display panel with high resolution, high response speed, high pixel density, and high aperture ratio. The first initial signal terminal, the second initial signal terminal, and the third initial signal terminal can output the same or different voltage signals according to actual conditions.

[0137] As shown in Figure 2, where G1 represents the timing of the first gate drive signal terminal G1, G2 represents the timing of the second gate drive signal terminal G2, Re2 represents the timing of the second reset signal terminal Re2, Re1 represents the timing of the first reset signal terminal Re1, and EM represents the timing of the enable signal terminal EM, a driving cycle of the pixel driving circuit may include a first reset phase t1, a second reset phase t2, a data writing phase t3, a third reset phase t4, and a light-emitting phase t5.

[0138] During the first reset phase t1, the second reset signal terminal Re2 outputs a low-level signal, the seventh transistor T7 and the eighth transistor T8 are turned on, the second initial signal terminal Vinit2 inputs a second initial signal to the first electrode of the light-emitting unit OLED, and the third initial signal terminal Vinit3 inputs a third initial signal to the first electrode of the driving transistor T3 to improve the hysteresis problem of the driving transistor T3. During the second reset phase t2, the first gate drive signal terminal G1 outputs a high-level signal, the first reset signal terminal Re1 outputs a low-level signal, the first transistor T1 and the second transistor T2 are turned on, and the first initial signal terminal Vinit1 inputs the first initial signal to the first node N1 through the first transistor T1 and the second transistor T2. During the data writing phase t3, the second gate drive signal terminal G2 outputs a low-level signal, the first gate drive signal terminal G1 outputs a high-level signal, the fourth transistor T4 and the second transistor T2 are turned on, and the data signal terminal Da writes the compensation voltage Vdata+Vth to the first node N1 through the fourth transistor T4 and the second transistor T2, where Vdata is the voltage of the data signal on the data signal terminal and Vth is the threshold voltage of the driving transistor T3. In the third reset phase t4: the second reset signal terminal RE2 outputs a low-level signal, the seventh transistor T7 and the eighth transistor T8 are turned on, the second initial signal terminal Vinit2 inputs the second initial signal to the first electrode of the light-emitting unit OLED, and the third initial signal terminal Vinit3 inputs the third initial signal to the first electrode of the driving transistor T3. In the light-emitting phase t5: the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light-emitting unit to emit light under the action of the compensation voltage Vdata + Vth stored in the capacitor C. The output current formula of the driving transistor is as follows: I = (μWCox / 2L)(Vgs-Vth) 2

[0139] Where I is the output current of the driver transistor; μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driver transistor channel, L is the length of the driver transistor channel, Vgs is the gate-source voltage difference of the driver transistor, and Vth is the threshold voltage of the driver transistor. The output current of the driver transistor in the above pixel driving circuit is I = (μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 The pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.

[0140] It should be understood that, in other exemplary embodiments, the pixel driving circuit shown in FIG. 1 may also have other driving methods. For example, other driving methods may not include the third reset phase t4.

[0141] As shown in Figures 1 and 2, there is a parasitic capacitor Cx between the third node N3 and the first gate drive signal terminal G1. After the data signal is written to the first node N1, when the first gate drive signal terminal G1 changes from a high level to a low level, the third node N3 is pulled down under the coupling effect of the parasitic capacitor Cx, thereby affecting the display effect of the display panel.

[0142] Based on this, this exemplary embodiment also provides a display panel, the display panel includes a pixel driving circuit, the pixel driving circuit includes a driving transistor, a first transistor, and a second transistor, the first electrode of the second transistor is connected to the gate of the driving transistor, the second electrode of the second transistor is connected to the second electrode of the driving transistor, the first electrode of the first transistor is connected to the first initial signal line, and the second electrode of the first transistor is connected to the second electrode of the driving transistor; the display panel also includes: a base substrate, a first gate line, a first conductive portion, a first bridge portion, and a ninth bridge portion, the orthographic projection of the first gate line on the base substrate extends along a first direction, and a partial structure of the first gate line is used to form the gate of the second transistor; the first conductive portion is used to form the driving The first bridge portion is connected to the gate of the driving transistor; the first bridge portion is connected to the second electrode of the first transistor, the second electrode of the driving transistor, and the second electrode of the second transistor through a via hole, and a parasitic capacitance Cx in Figure 1 is formed between the first bridge portion and the first gate line; the ninth bridge portion is connected to the first conductive portion and the first electrode of the second transistor through a through hole, and a parasitic capacitance Cy in Figure 1 is formed between the ninth bridge portion and the first gate line; the overlapping area of ​​the orthographic projection of the first bridge portion on the substrate and the orthographic projection of the first gate line on the substrate is a first overlapping area, and the overlapping area of ​​the orthographic projection of the ninth bridge portion on the substrate and the orthographic projection of the first gate line on the substrate is a second overlapping area, and the first overlapping area is less than or equal to the second overlapping area. This exemplary embodiment improves the display effect of the display panel by reducing the parasitic capacitance Cx between the third node and the first gate drive signal terminal.

[0143] In this exemplary embodiment, the display panel may include a base substrate, a shielding layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer stacked in sequence. Insulating layers may be provided between adjacent layers. As shown in Figures 3-19, Figure 3 is a structural layout diagram of an exemplary embodiment of the display panel disclosed herein, Figure 4 is a structural layout diagram of the blocking layer in Figure 3, Figure 5 is a structural layout diagram of the first active layer in Figure 3, Figure 6 is a structural layout diagram of the first conductive layer in Figure 3, Figure 7 is a structural layout diagram of the second conductive layer in Figure 3, Figure 8 is a structural layout diagram of the second active layer in Figure 3, Figure 9 is a structural layout diagram of the third conductive layer in Figure 3, Figure 10 is a structural layout diagram of the fourth conductive layer in Figure 3, Figure 11 is a structural layout diagram of the fifth conductive layer in Figure 3, Figure 12 is a structural layout diagram of the sixth conductive layer in Figure 3, Figure 13 is a structural layout diagram of the blocking layer and the first active layer in Figure 3, and Figure 14 is a structural layout diagram of the blocking layer, the first active layer, and the first conductive layer in Figure 3. FIG15 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, and the second conductive layer in FIG3 ; FIG16 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer in FIG3 ; FIG17 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in FIG3 ; FIG18 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in FIG3 ; FIG19 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer in FIG3 . The display panel may include a plurality of pixel driving circuits as shown in FIG1 . The plurality of pixel driving circuits may be arranged in an array along a first direction X and a second direction Y, wherein the first direction X and the second direction Y intersect. For example, the first direction X may be a row direction and the second direction Y may be a column direction. FIG3 only shows the layout structure of one pixel driving circuit. The pixel driving circuit shown in FIG3 can be arranged at least partially in mirror symmetry with the pixel driving circuit on the right side thereof.

[0144] As shown in FIG. 3 , 4 and 13 , the shielding layer includes a plurality of shielding portions 81 distributed in an array along the first direction X and the second direction Y, and the shielding portions 81 are connected to each other.

[0145] As shown in Figures 3, 5, 13 and 14, the first active layer may include: a first active portion 71, a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, a seventh active portion 77, an eighth active portion 78, a ninth active portion 79, a tenth active portion 710, an eleventh active portion 711, a twelfth active portion 712, a thirteenth active portion 713, a fourteenth active portion 714, a fifteenth active portion 715, a sixteenth active portion 716, a seventeenth active portion 717 and an eighteenth active portion 718. The first active portion 71 is used to form the channel region of the first transistor T1; the third active portion 73 can be used to form the channel region of the driving transistor T3; the fourth active portion 74 can be used to form the channel region of the fourth transistor T4; the fifth active portion 75 can be used to form the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; the seventh active portion 77 can be used to form the channel region of the seventh transistor T7; the eighth active portion 78 can be used to form the channel region of the eighth transistor T8; the ninth active portion 79 is connected between the third active portion 73 and the sixth active portion 76; the tenth active portion 710 and the twelfth active portion 712 are connected to both ends of the eighth active portion 78; The eleventh active portion 711 is connected between the fourth active portion 74 and the third active portion 73; the thirteenth active portion 713 is connected to the side of the fourth active portion 74 away from the third active portion 73; the fourteenth active portion 714 is connected to the side of the seventh active portion 77 away from the sixth active portion 76; the fifteenth active portion 715 is connected to the side of the fifth active portion 75 away from the third active portion 73, and the fifteenth active portion 715 in the pixel driving circuit shown in Figure 3 can be connected to the fifth active portion 75 in the pixel driving circuit on its right; the sixteenth active portion 716 is connected between the seventh active portion 77 and the sixth active portion 76, and the seventeenth active portion 717 and the eighteenth active portion 718 are connected to both ends of the first active portion 71. The first active layer may be formed of polysilicon material. Accordingly, the first transistor T1 , the driving transistor T3 , the fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 , the seventh transistor T7 , and the eighth transistor T8 may be P-type low-temperature polysilicon thin film transistors.

[0146] The orthographic projection of the shielding portion 81 on the substrate can at least partially overlap with the orthographic projection of the third active portion 73 on the substrate. The shielding portion 81 can shield the third active portion 73 from light, thereby improving the stability of the output characteristics of the driving transistor. The shielding layer can be a conductive structure and can be connected to a stable voltage source to provide signal shielding for the pixel driving circuit.

[0147] As shown in Figures 3, 6, and 14, the first conductive layer may include: a first conductive portion 11, a second gate line G2, an enable signal line EM, a first reset signal line Re1, and a second reset signal line Re2. The second gate line G2 can be used to provide the second gate drive signal terminal in Figure 1; the enable signal line EM can be used to provide the enable signal terminal in Figure 1; the first reset signal line Re1 can be used to provide the first reset signal terminal in Figure 1; and the second reset signal line Re2 can be used to provide the second reset signal terminal in Figure 1. The orthographic projection of the second gate line G2 on the base substrate, the orthographic projection of the enable signal line EM on the base substrate, the orthographic projection of the first reset signal line Re1 on the base substrate, and the orthographic projection of the second reset signal line Re2 on the base substrate can all extend along the first direction X. The orthographic projection of the second gate line G2 on the base substrate covers the orthographic projection of the fourth active portion 74 on the base substrate, and a portion of the structure of the second gate line G2 is used to form the gate of the fourth transistor. The orthographic projection of the enable signal line EM on the substrate overlaps the orthographic projection of the fifth active portion 75 and the orthographic projection of the sixth active portion 76 on the substrate. Portions of the enable signal line EM can be used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively. The orthographic projection of the first reset signal line Re1 on the substrate overlaps the orthographic projection of the first active portion 71 on the substrate. Portions of the first reset signal line Re1 can be used to form the gate of the first transistor T1. The orthographic projection of the second reset signal line Re2 on the substrate overlaps the orthographic projection of the seventh active portion 77 and the orthographic projection of the eighth active portion 78 on the substrate. Portions of the first reset signal line Re1 can be used to form the gates of the seventh transistor T7 and the eighth transistor T8, respectively. The orthographic projection of the first conductive portion 11 on the substrate overlaps the orthographic projection of the third active portion 73 on the substrate. The first conductive portion 11 can be used to form the gate of the drive transistor T3 and the first electrode of the capacitor C. The display panel can use the first conductive layer as a mask to perform conductor processing on the first active layer, that is, the area of ​​the first active layer covered by the first conductive layer can form the channel region of the transistor, and the area of ​​the first active layer not covered by the first conductive layer forms a conductor structure.

[0148] As shown in Figures 3, 7, and 15, the second conductive layer may include: a second sub-gate line 2G1 and a second conductive portion 22. The orthographic projection of the second sub-gate line 2G1 on the base substrate extends along the first direction X, and the second sub-gate line 2G1 can be used to provide the first gate drive signal terminal in Figure 1. The orthographic projection of the second conductive portion 22 on the base substrate can at least partially overlap with the orthographic projection of the first conductive portion 11 on the base substrate, and the second conductive portion 22 is used to form a second electrode of the capacitor C. The second conductive layer may also include a first connecting portion 23, and the second conductive portions 22 in the pixel drive circuits that are adjacent in the first direction X and at least partially mirror-symmetrical can be connected via the first connecting portion 23.

[0149] As shown in Figures 3, 8, and 16, the second active layer may include an active portion 9, which may include: a second active portion 92, a nineteenth active portion 919 connected to both ends of the second active portion 92, and a twentieth active portion 920. The second active portion 92 is used to form the channel region of the second transistor T2. The second active layer may be formed of indium gallium zinc oxide, and accordingly, the second transistor T2 may be an N-type metal oxide thin film transistor. The orthographic projection of the second sub-gate line 2G1 on the substrate may cover the orthographic projection of the second active portion 92 on the substrate, and a portion of the structure of the second sub-gate line 2G1 may be used to form the bottom gate of the second transistor T2.

[0150] As shown in Figures 3, 9, and 17, the third conductive layer may include a first sub-gate line 3G1, a first initial signal line Vinit1, a second initial signal line Vinit2, and a third initial signal line Vinit3. The orthographic projection of the first sub-gate line 3G1 on the substrate, the orthographic projection of the first initial signal line Vinit1 on the substrate, the orthographic projection of the second initial signal line Vinit2 on the substrate, and the orthographic projection of the third initial signal line Vinit3 on the substrate may all extend along the first direction X. The first sub-gate line 3G1 may be used to provide the first gate drive signal terminal in Figure 1, the orthographic projection of the first sub-gate line 3G1 on the substrate may cover the orthographic projection of the second active portion 92 on the substrate, and a partial structure of the first sub-gate line 3G1 may be used to form the top gate of the second transistor T2. At the same time, the first sub-gate line 3G1 may be connected to the second sub-gate line 2G1 through a via located in the frame area of ​​the display panel. The first initial signal line Vinit1 can be used to provide the first initial signal terminal in Figure 1, the second initial signal line Vinit2 can be used to provide the second initial signal terminal in Figure 1, and the third initial signal line Vinit3 can be used to provide the third initial signal terminal in Figure 1. In addition, the display panel can use the third conductive layer as a mask to perform a conductor processing on the second active layer, that is, the area of ​​the second active layer covered by the third conductive layer can form the channel region of the transistor, and the area of ​​the second active layer not covered by the third conductive layer forms a conductor structure.

[0151] As shown in Figures 3, 10, and 19, the fourth conductive layer may include a second sub-bridge portion 412, a third sub-bridge portion 413, a third bridge portion 43, a fourth bridge portion 44, a fifth bridge portion 45, a sixth bridge portion 46, a seventh bridge portion 47, an eighth bridge portion 48, a ninth bridge portion 49, and a tenth bridge portion 410. The second sub-bridge portion 412 is connected to the ninth active portion 79 and the twentieth active portion 920 via vias, respectively, to connect the second electrode of the second transistor T2 and the second electrode of the driving transistor T3. The third sub-bridge portion 413 is connected to the seventeenth active portion 717 via vias to connect the second electrode of the first transistor T1. The third bridge portion 43 is connected to the eighteenth active portion 718 and the first initial signal line Vinit1 via vias, respectively, to connect the first electrode of the first transistor T1 and the first initial signal terminal. The fourth bridge portion 44 is connected to the fourteenth active portion 714 and the second initial signal line Vinit2 through vias, thereby connecting the first electrode and the second initial signal terminal of the seventh transistor T7. The fifth bridge portion 45 is connected to the thirteenth active portion 713 through vias, thereby connecting the first electrode of the fourth transistor T4. The sixth bridge portion 46 is connected to the eleventh active portion 711 and the tenth active portion 710 through vias, thereby connecting the second electrode of the eighth transistor T8 and the first electrode of the driving transistor T3. The seventh bridge portion 47 is connected to the first connecting portion 23 and the fifteenth active portion 715 through vias, thereby connecting the second electrode of the capacitor C and the first electrode of the fifth transistor T5. The pixel driving circuit shown in Figure 3 can share the same seventh bridge portion 47 with the pixel driving circuit located to its right. The eighth bridge portion 48 is connected to the sixteenth active portion 716 through vias, thereby connecting the second electrode of the seventh transistor T7 and the second electrode of the sixth transistor T6. The ninth bridge portion 49 is connected to the nineteenth active portion 919 and the first conductive portion 11 through vias, thereby connecting the gate of the driving transistor T3 and the first electrode of the second transistor T2. An opening 221 may be formed on the second conductive portion 22, and a via connected between the ninth bridge portion 49 and the first conductive portion 11 is provided through the opening 221. The tenth bridge portion 410 may be connected to the third initial signal line Vinit3 and the twelfth active portion 712 through vias, thereby connecting the first electrode of the eighth transistor and the third initial signal line Vinit3.

[0152] As shown in Figures 3, 11, and 19, the fifth conductive layer may include: a first sub-bridge portion 51, a third conductive portion 53, a thirteenth bridge portion 513, a fourteenth bridge portion 514, and a first fan-out line FIPH. The orthographic projection of the first fan-out line FIPH on the substrate may extend along the first direction X, and the first fan-out line FIPH may serve as a row-direction fan-out line connecting the data line in the FIP (Fanout In Pixel, fan-out area in a pixel). The third conductive portion 53 may be connected to the seventh bridge portion 47 through a via to connect to the first pole of the fifth transistor T5. The thirteenth bridge portion 513 may be connected to the fifth bridge portion 45 through a via to connect to the first pole of the fourth transistor. The fourteenth bridge portion 514 may be connected to the eighth bridge portion 48 through a via to connect to the second pole of the sixth transistor T6.

[0153] It should be noted that in other exemplary embodiments, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 can also be located in other conductive layers. For example, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 can also be located in the second conductive layer, the fourth conductive layer, the fifth conductive layer, etc.

[0154] As shown in Figures 3 and 12, the sixth conductive layer may include: a data line Da, a first power line VDD, a second fan-out line FIPV, and a fifteenth bridge portion 615. The orthographic projections of the data line Da, the first power line VDD, and the second fan-out line FIPV on the base substrate may extend along the second direction Y. The data line Da is used to provide the data signal terminal in Figure 1, and the first power line VDD is used to provide the first power terminal in Figure 1. The data line Da may be connected to the thirteenth bridge portion 513 through a via to connect the data signal terminal and the first electrode of the fourth transistor. There may be multiple first power lines VDD, and the orthographic projections of the multiple first power lines VDD on the base substrate extend along the second direction Y and are spaced apart along the first direction X. The first power line VDD in the pixel driving circuit shown in Figure 3 may be connected to the first power line VDD in the pixel driving circuit to its left. The first power line VDD may be connected to the third conductive portion 53 intersecting with its orthographic projection on the base substrate through a via.

[0155] The second fan-out line FIPV can be used as a column-direction fan-out line connecting the data line in the FIP (Fanout In Pixel). The fifteenth bridge portion 615 can be connected to the fourteenth bridge portion 514 through a via. The fifteenth bridge portion 615 can be used to connect the first electrode of the light-emitting unit.

[0156] As shown in Figures 3 and 19 , the orthographic projection of the third conductive portion 53 on the substrate can overlap the orthographic projection of the second active portion 92 on the substrate. The third conductive portion 53 can reduce the impact of light on the characteristics of the second transistor T2. The orthographic projection of the third conductive portion 53 on the substrate can also at least partially overlap with the orthographic projection of the ninth bridge portion 49 on the substrate. The third conductive portion 53 can shield the ninth bridge portion 49 from noise interference from other signals, thereby improving the stability of the gate voltage of the driving transistor T3.

[0157] It should be understood that, in other exemplary embodiments, the display panel may not be provided with the first fan-out line FIPH and the second fan-out line FIPV.

[0158] In this exemplary embodiment, as shown in Figure 3-19, the first sub-bridge portion 51, the second sub-bridge portion 412, and the third sub-bridge portion 413 form a first bridge portion, the first sub-gate line 3G1 and / or the second sub-gate line 2G1 form a first gate line, and the orthographic projection of the first bridge portion on the substrate and the orthographic projection of the first gate line on the substrate do not overlap. This setting can reduce the parasitic capacitance Cx between the third node and the first gate drive signal terminal in Figure 1, thereby improving the display effect of the display panel.

[0159] It should be noted that the pixel driving circuit and the layout structure of the display panel can also be set in other ways. As long as the pixel driving circuit includes a first transistor, a second transistor, a driving transistor connected to each other, and a first bridge portion connected to the first transistor, the second transistor, and the driving transistor, the display panel can set the orthographic projection of the first reset signal line on the base substrate on the side of the orthographic projection of the first conductive portion on the base substrate away from the orthographic projection of the first gate line on the base substrate, so that the orthographic projections of the first bridge portion and the first gate line on the base substrate do not overlap, thereby reducing the parasitic capacitance between the output end of the driving transistor and the gate of the second transistor, thereby improving the display effect of the display panel.

[0160] In this exemplary embodiment, as shown in FIG3-19 , the orthographic projection of the second initial signal line Vinit2 on the substrate at least partially overlaps with the orthographic projection of the enable signal line EM on the substrate, and the second initial signal line Vinit2 can shield the enable signal line EM from coupling with the first bridge portion. Similarly, the orthographic projection of the third initial signal line Vinit3 on the substrate at least partially overlaps with the orthographic projection of the second reset signal line Re2 on the substrate, and the third initial signal line Vinit3 can shield the second reset signal line Re2 from coupling with the first bridge portion.

[0161] In this exemplary embodiment, as shown in FIG. 3-19 , the orthographic projection of the first bridge portion on the base substrate is located between the orthographic projection of the first gate line on the base substrate and the orthographic projection of the first reset signal line Re1 on the base substrate.

[0162] In the same pixel driving circuit, the orthographic projection of the second reset signal line Re2 on the base substrate and the orthographic projection of the enable signal line EM on the base substrate are located between the orthographic projection of the first conductive portion 11 on the base substrate and the orthographic projection of the first reset signal line Re1 on the base substrate; the orthographic projection of the first bridging portion on the base substrate and the orthographic projection of the second reset signal line Re2 on the base substrate and the orthographic projection of the enable signal line EM on the base substrate all overlap.

[0163] In this exemplary embodiment, as shown in FIG3-19 , the second reset signal line Re2 includes a first extension portion Re21 and a second extension portion Re22. The width of the orthographic projection of the first extension portion Re21 on the substrate is smaller than the width of the orthographic projection of the second extension portion Re22 on the substrate. The orthographic projection of the first bridge portion on the substrate extends along a second direction Y and intersects with the orthographic projection of the first extension portion Re21 on the substrate. The width of the first extension portion Re21 is perpendicular to its extension direction, and the width of the second extension portion Re22 is perpendicular to its extension direction. This arrangement can reduce the overlapping area between the second reset signal line Re2 and the first bridge portion, thereby reducing the coupling effect of the second reset signal line Re2 on the third node, thereby improving the voltage stability of the third node.

[0164] In this exemplary embodiment, as shown in FIG. 3-19 , the orthographic projection of the second reset signal line Re2 on the base substrate is located between the orthographic projection of the first reset signal line Re1 on the base substrate and the orthographic projection of the enable signal line EM on the base substrate.

[0165] In this exemplary embodiment, as shown in FIG3-19 , in the same pixel driving circuit, in the first direction X, the orthographic projection of the third active portion 73 on the base substrate is located between the orthographic projection of the first active portion 71 on the base substrate and the orthographic projection of the fifth active portion 75 on the base substrate. In the same pixel driving circuit, in the first direction X, the orthographic projection of the third active portion 73 on the base substrate is located between the orthographic projection of the second active portion 72 on the base substrate and the orthographic projection of the fifth active portion 75 on the base substrate.

[0166] In this exemplary embodiment, as shown in FIG3-19 , the first reset signal line Re1 and the first initial signal line Vinit1 are located on different conductive layers. Within the same pixel drive circuit, the orthographic projection of the first reset signal line Re1 on the substrate at least partially overlaps with the orthographic projection of the first initial signal line Vinit1 on the substrate. The third initial signal line Vinit3 and the second reset signal line Re2 are located on different conductive layers, while the second initial signal line Vinit2 and the enable signal line EM are located on different conductive layers. Within the same pixel drive circuit, the orthographic projection of the third initial signal line Vinit3 on the substrate at least partially overlaps with the orthographic projection of the second reset signal line Re2 on the substrate, while the orthographic projection of the second initial signal line Vinit2 on the substrate at least partially overlaps with the orthographic projection of the enable signal line EM on the substrate. This arrangement can improve the light transmittance of the display panel.

[0167] In this exemplary embodiment, as shown in FIG. 3-19 , the orthographic projection of the first bridge portion on the base substrate does not overlap with the orthographic projections of the first fan-out line FIPH and the second fan-out line FIPV on the base substrate.

[0168] It should be noted that, as shown in Figures 3, 18, and 19, the black squares drawn on the side of the fourth conductive layer facing away from the substrate represent vias connecting the fourth conductive layer to other layers facing the substrate; the black squares drawn on the side of the fifth conductive layer facing away from the substrate represent vias connecting the fifth conductive layer to other layers facing the substrate; and the black squares drawn on the side of the sixth conductive layer facing away from the substrate represent vias connecting the sixth conductive layer to other layers facing the substrate. Different vias represented by black squares in different locations can penetrate different insulating layers.

[0169] As shown in FIG20 , which is a partial cross-sectional view of the display panel shown in FIG3 taken along the dotted line AA, the display panel may further include a buffer layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, a fifth insulating layer 105, a first dielectric layer 106, a passivation layer 107, a first planarization layer 108, and a second planarization layer 109. The substrate 100, the shielding layer, the buffer layer 101, the first active layer, the second insulating layer 102, the first conductive layer, the third insulating layer 103, the second conductive layer, the fourth insulating layer 104, the second active layer, the fifth insulating layer 105, the third conductive layer, the first dielectric layer 106, the fourth conductive layer, the passivation layer 107, the first planarization layer 108, the fifth conductive layer, the second planarization layer 109, and the sixth conductive layer are stacked in sequence. The buffer layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be a single-layer structure or a multi-layer structure. The materials of the buffer layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride. The first dielectric layer 106 can be a silicon nitride layer. The materials of the first planarizing layer 108 and the second planarizing layer 109 can be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG), etc. The passivation layer 97 can be a silicon oxide layer. The base substrate 90 can include a glass substrate, a barrier layer, and a polyimide layer stacked in sequence. The barrier layer can be an inorganic material. The first, second, and third conductive layers can be made of molybdenum, aluminum, copper, titanium, or niobium, or an alloy thereof, or a molybdenum / titanium alloy or laminate thereof. The fourth, fifth, and sixth conductive layers can be made of a metal material, such as molybdenum, aluminum, copper, titanium, or niobium, or an alloy thereof, or a molybdenum / titanium alloy or laminate thereof, or a titanium / aluminum / titanium laminate thereof. The sheet resistance of any of the fourth, fifth, and sixth conductive layers can be less than the sheet resistance of any of the first, second, and third conductive layers.

[0170] This exemplary embodiment also provides another display panel, which may include a base substrate, a blocking layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer stacked in sequence. An insulating layer may be provided between the above-mentioned adjacent layers. As shown in Figures 21-35, Figure 21 is a structural layout diagram of an exemplary embodiment of the display panel disclosed herein, Figure 22 is a structural layout diagram of the blocking layer in Figure 21, Figure 23 is a structural layout diagram of the first active layer in Figure 21, Figure 24 is a structural layout diagram of the first conductive layer in Figure 21, Figure 25 is a structural layout diagram of the second conductive layer in Figure 21, Figure 26 is a structural layout diagram of the second active layer in Figure 21, Figure 27 is a structural layout diagram of the third conductive layer in Figure 21, Figure 28 is a structural layout diagram of the fourth conductive layer in Figure 21, Figure 29 is a structural layout diagram of the fifth conductive layer in Figure 21, Figure 30 is a structural layout diagram of the blocking layer and the first active layer in Figure 21, and Figure 31 is a structural layout diagram of the blocking layer, the first active layer, FIG32 is a structural layout diagram of the shielding layer, first active layer, first conductive layer, and second conductive layer in FIG21 ; FIG33 is a structural layout diagram of the shielding layer, first active layer, first conductive layer, second conductive layer, and second active layer in FIG21 ; FIG34 is a structural layout diagram of the shielding layer, first active layer, first conductive layer, second conductive layer, second active layer, and third conductive layer in FIG21 ; FIG35 is a structural layout diagram of the shielding layer, first active layer, first conductive layer, second conductive layer, second active layer, third conductive layer, and fourth conductive layer in FIG21 . The display panel may include multiple pixel drive circuits as shown in FIG1 . Multiple pixel drive circuits may be arranged in an array along a first direction X and a second direction Y, wherein the first direction X and the second direction Y intersect. For example, the first direction X may be a row direction and the second direction Y may be a column direction. FIG21 only shows the layout structure of one pixel drive circuit. The pixel drive circuit shown in FIG21 may be arranged at least partially in mirror symmetry with the pixel drive circuit located to its right.

[0171] As shown in FIG. 21 , 22 and 30 , the shielding layer includes a plurality of shielding portions 81 distributed in an array along the first direction X and the second direction Y, and the shielding portions 81 are connected to each other.

[0172] As shown in Figures 21, 23, 30 and 31, the first active layer may include: a first active portion 71, a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, a seventh active portion 77, an eighth active portion 78, a ninth active portion 79, a tenth active portion 710, an eleventh active portion 711, a twelfth active portion 712, a thirteenth active portion 713, a fourteenth active portion 714, a fifteenth active portion 715, a sixteenth active portion 716, a seventeenth active portion 717 and an eighteenth active portion 718. The first active portion 71 is used to form the channel region of the first transistor T1; the third active portion 73 can be used to form the channel region of the driving transistor T3; the fourth active portion 74 can be used to form the channel region of the fourth transistor T4; the fifth active portion 75 can be used to form the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; the seventh active portion 77 can be used to form the channel region of the seventh transistor T7; the eighth active portion 78 can be used to form the channel region of the eighth transistor T8; the ninth active portion 79 is connected between the third active portion 73 and the sixth active portion 76; The tenth active portion 710 and the twelfth active portion 712 are connected to both ends of the eighth active portion 78; the eleventh active portion 711 is connected between the fourth active portion 74 and the third active portion 73; the thirteenth active portion 713 is connected to the side of the fourth active portion 74 away from the third active portion 73; the fourteenth active portion 714 is connected to the side of the seventh active portion 77 away from the sixth active portion 76; the fifteenth active portion 715 is connected to the side of the fifth active portion 75 away from the third active portion 73, and the fifteenth active portion 715 in the pixel driving circuit shown in Figure 21 can be connected to the fifth active portion 75 in the pixel driving circuit on its right; the sixteenth active portion 716 is connected between the seventh active portion 77 and the sixth active portion 76, and the seventeenth active portion 717 and the eighteenth active portion 718 are connected to both ends of the first active portion 71. The first active layer may be formed of polysilicon material. Accordingly, the first transistor T1 , the driving transistor T3 , the fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 , the seventh transistor T7 , and the eighth transistor T8 may be P-type low-temperature polysilicon thin film transistors.

[0173] The orthographic projection of the shielding portion 81 on the substrate can at least partially overlap with the orthographic projection of the third active portion 73 on the substrate. The shielding portion 81 can shield the third active portion 73 from light, thereby improving the stability of the output characteristics of the driving transistor. The shielding layer can be a conductive structure and can be connected to a stable voltage source to provide signal shielding for the pixel driving circuit.

[0174] As shown in Figures 21, 24, and 31, the first conductive layer may include: a first conductive portion 11, a second gate line G2, an enable signal line EM, a first reset signal line Re1, and a second reset signal line Re2. The second gate line G2 can be used to provide the second gate drive signal terminal in Figure 1; the enable signal line EM can be used to provide the enable signal terminal in Figure 1; the first reset signal line Re1 can be used to provide the first reset signal terminal in Figure 1; and the second reset signal line Re2 can be used to provide the second reset signal terminal in Figure 1. The orthographic projection of the second gate line G2 on the base substrate, the orthographic projection of the enable signal line EM on the base substrate, the orthographic projection of the first reset signal line Re1 on the base substrate, and the orthographic projection of the second reset signal line Re2 on the base substrate can all extend along the first direction X. The orthographic projection of the second gate line G2 on the base substrate covers the orthographic projection of the fourth active portion 74 on the base substrate, and a portion of the structure of the second gate line G2 is used to form the gate of the fourth transistor. The orthographic projection of the enable signal line EM on the substrate overlaps the orthographic projection of the fifth active portion 75 and the orthographic projection of the sixth active portion 76 on the substrate. Portions of the enable signal line EM can be used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively. The orthographic projection of the first reset signal line Re1 on the substrate overlaps the orthographic projection of the first active portion 71 on the substrate. Portions of the first reset signal line Re1 can be used to form the gate of the first transistor T1. The orthographic projection of the second reset signal line Re2 on the substrate overlaps the orthographic projection of the seventh active portion 77 and the orthographic projection of the eighth active portion 78 on the substrate. Portions of the first reset signal line Re1 can be used to form the gates of the seventh transistor T7 and the eighth transistor T8, respectively. The orthographic projection of the first conductive portion 11 on the substrate overlaps the orthographic projection of the third active portion 73 on the substrate. The first conductive portion 11 can be used to form the gate of the drive transistor T3 and the first electrode of the capacitor C. The display panel can use the first conductive layer as a mask to perform conductor processing on the first active layer, that is, the area of ​​the first active layer covered by the first conductive layer can form the channel region of the transistor, and the area of ​​the first active layer not covered by the first conductive layer forms a conductor structure.

[0175] As shown in Figures 21, 25, and 32, the second conductive layer may include: a second sub-gate line 2G1, a second conductive portion 22, and a first initial signal line Vinit1. The orthographic projections of the first initial signal line Vinit1 and the second sub-gate line 2G1 on the base substrate extend along the first direction X. The second sub-gate line 2G1 can be used to provide the first gate drive signal terminal in Figure 1, and the first initial signal line Vinit1 can be used to provide the first initial signal terminal in Figure 1. The orthographic projection of the second conductive portion 22 on the base substrate can at least partially overlap with the orthographic projection of the first conductive portion 11 on the base substrate, and the second conductive portion 22 is used to form the second electrode of the capacitor C. The second conductive layer may also include a first connecting portion 23, and the adjacent second conductive portions 22 in the first direction X can be connected through the first connecting portion 23.

[0176] As shown in Figures 21, 26, and 33, the second active layer may include an active portion 9, which may include: a second active portion 92, a nineteenth active portion 919 connected to both ends of the second active portion 92, and a twentieth active portion 920. The second active portion 92 is used to form the channel region of the second transistor T2. The second active layer may be formed of indium gallium zinc oxide, and accordingly, the second transistor T2 may be an N-type metal oxide thin film transistor. The orthographic projection of the second sub-gate line 2G1 on the substrate may cover the orthographic projection of the second active portion 92 on the substrate, and a portion of the structure of the second sub-gate line 2G1 may be used to form the bottom gate of the second transistor T2.

[0177] As shown in Figures 21, 27, and 34, the third conductive layer may include a first sub-gate line 3G1, a second initial signal line Vinit2, and a third initial signal line Vinit3. The orthographic projection of the first sub-gate line 3G1 on the base substrate, the orthographic projection of the second initial signal line Vinit2 on the base substrate, and the orthographic projection of the third initial signal line Vinit3 on the base substrate may all extend along the first direction X. The first sub-gate line 3G1 may be used to provide the first gate drive signal terminal in Figure 1. The orthographic projection of the first sub-gate line 3G1 on the base substrate may cover the orthographic projection of the second active portion 92 on the base substrate. A partial structure of the first sub-gate line 3G1 may be used to form the top gate of the second transistor T2. At the same time, the first sub-gate line 3G1 may be connected to the second sub-gate line 2G1 through a via located in the frame area of ​​the display panel. The second initial signal line Vinit2 may be used to provide the second initial signal terminal in Figure 1, and the third initial signal line Vinit3 may be used to provide the third initial signal terminal in Figure 1. In addition, the display panel can use the third conductive layer as a mask to conduct the second active layer, that is, the area of ​​the second active layer covered by the third conductive layer can form the channel region of the transistor, and the area of ​​the second active layer not covered by the third conductive layer forms a conductor structure.

[0178] As shown in Figures 21, 28, and 35, the fourth conductive layer may include a first bridge portion 41, a second bridge portion 42, a third bridge portion 43, a fourth bridge portion 44, a fifth bridge portion 45, a sixth bridge portion 46, a seventh bridge portion 47, an eighth bridge portion 48, a ninth bridge portion 49, a tenth bridge portion 410, and a first fan-out line FIPH. The first bridge portion 41 is connected to the ninth active portion 79, the twentieth active portion 920, and the seventeenth active portion 717 through vias, respectively, to connect the second electrode of the second transistor T2, the second electrode of the driving transistor T3, and the second electrode of the first transistor T1. The third bridge portion 43 is connected to the eighteenth active portion 718 and the first initial signal line Vinit1 through vias, respectively, to connect the first electrode of the first transistor T1 to the first initial signal terminal. The fourth bridge portion 44 is connected to the fourteenth active portion 714 and the second initial signal line Vinit2 through vias, respectively, to connect the first electrode and the second initial signal terminal of the seventh transistor T7. The fifth bridge portion 45 is connected to the thirteenth active portion 713 through a via to connect the first electrode of the fourth transistor T4. The sixth bridge portion 46 is connected to the eleventh active portion 711 and the tenth active portion 710 through vias to connect the second electrode of the eighth transistor T8 and the first electrode of the driving transistor T3. The seventh bridge portion 47 is connected to the first connecting portion 23 and the fifteenth active portion 715 through vias to connect the second electrode of the capacitor C and the first electrode of the fifth transistor T5. The pixel driving circuit shown in Figure 21 can share the same seventh bridge portion 47 with the pixel driving circuit located to its right. The eighth bridge portion 48 is connected to the sixteenth active portion 716 through a via to connect the second electrode of the seventh transistor T7 and the second electrode of the sixth transistor T6. The ninth bridge portion 49 is connected to the nineteenth active portion 919 and the first conductive portion 11 through vias, thereby connecting the gate of the driving transistor T3 and the first electrode of the second transistor T2. An opening 221 may be formed on the second conductive portion 22, and a via connected between the ninth bridge portion 41 and the first conductive portion 11 is provided through the opening 221. The tenth bridge portion 410 may be connected to the third initial signal line Vinit3 and the twelfth active portion 712 through vias, thereby connecting the first electrode of the eighth transistor and the third initial signal line Vinit3.

[0179] The orthographic projection of the first fan-out line FIPH on the substrate may extend along the first direction X. The first fan-out line FIPH may serve as a row-direction fan-out line connecting the data line in a FIP (Fanout In Pixel).

[0180] As shown in Figures 21 and 29, the fifth conductive layer may include: a fourteenth bridge portion 514, a data line Da, a first power line VDD, a second fan-out line FIPV, and a third initial connection line 5Vinit3. The fourteenth bridge portion 514 may be connected to the eighth bridge portion 48 via a via to connect to the second electrode of the sixth transistor T6. The fourteenth bridge portion 514 may also be used to connect to the first electrode of the light-emitting unit. The orthographic projections of the data line Da, the first power line VDD, the second fan-out line FIPV, and the third initial connection line 5Vinit3 on the substrate may extend along the second direction Y. The data line Da is used to provide the data signal terminal shown in Figure 1, and the first power line VDD is used to provide the first power terminal shown in Figure 1. The data line Da may be connected to the fifth bridge portion 45 via a via to connect the data signal terminal to the first electrode of the fourth transistor. The first power line VDD may be connected to the seventh bridge portion 47 via a via. The second fan-out line FIPV may serve as a column-direction fan-out line connecting the data lines in a FIP (Fanout In Pixel). The two disconnected parts of the second fan-out line FIPV can be bridged by the second bridge portion 42. The third initial connection line 5Vinit3 can be connected to the third initial signal line Vinit3 whose orthographic projection intersects with its projection on the substrate through a via, so that the third initial signal line Vinit3 forms a grid structure. This arrangement can reduce the voltage difference at different positions of the third initial signal line Vinit3.

[0181] In this exemplary embodiment, the pixel driving circuits of other columns can replace the third initial connection line 5Vinit3 with the first initial connection line 5Vinit1 or the second initial connection line 5Vinit2. The first initial connection line 5Vinit1 can be connected to the first initial signal line Vinit1 that intersects with its orthographic projection on the substrate through a via hole, so that the first initial signal line Vinit1 forms a grid structure. This arrangement can reduce the voltage difference at different positions of the first initial signal line Vinit1. The second initial connection line 5Vinit2 can be connected to the second initial signal line Vinit2 that intersects with its orthographic projection on the substrate through a via hole, so that the second initial signal line Vinit2 forms a grid structure. This arrangement can reduce the voltage difference at different positions of the second initial signal line Vinit2. For example, three adjacent columns of pixel driving circuits can be respectively provided with the first initial connection line 5Vinit1, the second initial connection line 5Vinit2, and the third initial connection line 5Vinit3.

[0182] It should be noted that in other exemplary embodiments, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 can also be located in other conductive layers. For example, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 can also be located in the second conductive layer, the fourth conductive layer, the fifth conductive layer, etc.

[0183] As shown in Figures 21 and 29 , the orthographic projection of the first power line VDD on the substrate can overlap the orthographic projection of the second active portion 92 on the substrate. This can reduce the effects of light on the characteristics of the second transistor T2. The orthographic projection of the first power line VDD on the substrate can also at least partially overlap with the orthographic projection of the ninth bridge portion 49 on the substrate. This can shield the ninth bridge portion 49 from noise interference from other signals, thereby improving the stability of the gate voltage of the driving transistor T3.

[0184] It should be understood that, in other exemplary embodiments, the display panel may not be provided with the first fan-out line FIPH and the second fan-out line FIPV.

[0185] It should be noted that, as shown in Figures 21, 34, and 35, the black squares drawn on the side of the fourth conductive layer facing away from the substrate represent vias connecting the fourth conductive layer to other layers on the side facing the substrate; the black squares drawn on the side of the fifth conductive layer facing away from the substrate represent vias connecting the fifth conductive layer to other layers on the side facing the substrate. Different vias represented by black squares in different locations can penetrate different insulating layers.

[0186] In this exemplary embodiment, as shown in Figures 21-35, the display panel also reduces the parasitic capacitance between the output end of the driving transistor T3 and the gate of the second transistor T2 by arranging the orthographic projection of the first reset signal line Re1 on the base substrate on a side of the orthographic projection of the first conductive portion 11 on the base substrate away from the orthographic projection of the first gate line on the base substrate, so that the orthographic projections of the first bridge portion 41 and the first gate line on the base substrate do not overlap, thereby improving the display effect of the display panel.

[0187] In this exemplary embodiment, as shown in Figures 21-35, the orthographic projection of the first bridge portion 41 on the substrate is located between the orthographic projection of the first gate line on the substrate and the orthographic projection of the first reset signal line Re1 on the substrate, that is, the orthographic projection of the first bridge portion 41 on the substrate and the orthographic projection of the first gate line on the substrate do not overlap.

[0188] In the same pixel driving circuit, the orthographic projection of the second reset signal line Re2 on the substrate and the orthographic projection of the enable signal line EM on the substrate are located between the orthographic projection of the first conductive portion 11 on the substrate and the orthographic projection of the first reset signal line Re1 on the substrate; the orthographic projection of the first bridging portion 41 on the substrate and the orthographic projection of the second reset signal line Re2 on the substrate and the orthographic projection of the enable signal line EM on the substrate all overlap.

[0189] In this exemplary embodiment, as shown in Figures 21-35, the second reset signal line Re2 includes a first extension portion Re21 and a second extension portion Re22. The width of the orthographic projection of the first extension portion Re21 on the substrate is smaller than the width of the orthographic projection of the second extension portion Re22 on the substrate. The orthographic projection of the first bridge portion 41 on the substrate extends along the second direction Y and intersects with the orthographic projection of the first extension portion Re21 on the substrate. The width of the first extension portion Re21 is perpendicular to its extension direction, and the width of the second extension portion Re22 is perpendicular to its extension direction. This arrangement can reduce the overlapping area between the second reset signal line Re2 and the first bridge portion 41, thereby reducing the coupling effect of the second reset signal line Re2 on the third node, thereby improving the voltage stability of the third node.

[0190] In this exemplary embodiment, as shown in FIG. 21-35 , the orthographic projection of the second reset signal line Re2 on the base substrate is located between the orthographic projection of the first reset signal line Re1 on the base substrate and the orthographic projection of the enable signal line EM on the base substrate.

[0191] In this exemplary embodiment, as shown in Figures 21 to 35, in the same pixel driving circuit, in the first direction X, the orthographic projection of the third active portion 73 on the base substrate is located between the orthographic projection of the first active portion 71 on the base substrate and the orthographic projection of the fifth active portion 75 on the base substrate. In the same pixel driving circuit, in the first direction X, the orthographic projection of the third active portion 73 on the base substrate is located between the orthographic projection of the second active portion 72 on the base substrate and the orthographic projection of the fifth active portion 75 on the base substrate.

[0192] In this exemplary embodiment, as shown in Figures 21-35, in the same pixel driving circuit, the orthographic projection of the first reset signal line Re1 on the substrate is located between the orthographic projection of the first initial signal line Vinit1 on the substrate and the orthographic projection of the first conductive portion 11 on the substrate. The orthographic projection of the second initial signal line Vinit2 on the substrate at least partially overlaps with the orthographic projection of the first reset signal line Re1 on the substrate. The orthographic projection of the third initial signal line Vinit3 on the substrate at least partially overlaps with the orthographic projection of the second reset signal line Re2 on the substrate. This arrangement can improve the light transmittance of the display panel.

[0193] FIG36 is a partial cross-sectional view of the display panel shown in FIG21 taken along dotted line BB. The display panel may further include a buffer layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, a fifth insulating layer 105, a first dielectric layer 106, a passivation layer 107, and a first planarization layer 108. The substrate 100, the shielding layer, the buffer layer 101, the first active layer, the second insulating layer 102, the first conductive layer, the third insulating layer 103, the second conductive layer, the fourth insulating layer 104, the second active layer, the fifth insulating layer 105, the third conductive layer, the first dielectric layer 106, the fourth conductive layer, the passivation layer 107, the first planarization layer 108, and the fifth conductive layer are stacked in sequence. The buffer layer 101, second insulating layer 102, third insulating layer 103, fourth insulating layer 104, and fifth insulating layer 105 can be single-layer or multi-layer structures. The materials of the buffer layer 101, second insulating layer 102, third insulating layer 103, fourth insulating layer 104, and fifth insulating layer 105 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride. The first dielectric layer 106 can be a silicon nitride layer. The material of the first planarization layer 108 can be an organic material, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding (SOG), etc. The passivation layer 97 can be a silicon oxide layer. The base substrate 90 can include a glass substrate, a barrier layer, and a polyimide layer stacked in sequence. The barrier layer can be an inorganic material. The materials of the first, second, and third conductive layers can be molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a stacked conductive layer. The fourth and fifth conductive layers may be made of metal materials, such as molybdenum, aluminum, copper, titanium, or niobium, or an alloy thereof, or a molybdenum / titanium alloy or laminate, or a titanium / aluminum / titanium laminate. The sheet resistance of either the fourth or fifth conductive layer may be less than the sheet resistance of either the first, second, or third conductive layer.

[0194] As shown in Figures 21-35, the enable signal line EM is not shielded by the second initial signal line Vinit2. This exemplary embodiment can shield the enable signal line by other voltage-stabilizing conductive parts. The voltage-stabilizing conductive part is a conductive structure with a stable voltage. The voltage-stabilizing conductive part is located between the enable signal line EM and the first bridging part, and the orthographic projection of the voltage-stabilizing conductive part on the substrate overlaps with the orthographic projection of the enable signal line EM on the substrate.

[0195] For example, as shown in FIG37 , which is a partial structural diagram of another exemplary embodiment of the display panel disclosed herein, the second conductive layer may further include a first protruding portion 24 connected to the second conductive portion 22 , and the first protruding portion 24 may form the aforementioned voltage-stabilizing conductive portion.

[0196] For another example, as shown in FIG38 , which is a partial structural diagram of another exemplary embodiment of the display panel disclosed herein, the third conductive layer may further include a second protrusion Vinit31 connected to the third initial signal line Vinit3, and the second protrusion Vinit31 may form the above-mentioned voltage-stabilizing conductive portion.

[0197] It should be understood that there are other ways to achieve that the first overlapping area is less than or equal to the second overlapping area. As shown in FIG39, which is a partial structural schematic diagram of another exemplary embodiment of the display panel of the present disclosure, the orthographic projection of the first gate line (including the first sub-gate line 3G1 and the second sub-gate line 2G1) on the substrate can also be located between the orthographic projection of the first conductive portion 11 on the substrate and the orthographic projection of the first reset signal line Re1 on the substrate. In this exemplary embodiment, the first overlapping area can be achieved by reducing the width of the first bridge portion 41 or increasing the width of the ninth bridge portion 49 to be less than or equal to the second overlapping area. For example, the size of the overlapping area of ​​the orthographic projection of the first bridge portion 41 on the substrate and the orthographic projection of the first gate line on the substrate in the first direction X is smaller than the size of the overlapping area of ​​the orthographic projection of the ninth bridge portion 49 on the substrate and the orthographic projection of the first gate line on the substrate in the first direction X. This exemplary embodiment can also achieve the first overlapping area being less than or equal to the second overlapping area by reducing or increasing the local width of the first gate line. For example, the size of the overlapping area between the orthographic projection of the first gate line on the base substrate and the first bridge portion 41 in the second direction is smaller than the size of the overlapping area between the orthographic projection of the first gate line on the base substrate and the ninth bridge portion 49 in the second direction.

[0198] In addition, the second gate line G2 has a pull-up effect on the third node N3. This exemplary embodiment can also reduce the pull-down effect of the first gate line on the third node by adjusting the parasitic capacitance between the first bridge portion and the second gate line G2. This exemplary embodiment can improve the display effect by increasing the overlapping area between the first bridge portion and the second gate line G2 on the substrate. For example, the overlapping area between the first bridge portion and the second gate line G2 on the substrate is greater than or equal to the overlapping area between the first bridge portion and the first gate line on the substrate. As shown in Figure 40, a partial structural schematic diagram of another exemplary embodiment of the display panel disclosed herein can be provided. This exemplary embodiment can add a lateral protrusion 411 connected to the first bridge portion 41. The lateral protrusion 411 is arranged to protrude from the first bridge portion 41 along the second direction Y. The orthographic projection of the lateral protrusion 411 on the substrate overlaps with the second gate line G2 on the substrate. The lateral protrusion 411 can increase the overlapping area between the first bridge portion and the second gate line G2 on the substrate. In this exemplary embodiment, the lateral protrusion 411 is located in the fourth conductive layer. It should be understood that in other exemplary embodiments, the lateral protrusion 411 may also be located in other conductive layers, for example, the lateral protrusion 411 may be located in the fifth conductive layer.

[0199] In this exemplary embodiment, the parasitic capacitance between the first node N1 and the first gate drive signal terminal G1 in FIG1 may be greater than the parasitic capacitance between the third node N3 and the first gate drive signal terminal G1. The parasitic capacitance may be adjusted by adjusting the overlap area between the conductive portions or by adjusting the thickness of the dielectric layer between the conductive portions.

[0200] It should be noted that the proportions of the drawings in this disclosure can be used as a reference in actual processes, but are not limited to this. For example, the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematics. In addition, qualifiers such as first and second are only used to limit different structural names, and they do not have a specific order of meaning. The same structural layer can be formed by the same composition process. In this exemplary embodiment, the orthographic projection of a certain structure on the base substrate extends in a certain direction, which can be understood as the orthographic projection of the structure on the base substrate extending in a straight line or bending along that direction.

[0201] This exemplary embodiment also provides a display device, which includes the above-mentioned display panel. The display device can be a mobile phone, a tablet computer, a television, or other display device.

[0202] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0203] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0204] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A display panel, wherein: The display panel includes a pixel driving circuit, the pixel driving circuit includes a driving transistor, a first transistor, and a second transistor, wherein a first electrode of the second transistor is connected to a gate of the driving transistor, a second electrode of the second transistor is connected to a second electrode of the driving transistor, a first electrode of the first transistor is connected to a first initial signal line, and a second electrode of the first transistor is connected to a second electrode of the driving transistor; The display panel further includes: substrate; a first gate line, an orthographic projection of the first gate line on the substrate extending along a first direction, and a portion of the first gate line being used to form a gate of the second transistor; a first conductive portion, wherein the first conductive portion is used to form a gate of the driving transistor; a first bridge portion, the first bridge portion being connected to the second electrode of the first transistor, the second electrode of the driving transistor, and the second electrode of the second transistor through via holes; a ninth bridge portion, the ninth bridge portion being connected to the first conductive portion and the first electrode of the second transistor through a through hole; An overlapping area of ​​an orthographic projection of the first bridging portion on the base substrate and an orthographic projection of the first gate line on the base substrate is a first overlapping area, an overlapping area of ​​an orthographic projection of the ninth bridging portion on the base substrate and an orthographic projection of the first gate line on the base substrate is a second overlapping area, and the first overlapping area is less than or equal to the second overlapping area.

2. The display panel according to claim 1, wherein The display panel further includes: a first reset signal line, wherein an orthographic projection of the first reset signal line on the substrate extends along the first direction, and a portion of the first reset signal line is used to form a gate of the first transistor; In the same pixel driving circuit, an orthographic projection of the first conductive portion on the base substrate is located between an orthographic projection of the first gate line on the base substrate and an orthographic projection of the first reset signal line on the base substrate; An orthographic projection of the first bridge portion on the base substrate is located between an orthographic projection of the first gate line on the base substrate and an orthographic projection of the first reset signal line on the base substrate.

3. The display panel according to claim 2, wherein: The display panel further includes a light-emitting unit, and the pixel driving circuit is used to drive the light-emitting unit to emit light; The pixel driving circuit further includes: a sixth transistor and a seventh transistor, wherein a first electrode of the sixth transistor is connected to the second electrode of the driving transistor, a second electrode of the sixth transistor is connected to the first electrode of the light-emitting unit, a first electrode of the seventh transistor is connected to the second initial signal line, and a second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit; The display panel further includes: a second reset signal line, an orthographic projection of the second reset signal line on the substrate extending along the first direction, and a portion of the second reset signal line forming a gate of the seventh transistor; an enable signal line, an orthographic projection of the enable signal line on the substrate extending along the first direction, and a partial structure of the enable signal line being used to form a gate of the sixth transistor; In the same pixel driving circuit, an orthographic projection of the second reset signal line on the base substrate and an orthographic projection of the enable signal line on the base substrate are located between an orthographic projection of the first conductive portion on the base substrate and an orthographic projection of the first reset signal line on the base substrate; The orthographic projection of the first bridge portion on the base substrate overlaps with the orthographic projection of the second reset signal line on the base substrate and the orthographic projection of the enable signal line on the base substrate.

4. The display panel according to claim 3, wherein: The second reset signal line includes a first extending portion and a second extending portion, wherein a width of an orthographic projection of the first extending portion on the base substrate is smaller than a width of an orthographic projection of the second extending portion on the base substrate; An orthographic projection of the first bridging portion on the base substrate extends along a second direction and intersects with an orthographic projection of the first extending portion on the base substrate, and the second direction intersects with the first direction.

5. The display panel according to claim 3, wherein: An orthographic projection of the second reset signal line on the base substrate is located between an orthographic projection of the first reset signal line on the base substrate and an orthographic projection of the enable signal line on the base substrate. The display panel according to claim 1 , wherein: The pixel driving circuit further includes: a fifth transistor, a first electrode of the fifth transistor being connected to a power line, and a second electrode of the fifth transistor being connected to the first electrode of the driving transistor; The display panel further includes: a first active layer located on one side of the base substrate, the first active layer comprising a first active portion, a third active portion, and a fifth active portion, the first active portion being used to form a channel region of the first transistor, the third active portion being used to form a channel region of the driving transistor, and the fifth active portion being used to form a channel region of the fifth transistor; In the same pixel driving circuit, in the first direction, the orthographic projection of the third active portion on the base substrate is located between the orthographic projection of the first active portion on the base substrate and the orthographic projection of the fifth active portion on the base substrate.

7. The display panel according to claim 1, wherein: The pixel driving circuit further includes: a fifth transistor, a first electrode of the fifth transistor being connected to a power line, and a second electrode of the fifth transistor being connected to the first electrode of the driving transistor; The display panel further includes: a first active layer located on one side of the base substrate, the first active layer comprising a third active portion and a fifth active portion, the third active portion being used to form a channel region of the driving transistor, and the fifth active portion being used to form a channel region of the fifth transistor; a second active layer, located on a side of the first active layer facing away from the base substrate, the second active layer comprising a second active portion, and the second active portion is used to form a channel region of the second transistor; In the same pixel driving circuit, in the first direction, the orthographic projection of the third active portion on the base substrate is located between the orthographic projection of the second active portion on the base substrate and the orthographic projection of the fifth active portion on the base substrate.

8. The display panel according to claim 1, wherein: The display panel further includes: a fourth conductive layer, located on one side of the base substrate, the fourth conductive layer including the ninth bridge portion; A fifth conductive layer is located on a side of the fourth conductive layer away from the base substrate, and at least a portion of the structure of the first bridging portion is located on the fifth conductive layer.

9. The display panel according to claim 8, wherein: The first bridging portion includes: a first sub-bridge portion, located in the fifth conductive layer; a second sub-bridging portion, located in the fourth conductive layer; a third sub-bridging portion, located in the fourth conductive layer; Among them, the second sub-bridge portion is connected to the second electrode of the second transistor and the second electrode of the driving transistor through vias, the third sub-bridge portion is connected to the second electrode of the first transistor through a via, and the first sub-bridge portion is connected to the second sub-bridge portion and the third sub-bridge portion through vias.

10. The display panel according to claim 8, wherein: The fifth conductive layer further includes: a first fan-out line, wherein an orthographic projection of the first fan-out line on the substrate extends along the first direction; The display panel further includes: a sixth conductive layer, located on a side of the fifth conductive layer facing away from the base substrate, the sixth conductive layer comprising a second fan-out line, an orthographic projection of the second fan-out line on the base substrate extending along a second direction, and the second direction intersecting the first direction; A data line is used to provide a data signal to the pixel driving circuit, the data line is connected to the first fan-out line, and the second fan-out line is connected to the first fan-out line.

11. The display panel according to claim 1, wherein: The display panel further includes: a fourth conductive layer, located on one side of the base substrate, the fourth conductive layer comprising a ninth bridge portion, the ninth bridge portion being connected to the first conductive portion and the first electrode of the second transistor through a through hole; The first bridge portion is located in the fourth conductive layer, and the first bridge portion is connected to the second electrode of the second transistor, the second electrode of the driving transistor, and the second electrode of the first transistor through via holes.

12. The display panel according to claim 11, wherein: The fourth conductive layer further includes: a first fan-out line, wherein an orthographic projection of the first fan-out line on the substrate extends along the first direction; The display panel further includes: a fifth conductive layer, located on a side of the fourth conductive layer facing away from the base substrate, the fifth conductive layer comprising a second fan-out line, an orthographic projection of the second fan-out line on the base substrate extending along a second direction, and the second direction intersecting the first direction; A data line is used to provide a data signal to the pixel driving circuit, the data line is connected to the first fan-out line, and the second fan-out line is connected to the first fan-out line.

13. The display panel according to claim 1, wherein: The display panel further includes: a second active layer located on one side of the base substrate, the second active layer comprising a second active portion, the second active portion being used to form a channel region of the second transistor; The first gate line includes any one of a first sub-gate line and a second sub-gate line, the first sub-gate line is located on the side of the second active portion facing away from the substrate, and a partial structure of the first sub-gate line is used to form the top gate of the second transistor, and the second sub-gate line is located between the second active portion and the substrate, and a partial structure of the second sub-gate line is used to form the bottom gate of the second transistor.

14. The display panel according to claim 2, wherein: The first reset signal line and the first initial signal line are located in different conductive layers. In the same pixel driving circuit, the orthographic projection of the first reset signal line on the base substrate and the orthographic projection of the first initial signal line on the base substrate at least partially overlap.

15. The display panel according to claim 1, wherein The display panel further includes a light-emitting unit, and the pixel driving circuit is used to drive the light-emitting unit to emit light; The pixel driving circuit further includes: a sixth transistor, a seventh transistor, and an eighth transistor, wherein a first electrode of the sixth transistor is connected to the second electrode of the driving transistor, a second electrode of the sixth transistor is connected to the first electrode of the light-emitting unit, a first electrode of the seventh transistor is connected to the second initial signal line, a second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit, a first electrode of the eighth transistor is connected to the third initial signal line, and a second electrode of the eighth transistor is connected to the first electrode of the driving transistor; The display panel further includes: a second reset signal line, an orthographic projection of the second reset signal line on the substrate extending along the first direction, and a portion of the second reset signal line forming a gate of the eighth transistor; an enable signal line, an orthographic projection of the enable signal line on the substrate extending along the first direction, and a partial structure of the enable signal line being used to form a gate of the sixth transistor; Wherein, the third initial signal line and the second reset signal line are located in different conductive layers, and the second initial signal line and the enable signal line are located in different conductive layers; In the same pixel driving circuit, the orthographic projection of the third initial signal line on the substrate and the orthographic projection of the second reset signal line on the substrate at least partially overlap. An orthographic projection of the second initial signal line on the base substrate and an orthographic projection of the enable signal line on the base substrate at least partially overlap.

16. The display panel according to claim 2, wherein: The display panel further includes a light-emitting unit, and the pixel driving circuit is used to drive the light-emitting unit to emit light; The pixel driving circuit further includes: a sixth transistor, a seventh transistor, and an eighth transistor, wherein a first electrode of the sixth transistor is connected to the second electrode of the driving transistor, a second electrode of the sixth transistor is connected to the first electrode of the light-emitting unit, a first electrode of the seventh transistor is connected to the second initial signal line, a second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit, a first electrode of the eighth transistor is connected to the third initial signal line, and a second electrode of the eighth transistor is connected to the first electrode of the driving transistor; The display panel further includes: a second reset signal line, an orthographic projection of the second reset signal line on the substrate extending along the first direction, and a portion of the second reset signal line forming a gate of the eighth transistor; an enable signal line, an orthographic projection of the enable signal line on the substrate extending along the first direction, and a partial structure of the enable signal line being used to form a gate of the sixth transistor; Wherein, the second initial signal line and the first reset signal line are located in different conductive layers, and the third initial signal line and the second reset signal line are located in different conductive layers; In the same pixel driving circuit, the orthographic projection of the first reset signal line on the substrate is located between the orthographic projection of the first initial signal line on the substrate and the orthographic projection of the first conductive portion on the substrate, the orthographic projection of the second initial signal line on the substrate and the orthographic projection of the first reset signal line on the substrate at least partially overlap, and the orthographic projection of the third initial signal line on the substrate and the orthographic projection of the second reset signal line on the substrate at least partially overlap.

17. The display panel according to claim 1, wherein: The display panel further includes a light-emitting unit, and the pixel driving circuit is used to drive the light-emitting unit to emit light. The pixel driving circuit further includes: a fourth transistor, a first electrode of which is connected to the data line, and a second electrode of which is connected to the first electrode of the driving transistor; A fifth transistor, a first electrode of which is connected to the first power line, and a second electrode of which is connected to the driving transistor First Pole; a sixth transistor, a first electrode of which is connected to the second electrode of the driving transistor, and a second electrode of which is connected to the first electrode of the light-emitting unit; a seventh transistor, a first electrode connected to the second initial signal line, and a second electrode connected to the first electrode of the light-emitting unit; an eighth transistor, a first electrode of which is connected to the third initial signal line, and a second electrode of which is connected to the first electrode of the driving transistor; a capacitor, a first electrode of which is connected to the gate of the driving transistor, and a second electrode of which is connected to the first power line; The first transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are P-type transistors, and the second transistor is an N-type transistor.

18. The display panel according to claim 1, wherein: The pixel driving circuit includes a P-type transistor and an N-type transistor, and the display panel further includes: a first active layer, located on one side of the base substrate, wherein a portion of the first active layer is used to form a channel region of a P-type transistor in the pixel driving circuit; a first conductive layer, located on a side of the first active layer facing away from the base substrate, wherein a portion of the first conductive layer is used to form a gate of a P-type transistor in the pixel driving circuit; a second conductive layer, located on a side of the first conductive layer away from the base substrate, wherein a portion of the second conductive layer is used to form a bottom gate of an N-type transistor in the pixel driving circuit; a second active layer, located on a side of the second conductive layer facing away from the base substrate, wherein a portion of the second active layer is used to form a channel region of an N-type transistor in the pixel driving circuit; a third conductive layer, located on a side of the second active layer facing away from the substrate, wherein a portion of the third conductive layer is used to form a top gate of an N-type transistor in the pixel driving circuit; The fourth conductive layer is located on a side of the third conductive layer away from the base substrate, and a portion of the structure of the fourth conductive layer is used to form a bridge portion connecting different transistors.

19. A display device, wherein: The display device comprises the display panel according to any one of claims 1 to 18.

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