Array substrate, display panel, and display apparatus

Abstract

An array substrate, a display panel, and a display apparatus. The array substrate comprises: a plurality of first light-shielding patterns (21) sequentially arranged at intervals in a first direction (X). At least one first light-shielding pattern (21) among the plurality of first light-shielding patterns (21) comprises: a plurality of first light-shielding main portions (211) and a plurality of first light-shielding connecting portions (212). In the same first light-shielding pattern (21), the first light-shielding main portions (211) and the first light-shielding connecting portions (212) are alternately arranged. A first electrode layer (3) comprises: first hollow portions (30). Each first hollow portion (30) comprises: a corner portion (G), wherein an orthographic projection of the corner portion (G) on a first substrate (1) is located between two adjacent first light-shielding connecting portions (212) in the first direction (X). Each first light-shielding main portion (211) is provided with a first outer edge (w1) extending in a second direction (Y), wherein the orthographic projection of an extension line of the first outer edge (w1) on the first substrate (1) and the orthographic projection of the corner portion (G) on the first substrate (1) have an overlapping area.

Description

Array substrate, display panel, and display device Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0002] Virtual reality technology seamlessly integrates real-world and virtual-world information. Compared to conventional display products, the most notable feature of VR display products is their ultra-high resolution. Liquid crystal display (LCD) technology is currently the best choice for achieving ultra-high resolution displays. This is because LCD display architectures use only a single switching transistor (TFT) in the pixel area, making it highly suitable for achieving high PPI.

[0003] Summary of the Invention

[0004] The present disclosure provides an array substrate, a display panel, and a display device. The array substrate includes:

[0005] a first substrate;

[0006] A first light-shielding layer is located on one side of the first substrate, and includes: a plurality of first light-shielding patterns arranged in sequence and spaced apart along a first direction; at least one of the plurality of first light-shielding patterns includes: a plurality of first light-shielding main portions and a plurality of first light-shielding connecting portions; in the same first light-shielding pattern, the first light-shielding main portions and the first light-shielding connecting portions are alternately arranged, and an extension direction of the first light-shielding connecting portions intersects an extension direction of the first light-shielding main portions; and two adjacent first light-shielding connecting portions in the first direction are spaced apart from each other;

[0007] a first electrode layer located on a side of the first light-shielding layer facing away from the first substrate; the first electrode layer comprising: a first hollow portion; the first hollow portion comprising: a corner portion, the orthographic projection of the corner portion on the first substrate being located between two adjacent first light-shielding connecting portions in the first direction;

[0008] The first light-shielding main portion has a first outer edge extending along a second direction, an orthographic projection of an extension line of the first outer edge on the first substrate has an overlapping area with an orthographic projection of the corner portion on the first substrate, and the second direction intersects with the first direction.

[0009] In a possible implementation manner, orthographic projections of the corner portions on the first substrate are all located between two adjacent first light-shielding connection portions in the first direction.

[0010] In a possible implementation manner, an orthographic projection of a portion of the first light-shielding connection portion on the first substrate overlaps with an orthographic projection of a portion of a boundary of the corner portion on the first substrate.

[0011] In a possible implementation manner, at least a portion of the end portion of the first light-shielding main portion is located within the orthographic projection of the corner portion on the first substrate when projected on the first substrate.

[0012] In a possible implementation manner, a maximum width of the first light-shielding connecting portion in the first direction is smaller than a maximum width of the first light-shielding main portion in the first direction.

[0013] In a possible implementation, the first light-shielding connection portion includes: a first sub-connection portion, a second sub-connection portion located on one side of the first sub-connection portion, and a third sub-connection portion located on the other side of the first sub-connection portion;

[0014] One end of the second sub-connection portion is connected to the first light-shielding main portion, and the other end is connected to one end of the first sub-connection portion;

[0015] One end of the third sub-connection portion is connected to another first light-shielding main portion, and the other end is connected to the other end of the first sub-connection portion.

[0016] In a possible implementation, the second sub-connection portion extends along the second direction; the first sub-connection portion and the third sub-connection portion extend along a third direction, wherein the third direction intersects with the first direction and the second direction.

[0017] In a possible implementation, the first sub-connection portion, the second sub-connection portion, and the third sub-connection portion all extend along a third direction, wherein the third direction intersects with the first direction and the second direction.

[0018] In a possible implementation, the first electrode layer further includes: a first electrode portion; an orthographic projection of the first electrode portion on the first substrate is complementary to an orthographic projection of the first hollow on the first substrate;

[0019] An orthographic projection of the first electrode portion on the first substrate covers an orthographic projection of the first light-shielding pattern on the first substrate.

[0020] In one possible embodiment, the plurality of first light-shielding patterns include: a plurality of first light-shielding main portion rows; at least one of the plurality of first light-shielding main portion rows includes: a plurality of first light-shielding main portions arranged sequentially along the first direction; the plurality of first hollows include: a plurality of first hollow rows; at least one of the plurality of first hollow rows includes: a plurality of first hollows arranged sequentially along the first direction; an orthographic projection of the Nth first light-shielding main portion row on the substrate has an overlapping area with an orthographic projection of the Nth hollow row on the first substrate;

[0021] The first hollowing includes: a first sub-hollowing portion, a second sub-hollowing portion, and a third sub-hollowing portion; the second sub-hollowing portion of the Nth hollowing row is located on the side of the first sub-hollowing portion facing the N-1th hollowing row; the third sub-hollowing portion of the Nth hollowing row is located on the side of the first sub-hollowing portion facing the N+1th hollowing row; the extension direction of the second sub-hollowing portion intersects with the extension direction of the first sub-hollowing portion, and the extension direction of the third sub-hollowing portion intersects with the extension direction of the first sub-hollowing portion;

[0022] The orthographic projection of the extended line of the first outer edge of the first light-shielding main part in the Nth row of the first light-shielding main parts on the first substrate overlaps with the orthographic projection of the third sub-hollow part of the Nth hollow row on the first substrate, and overlaps with the orthographic projection of the second sub-hollow part of the N+1th hollow row on the first substrate.

[0023] In a possible implementation, the array substrate further includes: a second electrode layer located on a side of the first light shielding layer facing the first substrate;

[0024] The second electrode layer includes: a plurality of second electrode rows extending along the first direction and arranged along the second direction; at least one second electrode row among the plurality of second electrode rows includes: a plurality of second electrodes; the orthographic projection of the second electrode on the first substrate is a rectangle.

[0025] In one possible embodiment, the orthographic projection of the Nth row of second electrodes on the first substrate has an overlapping area with the orthographic projection of the Nth hollow row on the first substrate, and the orthographic projection of the second electrode of the Nth row of second electrodes on the first substrate covers at least part of the orthographic projection of the second sub-hollow portion of the Nth hollow row on the first substrate, where N is a positive integer greater than or equal to 1.

[0026] In one possible embodiment, the second electrode of the Nth second electrode row has a second outer edge close to the N-1th second electrode row and extending along the first direction; the second sub-hollow portion of the Nth hollow row has a third outer edge extending along the first direction; the orthographic projection of the second outer edge on the first substrate is located on the side of the orthographic projection of the third outer edge on the first substrate facing the N-1th second electrode row.

[0027] In a possible implementation manner, the second electrode includes: a second electrode main portion, and a second electrode extension portion connected to the second electrode main portion;

[0028] The orthographic projection of the second electrode extension portion on the first substrate covers at least a portion of the orthographic projection of the second sub-hollow portion on the first substrate.

[0029] In a possible implementation manner, an extending direction of the second electrode extension portion is the same as an extending direction of the second sub-hollow portion.

[0030] In a possible implementation manner, a line width of the second electrode extension portion in a direction perpendicular to the extension direction is smaller than a width of the second sub-hollow portion in the direction perpendicular to the extension direction.

[0031] In a possible implementation manner, an orthographic projection of the second electrode main portion on the first substrate and an orthographic projection of the second sub-hollow portion on the first substrate do not overlap with each other.

[0032] In a possible implementation, the array substrate further includes: an active layer located between the second electrode layer and the first substrate, and a first insulating layer located between the second electrode layer and the active layer; the first insulating layer has a first via hole, and the second electrode is electrically connected to a portion of the active layer at least through the first via hole;

[0033] The array substrate further includes a second insulating layer filled in the first via hole.

[0034] In a possible implementation manner, an orthographic projection of the first via hole on the first substrate and an orthographic projection of the first light-shielding connection portion on the first substrate have an overlapping area.

[0035] In a possible implementation, the array substrate further includes: a third electrode layer located between the active layer and the second electrode layer, and a third insulating layer located between the third electrode layer and the active layer; the third electrode layer includes: a plurality of third electrodes; and the third insulating layer has a second via hole.

[0036] The second electrode is electrically connected to the third electrode through the first via hole, and the third electrode is electrically connected to the active layer through the second via hole.

[0037] In a possible implementation, the array substrate further includes: a first signal line extending along the first direction, and a second signal line extending along the second direction;

[0038] The orthographic projection of the first light-shielding main portion on the first substrate is located between the orthographic projections of two adjacent first signal lines on the first substrate, and the orthographic projection of the first light-shielding main portion on the first substrate has an overlapping area with the orthographic projection of the second signal line on the first substrate.

[0039] In one possible embodiment, in the same first light-shielding pattern, the orthographic projection of the Tth first light-shielding main portion along the second direction on the first substrate overlaps with the orthographic projection of the Jth second signal line along the first direction on the first substrate; the orthographic projection of the T+1th first light-shielding main portion along the second direction on the first substrate overlaps with the orthographic projection of the J+1th second signal line along the first direction on the first substrate, where T is a positive integer greater than or equal to 1, and J is a positive integer greater than or equal to 1.

[0040] In a possible implementation manner, an orthographic projection of the first light-shielding connection portion on the first substrate and an orthographic projection of the first signal line on the first substrate have an overlapping area.

[0041] In a possible implementation manner, at least a portion of an orthographic projection of the first light-shielding connection portion on the first substrate does not overlap with an orthographic projection of the second signal line on the first substrate.

[0042] In a possible implementation manner, an orthographic projection of the first hollow on the first substrate and an orthographic projection of the second signal line on the first substrate have an overlapping area.

[0043] In a possible embodiment, the array substrate further includes: a second light-shielding layer; the second light-shielding layer includes: a second light-shielding pattern extending along the first direction; an orthographic projection of the second light-shielding pattern on the first substrate covers an orthographic projection of the first signal line on the first substrate;

[0044] An orthographic projection of the first light-shielding main portion on the first substrate is located between two adjacent orthographic projections of the second light-shielding patterns on the first substrate.

[0045] In a possible implementation manner, the length of the first light-shielding main portion in the second direction is equal to the distance between two adjacent second light-shielding patterns in the second direction.

[0046] In a possible implementation, the second signal line is located between the third electrode layer and the active layer; the first signal line is located between the layer where the second signal line is located and the active layer; the third insulating layer includes: a first sub-insulating layer located between the first signal line and the active layer, and a second sub-insulating layer located between the first signal line and the second signal line;

[0047] The active layer includes: a first portion extending along the second direction, and a second portion extending from one end of the first portion; the first portion, in an orthographic projection on the first substrate, has a first overlapping area with the orthographic projection of the third electrode on the substrate, and is electrically connected to the third electrode through the second via in the first overlapping area; the second portion, in an orthographic projection on the first substrate, has a second overlapping area with the orthographic projection of the second signal line on the first substrate, and is electrically connected to the second signal line through a third via that penetrates the first sub-insulating layer and the second sub-insulating layer in the second overlapping area.

[0048] In a possible implementation, the array substrate further includes: a color filter layer located on a side of the second electrode layer facing the first substrate;

[0049] The color filter layer includes: a first color resistance portion, a second color resistance portion, and a third color resistance portion.

[0050] The embodiment of the present disclosure further provides a display panel, which includes the array substrate provided in the embodiment of the present disclosure, and also includes an opposite substrate arranged opposite to the array substrate.

[0051] In a possible implementation, the counter substrate includes: a second substrate, and a light shielding structure located on a side of the second substrate facing the first substrate;

[0052] The light-shielding structure includes: a first film layer, and a second film layer located on the side of the light-shielding layer facing the second substrate; the first film layer is a metal layer, and the second film layer includes at least a non-metal layer.

[0053] In one possible embodiment, the second film layer includes a first sub-film layer stacked in sequence, a second sub-film layer located on the side of the first sub-film layer facing the array substrate, and a third sub-film layer located on the side of the second sub-film layer facing the array substrate; wherein, the first sub-film layer and the third sub-film layer are non-metallic layers, and the second sub-film layer is a metal layer.

[0054] In a possible implementation, the second film layer includes: an organic film layer; the thickness of the organic film layer is smaller than the thickness of the first film layer.

[0055] An embodiment of the present disclosure further provides a display device, which includes the display panel provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] FIG1 is a schematic diagram of an array substrate according to an embodiment of the present disclosure;

[0057] FIG2 is a second schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0058] FIG3 is a third schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0059] FIG4A is a fourth schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0060] FIG4B is one of the schematic diagrams of the first hollowing design provided by an embodiment of the present disclosure;

[0061] FIG4C is a fifth schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0062] FIG4D is a schematic diagram of a stack of a first light shielding layer and a first electrode layer according to an embodiment of the present disclosure;

[0063] FIG5 is a sixth schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0064] FIG6A is one of the cross-sectional schematic diagrams along the dotted line A1A2 in FIG8A ;

[0065] FIG6B is a schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure;

[0066] FIG6C is a second schematic cross-sectional view of an array substrate provided in an embodiment of the present disclosure;

[0067] FIG7A is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure;

[0068] FIG7B is a second schematic cross-sectional view of a display panel provided in an embodiment of the present disclosure;

[0069] FIG8A is a schematic diagram of a structure of an array substrate according to an embodiment of the present disclosure;

[0070] FIG8B is a schematic diagram of a single film layer where the second light-shielding pattern in FIG8A is located;

[0071] FIG8C is a schematic diagram of a single film layer of the active layer in FIG8A;

[0072] FIG8D is a schematic diagram of a single film layer where the first signal line is located in FIG8A;

[0073] FIG8E is a schematic diagram of a single film layer where the second signal line is located in FIG8A ;

[0074] FIG8F is a schematic diagram of a single film layer of the third electrode layer in FIG8A ;

[0075] FIG8G is a schematic diagram of a single film layer of the second electrode layer in FIG8A ;

[0076] FIG8H is a schematic diagram of a single film layer of the light shielding layer in FIG8A;

[0077] FIG8I is a schematic diagram of a single film layer of the first electrode layer in FIG8A ;

[0078] FIG8J is a schematic diagram of the structure of an array substrate provided with a color filter layer;

[0079] FIG8K is a schematic diagram of a single film layer of the color filter layer in FIG8J ;

[0080] FIG9 is a seventh schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0081] FIG10 is an eighth schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0082] FIG11A is a schematic diagram of light effects corresponding to a conventional array substrate;

[0083] FIG11B is a schematic diagram of light effects corresponding to the array substrate corresponding to FIG1 ;

[0084] FIG11C is a schematic diagram of light effects corresponding to the array substrate corresponding to FIG4A ;

[0085] FIG11D is a schematic diagram of light effects corresponding to the array substrate corresponding to FIG5 ;

[0086] FIG. 11E is a schematic diagram of light effects corresponding to the array substrate of FIG. 4C . DETAILED DESCRIPTION

[0087] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other in any way.

[0088] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0089] In this specification, ordinal numbers such as "first", "second", and "third" are provided to avoid confusion among constituent elements, rather than to limit the quantity. The "plurality" in this disclosure may include two or more.

[0090] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which the constituent elements are described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0091] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the specific circumstances.

[0092] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with one or more functions.

[0093] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode (gate), a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0094] In this specification, in order to distinguish the two electrodes of a transistor other than the gate electrode, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode. The first electrode can be a source electrode or a drain electrode, and the second electrode can be a drain electrode or a source electrode. In addition, the gate electrode of a transistor can be referred to as a control electrode. In cases where transistors with opposite polarity are used or where the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" can be interchanged.

[0095] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus includes a state where the angle is greater than 85° and less than 95°.

[0096] In this specification, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0097] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0098] In this specification, "approximately" and "substantially" are used without strict limits and allow for process and measurement errors. In this specification, "substantially the same" may refer to values ​​that differ by less than 10%.

[0099] To provide a better immersive experience and reduce the screen door effect in the use of virtual reality (VR) technology, the resolution (Pixels Per Inch, PPI) of VR products has been continuously improved. However, the higher the PPI, the smaller the pixel size, and the lower the transmittance of the display panel. Therefore, the demand for improved transmittance is becoming more and more urgent.

[0100] In view of this, an embodiment of the present disclosure provides an array substrate, as shown in FIG1 , wherein the array substrate includes:

[0101] a first substrate 1;

[0102] The first light-shielding layer 2 is located on one side of the first substrate 1 and includes: a plurality of first light-shielding patterns 21 arranged in sequence and spaced apart along the first direction X; at least one of the plurality of first light-shielding patterns 21 includes: a plurality of first light-shielding main portions 211 and a plurality of first light-shielding connecting portions 212; within the same first light-shielding pattern 21, the first light-shielding main portions 211 and the first light-shielding connecting portions 212 are alternately arranged, and the extension direction of the first light-shielding connecting portions 212 intersects the extension direction of the first light-shielding main portions 211; and two adjacent first light-shielding connecting portions 212 in the first direction X are spaced apart from each other;

[0103] The first electrode layer 3 is located on a side of the first light-shielding layer 2 facing away from the first substrate 1. The first electrode layer 3 includes a first hollow 30. The first hollow 30 includes a corner portion G. The corner portion G is located between two adjacent first light-shielding connecting portions 212 in the first direction X in the orthographic projection of the first substrate 1. Optionally, as shown in FIG5 , the first hollow 30 may include a first sub-hollow portion 301, a second sub-hollow portion 302, and a third sub-hollow portion 303. The corner portion G may include a second sub-hollow portion 302 and a third sub-hollow portion 303.

[0104] The first light-shielding main portion 211 has a first outer edge w1 extending along a second direction Y. The orthographic projection of the extension line of the first outer edge w1 on the first substrate 1 overlaps with the orthographic projection of the corner portion G on the first substrate 1. The second direction Y intersects the first direction X. Optionally, the second direction Y is perpendicular to the first direction X.

[0105] In the embodiment of the present disclosure, the first light-shielding layer 2 includes a plurality of first light-shielding patterns 21; the first light-shielding pattern 21 includes a first light-shielding main portion 211 and a first light-shielding connecting portion 212 alternately arranged along the second direction Y, the extension direction of the first light-shielding connecting portion 212 intersects with the extension direction of the first light-shielding main portion 211, and the first light-shielding main portion 211 has a first outer edge w1 extending along the second direction Y, the orthographic projection of the extension line of the first outer edge w1 on the first substrate 1 has an overlapping area with the orthographic projection of the corner portion G on the first substrate 1, and at least part of the orthographic projection of the first light-shielding connecting portion 212 does not overlap with the orthographic projection of the first hollow 30, that is, the first light-shielding pattern 21 adopts a bending design to avoid the area of ​​the first hollow 30, thereby reducing the influence of the first light-shielding layer 2 on the electric field driving the liquid crystal deflection, and can optimize the dark area in the sub-pixel area and improve the transmittance.

[0106] Specifically, the first light-shielding main portion 211 can extend along the second direction Y, the portion of the first light-shielding pattern 21 extending along the second direction Y can be used as the first light-shielding main portion 211, and the portion connecting two adjacent first light-shielding main portions 211 can be used as the first light-shielding connecting portion 212.

[0107] As shown in FIG11A , in a conventional array substrate structure, the first light-shielding pattern is linear and extends vertically along the second direction. This first light-shielding pattern design, due to the overlap with the hollowed-out area in the first electrode layer and the effect of the fringe electric field of the pixel electrode layer, results in a large dark area in the sub-pixel opening area. Dark areas exist in the upper left and lower right corners of the sub-pixel opening area, such as the areas S1 and S2 in FIG11A . The dark areas are caused by the opposite deflection directions of the liquid crystal in these areas, resulting in the inability of the liquid crystal molecules in these areas to deflect, thereby forming dark areas. In the embodiment of the present disclosure, by providing the array substrate structure as shown in FIG1 , that is, by providing the first light-shielding pattern as a curved strip, the first light-shielding pattern 21 of each strip is spaced apart from each other, and at least a portion of the first light-shielding connection portion 212 avoids overlapping with the first hollowed-out area in the first electrode layer, the dark area at position S2 in the sub-pixel opening area can be improved, as shown in FIG11B .

[0108] In a possible implementation, each of the first light-shielding patterns 21 may be strip-shaped, extending as a whole along the second direction Y, and may not be connected to each other in the first direction X.

[0109] In one possible embodiment, the first light-shielding layer 2 may be a film layer located on the side of the first electrode layer 3 facing away from the first substrate 1 and in direct contact with the first electrode layer 3; in one possible embodiment, the first light-shielding layer 2 may be a metal layer, which, on the one hand, can serve to shield light and prevent cross-color between adjacent sub-pixels, thereby reducing the level of cross-color between adjacent sub-pixels without increasing the black matrix opening; on the other hand, the first light-shielding layer 2 is a metal layer, which can reduce the resistance of the first electrode layer 3.

[0110] In a possible embodiment, when the first light-shielding layer 2 is a metal layer, the material of the first light-shielding layer 2 may include: any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), black chromium (Cr) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, etc.;

[0111] In a possible implementation, the material of the first light-shielding layer 2 may also be non-metallic. For example, the first light-shielding layer 2 may be a film layer coated with black pigment, such as a film layer made of the same material as the black matrix.

[0112] In one possible embodiment, the first electrode layer 3 may be a common electrode layer, and the first electrode layer 3 may be a transparent electrode layer; in one possible embodiment, the material of the first electrode layer 3 may include: metal oxide (for example, indium tin oxide, indium-doped zinc oxide (AZO), fluorine-doped tin oxide (AZO), aluminum-doped zinc oxide (AZO), indium-doped cadmium oxide).

[0113] In one possible embodiment, as shown in FIG1 , adjacent first light-shielding connecting portions 212 are spaced apart in the second direction Y, e.g., separated by the first light-shielding main portion 211. The orthographic projection of the first hollow 30 on the first substrate 1 does not overlap with the orthographic projection of the entire first light-shielding connecting portion 212 on the first substrate 1. This prevents the orthographic projection of the first light-shielding connecting portion 212 from overlapping with the orthographic projection of the first hollow 30, thereby further avoiding the area of ​​the first hollow 30 and significantly improving transmittance.

[0114] In one possible embodiment, as shown in FIG1 , the orthographic projection of the corner portion G on the first substrate 1 is entirely located between two adjacent first light-shielding connecting portions 211 in the first direction X. That is, the orthographic projection of the first hollow 30 on the first substrate 1 does not overlap with the orthographic projection of the first light-shielding main portion 211 on the first substrate 1. In other words, the orthographic projection of the entire first light-shielding pattern 21 on the first substrate 1 does not overlap with the orthographic projection of the first hollow 30 on the first substrate 1. This prevents the orthographic projection of the entire first light-shielding pattern 21 from overlapping with the orthographic projection of the first hollow 30, thereby minimizing the need to avoid the area of ​​the first hollow 30 and maximizing transmittance.

[0115] In a possible embodiment, the orthographic projection of the corner portion G on the first substrate 1 may also be partially located between two adjacent first light-shielding connection portions 211 in the first direction X. As shown in Figure 2, the orthographic projection of a portion of the first light-shielding connection portion 212 on the first substrate 1 overlaps with the orthographic projection of a portion of the boundary of the corner portion G on the first substrate 1.

[0116] In a possible implementation, as shown in FIG. 2 , at least a portion of the end portion of the first light-shielding main portion 211 is orthographically projected on the first substrate 1 and is located within the orthographic projection of the corner portion G on the first substrate 1 .

[0117] In one possible embodiment, as shown in FIG1 , the first light-shielding main portion 211 extends along the second direction Y. The first light-shielding main portion 211 has a first outer edge w1 extending along the second direction Y. Furthermore, within the same first light-shielding pattern 21, the extension lines of the first outer edges w1 of two adjacent first light-shielding main portions 211 do not overlap. That is, due to the overall meandering distribution of the first light-shielding pattern 21, the two adjacent first light-shielding main portions 211 do not extend in the same direction.

[0118] In a possible implementation, as shown in FIG. 1 , in the same first light-shielding pattern 21 , each first light-shielding main portion 211 is along the second direction Y, but the extension directions of at least two adjacent first light-shielding main portions 211 do not overlap.

[0119] As shown in Figure 1, since the shape of the first hollow 30 is usually a bent shape, it extends in two opposite directions at the two ends, thereby occupying a larger space in the first direction X. In a possible implementation, in the embodiment of the present disclosure, the maximum width a1 of the first light-shielding connection portion 212 in the first direction X is smaller than the maximum width a2 of the first light-shielding main portion 211 in the first direction X, that is, the line width of the first light-shielding pattern 21 in the area where the end of the first hollow 30 is located is reduced. In this way, the first light-shielding pattern 21 can be avoided from overlapping with the first hollow portion 30 at its end, thereby improving the transmittance of the display panel.

[0120] In a possible embodiment, referring to FIG1 , the first light-shielding connection portion 212 includes: a first sub-connection portion L1, a second sub-connection portion L2 located on one side of the first sub-connection portion L1, and a third sub-connection portion L3 located on the other side of the first sub-connection portion L1; one end of the second sub-connection portion L2 is connected to a first light-shielding main portion 211, for example, as shown in FIG1 , connected to an upper first light-shielding main portion 211, and the other end is connected to one end of the first sub-connection portion L2, for example, as shown in FIG1 , connected to an upper end of the first sub-connection portion L2; one end of the third sub-connection portion L3 is connected to another first light-shielding main portion 211, for example, as shown in FIG1 , connected to a next first light-shielding main portion 211, and the other end is connected to the other end of the first sub-connection portion L1, for example, as shown in FIG1 , connected to a lower end of the first sub-connection portion L2.

[0121] In a possible embodiment, as shown in Figure 1, the extension directions of the first sub-connection portion L1, the second sub-connection portion L2, and the third sub-connection portion L3 do not overlap with each other, so as to completely avoid the end of the first hollow portion 30, thereby preventing the first shading pattern 21 from overlapping with the first hollow portion 30 at the end thereof, thereby improving the transmittance of the display panel.

[0122] In a possible embodiment, referring to Figure 1, the second sub-connection portion L2 extends along the second direction Y; the first sub-connection portion L1 and the third sub-connection portion L3 extend along the third direction Z, wherein the third direction Z intersects the first direction X and the second direction X, and the first sub-connection portion L1 can extend along the second direction Y; the first angle α1 formed by the second sub-connection portion L2 and the first sub-connection portion L1 can be 35° to 60°, for example, it can be 35°, 40°, 45°, 50°, 55°, 60°; the second angle α2 formed by the third sub-connection portion L3 and the first sub-connection portion L1 can be 35° to 60°, for example, it can be 35°, 40°, 45°, 50°, 55°, 60°; but the second sub-connection portion L2 and the third sub-connection portion L3 are respectively located on different sides of the first sub-connection portion L1. Optionally, the angle formed by the third direction Z and the second direction Y may be 35° to 60°, for example, 35°, 40°, 45°, 50°, 55°, or 60°;

[0123] In a possible embodiment, as shown in Figure 2, the first sub-connection portion L1, the second sub-connection portion L2, and the third sub-connection portion L3 all extend along the third direction Z, wherein the third direction Z intersects with the first direction X and the second direction Y, and the extension directions of the first sub-connection portion L1, the second sub-connection portion L2, and the third sub-connection portion L3 may also coincide, that is, the third angle α3 formed by the three and the first light-shielding main portion 211 can be 35°~60°, for example, it can be 35°, 40°, 45°, 50°, 55°, or 60°.

[0124] In one possible embodiment, as shown in FIG3 , the first light-shielding pattern 21 may also include only first light-shielding main portions 211. Within the same first light-shielding pattern 21, the first light-shielding main portions 211 are spaced apart and disconnected from one another. This prevents overlap between the first light-shielding pattern 21 and the first hollow portion 30, thereby increasing the transmittance of the display panel.

[0125] In a possible embodiment, referring to FIG1 , the first electrode layer 3 further includes: a first electrode portion 31; an orthographic projection of the first electrode portion 31 on the first substrate 1 is complementary to an orthographic projection of the first hollowing out 30 on the first substrate 1, that is, a part of the first electrode layer 3 is hollowed out, the hollowed-out area serves as the first hollowing out 30, and the remaining part serves as the first electrode portion 31; the orthographic projection of the first electrode portion 31 on the first substrate 1 covers the orthographic projection of the first shading pattern 21 on the first substrate 1, and the orthographic projection of the first shading pattern 21 on the first substrate 1 can be located within the orthographic projection of the first electrode portion 31 on the first substrate 1.

[0126] In a possible embodiment, referring to FIG4D , the plurality of first light-shielding patterns 21 include: a plurality of first light-shielding main portion rows 200; at least one of the plurality of first light-shielding main portion rows 200 includes: a plurality of first light-shielding main portions 211 arranged sequentially along the first direction; the array substrate may include a plurality of first hollow rows 300 extending along the first direction X and arranged sequentially along the second direction Y; at least one of the plurality of first hollow rows 300 includes: a plurality of first hollows 30 arranged sequentially along the first direction X; the first hollow 30 includes: a first sub-hollow portion 301, a second sub-hollow portion 302, and a third sub-hollow portion 303; the extension direction of the second sub-hollow portion 302 is the same as that of the first hollow portion 301; The extension direction of the sub-hollow portion 301 intersects, the extension direction of the third sub-hollow portion 303 intersects with the extension direction of the first sub-hollow portion 301, and the extension directions of the first sub-hollow portion 301, the second sub-hollow portion 302, and the third sub-hollow portion 303 are different; the second sub-hollow portion 302 of the Nth hollow row 300 is located on the side of the first sub-hollow portion 301 facing the N-1th hollow row 300; the third sub-hollow portion 303 of the Nth hollow row 300 is located on the side of the first sub-hollow portion 301 facing the N+1th hollow row 300, that is, in the Nth hollow row 300, the second sub-hollow portion 302 is located on the upper side of the first sub-hollow portion 301, and the third sub-hollow portion 303 is located on the lower side of the first sub-hollow portion 301;

[0127] The orthographic projection of the first outer edge extension line w1 of the first light-shielding main portion 211 in the Nth first light-shielding main portion row 200 on the first substrate 1 overlaps with the orthographic projection of the third sub-hollow portion 303 of the Nth hollow row 300 on the first substrate 1, and overlaps with the orthographic projection of the second sub-hollow portion 302 of the N+1th hollow row 300 on the first substrate 1.

[0128] In a possible implementation, the (N+1)th hollowed-out row 300 may be the next hollowed-out row 300 after the (N)th hollowed-out row 300 in the gate signal scanning direction.

[0129] In a possible embodiment, referring to FIG. 4B , the angle θ1 formed between the first hollow 30 and the first direction X may be 80° to 100°, for example, 80°, 85°, 90°, 95°, or 100°; in a possible embodiment, referring to FIG. 4B , the angle θ2 formed between the second sub-hollow portion 302 and the first sub-hollow portion 301 may be 140° to 145°, for example, 140°, 141°, 142°, 4B , the angle θ3 formed between the third sub-hollow portion 303 and the first sub-hollow portion 301 may be 140° to 145°, for example, 140°, 141°, 142°, 143°, 144°, or 145°; in a possible embodiment, referring to FIG. 4B , the length h1 of the second sub-hollow portion 302 in the second direction Y may range from 1.5 μm to 3 μm, for example, 1.5 μm, 2.0 μm, 2.5 μm, or 3 μm; in a possible embodiment, referring to FIG. In the formula, referring to Figure 4B, the length h2 of the third sub-hollow portion 303 in the second direction Y can range from 1.5μm to 3μm, for example, it can be 1.5μm, 2.0μm, 2.5μm, or 3μm; in one possible embodiment, the angle θ2 formed by the second sub-hollow portion 302 and the first sub-hollow portion 301, and the angle θ3 formed by the third sub-hollow portion 303 and the first sub-hollow portion 301 can be equal; in one possible embodiment, the length h1 of the second sub-hollow portion 302 in the second direction Y, and the length h2 of the third sub-hollow portion 303 in the second direction Y can be equal. Among them, the angle θ2 formed by the second sub-hollow portion 302 and the first sub-hollow portion 301, the angle θ3 formed by the third sub-hollow portion 303 and the first sub-hollow portion 301, the length h1 of the second sub-hollow portion 302 in the second direction Y, and the length h2 of the third sub-hollow portion 303 in the second direction Y can characterize the morphology of the corners of the first hollow 30 at the upper and lower positions, and the above design can be carried out by comprehensively considering the scratches (trace mura) and the corner morphology.

[0130] In one possible embodiment, as shown in FIG4A , the array substrate further includes: a second electrode layer 4 located on the side of the first light shielding layer 2 facing the first substrate 1; the second electrode layer 4 includes: a plurality of second electrode rows 400 extending along the first direction X and arranged along the second direction Y; at least one second electrode row 400 of the plurality of second electrode rows 400 includes: a plurality of second electrodes 41;

[0131] The orthographic projection of the Mth second electrode row 400 on the first substrate 1 has an overlapping area with the orthographic projection of the Nth hollow row 300 on the first substrate 1, that is, the Mth second electrode row 400 and the Nth hollow row 300 may be located in the same row; the orthographic projection of the second electrode 41 of the Mth second electrode row 400 on the first substrate 1 covers at least part of the orthographic projection of the second sub-hollow portion 302 of the Nth hollow row on the first substrate 1, wherein M is a positive integer greater than or equal to 1, and N is a positive integer greater than or equal to 1.

[0132] In the embodiment of the present disclosure, the orthographic projection of the second electrode 41 of the Mth second electrode row 400 on the first substrate 1 covers at least a portion of the orthographic projection of the second sub-hollow portion 302 of the Nth hollow row on the first substrate 1. That is, the second electrode layer 4 is moved upward relative to the first electrode layer 3 so that the second electrode 41 covers at least a portion of the second sub-hollow portion 302. In this way, the electric field is moved outward, and the dark area is moved outside the sub-pixel opening area, thereby reducing the dark area in the sub-pixel area and improving the transmittance. Specifically, in conjunction with Figure 11C, the embodiment of the present disclosure, by providing the array substrate structure shown in Figure 4A, that is, moving the second electrode layer 4 upward, can improve the dark area at the S1 position, thereby improving the transmittance of the display panel. Specifically, the transmittance of the display panel can be increased by 8%.

[0133] In a possible implementation, the (M+1)th second electrode row 400 may be the next second electrode row 400 following the (M)th second electrode row 400 in the gate signal scanning direction.

[0134] In one possible embodiment, the second electrode layer 4 may be a pixel electrode layer; in one possible embodiment, the second electrode layer 4 may be a transparent electrode layer; in one possible embodiment, the material of the second electrode layer 4 may include: metal oxide (for example, indium tin oxide, indium-doped zinc oxide (AZO), fluorine-doped tin oxide (AZO), aluminum-doped zinc oxide (AZO), indium-doped cadmium oxide).

[0135] In a possible implementation, referring to FIG. 4A , the orthographic projection of the second electrode 41 on the first substrate 1 is a rectangle.

[0136] In a possible implementation, as shown in FIG. 4A , the length of the second electrode 41 in the second direction Y may be greater than the length in the first direction X.

[0137] In a possible implementation, as shown in FIG. 4A , a length d1 of the second electrode 41 in the second direction Y may be substantially equal to a length d2 of the first hollow 30 in the second direction Y.

[0138] In a possible implementation, as shown in FIG. 4A , the orthographic projection of the second electrode 42 on the first substrate 1 may cover the orthographic projection of the first sub-hollow portion 301 on the first substrate 1 .

[0139] In one possible embodiment, as shown in FIG4A , the second electrode 41 of the Mth second electrode row 400 has a second outer edge w2 proximate to the M-1th second electrode row 400 and extending along the first direction X. The second sub-hollow portion 302 of the Nth hollow row 300 has a third outer edge w3 extending along the first direction X. The orthographic projection of the second outer edge w2 of the Mth second electrode row 400 on the first substrate 1 is located on the side of the orthographic projection of the third outer edge w3 of the Nth hollow row 300 on the first substrate 1 facing the N-1th second electrode row 400. In this way, the electric field can be shifted outward, the dark area can be moved outside the subpixel opening area, the dark area in the subpixel region can be reduced, and the transmittance of the display panel can be improved.

[0140] In a possible implementation, the orthographic projection of the second outer edge w2 of the Mth second electrode row 400 on the first substrate 1 may coincide with the orthographic projection of the third outer edge w3 of the Nth hollow row 300 on the first substrate 1 .

[0141] In one possible embodiment, the orthographic projection of the second outer edge w2 of the Mth second electrode row 400 on the first substrate 1 can be located on the side of the first corner facing the N-1th second electrode row 400, wherein the first corner can be the position where the first sub-hollow portion 301 and the second sub-hollow portion 302 are connected.

[0142] In a possible embodiment, referring to FIG5 , the second electrode 41 includes: a second electrode main portion 411, and a second electrode extension portion 412 connected to the second electrode main portion 411; the second electrode extension portion 412 is an orthographic projection of the first substrate 1, covering at least a portion of the orthographic projection of the second sub-hollow portion 302 on the first substrate 1. In the embodiment of the present disclosure, by providing the second electrode extension portion 412 at one end of the second electrode main portion 411, it is also possible to achieve the outward shift of the electric field that will form the dark area, thereby moving the dark area to the outside of the sub-pixel opening area, reducing the dark area in the sub-pixel area, and improving the transmittance of the display panel. Specifically, in combination with FIG11D , the embodiment of the present disclosure can improve the dark area at the S1 position by providing the array substrate structure shown in FIG5 , that is, by moving the second electrode layer 4 upward, thereby improving the transmittance of the display panel. Specifically, the transmittance of the display panel can be increased by 3%.

[0143] In one possible implementation, as shown in FIG5 , the extension direction of the second electrode extension portion 412 is the same as the extension direction of the second sub-hollow portion 302. In the disclosed embodiment, setting the extension direction of the second electrode extension portion 412 to be substantially the same as the extension direction of the second sub-hollow portion 302 allows the second electrode extension portion 412 to avoid the location of some via holes (for example, as shown in FIG5 , a via hole connecting the second electrode 41 to the active layer is provided directly above the second electrode 41), thereby avoiding affecting the flatness of the second electrode 41 and, in turn, preventing an impact on the display effect.

[0144] In one possible embodiment, as shown in FIG5 , the line width b1 of the second electrode extension 412 in the direction perpendicular to the extension direction is smaller than the width b2 of the second sub-hollow portion 302 in the direction perpendicular to the extension direction. In the disclosed embodiment, by setting the line width b1 of the second electrode extension 412 smaller in the direction perpendicular to the extension direction, the second electrode extension 412 can avoid the location of some vias (for example, as shown in FIG5 , a via connecting the second electrode 41 to the active layer is located directly above the second electrode 41), thereby avoiding affecting the flatness of the second electrode 41 and, in turn, the display effect.

[0145] In one possible embodiment, as shown in FIG5 , the orthographic projection of the second electrode main portion 411 on the first substrate 1 does not overlap with the orthographic projection of the second sub-hollow portion 302 on the first substrate 1. In other words, in the disclosed embodiment, rather than moving the second electrode layer 4 upward as a whole, the electric field forming the dark region can be shifted outward by providing the second electrode extension portion 412, thereby improving the transmittance of the display panel.

[0146] In a possible embodiment, as shown in Figure 5, the fourth angle α4 formed by the second electrode extension portion 412 and the second electrode main portion 411 can be in the range of 95° to 160°, for example, it can be 95°, 100°, 110°, 120°, 130°, 140°, 145°, 150°, or 160°.

[0147] In a possible embodiment, referring to FIG4C , the first shading pattern 21 can be set to a bent structure, and the second electrode 41 can be moved upwards. The two can be combined to improve the transmittance of the display panel. Specifically, in combination with FIG11E , the array substrate structure shown in FIG4C can simultaneously improve the dark areas at positions S1 and S2, and the transmittance of the display panel can be increased by 18%.

[0148] In a possible embodiment, refer to Figures 6A and 8A-8H, wherein Figure 6A may be a cross-sectional schematic diagram along the dotted line A1A2 in Figure 8A, Figure 8A is one of the schematic diagrams of the array substrate structure provided in an embodiment of the present disclosure, Figure 8B is a schematic diagram of a single film layer of the layer where the second light-shielding pattern is located in Figure 8A, Figure 8C is a schematic diagram of a single film layer of the active layer in Figure 8A, Figure 8D is a schematic diagram of a single film layer of the layer where the first signal line is located in Figure 8A, Figure 8E is a schematic diagram of a single film layer of the layer where the second signal line is located in Figure 8A, Figure 8F is a schematic diagram of a single film layer of the third electrode layer in Figure 8A, and Figure 8G is a schematic diagram of a single film layer of the second electrode layer in Figure 8A. 8H is a schematic diagram of a single film layer of the light-shielding layer in FIG8A , and FIG8I is a schematic diagram of a single film layer of the first electrode layer in FIG8A . The array substrate further includes: an active layer 5 located between the second electrode layer 4 and the first substrate 1, and a first insulating layer 61 located between the second electrode layer 4 and the active layer 5; the first insulating layer 61 has a first via hole K1, and the second electrode 41 is electrically connected to a portion of the active layer 5 through at least the first via hole K1; the array substrate further includes: a second insulating layer 62 filled in the first via hole K1, and the second insulating layer 62 is away from the surface of the first substrate 1, and the step difference between the surface of the first insulating layer 61 away from the first substrate 1 and the first insulating layer 61 is less than 0.2 μm. In the embodiment of the present disclosure, the display substrate further includes a second insulating layer 62 filled in the first via hole K1, and the surface of the second insulating layer 62 facing away from the first substrate 1 has a step difference of less than 0.2 μm from the surface of the first insulating layer 61 facing away from the first substrate 1. This can achieve filling the first via hole K1 and making the position of the first via hole K1 relatively flat. When the second electrode 41 is moved upward through the array substrate structure as shown in FIG5 to achieve outward shift of the electric field forming the dark area, the second electrode 41 can be avoided from being relatively flat at the position of the first via hole K1 during the upward movement of the second electrode 41, thereby avoiding affecting the flatness of the second electrode 41 and further avoiding affecting the display effect. Moreover, the surface of the second insulating layer 62 facing away from the first substrate 1 has a step difference of less than 0.2 μm from the surface of the first insulating layer 61 facing away from the first substrate 1. This can avoid abnormal liquid crystal orientation during the cell alignment process if the step difference is greater than 0.2 μm, and avoid light leakage problems caused by excessive step difference around the first via hole K1.

[0149] In a possible implementation, as shown in FIG. 8A , the orthographic projection of the first via hole K1 on the first substrate 1 and the orthographic projection of the first light-shielding connection portion 212 on the first substrate 1 have an overlapping area.

[0150] In one possible embodiment, as shown in FIG6B , the second electrode 41 may include a first sub-electrode 401 and a second sub-electrode 402; the first sub-electrode 401 is partially located at the bottom of the first via hole K1, partially located on the sidewall of the first via hole K1, and partially extended to the surface of the first insulating layer 61 facing away from the first substrate 1; the second sub-electrode 402 is located on the side of the first sub-electrode 401 facing away from the first substrate 1, and is in direct contact with the portion of the first sub-electrode 401 that extends to the surface of the first insulating layer 61 facing away from the first substrate 1.

[0151] In one possible embodiment, the orthographic projection of the second sub-electrode 402 on the first substrate 1 can cover at least part of the orthographic projection of the first via K1 on the first substrate 1; since the second electrode 41 is distributed in the first via K1, the second electrode 41 in the hole can form an electric field with the electrode layer above the second electrode 41 (for example, the first electrode layer 3), which may interfere with the normal electric field formed by the second electrode 41 and the first electrode layer 3, thereby affecting the normal deflection loaded on the liquid crystal. By covering the orthographic projection of the first via K1 on the first substrate 1 with the second sub-electrode 402, the electric field in the hole can be shielded, thereby achieving the effect of stabilizing the electric field.

[0152] In a possible embodiment, referring to Figures 6B and 8A-8H, the array substrate further includes: a third electrode layer 7 located between the active layer 5 and the second electrode layer 4, and a third insulating layer 63 located between the third electrode layer 7 and the active layer 5; the third electrode layer 7 includes: a plurality of third electrodes 71; the third insulating layer 63 has a second via hole K2; specifically, in combination with Figures 6B and 9, the second electrode 41 is electrically connected to the third electrode 71 through the first via hole K1, and the third electrode 71 is electrically connected to the active layer 5 through the second via hole K2.

[0153] In one possible embodiment, specifically, in combination with FIG6B and FIG9 , the third electrode layer 7 may be a switching electrode layer; in one possible embodiment, the third electrode layer 7 may be a transparent electrode layer; in one possible embodiment, the material of the third electrode layer 7 may include: metal oxide (for example, indium tin oxide, indium-doped zinc oxide (AZO), fluorine-doped tin oxide (AZO), aluminum-doped zinc oxide (AZO), indium-doped cadmium oxide).

[0154] In a possible embodiment, referring to FIG10 , FIG10 is a schematic diagram of the stacking of some film layers in FIG8A , and the array substrate further includes: a first signal line 81 extending along a first direction X, and a second signal line 82 extending along a second direction Y; the orthographic projection of the first light-shielding main portion 211 on the first substrate 1 is located between the orthographic projections of two adjacent first signal lines 81 on the first substrate 1, and the orthographic projection of the first light-shielding main portion 211 on the first substrate 1 has an overlapping area with the orthographic projection of the second signal line 82 on the first substrate 1.

[0155] In one possible embodiment, as shown in FIG10 , in the same first light-shielding pattern 21, the orthographic projection of the Tth first light-shielding main portion 211 along the second direction Y on the first substrate 1 overlaps with the orthographic projection of the Jth second signal line 82 along the first direction X on the first substrate 1; and the orthographic projection of the T+1th first light-shielding main portion 211 along the second direction Y on the first substrate 1 overlaps with the orthographic projection of the J+1th second signal line 82 along the first direction X on the first substrate 1, where M is a positive integer greater than or equal to 1, and J is a positive integer greater than or equal to 1. That is, in the same first light-shielding pattern 21, two adjacent first light-shielding main portions 211 overlap with two adjacent second signal lines 82, respectively. In other words, the multiple first light-shielding main portions 211 of the first light-shielding pattern 21 are staggered in different sub-pixel rows, with each sub-pixel row shifted downward. In this way, while forming a zigzag structure, it is also possible to avoid affecting the light transmission of the sub-pixel opening area.

[0156] In a possible implementation, as shown in FIG. 10 , the orthographic projection of the first light-shielding connection portion 212 on the first substrate 1 and the orthographic projection of the first signal line 81 on the first substrate 1 have an overlapping area.

[0157] In one possible embodiment, as shown in FIG10 , at least a portion of the orthographic projection of the first light-shielding connecting portion 212 on the first substrate 1 does not overlap with the orthographic projection of the second signal line 82 on the first substrate 1. In one possible embodiment, as shown in FIG10 , the orthographic projection of the first light-shielding connecting portion 212 on the first substrate 1 is located between the orthographic projections of two adjacent second signal lines 82 on the first substrate 1.

[0158] In a possible implementation, as shown in FIG. 10 , the orthographic projection of the first hollow 30 on the first substrate 1 and the orthographic projection of the second signal line 82 on the first substrate 1 have an overlapping area.

[0159] In a possible embodiment, as shown in Figure 10, the array substrate also includes: a second light-shielding layer; the second light-shielding layer includes: a second light-shielding pattern 83 extending along the first direction X; the orthographic projection of the second light-shielding pattern 83 on the first substrate 1 covers the orthographic projection of the first signal line 81 on the first substrate 1; the orthographic projection of the first light-shielding main portion 211 on the first substrate 1 is located between the orthographic projections of two adjacent second light-shielding patterns 83 on the first substrate 1.

[0160] In a possible implementation, as shown in FIG. 10 , a length c1 of the first light-shielding main portion 211 in the second direction Y is equal to a distance c2 between two adjacent second light-shielding patterns 83 in the second direction Y.

[0161] In a possible embodiment, referring to FIG6B and FIG8A-FIG8H, the second signal line 82 is located between the third electrode layer 7 and the active layer 5; the first signal line 81 is located between the layer where the second signal line 82 is located and the active layer 5; the third insulating layer 63 includes: a first sub-insulating layer 631 located between the first signal line 81 and the active layer 5, and a second sub-insulating layer located between the first signal line 81 and the second signal line 82; the active layer 5 includes: a first portion 51 extending along the second direction Y, and a first portion 51 extending along the second direction Y, and a second portion 51 extending along the second direction Y. The second portion 52 extends from the end; the first portion 51 is an orthographic projection of the first substrate 1, and has a first overlapping area with the orthographic projection of the third electrode 71 on the first substrate 1, and is electrically connected to the third electrode 71 through the second via K2 in the first overlapping area; the second portion 52 is an orthographic projection of the first substrate 1, and has a second overlapping area with the orthographic projection of the second signal line 82 on the first substrate 1, and is electrically connected to the second signal line 82 through the third via K3 that penetrates the first sub-insulating layer 631 and the second sub-insulating layer 632 in the second overlapping area.

[0162] In one possible embodiment, the first signal line 81 may be a gate line, the second signal line 82 may be a data line, and the second shading pattern 83 may be a shading layer; in one possible embodiment, the orthographic projection of the third shading pattern 83 on the first substrate 1 may cover at least a portion of the orthographic projection of the active layer 5 on the first substrate 1, thereby preventing external light from irradiating the channel region of the active layer 5 and affecting the transistor characteristics.

[0163] In a possible embodiment, as shown in Figure 6B, the array substrate further includes: a first spacer 91 located on the side of the first electrode layer 3 away from the first light shielding layer 2; the orthographic projection of the first spacer 91 on the first substrate 1 overlaps with the orthographic projection of the first via K1 on the first substrate 1.

[0164] In one possible implementation, as shown in Figures 8J, 8K, and 6B, the array substrate further includes a color filter layer 93 located on the side of the second electrode layer 4 facing the first substrate 4. The color filter layer 93 includes a first color resist portion 931, a second color resist portion 932, and a third color resist portion 933. In this disclosed embodiment, the array substrate further includes the color filter layer 93 to prevent cross-coloring between different sub-pixels, making it suitable for display products with a PPI of 1500 or higher.

[0165] In a possible implementation, as shown in FIG6C , the array substrate may not be provided with a color filter layer, and the first light shielding layer 2 may be used to improve cross-color between different sub-pixels, thereby reducing the cross-color level without increasing the black matrix.

[0166] In one possible embodiment, the material of the active layer 5 includes a metal oxide semiconductor material. The metal oxide semiconductor material may include any one or more of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), and rare earth element-doped metal oxide (RE-OS), wherein the rare earth element-doped metal oxide may include lanthanide-doped metal oxide (Ln-OS). The crystalline state of the active layer material may be amorphous, partially crystalline, or polycrystalline. In the embodiment of the present disclosure, the material of the active layer 5 is a rare earth element-doped metal oxide. The active layer 5 can maintain stable performance even when exposed to light, thereby eliminating the need for a light shielding layer in the pixel transmissive area, further improving the aperture ratio of the display panel. In the embodiment of the present disclosure, the active layer 5 of the display area transistor can be an oxide active layer. That is, the thin film transistor with an oxide active layer has advantages such as low leakage current.

[0167] The present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology or organic technology.

[0168] In one possible embodiment, the first insulating layer 62 may be a first flat layer; the second insulating layer 63 may be a second flat layer; the first sub-insulating layer 631 may be a first gate insulating layer; the second sub-insulating layer 632 may be a first interlayer dielectric layer, and the third sub-insulating layer 633 may be a second interlayer dielectric layer.

[0169] In a possible embodiment, in combination with Figure 6B or Figure 6C, the array substrate may further include: a third interlayer dielectric layer 14 located between the active layer 5 and the layer where the second shading pattern 83 is located, a second gate insulating layer 13 located between the layer where the second shading pattern 83 is located and the first substrate 1, a buffer layer 12 located between the second gate insulating layer 13 and the first substrate 1, and a passivation layer 15 located between the second electrode layer 4 and the first shading layer 2.

[0170] The present disclosure also provides a display panel, as shown in FIG7A , comprising the array substrate provided in the present disclosure, an opposing substrate disposed opposite the array substrate, and a liquid crystal layer 94 located between the array substrate and the opposing substrate.

[0171] For high-PPI VR display products, as the aperture ratio becomes smaller and smaller, the black matrix of organic resin materials is prone to residue during the photolithography patterning process, resulting in the whole machine being dirty and half-pixel bright spots. In related technologies, a black matrix of metal materials is used to improve this problem. However, the black matrix of metal materials has a high reflectivity and is prone to ghosting problems, so it is urgent to reduce the reflectivity of the black matrix of metal materials.

[0172] In view of this, referring to FIG7A , the opposing substrate includes: a second substrate 19, and a light-shielding structure 18 located on the side of the second substrate 19 facing the first substrate 1; specifically, the light-shielding structure 18 can be a black matrix; the light-shielding structure 18 includes: a first film layer 181, and a second film layer 182 located on the side of the first film layer 181 facing the second substrate 19; the first film layer 181 is a metal layer, and the second film layer 182 includes at least a non-metallic layer. In the embodiment of the present disclosure, by making the light-shielding structure 18 include a first film layer 181 and a second film layer 182; the first film layer 181 is a metal layer, and the second film layer 182 includes at least a non-metallic layer, wherein the second film layer 82 can be a film layer that reduces reflectivity, that is, by providing a second film layer including a non-metallic layer on the side of the first film layer 181 of a metal material facing the array substrate, the reflectivity of the light-shielding structure 18 can be reduced, thereby reducing the reflectivity of the display panel and improving the problem of poor ghosting.

[0173] In one possible embodiment, the second film layer 182 may also be a composite film layer structure, as shown in FIG7B , the second film layer 182 includes: a first sub-film layer 183, a second sub-film layer 184 located on the side of the first sub-film layer 183 facing the array substrate, and a third sub-film layer 185 located on the side of the second sub-film layer 184 facing the array substrate; wherein the first sub-film layer 183 and the third sub-film layer 185 are non-metallic layers, and the second sub-film layer 184 is a metal layer. In the embodiment of the present disclosure, multi-film deposition is performed on the side of the first film layer 181 of the metal material facing the array substrate, and the principle of multi-film interference is utilized to reduce the reflectivity of the first film layer 181 of the metal material. This combination of film layers can reduce the reflectivity of the shading structure from 45% to 6%, reaching the same level as the black matrix of the resin material.

[0174] In a possible embodiment, the thickness range of the first film layer 181 can be In this way, the light shielding performance of the light shielding structure 18 is guaranteed. Specifically, the thickness of the first film layer 181 can be or

[0175] In one possible embodiment, the thickness of the first sub-membrane layer 183 in a direction perpendicular to the second substrate 19 may be greater than the thickness of the third sub-membrane layer 185 in a direction perpendicular to the second substrate 19. In one possible embodiment, the thickness of the second sub-membrane layer 184 in a direction perpendicular to the second substrate 19 may be less than the thickness of the first film layer 181 in a direction perpendicular to the second substrate 19.

[0176] In a possible embodiment, the thickness range of the first sub-film layer 183 in the direction perpendicular to the second substrate 19 can be For example, it can be or In a possible embodiment, the thickness range of the second sub-film layer 184 in the direction perpendicular to the second substrate 19 can be For example, it can be or In a possible embodiment, the thickness range of the third sub-film layer 185 in the direction perpendicular to the second substrate 19 can be For example, it can be or

[0177] In a possible implementation, the material of the first sub-layer 183 and the material of the third sub-layer may be the same. For example, both may be silicon nitride (SiN).

[0178] In a possible implementation, the second film layer 182 may also be a single film layer structure. Specifically, the second film layer 182 may include: an organic film layer. Specifically, the second film layer 182 may be a resin material.

[0179] In one possible embodiment, the thickness of the organic film layer is less than the thickness of the first film layer 181. In one possible embodiment, the thickness of the organic film layer may be equal to the thickness of the first film layer 181. In one possible embodiment, the thickness of the organic film layer may be greater than the thickness of the first film layer 181.

[0180] In a possible implementation, as shown in FIG. 7A , the counter substrate may further include: a first protective layer 16 located on the side of the light shielding structure 18 facing away from the second substrate 19 , and a second spacer 92 located on the side of the first protective layer 16 facing away from the second substrate 19 .

[0181] In a possible implementation, as shown in FIG. 7A , the orthographic projection of the second spacer 92 on the first substrate 1 may overlap with the orthographic projection of the first spacer 91 on the first substrate 1 .

[0182] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes a display panel provided by the embodiment of the present disclosure.

[0183] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0184] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An array substrate, wherein, include: a first substrate; The first light shielding layer is located on one side of the first substrate, and includes: a plurality of first light shielding patterns arranged in sequence and at intervals along a first direction; at least one of the plurality of first light shielding patterns includes: a plurality of first light shielding main parts and a plurality of first light shielding connecting parts; in the same first light shielding pattern, the first light shielding main parts and the first light shielding connecting parts are arranged alternately, and the extension direction of the first light shielding connecting parts crosses the extension direction of the first light shielding main parts; two adjacent first light shielding connecting parts in the first direction are spaced from each other; A first electrode layer is located on a side of the first light-shielding layer away from the first substrate; the first electrode layer comprises: a first hollow portion; the first hollow portion comprises: a corner portion, the orthographic projection of the corner portion on the first substrate is located between two adjacent first light-shielding connecting portions in the first direction; The first light-shielding main portion has a first outer edge extending along a second direction, an orthographic projection of an extension line of the first outer edge on the first substrate has an overlapping area with an orthographic projection of the corner portion on the first substrate, and the second direction intersects with the first direction.

2. The array substrate according to claim 1, wherein, The orthographic projections of the corner portions on the first substrate are all located between two adjacent first light-shielding connecting portions in the first direction.

3. The array substrate according to claim 1, wherein, An orthographic projection of a portion of the first light-shielding connection portion on the first substrate overlaps an orthographic projection of a portion of a boundary of the corner portion on the first substrate.

4. The array substrate according to claim 3, wherein, At least a portion of the end portion of the first light-shielding main portion is located within the orthographic projection of the corner portion on the first substrate.

5. The array substrate according to any one of claims 1-4, wherein, A maximum width of the first light-shielding connecting portion in the first direction is smaller than a maximum width of the first light-shielding main portion in the first direction.

6. The array substrate according to any one of claims 1-5, wherein, The first light-shielding connecting portion comprises: a first sub-connecting portion, a second sub-connecting portion located on one side of the first sub-connecting portion, and a third sub-connecting portion located on the other side of the first sub-connecting portion; One end of the second sub-connecting portion is connected to the first light-shielding main portion, and the other end is connected to one end of the first sub-connecting portion; One end of the third sub-connection portion is connected to another first light-shielding main portion, and the other end of the third sub-connection portion is connected to the other end of the first sub-connection portion.

7. The array substrate according to claim 6, wherein The second sub-connection portion extends along the second direction; the first sub-connection portion and the third sub-connection portion extend along a third direction, wherein the third direction intersects with the first direction and the second direction.

8. The array substrate according to claim 4, wherein The first sub-connection portion, the second sub-connection portion, and the third sub-connection portion all extend along a third direction, wherein the third direction intersects with the first direction and the second direction.

9. The array substrate according to any one of claims 1-8, wherein, The first electrode layer further includes: a first electrode portion; an orthographic projection of the first electrode portion on the first substrate is complementary to an orthographic projection of the first hollow on the first substrate; An orthographic projection of the first electrode portion on the first substrate covers an orthographic projection of the first light-shielding pattern on the first substrate.

10. The array substrate according to any one of claims 1-9, wherein, The multiple first light-shielding patterns include: multiple first light-shielding main part rows; at least one first light-shielding main part row among the multiple first light-shielding main part rows includes: multiple first light-shielding main parts arranged in sequence along the first direction; the multiple first hollow-outs include: multiple first hollow-out rows; at least one hollow-out row among the multiple first hollow-out rows includes: multiple first hollow-outs arranged in sequence along the first direction; the orthographic projection of the Nth first light-shielding main part row on the substrate overlaps with the orthographic projection of the Nth hollow-out row on the first substrate. The first hollow-out includes: a first sub-hollow-out part, a second sub-hollow-out part, and a third sub-hollow-out part; the second sub-hollow-out part of the Nth hollow-out row is located on the side of the first sub-hollow-out part facing the (N - 1)th hollow-out row; the third sub-hollow-out part of the Nth hollow-out row is located on the side of the first sub-hollow-out part facing the (N + 1)th hollow-out row; the extending direction of the second sub-hollow-out part intersects with the extending direction of the first sub-hollow-out part, and the extending direction of the third sub-hollow-out part intersects with the extending direction of the first sub-hollow-out part. The orthographic projection on the substrate of the extension line of the first outer edge of the first light-shielding main part in the Nth first light-shielding main part row overlaps with the orthographic projection on the substrate of the third sub-hollow-out part of the Nth hollow-out row, and overlaps with the orthographic projection on the first substrate of the second sub-hollow-out part of the (N + 1)th hollow-out row.

11. The array substrate according to claim 10, wherein, The array substrate further includes: a second electrode layer located on the side of the first light-shielding layer facing the first substrate. The second electrode layer includes: multiple second electrode rows extending along the first direction and arranged along the second direction; at least one second electrode row among the multiple second electrode rows includes: multiple second electrodes; the orthographic projection of the second electrode on the first substrate is rectangular.

12. The array substrate according to claim 11, wherein, The orthographic projection of the Nth second electrode row on the first substrate overlaps with the orthographic projection of the Nth hollow-out row on the first substrate, and the orthographic projection of the second electrode of the Nth second electrode row on the first substrate covers at least part of the orthographic projection of the second sub-hollow-out part of the Nth hollow-out row on the first substrate, where N is a positive integer greater than or equal to 1.

13. The array substrate according to claim 11 or 12, wherein, The second electrode of the Nth second electrode row has a second outer edge close to the (N - 1)th second electrode row and extending along the first direction; the second sub-hollow-out part of the Nth hollow-out row has a third outer edge extending along the first direction. The orthographic projection of the second outer edge on the first substrate is located on the side of the orthographic projection of the third outer edge on the first substrate facing the (N - 1)th second electrode row.

14. The array substrate according to claim 13, wherein, The second electrode includes: a second electrode main part, and a second electrode extension part connected to the second electrode main part. The orthographic projection of the second electrode extension part on the first substrate covers at least part of the orthographic projection of the second sub-hollow-out part on the first substrate.

15. The array substrate according to claim 14, wherein, The extending direction of the second electrode extension part is the same as the extending direction of the second sub-hollow-out part.

16. The array substrate according to claim 15, wherein, The line width of the second electrode extension in a direction perpendicular to the extension direction is less than the width of the second sub-hollow portion in a direction perpendicular to the extension direction.

17. The array substrate according to any one of claims 13-16, wherein, The orthographic projection of the second electrode main portion on the first substrate does not overlap with the orthographic projection of the second sub-hollow portion on the first substrate.

18. The array substrate according to any one of claims 11-17, wherein, The array substrate further includes: an active layer located between the second electrode layer and the first substrate, and a first insulating layer located between the second electrode layer and the active layer; the first insulating layer has a first via hole, and the second electrode is electrically connected to at least a part of the active layer through the first via hole; The array substrate further includes: a second insulating layer filled in the first via hole.

19. The array substrate according to claim 18, wherein, The orthographic projection of the first via hole on the first substrate has an overlapping area with the orthographic projection of the first light-shielding connection portion on the first substrate.

20. The array substrate according to claim 19, wherein, The array substrate further includes: a third electrode layer located between the active layer and the second electrode layer, and a third insulating layer located between the third electrode layer and the active layer; the third electrode layer includes: a plurality of third electrodes; the third insulating layer has a second via hole; The second electrode is electrically connected to the third electrode through the first via hole, and the third electrode is electrically connected to the active layer through the second via hole.

21. The array substrate according to claim 20, wherein, The array substrate further includes: a first signal line extending along the first direction, and a second signal line extending along the second direction; The orthographic projection of the first light-shielding main portion on the first substrate is located between the orthographic projections of two adjacent first signal lines on the first substrate, and the orthographic projection of the first light-shielding main portion on the first substrate has an overlapping area with the orthographic projection of the second signal line on the first substrate.

22. The array substrate according to claim 21, wherein, In the same first light-shielding pattern, the orthographic projection of the T-th first light-shielding main portion along the second direction on the first substrate overlaps with the orthographic projection of the J-th second signal line along the first direction on the first substrate; The orthographic projection of the (T + 1)-th first light-shielding main portion along the second direction on the first substrate overlaps with the orthographic projection of the (J + 1)-th second signal line along the first direction on the first substrate, where T is a positive integer greater than or equal to 1, and J is a positive integer greater than or equal to 1.

23. The array substrate according to claim 21 or 22, wherein, The orthographic projection of the first light-shielding connection portion on the first substrate has an overlapping area with the orthographic projection of the first signal line on the first substrate.

24. The array substrate according to any one of claims 21-23, wherein, At least a part of the orthographic projection of the first light-shielding connection portion on the first substrate does not overlap with the orthographic projection of the second signal line on the first substrate.

25. The array substrate according to any one of claims 22-24, wherein, The orthographic projection of the first hollow portion on the first substrate has an overlapping area with the orthographic projection of the second signal line on the first substrate.

26. The array substrate according to any one of claims 20-25, wherein, The array substrate further includes: a second light-shielding layer; the second light-shielding layer includes: a second light-shielding pattern extending along the first direction; the orthographic projection of the second light-shielding pattern on the first substrate covers the orthographic projection of the first signal line on the first substrate; The orthographic projection of the first light-shielding main portion on the first substrate is located between the orthographic projections of two adjacent second light-shielding patterns on the first substrate.

27. The array substrate according to claim 26, wherein, The length of the first light-shielding main part in the second direction is equal to the pitch between two adjacent second light-shielding patterns in the second direction.

28. The array substrate according to any one of claims 22-27, wherein, The second signal line is located between the third electrode layer and the active layer; The first signal line is located between the layer where the second signal line is located and the active layer; the third insulating layer includes: a first sub-insulating layer located between the first signal line and the active layer, and a second sub-insulating layer located between the first signal line and the second signal line; The active layer includes: a first part extending along the second direction, and a second part extending from one end of the first part; the orthographic projection of the first part on the first substrate and the orthographic projection of the third electrode on the substrate have a first overlapping region, and are electrically connected to the third electrode through the second via hole in the first overlapping region; a part of the orthographic projection of the second part on the first substrate and the orthographic projection of the second signal line on the first substrate have a second overlapping region, and are electrically connected to the second signal line through a third via hole penetrating through the first sub-insulating layer and the second sub-insulating layer.

29. The array substrate according to any one of claims 9-28, wherein, The array substrate further includes: a color filter layer on the side of the second electrode layer facing the first substrate; The color filter layer includes: a first color resist part, a second color resist part, and a third color resist part.

30. A display panel, wherein, Including the array substrate according to any one of claims 1-29, further including a counter substrate disposed opposite to the array substrate.

31. The display panel according to claim 30, wherein, The counter substrate includes: a second substrate, and a light-shielding structure on the side of the second substrate facing the first substrate; The light-shielding structure includes: a first film layer, and a second film layer on the side of the light-shielding layer facing the second substrate; the first film layer is a metal layer, and the second film layer at least includes a non-metal layer.

32. The display panel according to claim 31, wherein The second film layer includes a first sub-film layer, a second sub-film layer on the side of the first sub-film layer facing the array substrate, and a third sub-film layer on the side of the second sub-film layer facing the array substrate, which are stacked in sequence; wherein, the first sub-film layer and the third sub-film layer are non-metal layers, and the second sub-film layer is a metal layer.

33. The display panel according to claim 32, wherein, The second film layer includes: an organic film layer; the thickness of the organic film layer is less than the thickness of the first film layer.

34. A display device, wherein, Including the display panel according to any one of claims 30-33.

Images