Image display method and electronic device

Abstract

Provided in the present application are an image display method and an electronic device. The method is applied to an electronic device comprising a display screen. The method comprises: at a first moment, generating a first Vsync signal, and in response to the first Vsync signal, starting to display a first image, wherein the first Vsync signal corresponds to a first Vsync signal period, and a first display duration for displaying the first image is the same as the duration of the first Vsync signal period; at a second moment, generating a second Vsync signal, and in response to the second Vsync signal, starting to display a second image, wherein the second Vsync signal corresponds to a second Vsync signal period, the second moment is after the first moment, and the second image is the next image frame of the first image; after display of the second image is started, detecting whether display data of a third image has been synthesized, wherein the third image is the next image frame of the second image; and if the display data of the third image has been synthesized, issuing to a display screen a control instruction for controlling the frequency at which Vsync signals are generated. The present solution can accelerate the speed at which electronic devices display images, thereby enhancing responsiveness.

Description

Image display method and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on January 9, 2024, with application number 202410035569.5 and invention name “Image Display Method and Electronic Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of display technology, and in particular to an image display method and electronic equipment. Background Art

[0003] The refresh rate of the display screen of the electronic device can be 60 Hz, 70 Hz, 75 Hz, 80 Hz, 90 Hz or 120 Hz, etc. When the display screen uses different refresh rates for image display, the time length that the image display driver of the electronic device waits for sending the image to the display screen to drive the display screen to display the screen change is also different. Taking the display screen using refresh rates of 60 Hz and 120 Hz for image refresh display as an example, when the display screen uses a 60 Hz refresh rate, the waiting time for the image display driver to write the image display data to the display screen can be up to 1 / 60 second (s) = 0.01667 (s) = 16.667 milliseconds (ms), while when the display screen uses a 120 Hz refresh rate, the waiting time for the image display driver to write the image display data to the display screen also needs to be up to 1 / 120 (s) = 0.00833 (s) = 8.33 (ms).

[0004] However, when users use electronic devices, it is common for them to interact with the screen by touching it. If the image display driver waits for the display data of the image to be written to the display screen to drive the display screen to display the image, the longer the electronic device's overall response to the user's touch operation to display the screen changes will be worse. Even when the electronic device's display screen uses a 120Hz refresh rate to respond to the user's touch operation to display the screen changes, the user will still feel that the screen changes are poorly followed. Therefore, how to effectively shorten the response time of the electronic device to the user's touch operation, thereby improving the display screen's follow-up performance with the user's touch operation, is a technical problem that urgently needs to be solved in the current field. Summary of the Invention

[0005] Embodiments of the present application provide an image display method and an electronic device for shortening the response time of the electronic device to a user touch operation, accelerating the speed of image display, and thereby improving the tracking performance of the display screen as the user touches the screen.

[0006] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0007] In a first aspect, an image display method is provided, which is applied to an electronic device, the electronic device including a display screen, the method comprising: at a first moment, the electronic device generates a first Vsync signal, and in response to the first Vsync signal, the display screen displays a first image; wherein the first Vsync signal corresponds to a first Vsync signal period, the first Vsync signal period corresponds to a first display duration, and the first display duration is the display duration of the first image; at a second moment, the electronic device generates a second Vsync signal, and in response to the second Vsync signal, the display screen displays a second image; wherein the second Vsync signal corresponds to a second Vsync signal period, the second Vsync signal period is equal to the first Vsync signal period, and the second moment is after the first moment; at a third moment, in response to the completion of preparation of display data for a third image, the electronic device generates a third Vsync signal; wherein the third Vsync signal corresponds to a third Vsync signal period, the third moment is after the second moment, and the third Vsync signal period is less than the first Vsync signal period.

[0008] In an embodiment of the present application, after the image display data is prepared, the frequency of the vertical synchronization signal is increased by the image display driver of the electronic device, and the image display driver responds to the vertical synchronization signal after the frequency is increased, and writes the display data of the target image obtained by the electronic device in response to the user's interactive operation to the display screen of the electronic device, so as to quickly drive the display screen to display the target image. In this way, this solution can effectively shorten the time the image waits for display after the display data is prepared, thereby speeding up the image display speed. For scenarios where the user touches the display screen to interact, this solution can shorten the response time of the electronic device in response to the user's touch operation, thereby improving the chirality of the device's display screen as the user's interactive operation changes.

[0009] In the present application, since the image display driver increases the frequency of the vertical synchronization signal, the image display driver can respond to the vertical synchronization signal with the increased frequency after receiving the display data of the image corresponding to the user interaction operation, and write the display data of the image to the display screen in a very short time, thereby realizing rapid driving of the display screen to refresh the image display.

[0010] In a possible implementation, the second Vsync signal period corresponds to a second display duration, the second display duration is shorter than the first display duration, and the second display duration is the display duration of the second image.

[0011] In a possible implementation, the first display duration is 16.6 ms, and the second display duration is 13.8 ms.

[0012] In a possible implementation, the second display duration is a difference between the first Vsync signal period and the third Vsync signal period.

[0013] In this application, there may be a situation where the time between the image display data preparation and the moment when the next VSync signal is to be generated exceeds two 360Hz cycles, that is, exceeds 5.6ms. In this case, this application can increase the frequency of the output Vsync signal to 360Hz and output the next VSync signal 2.8ms in advance. That is, the above-mentioned second display time length is the difference between the first Vsync signal cycle and the third Vsync signal cycle. In another example, this application can also increase the frequency of the output VSync signal to 360Hz and output the next VSync signal 5.6ms in advance.

[0014] It is understood that the time values ​​mentioned in this application are approximate values ​​and can be adjusted within a smaller range. For example, 2.8ms can also be 2.7ms, and 5.5ms can also be 5.4ms. This application does not impose any restrictions on this.

[0015] In a possible implementation, the second Vsync signal period corresponds to a second display duration, the second display duration is greater than the first display duration, and the second display duration is the display duration of the second image.

[0016] In a possible implementation, in response to the third Vsync signal, the display screen displays a third image, where the third image is a next frame image of the second image.

[0017] In one possible implementation, at a fourth moment, the electronic device generates a fourth Vsync signal, and in response to the fourth Vsync signal, the display screen displays a fourth image; wherein the fourth moment is after the third moment, the fourth Vsync signal corresponds to a fourth Vsync signal cycle, the fourth Vsync signal cycle corresponds to a fourth display duration, the fourth display duration is the display duration of the fourth image, and the fourth display duration is equal to the first display duration. Thus, after the present application outputs the third Vsync signal in advance, the electronic device will maintain the display duration of the fourth image.

[0018] In the present application, after determining that the display screen has stabilized the display of the third image, the frequency of the output Vsync signal can be reduced. This can avoid the display screen outputting the Vsync signal at an increased frequency for a long time, which causes wasteful power consumption of the device, thereby achieving the purpose of saving device power consumption.

[0019] In one possible implementation, at a fifth moment, the electronic device generates a fifth Vsync signal; wherein the fifth Vsync signal corresponds to a fifth Vsync signal period, and the fifth Vsync signal period is equal to the first Vsync signal period. In the present application, after maintaining the display duration of the fourth image, the electronic device can continue to detect the duration between the moment when the display data of the frame following the fifth image is prepared and when the next Vsync signal is to be generated during the display process of the fifth image, which is the frame following the fourth image.

[0020] In a possible implementation, the first image is an image frame preceding the second image.

[0021] In one possible implementation, when the display screen displays the first image, the time period for the display data of the second image to wait for the second Vsync signal is greater than 2.8ms. In the present application, the time period for the display data of the previous frame of image to wait for the next Vsync signal after preparation is completed can be detected. If the time period is greater than the set time period (2.8ms), the Vsync signal with a higher frequency can be output in advance.

[0022] In one possible implementation, the first Vsync signal period is 16.6ms, and the third Vsync signal period is 2.8ms. It is understandable that the maximum refresh rate of 360Hz for electronic devices corresponds to a period of 2.8ms, so the frequency of the third Vsync signal is increased to 360Hz at most.

[0023] In one possible implementation, the electronic device further includes an image display driver; the method further includes: in response to the display screen displaying the second image, the image display driver detecting whether the display data of the third image is ready; in response to the display data of the third image being ready, the image display driver sending a control instruction to the display screen, and the display screen generating a third Vsync signal.

[0024] In one possible implementation, the electronic device adds a frame tracking detection module to the system kernel layer, and uses the frame tracking detection module to detect whether the image display data is ready. When the frame tracking detection module detects that the image display data is ready, the frequency of the Vsync signal output by the display screen is increased to shorten the waiting time for display after the image display data is ready, thereby achieving the purpose of improving the tracking performance.

[0025] In a second aspect, the present application provides an electronic device that has the functionality to implement the method described in the first aspect. This functionality can be implemented in hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the functionality described above.

[0026] In a third aspect, the present application provides an electronic device comprising: a processor and a memory; the memory is used to store computer program code, the computer program code including computer execution instructions, and when the electronic device is running, the processor executes the computer execution instructions to enable the electronic device to perform the method described in the first aspect above.

[0027] In a fourth aspect, the present application provides an electronic device comprising: a processor; the processor is configured to be coupled to a memory, and after reading instructions in the memory, execute the method described in the first aspect above according to the instructions.

[0028] In a fifth aspect, the present application provides a computer-readable storage medium, which stores computer instructions. When the computer-readable storage medium is run on an electronic device, the electronic device can execute the method described in the first aspect above.

[0029] In a sixth aspect, the present application provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the method described in the first aspect above.

[0030] In a seventh aspect, a device (e.g., a display system) is provided, comprising a processor configured to support an electronic device in implementing the functions described in the first aspect. In one possible design, the device further comprises a memory configured to store program instructions and data necessary for the electronic device.

[0031] Among them, the technical effects brought about by any design method in the second to seventh aspects can refer to the technical effects brought about by different implementation methods in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] FIG1 is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present application;

[0033] FIG2 is a schematic diagram of a system architecture of an electronic device in conventional technology;

[0034] FIG3 is a schematic diagram showing the principles of layer drawing, rendering, synthesis and image frame display by an electronic device in conventional technology;

[0035] FIG4 is a schematic diagram of a system architecture of an electronic device according to an embodiment of the present application;

[0036] FIG5 is a schematic diagram showing the principles of layer drawing, rendering, synthesis, and image frame display by an electronic device according to an embodiment of the present application;

[0037] FIG6 is a schematic diagram showing the principles of another electronic device performing layer drawing, rendering, synthesis, and image frame display in an embodiment of the present application;

[0038] FIG7 is a schematic diagram showing the principles of another electronic device performing layer drawing, rendering, synthesis, and image frame display in an embodiment of the present application;

[0039] FIG8 is a first flow chart of an image display method according to an embodiment of the present application;

[0040] FIG9 is a schematic diagram showing the principles of another electronic device performing layer drawing, rendering, synthesis, and image frame display in an embodiment of the present application;

[0041] FIG10 is a schematic diagram showing the principles of another electronic device performing layer drawing, rendering, synthesis, and image frame display in an embodiment of the present application;

[0042] FIG11 is a schematic diagram showing the principles of another electronic device performing layer drawing, rendering, synthesis, and image frame display in an embodiment of the present application;

[0043] FIG12 is a schematic diagram of the duration of an image displayed on a display screen under a situation according to an embodiment of the present application;

[0044] FIG13 is a schematic diagram showing the principle of an electronic device transmitting and displaying an image in response to a Vsync signal with an increased frequency under one embodiment of the present application;

[0045] FIG14 is a schematic diagram of the system architecture and data signal flow of an electronic device involved in an embodiment of the present application;

[0046] FIG15 is a schematic diagram of a control logic for image display by an electronic device according to an embodiment of the present application;

[0047] FIG16 is a second flow chart of an image display method provided in an embodiment of the present application;

[0048] FIG17 is another schematic diagram of control logic for image display by an electronic device according to an embodiment of the present application;

[0049] FIG18 is a schematic diagram of control logic for obtaining the time duration for waiting for the next Vsync signal after display data preparation is completed for a second image according to an embodiment of the present application;

[0050] FIG19 is a schematic diagram of a flow chart of a frame tracking configuration solution provided in an embodiment of the present application;

[0051] FIG20 is a schematic structural diagram of a chip system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0052] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. The following terms "first", "second", etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, features defined as "first", "second", etc. may explicitly or implicitly include one or more of the features.

[0053] An embodiment of the present application provides an image display method, which can be applied to an electronic device including a display screen. In response to the completion of the preparation of the display data of the image, the frequency of the vertical synchronization signal output by the display screen is increased, so that the image display driver of the electronic device responds to the vertical synchronization signal with a higher frequency to send and display the image, thereby realizing rapid driving of the display screen to display the image.

[0054] It should be noted that the above-mentioned electronic devices can be mobile phones, tablet computers, desktop / laptop / handheld computers, notebook computers, ultra-mobile personal computers (UMPCs), netbooks, personal digital assistants (PDAs), augmented reality (AR) and virtual reality (VR) devices, and other electronic devices with display screens. The embodiments of the present application do not impose any special restrictions on the specific form of the electronic devices.

[0055] The implementation of the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0056] Please refer to Figure 1, which is a schematic diagram of the structure of an electronic device 100 provided in an embodiment of the present application. As shown in Figure 1, the electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 111, a power management module 112, a battery 113, an antenna 1, an antenna 2, a mobile communication module 140, a wireless communication module 150, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, a sensor module 180, a button 190, a motor 191, an indicator 192, a camera 193, a display 194, and a subscriber identification module (SIM) card interface 195.

[0057] It should be understood that the structure illustrated in the embodiments of the present invention does not constitute a specific limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 may include more or fewer components than shown, or may combine or separate certain components, or arrange the components differently. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0058] The processor 110 may include one or more processing units, for example: the processor 110 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a memory, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU), etc. Among them, different processing units can be independent devices or integrated into one or more processors. Among them, the controller can be the nerve center and command center of the electronic device 100. The controller can generate an operation control signal based on the instruction opcode and the timing signal to complete the control of instruction fetching and execution.

[0059] Processor 110 may also include a memory for storing instructions and data. In some embodiments, the memory in processor 110 is a cache memory. This memory can store instructions or data that have just been used or are being recycled by processor 110. If processor 110 needs to use the same instruction or data again, it can directly access the memory. This avoids duplicate accesses, reduces processor 110 latency, and thus improves system efficiency.

[0060] In some embodiments, the processor 110 may include one or more interfaces. The interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface.

[0061] It is understood that the interface connection relationship between the modules illustrated in the embodiment of the present invention is merely an illustrative illustration and does not constitute a structural limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 may also adopt different interface connection methods from the above embodiments, or a combination of multiple interface connection methods.

[0062] The charging management module 111 is configured to receive charging input from a charger. While charging the battery 113, the charging management module 111 can also power the electronic device through the power management module 112. The wireless communication functionality of the electronic device 100 is implemented via antenna 1, antenna 2, mobile communication module 140, wireless communication module 150, a modem processor, and a baseband processor.

[0063] Antenna 1 and Antenna 2 are used to transmit and receive electromagnetic wave signals. Each antenna in electronic device 100 can be used to cover a single or multiple communication frequency bands. Different antennas can also be reused to improve antenna utilization. For example, antenna 1 can be reused as a diversity antenna for a wireless local area network. In other embodiments, the antennas can be used in conjunction with a tuning switch.

[0064] The mobile communication module 140 can provide solutions for wireless communications including 2G / 3G / 4G / 5G / 6G applied to the electronic device 100. The modulation and demodulation processor may include a modulator and a demodulator. The wireless communication module 150 can provide solutions for wireless communications including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared technology (IR), etc. applied to the electronic device 100.

[0065] Electronic device 100 implements display functionality through a GPU, display screen 194, and an application processor. A GPU is a microprocessor for image processing that connects display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. Processor 110 may include one or more GPUs that execute program instructions to generate or modify display information.

[0066] Display screen 194 is used to display images, videos, and the like. Display screen 194 includes a display panel. The display panel may include, but is not limited to, a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a mini organic light-emitting diode (MINILED), a micro organic light-emitting diode (MicroLed), a quantum dot light-emitting diode (QLED), and the like. In some embodiments, electronic device 100 may include one or N display screens 194, where N is a positive integer greater than one.

[0067] The electronic device 100 can implement a shooting function through an ISP, a camera 193, a video codec, a GPU, a display screen 194, and an application processor.

[0068] The external memory interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device 200.

[0069] The internal memory 121 may be used to store computer-executable program codes, where the executable program codes include instructions.

[0070] The processor 110 executes various functional applications and data processing of the electronic device 100 by running instructions stored in the internal memory 121. The internal memory 121 may include a program storage area and a data storage area. Among them, the program storage area may store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc. The data storage area may store data created during the use of the electronic device 100 (such as audio data, a phone book, etc.), etc. In addition, the internal memory 121 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, a universal flash storage (UFS), etc.

[0071] The electronic device 100 can implement audio functions such as music playback and recording through the audio module 170, the speaker 170A, the receiver 170B, the microphone 170C, the headphone jack 170D, and the application processor.

[0072] The buttons 190 include a power button, a volume button, etc. The indicator 192 may be an indicator light.

[0073] The sensor module 180 may include a folding angle detection sensor, a pressure sensor, a gyro sensor, an air pressure sensor,

[0074] Magnetic sensor, acceleration sensor, distance sensor, proximity sensor, fingerprint sensor, temperature sensor, touch sensor, ambient light sensor, bone conduction sensor, etc.

[0075] It should be noted that, in the embodiments of the present application, the display screen of the electronic device to which the image display method provided in the embodiments of the present application is applied is a screen type that supports source chip (Source IC) refresh interrupts. A Source IC refresh interrupt is a state in which the Source IC of the display screen can be driven to interrupt at any time (referred to as a Source refresh interrupt) when not in a refresh state, thereby re-entering the refresh state and resuming operation. The Source IC's work in the refresh state can include refreshing the image display data to cause the display screen to begin displaying the image, or responding to a frame cut instruction to switch the refresh rate of the display screen.

[0076] For example, the display screen of an electronic device may be a display screen that uses low-temperature polysilicon oxide (LTPO) transistors, thereby supporting Source refresh interruption based on the low leakage characteristic of LTPO. However, the display screen of an electronic device cannot usually be a display screen that uses low-temperature polysilicon (LTPS) transistors. Because as the leakage of the transistor increases, even if the Source refresh interruption can still be supported, the overall display effect of the display screen will be seriously affected. Therefore, due to the serious leakage characteristic of LTPS, the display screen using LTPS usually does not support the Source refresh interruption function. Therefore, it can be understood that as long as the display screen of an electronic device uses transistors with low leakage characteristics, it can support Source refresh interruption.

[0077] Based on the different design requirements of actual applications, the transistor types used in electronic device displays can certainly be other types besides LTPO. However, regardless of the specific type of transistor used in the display screen, and regardless of whether the transistor has low leakage characteristics that enable support for source refresh interrupts, as long as the display screen of the electronic device is of a screen type that supports source refresh interrupts, it should be included in the scope of protection of the image display method provided in the embodiments of this application.

[0078] In an embodiment of the present application, the base frequency supported by the display screen of the electronic device may be 60 Hz, 70 Hz, 75 Hz, 80 Hz, 90 Hz, 120 Hz, or 360 Hz, etc. The refresh rate of the display screen for displaying images (abbreviated as image refresh rate or display frame rate) is less than or equal to the base frequency supported by the display screen. Furthermore, the image refresh rate supported by the display screen is typically less than or equal to 120 Hz. For example, the image refresh rate of the display screen can typically be configured as 60 Hz, 70 Hz, 75 Hz, 80 Hz, 90 Hz, or 120 Hz.

[0079] When the display screen supports a 120Hz image refresh rate, the display screen can increase the image refresh rate from 60Hz, 70Hz, 75Hz, 80Hz, 90Hz to 120Hz, or reduce the image refresh rate from 120Hz to 90Hz, 80Hz, 75Hz, 70Hz, or 60Hz. In the embodiments of the present application, the image refresh rate of the electronic device is the image refresh rate currently used by the display screen of the electronic device. Therefore, in some feasible embodiments of the present application, the image refresh rate of the electronic device or the image refresh rate of the display screen of the electronic device may also be referred to as the current refresh rate.

[0080] It should be noted that in the embodiments of the present application, the vertical synchronization (VSync) signal is a periodic discrete signal used in electronic devices using VSync technology. Specifically, a VSync signal is triggered by a hardware driver every VSync period (also known as a refresh period or refresh duration).

[0081] It should be noted that in the embodiments of the present application, the VSync signal is used to trigger the hardware to refresh the displayed image frame. The VSync signal can be generated by the display and fed back to the APP, modem processor, GPU, ISP, and controller. Therefore, the VSync signal can also be considered a type of tearing effect (TE) signal fed back from the display 194 to the processor 110.

[0082] In an embodiment of the present application, when the display screen supports a base frequency of 360 Hz, the display screen can adaptively switch the frequency of the output VSync signal to 60 Hz, 90 Hz, 120 Hz or 360 Hz based on the control of the image display driver in the electronic device, thereby triggering and outputting VSync signals with different VSync periods at different times.

[0083] In different systems or architectures, the name of the VSync signal may be different. For example, in some systems or architectures, the VSync signal may be VSYNC_APP, VSYNC_SF, or VSYNC_HW. But no matter what the name of the VSync signal is, as long as it is a synchronization signal with similar functions and conforms to the technical ideas of the method provided in the embodiments of this application, it should be covered by the protection scope of this application. Moreover, in different systems or architectures, the definition of the VSync signal may also be different, but no matter what definition is made of the VSync signal, as long as it is a synchronization signal with similar functions and conforms to the technical ideas of the method provided in the embodiments of this application, it should also be covered by the protection scope of this application.

[0084] It should be noted that the software system of the electronic device can adopt a layered architecture, an event-driven architecture, a micro-kernel architecture, a microservice architecture, or a cloud architecture. For ease of understanding, the present embodiment takes the Android system with a layered architecture as an example to explain in detail the image display method provided by the present embodiment of the electronic device when applied to the present invention.

[0085] 2 , taking the example of an electronic device sending (or writing) an image to a display screen for display in response to a VSync signal as an example, the software and hardware processing flow of an electronic device of the Android system in this process will be described.

[0086] As shown in Figure 2, the hardware and software architecture of an electronic device utilizes a layered design. The software layer includes the application layer (APP layer), the application framework layer (FWK layer), the hardware abstraction layer (HAL), and the kernel layer. The hardware layer includes the display panel. The application layer can include various applications running on the electronic device, such as gallery, browser, theme apps, and wallpaper apps. The application framework layer primarily provides graphics processing services, such as the surface flinger (SF) service for rendering images provided by the application and the GPU service for compositing multiple layers of the image to be displayed. The kernel layer primarily includes the image display driver, which is responsible for delivering images to the display panel after being processed and issued by upper system layers (other system layers above the kernel layer where the image display driver resides, such as the application layer, application framework layer, and hardware abstraction layer). The hardware layer primarily includes the display panel, which refreshes the image to be displayed based on calls from the image display driver.

[0087] In the image display process of an electronic device, VSync alignment can be performed between the APP and SF, and between the SF and the driver, or not. If VSync alignment is not performed between the APP and SF, and between the SF and the driver, the hand tracking performance of the electronic device can be further improved. The following explanation uses the example of not performing VSync alignment between the APP and SF, and between the SF and the driver.

[0088] In the system framework of an electronic device as shown in FIG2 , an application program APP (e.g., a gallery, browser, theme application, or wallpaper application) at the application layer performs image drawing. The APP then sends the drawn image to the application framework layer, where the SF and GPU at the application framework layer respectively perform image rendering and layer synthesis on the drawn image to obtain display data for the image to be displayed. The display data for the image to be displayed is then passed to the image display driver at the kernel layer via the hardware abstraction layer. Furthermore, the image display driver responds to a new VSync signal by calling the display module serial interface (DSI) via the smart display engine (SDE) to write the display data for the image to be displayed to the display driver integrated circuit (DDIC) of the display screen. The DDIC of the display screen then stores the image data sent by the software side in a buffer, thereby controlling the display panel to refresh the image by scanning (or reading) the display data in the buffer.

[0089] For scenarios that pursue extreme tracking, VSync alignment is not required between APP and SF, as well as between SF and driver. The goal at this time is to display a frame of image on the display as quickly as possible after the APP draws it.

[0090] In a gaming scenario with a frame rate of 60 Hz, as shown in FIG3 , the DDIC of the display screen of the electronic device supports a 60 Hz image refresh rate. When the DDIC refreshes and outputs the vertical synchronization signal at a frequency of 60 Hz, the VSync period of the output vertical synchronization signal is approximately 16.6 ms. Thus, the display screen also displays the image for approximately 16.6 ms.

[0091] At time t1, the display screen responds to the VSync signal 1 and starts to display image-1 for a period of 16.6ms. During the display of image-1, the APP of the electronic device application layer starts to draw image 0. After the drawing of image 0 is completed, the SF of the electronic device application framework layer renders the image 0 drawn by the APP through the rendering service render server (also called the render thread), and after the SF completes the rendering of image 0, it will further send image 0 downward to the GPU, so that after receiving image 0, the GPU immediately starts to process the layer synthesis of image 0. Then, after synthesis, image 0 is sent to the image display driver. Wait until time t2, the image display driver writes the display data of image 0 to the display screen in response to the VSync signal 2 output by the display screen, so that the display screen refreshes the display image 0 at time t2 until time t3.

[0092] After time t2, the APP of the electronic device's application layer begins to draw image 1. After image 1 is drawn, SF renders image 1 sent by APP, and after SF completes rendering image 1, it further sends image 1 to GPU, so that after receiving image 1, GPU starts to perform layer synthesis on image 1. At this time, after the GPU completes synthesis of image 1, it will synchronously send the display data of image 1 to the image display driver of the electronic device's system kernel layer (that is, the moment when the GPU completes image synthesis also means that the image display driver has received the display data of the synthesized image 1). Therefore, after the GPU completes synthesis of image 1 before time t3 and sends image 1 to the image display driver, the image display driver writes the display data of image 1 to the display screen in response to the VSync signal 3 at time t3, so that the display screen refreshes the display image 1 at time t3.

[0093] After time t3, while the display screen is displaying image 1, the APP starts drawing image 2. After image 2 is drawn, the SF renders image 2 sent by the APP, and after SF completes rendering image 2, it further sends image 2 to the GPU. After receiving image 2, the GPU starts to perform layer synthesis on image 2. As shown in Figure 3, image 2 has been synthesized at time t0, and the GPU synchronously sends the display data of image 1 to the image display driver of the kernel layer of the electronic device system. At this time, the image display driver waits from time t0 to time t4, and the display screen generates VSync signal 4. At time t4, the image display driver responds to VSync signal 4 and writes the display data of image 2 to the display screen, so that the display screen refreshes the display image 2 at time t4.

[0094] At time t5, the app has already completed the electronic device's previous image display request and therefore does not draw a new image. Furthermore, the electronic device has not generated any new image display requests from time t4 until time t5. Therefore, the display screen stops refreshing the image after it finishes displaying Image 2 at time t5. At this point, the display screen enters a dormant or off state.

[0095] In combination with the above, after the display data of Image 2 is prepared, that is, after Image 2 completes the drawing of the APP, the rendering of the SF and the synthesis processing of the GPU, the time waiting for the next VSync signal (VSync signal 4) to arrive in the image display driver is long, and Image 2 cannot be displayed on the display screen more quickly.

[0096] Therefore, in gaming scenarios that require high chirality, if a frame of image needs to wait a long time before being displayed on the display screen after the display data is prepared, it will result in an inability to respond to user interactions on the interface in a timely manner, resulting in poor chirality and affecting the user's gaming experience.

[0097] In order to improve the hand tracking performance of electronic devices, the present application proposes an image display method, which improves the hand tracking performance of electronic devices by reducing the waiting time for the next VSync signal after the image display data is prepared.

[0098] It should be noted that the method proposed in the embodiment of the present application can be considered as a separate improvement to the above-mentioned solution for adjusting the software control logic of the upper layer of the electronic device system (such as the application layer, application framework layer, or hardware abstraction layer), and can also be considered as a further optimization and supplement to the solution for adjusting the software control logic. That is, the image display method proposed in the embodiment of the present application has been improved separately at the software control level of the electronic device system, and the method proposed in the embodiment of the present application has also been creatively improved at the system hardware level, thereby combining the improvements at both the system software and hardware levels to further reduce the time the image waits for display after the display data is prepared, thereby greatly improving the chirality.

[0099] In a feasible implementation of the embodiment of the present application, as shown in FIG4 , the method proposed in the embodiment of the present application can be implemented by adding a frame tracking detection module to the core layer of the electronic device system to detect whether the image display data is ready. Based on this, when the frame tracking detection module detects that the image display data is ready, the image display driver of the electronic device immediately increases the frequency of the VSync signal output by the display screen, advances the time when the VSync signal is generated, and responds to the VSync signal with the increased frequency at the advanced time to drive the display screen to display the frame image. That is, the method proposed in the embodiment of the present application can enable the display screen to quickly display the next frame image when the image display data is ready, instead of requiring the display screen to display the next frame image after the previous frame image is displayed for the corresponding image display duration of the corresponding VSync cycle as in the traditional solution. In this way, it can effectively shorten the time it takes for the image display driver to send the image to the display screen, speed up the speed at which the electronic device responds to the interactive operations performed by the user on the display screen, and thus improve the hand tracking performance of the electronic device. Frame tracking here can be understood as setting the time in advance when the image display driver of the electronic device generates the VSync signal.

[0100] The method proposed in the embodiment of the present application improves the comprehensiveness of detecting whether the image display data is ready by configuring the frame tracking detection module in the image display driver of the core layer of the electronic device system, and improves the accuracy of the image display driver in instantly displaying the next frame of image by increasing the frequency of the output VSync signal and outputting the frequency of the next VSync signal in advance.

[0101] Next, in conjunction with FIG5 , a feasible specific implementation of the image display method provided in the embodiment of the present application is described.

[0102] As shown in Figure 5, if in a game scene with a frame rate of 60Hz, when the display screen of an electronic device (supporting a 360Hz base frequency) is performing image refresh display at the current refresh rate of 120Hz, if image 2 is displayed after data preparation is completed (synthesis is completed), it will take a while to reach the moment of generating the next VSync signal. The image display method provided by the embodiment of the present application detects and identifies that when image 2 is displayed, data preparation is completed (synthesis is completed) by adding a new hardware module - a frame tracking detection module in the core layer of the electronic device system. In response to the display data preparation of image 2, the image display driver of the electronic device increases the frequency of the VSync signal output by the display screen to 360Hz at time t4, and outputs VSync signal 4 at time t4.

[0103] It is understandable that since the maximum frequency of the VSync signal output by the display screen of the electronic device is 360Hz, the corresponding Vsync period is 2.8ms. In Figure 5, the time (t4) corresponding to the completion of the display data preparation of Image 2 is 2.8ms away from the time when the display screen is originally about to output the next VSync signal. Therefore, the image display driver of the electronic device can advance the time when the display screen outputs the next VSync signal by 2.8ms, that is, the display screen outputs the VSync signal 4 with a frequency increase at time t4 (the corresponding Vsync period is 2.8ms). The image display driver used to drive the display screen in the system kernel layer can then write the received display data of Image 2 to the display screen at time t4 in response to VSync signal 4 after receiving VSync signal 4. In this way, the display screen can start displaying Image 2 as soon as the display data of Image 2 is prepared, reducing the time that Image 2 waits for the next VSync signal after the display data preparation is completed.

[0104] In some feasible embodiments, the time corresponding to the completion of preparation of the display data of image 2 may be earlier, that is, the duration between this time and the time when the display screen is originally about to output the next VSync signal is greater than 2.8 ms.

[0105] As shown in Figure 6, if in a game scene with a frame rate of 60Hz, when the display screen of an electronic device (supporting a 360Hz base frequency) performs image refresh display at the current refresh rate of 120Hz, if the image 2 waits for the next VSync signal for more than 2.8ms after the display data is prepared (synthesis is completed) in the display data preparation (synthesis is completed) of the image 2, the image display method provided in the embodiment of the present application detects that the image 2 waits for the next VSync signal for more than 2.8ms after the display data preparation (synthesis is completed) is completed by adding a new hardware module in the kernel layer of the electronic device system - a frame tracking detection module. When the image 2 is detected to be waiting for the next VSync signal after the display data preparation (synthesis is completed), the image display driver of the electronic device increases the frequency of the VSync signal output by the display screen to 360Hz, and advances the time when the display screen outputs the next VSync signal by 2.8ms. Thus, the display screen outputs the VSync signal 4 with the frequency increased at time t4 (the corresponding Vsync period is 2.8ms), and the image display driver for driving the display screen in the kernel layer of the system can write the display data of the received image 2 to the display screen at time t4 in response to the VSync signal 4 after receiving the VSync signal 4. In this way, the display screen can start displaying the image 2 at time t4, thereby shortening the time for the image 2 to wait for the next VSync signal after the display data preparation is completed.

[0106] As shown in Figure 7, if in a game scene with a frame rate of 60Hz, when the display screen of the electronic device (supporting a 360Hz base frequency) performs image refresh display at the current refresh rate of 120Hz, if the GPU of the system application framework layer synthesizes image 2 for more than 16.6ms, that is, exceeds the time t7, the time when the GPU completes the synthesis of image 2 is t8. Then, the GPU will not send the display data of image 2 to the image display driver of the kernel layer until after the time t8, and thus cause the image display driver to miss the VSync signal generated at the time t7 and fail to send the image to the display screen at the time t7, resulting in the phenomenon that the display screen times out displaying image 1. In response to this phenomenon, the image display method provided in the embodiment of the present application, when the electronic device detects through the frame tracking detection module that the time for image 2 to wait for the next VSync signal after the display data preparation is completed exceeds 2.8ms, the frequency of the VSync signal output by the display screen is increased to 360Hz, and the time when the display screen outputs the next VSync signal is advanced by 2.8ms. Thus, the display screen can output the VSync signal 4 with the increased frequency at the time t4 (the corresponding Vsync period is 2.8ms). At time t4, the image display driver responds to VSync signal 4 and writes the display data of Image 2, which the GPU had synthesized and sent to the image display driver before time t4, to the display screen. This allows the display screen to start displaying Image 2 at time t4, shortening the time Image 2 waits for the next VSync signal after display data preparation is completed. This also shortens the display timeout period for Image 1.

[0107] Compared with the traditional solution, the image display method provided by the embodiment of the present application uses a newly added frame tracking detection module. When it is found that the image of the electronic device is ready for display data, the display screen increases the frequency of the VSync signal output by the display screen, and advances the time of outputting the VSync signal by a set time, so that the image display driver can immediately display the image based on the VSync signal with the increased frequency at the advanced time. In this way, the display screen does not need to use a frame rate of 120hz (corresponding to 1 VSync cycle of 8.3ms) at the driver layer as in the traditional solution. When a frame of image waits for the next VSync signal for more than the set time (such as 2.8ms) after the display data is prepared, the image display driver writes the image to the display screen for display, resulting in the problem of not being able to display the image quickly and having low chirality. The embodiment of the present application can increase the frequency of the VSync signal output by the display screen and advance the time when the display screen outputs the VSync signal, so as to write the image to the display screen in advance based on the VSync signal with the increased frequency, so as to achieve fast display of the next frame of image by the display screen and improve chirality. Therefore, the present application can advance the time of generating the next VSync signal after the display data of the image is prepared, and display the frame image in time, thereby improving the hand tracking performance of the electronic device.

[0108] Based on the overall overview of the image display method provided by the above-mentioned embodiment of the present application, the specific embodiments of the image display method provided by the embodiment of the present application are described in turn below.

[0109] Please refer to Figure 8, which is a flowchart of a specific implementation of the image display method provided in an embodiment of the present application. It should be understood that although the execution order of some method steps is shown in Figure 8, the image display method provided in the embodiment of the present application can adopt an execution order different from the method steps shown in the figure based on the different design needs of actual applications. That is, the order of the method steps shown in Figure 8 does not constitute a limitation on the execution logical order of the image display method provided in the embodiment of the present application, and any other reasonable changes based on the order of the method steps shown in Figure 8 should be included in the scope of protection of the image display method provided in the embodiment of the present application.

[0110] In one feasible embodiment of the image display method provided in the embodiments of the present application, when the image display method is executed by an electronic device, at a first moment, the electronic device generates a first Vsync signal. In response to the first Vsync signal, the display screen of the electronic device begins to display a first image. At a second moment after the first moment, the electronic device generates a second Vsync signal. In response to the second Vsync signal, the display screen begins to display a second image. At a third moment after the second moment, in response to the completion of preparation of display data for the second image, the electronic device generates a third Vsync signal.

[0111] It should be noted that in the embodiment of the present application, the first Vsync signal generated by the electronic device at the first moment corresponds to the first Vsync cycle, and the first Vsync cycle corresponds to the first display duration of the first image, that is, the first VSync cycle is equal to the first display duration. The second Vsync signal generated by the electronic device at the second moment corresponds to the second Vsync cycle, and the second Vsync cycle is equal to the first Vsync cycle. The third Vsync signal generated by the electronic device at the third moment corresponds to the third Vsync cycle, and the third Vsync cycle is shorter than the first Vsync cycle.

[0112] In the embodiment of the present application, a smaller Vsync period indicates a higher frequency of the output Vsync signal. The electronic device may generate the third Vsync signal at the third moment in response to the completion of display data preparation for the third image. This may be achieved by controlling the display screen, through its own image display driver, to increase the frequency of the trigger Vsync signal when the display data for the third image is ready, so that the display screen outputs the third Vsync signal at the increased frequency at the third moment.

[0113] In the embodiment of the present application, by generating a third Vsync signal at the third moment, the display screen can start displaying the third image after the display data of the third image is prepared and the time the third image waits for the Vsync signal is extremely short.

[0114] In a feasible embodiment, the electronic device controls the display screen through the image display driver to advance the time of generating the Vsync signal, and increases the frequency of triggering the Vsync signal, and the specific process of the electronic device generating the third Vsync signal at the third time can be referred to S1 to S3 shown in Figure 8.

[0115] S1: Detecting whether display data of the third image is ready.

[0116] In the embodiment of the present application, the image display driver of the electronic device detects in real time whether display data of the third image is ready after the display screen displays the second image in response to the second Vsync signal at the second moment.

[0117] It should be noted that, in the embodiment of the present application, the second image displayed on the display screen is the next frame image of the first image displayed on the display screen.

[0118] For example, when the display screen uses 60Hz as the current refresh rate to refresh the image and uses this 60Hz frequency as the frequency for triggering the Vsync signal, when the first Vsync signal is triggered at the first moment, the first Vsync period corresponding to the first Vsync signal is approximately 1 / 60≈16.6ms, that is, the display screen triggers a first Vsync signal every 16.6ms. At this time, the first display duration corresponding to the first Vsync period is also approximately 16.6ms, that is, the display screen refreshes and displays one frame of image every approximately 16.6ms. At the second moment, the display screen responds to the second Vsync signal to display the second image. While the display screen is displaying the second image, it detects whether the display data for the third image is ready.

[0119] Since the second Vsync period is equal to the first Vsync period, after the display screen displays the second image in response to the second Vsync signal at the second moment, the second display duration for the display screen to display the second image is normally approximately 16.6ms. The moment when the display of the second image ends can be recorded as time 1, which is the moment when the next Vsync signal is generated. Prior to time 1, the image display driver of the electronic device detects whether the display data for the third image is ready.

[0120] S2: When the display data of the third image is ready, the frequency of outputting the third Vsync signal is increased.

[0121] In an embodiment of the present application, the image display driver of the electronic device controls the display screen to increase the frequency of the output Vsync signal and generate a third Vsync signal when detecting that display data of the third image is ready during the process of the display screen displaying the second image.

[0122] Exemplarily, in the image display driver of an electronic device, when the display screen adopts the current refresh rate of 60 Hz as the frequency of the output Vsync signal and displays the second image, the image display driver detects that the display data of the third image is ready, and records the moment when the display data of the third image is ready as moment 2. Among them, moment 2 is before moment 1. If the duration between moment 2 and moment 1 is greater than or equal to the set duration, the set duration can be a period corresponding to the maximum refresh rate of 360 Hz of the electronic device, which is approximately 1 / 360≈2.8ms. That is to say, if the duration between moment 2 and moment 1 is greater than or equal to 2.8ms, the image display driver of the electronic device sends a control instruction to the display screen to increase the frequency of the currently adopted output Vsync signal of 60 Hz, so that the display screen can be controlled to generate a third Vsync signal at a moment 2.8ms before moment 1.

[0123] If the duration between time 2 and time 1 is less than 2.8 ms, the image display driver of the electronic device sends a control instruction to the display screen to control the display screen to generate a third Vsync signal at time 1. In addition, the image display driver can also control the display screen to increase the frequency of the currently used output Vsync signal of 60 Hz.

[0124] In other examples, if the duration between time 2 and time 1 is less than 2.8 ms, the image display driver of the electronic device may not send a control instruction to the display screen, and wait until time 1 for the display screen to generate the third Vsync signal.

[0125] S3: Generate a third Vsync signal.

[0126] In the embodiment of the present application, if the duration between time 2 and time 1 is greater than or equal to 2.8 ms, then the third time is 2.8 ms before time 1. If the duration between time 2 and time 1 is less than 2.8 ms, then the third time is time 1. At the third time, the image display driver of the electronic device outputs a third Vsync signal with a raised frequency to the image display driver and other software and hardware modules.

[0127] It should be noted that in the embodiment of the present application, since the higher the frequency of the output Vsync signal, the smaller the Vsync period, therefore, after the display screen increases the frequency of the output Vsync signal, the third Vsync period corresponding to the third Vsync signal triggered at the third moment is smaller than the above-mentioned first Vsync period and also smaller than the above-mentioned second Vsync period (when the display screen outputs the first Vsync signal at the first moment and outputs the second Vsync signal at the second moment, the frequency of the output Vsync signal has not yet been increased).

[0128] For example, after the electronic device controls the display to increase the frequency of the currently used output Vsync signal from 60Hz to 360Hz, the display outputs a third Vsync signal with a first increased output frequency after increasing the frequency of the output Vsync signal by approximately 2.8ms, based on a Vsync period corresponding to the increased frequency of 360Hz, 1 / 360≈2.8ms. At this time, the third Vsync period corresponding to the third Vsync signal is approximately 2.8ms, which is shorter than the first Vsync period of approximately 16.6ms.

[0129] In a feasible embodiment, the specific process of the display screen displaying the next frame image of the second image in response to the third Vsync signal can be further referred to S4 shown in FIG8 .

[0130] S4: Writing display data of the third image.

[0131] It should be noted that, in the embodiment of the present application, the third image is the next frame image of the above-mentioned second image.

[0132] In the embodiment of the present application, in response to the electronic device generating a third Vsync signal at a third moment, the display screen displays a third image. That is, after receiving the display data of the third image sent by the upper layer of the system, the image display driver of the electronic device writes the display data of the third image to the display screen in response to the third Vsync signal with a frequency boost output by the display screen at the third moment, so that the display screen displays the third image at the third moment.

[0133] For example, assuming the electronic device's display screen supports a 360Hz base frequency, then when the display screen uses the current 60Hz refresh rate, the image display duration corresponding to 16.6ms. During the image display process, the display screen uses this 60Hz frequency as the frequency of the output Vsync signal. After the display screen responds to the second Vsync signal at a second moment and begins displaying the second image, the electronic device's image display driver detects whether the display data for the third image is ready. Upon detecting that the display data for the third image is ready, the image display driver controls the display screen to activate a pre-set 360Hz-TE high-frequency synchronization scheme, thereby increasing the frequency of the output Vsync signal to 360Hz. Thus, at the third moment, the display screen outputs the increased third Vsync signal, corresponding to a Vsync period of 1 / 360≈2.8ms corresponding to a 360Hz frequency. After receiving the third Vsync signal, the image display driver responds to the third Vsync signal and writes the display data for the third image, sent by the upper system layer before the third moment, to the display screen. Thus, the display screen begins refreshing and displaying the third image at the third moment. At this time, after the display data of the third image is prepared, the time it takes to wait for the next Vsync signal is extremely short, and will not exceed 2.8ms.

[0134] In other feasible embodiments, if the duration between the moment when the display data for the third image is ready and time 1 is exactly 2.8 ms, then the moment when the display data for the third image is ready is the third time. In this case, the display screen begins refreshing and displaying the third image at the moment when the display data for the third image is ready, and there is no waiting period for the third image to be displayed.

[0135] It should be noted that in the embodiment of the present application, the 360Hz-TE high-frequency synchronization solution can be a Vsync signal output control solution pre-added to the display screen, allowing the display screen to switch the frequency of the output Vsync signal based on needs. It should be understood that based on the different design requirements of actual applications, other Vsync signal output control solutions of the same type but with different frequencies can of course be pre-added to the display screen, such as a 60Hz-TE low-frequency synchronization solution and a 120Hz-TE standard frequency synchronization solution.

[0136] When a display responds to a synchronization scheme with a specific frequency, it outputs a Vsync signal based on the Vsync period corresponding to that frequency. For example, when a 360Hz-TE high-frequency synchronization scheme is enabled, the display outputs a Vsync signal every 2.8ms, with a Vsync period corresponding to the 360Hz frequency of 2.8ms. When a 120Hz-TE standard-frequency synchronization scheme is enabled, the display outputs a Vsync signal every 8.3ms, with a Vsync period corresponding to the 120Hz frequency of 8.3ms. And when a 60Hz-TE low-frequency synchronization scheme is enabled, the display outputs a Vsync signal every 16.6ms, with a Vsync period corresponding to the 60Hz frequency of 16.6ms.

[0137] In an embodiment of the present application, when the display screen of the electronic device uses 60 Hz as the current refresh rate for image refresh display, a 60 Hz-TE low-frequency synchronization scheme can be used by default to output a Vsync signal with 60 Hz as the original frequency.

[0138] Compared to the traditional solution that always uses a 120Hz image refresh rate, the embodiment of the present application uses a 60Hz image refresh rate when the 360Hz-TE high-frequency synchronization solution is not enabled. The actual number of times 360Hz-TE is enabled is approximately one-third less than the number of times 120Hz-TE is always enabled in the traditional solution. Therefore, this solution can minimize the time the image waits for the Vsync signal after display data preparation is completed, thereby achieving high-chirality performance requirements while reducing power consumption.

[0139] In other feasible embodiments, the electronic device can also detect through the image display driver the length of time that the previous frame image waits for the next Vsync signal after the display data preparation is completed. If the length of time exceeds the first set length, and the length of time that the display data of the current frame image waits for the next Vsync signal after the display data is completed exceeds the second set length, then the image display driver can control the display screen to increase the frequency of the output Vsync signal, and in response to the Vsync signal with the increased frequency output by the display screen at this moment, write the display data of the current frame image to the display screen, so that the display screen starts to display the current frame image at this moment.

[0140] In some examples, the first set duration and the second set duration may be equal, both being 2.8 ms. In other examples, the first set duration and the second set duration may be unequal, such as 5.5 ms and 2.8 ms. In this application, the first set duration and the second set duration may be adjusted according to actual circumstances, and there is no limitation on this.

[0141] As shown in Figure 9, while the display screen is displaying Image-1, the image display driver detects that the display data for Image 0 is ready and that the waiting time for Vsync signal 2 exceeds 2.8ms. Then, when the display screen responds to Vsync signal 2 and begins refreshing and displaying Image 0 at time t2, if the image display driver detects that the waiting time for the next Vsync signal after the display data preparation for Image 1 has also exceeded 2.8ms, the image display driver increases the frequency of the next Vsync signal and controls the display screen to output Vsync signal 3 2.8ms in advance. After receiving Vsync signal 3, the image display driver responds to Vsync signal 3 and writes the display data for Image 1 sent by the upper layer of the system before time t3 to the display screen. In this way, the display screen begins refreshing and displaying Image 1 at time t3.

[0142] Therefore, the electronic device shortens the time it takes for the image to wait for the next Vsync signal after display data preparation is completed, thereby speeding up the display speed of the image.

[0143] In other feasible embodiments, as shown in Figure 10, after reducing the display duration of Image 0, the electronic device ensures that the display duration of Image 1 remains normal, that is, the display duration remains at 16.6ms. In this case, at time t4, the electronic device can turn off the 360Hz high-frequency synchronization signal. Then, during the subsequent display process, the electronic device continues to detect the duration of the next Vsync signal after the display data of Image 3 is prepared.

[0144] In other feasible embodiments, if the time between when image 2 waits for the next VSync signal to be generated after the display data preparation is completed exceeds two 360Hz cycles, that is, exceeds 5.6ms. The present application can increase the frequency of the output VSync signal to 360Hz, and output the next VSync signal 2.8ms in advance. As shown in Figure 10, the moment when the display data of image 2 is ready is before the moment t41, then the image display driver can control the display screen to output the VSync signal 4 with the frequency increased at the moment t42. Then, the image display driver writes the received display data of image 2 to the display screen in response to the VSync signal 4 output at the moment t42. In this way, the display screen can start displaying image 2 at the moment t42, saving the time when image 2 waits for the next VSync signal after the display data preparation is completed.

[0145] In other feasible embodiments, if the time between when image 2 waits for the next VSync signal to be generated after the display data preparation is completed exceeds two 360Hz cycles, that is, exceeds 5.6ms. The present application can increase the frequency of the output VSync signal to 360Hz, and output the next VSync signal 5.6ms in advance. As shown in Figure 11, the moment when the display data of image 2 is ready is before the moment t41, then the image display driver can control the display screen to output the VSync signal 4 with the frequency increased at the moment t41. Then, the image display driver writes the received display data of image 2 to the display screen in response to the VSync signal 4 output at the moment t41. In this way, the display screen can start displaying image 2 at the moment t41, saving the time when image 2 waits for the next VSync signal after the display data preparation is completed.

[0146] It will be appreciated that the advance timing at which the display generates the next VSync signal may be related to the number of 360Hz cycles that the image waits for the next VSync signal after display data preparation is completed. For example, if the wait time for image 2 to generate the next VSync signal after display data preparation is completed exceeds two 360Hz cycles, the image display driver may control the display to output the frequency-boosted VSync signal 4 5.6ms in advance. If the wait time for image 2 to generate the next VSync signal after display data preparation is completed exceeds one 360Hz cycle, the image display driver may control the display to output the frequency-boosted VSync signal 4 2.8ms in advance. To minimize refresh rate fluctuations in electronic devices, the image display driver may control the display to output the frequency-boosted VSync signal only 2.8ms in advance, even if the wait time for the next VSync signal after display data preparation is completed exceeds two or more 360Hz cycles.

[0147] In an embodiment of the present application, an electronic device detects the time that the previous frame image waits for the next Vsync signal after the display data is prepared through an image display driver to determine whether to increase the frequency of the next VSync signal of the current frame image after the display data is prepared. The time that the previous frame image waits for the next Vsync signal after the display data is prepared is related to the advance moment corresponding to the next VSync signal generated by the display screen. The shorter the time that the previous frame image waits for the next Vsync signal after the display data is prepared, the greater the jitter of the displayed image; the longer the time that the previous frame image waits for the next Vsync signal after the display data is prepared, the smaller the jitter of the displayed image. For example, when the time that the previous frame image waits for the next Vsync signal after the display data is prepared is about 2.7ms, the frequency of triggering frame chasing is 100 / 600, and the greater the jitter of the displayed image, wherein the average time that the image waits for the next Vsync signal after the display data is prepared is 4ms. If the previous frame waits for the next Vsync signal for approximately 5.4ms after display data preparation is completed, the frame tracking frequency is triggered at 90 / 600, and the average waiting time for the next Vsync signal after display data preparation is completed is 6ms. If the previous frame waits for the next Vsync signal for approximately 8.1ms after display data preparation is completed, the frame tracking frequency is triggered at 80 / 600, and the average waiting time for the next Vsync signal after display data preparation is completed is 9ms.

[0148] In traditional solutions, a 120hz frame rate is used at the driver layer. However, in a game scenario with a frame rate of 60Hz, if you look at the actual frame rate of the game engine over a longer period of time, it will be drawn at 60Hz+, but the time interval between two or more local frames is uncontrollable. As a result, a situation like Figure 12 will occur. As shown in Figure 12, the DDIC of the display screen of the electronic device supports a 120Hz image refresh rate. When the DDIC refreshes and outputs the vertical synchronization signal at a frequency of 120Hz, the VSync period of the output vertical synchronization signal is approximately 8.3ms. In this way, in a 60Hz game scenario, each image usually needs to display two VSync periods of approximately 16.6ms.

[0149] The display starts to display image-1 for 16.6ms at time t1. During the display of image-1, if the APP of the electronic device application layer starts to draw image 0, the SF of the electronic device application framework layer renders the image 0 previously sent by the APP through the rendering service render server (also called the render thread), and after SF completes the rendering of image 0, it will further send image 0 downward to the GPU, so that after receiving image 0, the GPU immediately starts to process the layer synthesis of image 0. Since the time when image 0 is completed is more than t2, image 0 waits until time t3 after synthesis, and writes the display data of image 0 to the display in response to the VSync signal output by the display, so that the display refreshes the display image 0 at time t3 until time t5.

[0150] The APP in the application layer of the electronic device starts drawing image 1, and the SF renders the image 1 sent by the APP, and after the SF completes the rendering of image 1, it further sends the image 1 to the GPU, so that after receiving the image 1, the GPU starts to perform layer synthesis on the image 1. At this time, after the GPU completes the synthesis of image 1, it will synchronously send the display data of image 1 to the image display driver in the kernel layer of the electronic device system (that is, the moment when the GPU completes the image synthesis also means that the image display driver has received the display data of the synthesized image 1). Therefore, after the GPU completes the synthesis of image 1 before time t5 and sends image 1 to the image display driver, the image display driver writes the display data of image 1 to the display screen in response to the VSync signal at time t5, so that the display screen refreshes the display image 1 at time t5.

[0151] After Image 1 is displayed for 16.6ms, at time t7, Image 2 synthesis is completed after t7. At this point, the image display driver fails to receive the display data for Image 2 at t7 and does not perform any image processing until the next VSync signal arrives. The display continues to display Image 1 until a new VSync signal is generated at t8. Therefore, Image 1 is displayed for 25ms. At this point, Image 2 synthesis is complete, and the display refreshes and displays Image 2 at t8.

[0152] At time t9, the display receives a new VSync signal. Because the GPU had already completed compositing Image 3 and sent the display data for Image 3 to the display driver before t9, the display driver responds to the VSync signal and writes the display data for Image 3 to the display at t9. The display begins refreshing Image 3 at t9 and continues displaying Image 3 until t11. Therefore, Image 2 is displayed for 8.3ms, and Image 3 for 16.6ms.

[0153] At time t11, the app had already completed the electronic device's previous image display request and therefore did not draw a new image. Furthermore, the electronic device had not generated any new image display requests from time t9 until time t11. Therefore, the display screen stopped refreshing the image after it finished displaying image 3 at time t11. At this point, the display screen enters a dormant or off-screen state.

[0154] In combination with the above, electronic devices may experience an application layer APP drawing image timeout (not shown in the attached figure), which may cause the SF rendering image of the application framework layer and the GPU synthesis image of the application framework layer to time out, or the SF rendering image of the application framework layer may time out the GPU synthesis image of the application framework layer, or the GPU synthesis image of the application framework layer may time out, thereby causing the image display driver of the kernel layer to miss the VSync signal to send the image to the display screen. Therefore, even if the electronic device uses a 120Hz refresh rate at the driver layer, the display screen needs to time out the displayed image for a period corresponding to the 120Hz refresh rate (8.3ms).

[0155] Therefore, in the above-mentioned gaming scenario, the electronic device may encounter a situation where the display data of a certain frame image is generated slowly and the display data of the next frame image is generated quickly, resulting in the display time of the previous frame image of the frame image timing out, and the display time of the frame image is too short, and the display time of the next frame image of the frame image returns to normal. For example, in Figure 12, when the display data of image 1 is generated slowly and the display data of image 2 is generated quickly, the display time of image 1 is 25ms, the display time of image 2 is 8.3ms, and the display time of image 3 is 16.6ms. That is, at this time, the display screen shows that the current refresh rate increases from 40Hz to 120Hz, and then drops directly from 120Hz to 60Hz. For users, because the human eye is more sensitive to refresh rate fluctuations, the current refresh rate of the display screen increases from 40Hz to 120Hz, and then drops directly from 120Hz to 60Hz, which will be visually perceived as jittering.

[0156] In order to improve the hand tracking performance of electronic devices and reduce the actual jitter caused by frame rate fluctuations when actual freezes occur, the present application proposes an image display method. By reducing the waiting time for the next VSync signal after the image display data is prepared, and turning off the high-frequency TE signal for the duration of the next frame to ensure the continuation of the current refresh rate, the hand tracking performance of the electronic device can be improved while making it difficult for users to notice the jitter in the device display screen.

[0157] As shown in Figure 13, during the image refresh process of an electronic device's display (supporting a 360Hz base frequency) at a current refresh rate of 60Hz, if the GPU of the system application framework layer synthesizes image 2 beyond the time (t7) at which VSync signal 4 is generated, the electronic device, upon detecting that the time that image 2 waits for the next VSync signal after display data preparation is completed exceeds 2.8ms, increases the frequency of the VSync signal output by the display to 360Hz and advances the time at which the display outputs the next VSync signal by 2.8ms. As shown in Figure 13, the display can then output the increased frequency VSync signal 5 at time t8 (corresponding to a VSync period of 2.8ms). At time t8, the image display driver, in response to VSync signal 5, writes the display data of image 2, which had been synthesized by the GPU and sent to the image display driver before time t8, to the display, allowing the display to begin displaying image 2 at time t8, significantly shortening the time that image 2 waits for the next VSync signal after display data preparation is completed. Moreover, the display timeout duration of image 1 is shortened, and the display time of image 2 can be restored to a normal time.

[0158] Then, when the display starts displaying Image 2 at time t8, the display duration of Image 2 will be maintained at 16.6ms, that is, the display will continue until time t10. In other words, if the display data of Image 3 is ready before time t10, even if the time between the time when the display data of Image 3 is ready and time t10 exceeds 2.8ms, the image display driver will not advance the time when the display outputs the next VSync signal. Instead, at time t10, the image display driver writes the display data of Image 3 to the display in response to VSync signal 6, so that the display can start displaying Image 3 at time t10. In addition, the electronic device will maintain the display duration of Image 3 for 16.6ms, that is, the display will continue until time t12.

[0159] Therefore, this solution can reduce the image timeout display duration by shortening the time the image waits for display after the display data is prepared, while stabilizing the display duration of subsequent images, so that the display duration difference between adjacent images is small, which makes it difficult for users to notice jitter in the device display screen.

[0160] In other feasible embodiments, frame rate tracking may occur for every frame. Since each frame is displayed in advance for a short period of time, typically only 2.8ms, the user cannot perceive the frame rate fluctuations because the display durations of consecutive frames may vary.

[0161] In an embodiment of the present application, the electronic device can determine whether to increase the frequency of the output Vsync signal by combining improvements at the software and hardware levels. That is, the electronic device adds a new hardware module to the system kernel layer, and uses the hardware module to detect whether the display data of the image is ready. When the hardware module detects that the display data of the image is ready, the display screen outputs the Vsync signal. This reduces the waiting time for the display data to be displayed after the image is ready, thereby improving the chirality. As shown in FIG14 , the electronic device configures a new frame tracking detection module in the image display driver of the kernel layer. Based on this, in response to the display screen starting to display the second image, the electronic device continuously detects whether the display data of the third image is ready through the frame tracking detection module, and detects whether the waiting time for the third image to wait for the next Vsync signal is greater than or equal to the set time (2.8ms). Afterwards, when the frame tracking detection module detects that the display data of the third image is ready and the waiting time for the next Vsync signal is greater than or equal to 2.8ms, the image display driver sends a control instruction to the display screen to control the display screen to increase the frequency of the output Vsync signal.

[0162] In an embodiment of the present application, when detecting whether the time the third image waits for the next Vsync signal is greater than or equal to a set time, the image display driver of the electronic device can use its newly added frame tracking detection module to detect whether the time the third image waits for the next Vsync signal is greater than or equal to the set time while the display screen is displaying the second image. If the frame tracking detection module detects that the time the third image waits for the next Vsync signal is greater than or equal to the set time, the image display driver determines that the third image meets the conditions for outputting the next Vsync signal in advance.

[0163] When the image display driver determines that the third image waits for the next Vsync signal for a duration greater than or equal to a predetermined duration, and thus outputs the Vsync signal in advance and increases the frequency of the display's output Vsync signal, the image display driver can issue a control instruction to the display via the display module serial interface, which establishes a communication connection between the display driver and the display. Upon receiving the control instruction, the display immediately responds, increasing the frequency of the output Vsync signal from the original frequency to the frequency indicated by the control instruction.

[0164] In an embodiment of the present application, when the frame tracking detection module detects that the time the third image waits for the next Vsync signal after the display data preparation is completed is greater than or equal to the set time, the image display driver of the electronic device immediately increases the frequency of the Vsync signal output by the display screen, sets the time in advance to output the Vsync signal with the increased frequency, and responds to the Vsync signal with the increased frequency to write the display data of the third image to the display screen to drive the display screen to display the third image. In this way, it can effectively reduce the time the third image waits for the next Vsync signal after the display data preparation is completed, thereby speeding up the display speed of the third image. In addition, it can also improve the comprehensiveness of detecting whether the time the third image waits for the next Vsync signal after the display data preparation is completed is greater than or equal to the set time, and increase the frequency of the output Vsync signal to enable the image display driver to instantly display the third image.

[0165] In other feasible embodiments, the frame tracking detection module may also be used to detect whether the time the second image waits for the next Vsync signal after display data preparation is completed is greater than or equal to a set time. When the electronic device detects through the frame tracking detection module that the time the second image waits for the next Vsync signal after display data preparation is completed is greater than or equal to the set time, and that the display data of the third image is prepared and the time it waits for the next Vsync signal is greater than or equal to 2.8ms, the image display driver sends a control instruction to the display screen to control the display screen to increase the frequency of the output Vsync signal.

[0166] Exemplarily, in combination with the system framework of the electronic device shown in Figure 14 and the electronic device shown in Figure 15, the control logic for image display using the method provided in the embodiment of the present application is assumed to support a 360Hz base frequency. When the display screen displays an image according to the first Vsync period of 16.6ms corresponding to a 60Hz refresh rate, while the display screen displays the second image, the browser application APP of the electronic device system application layer also draws the third image of the next frame of the second image, and sends the display data of the third image that has been drawn but needs to be rendered to the image rendering service (SF) in the application framework layer. After the SF completes rendering the display data, if the display data needs to be further synthesized, the rendered display data is further sent to the image synthesis service (GPU). After the GPU synthesizes the display data, it is sent to the hardware abstraction layer as the display data of the third image to be displayed, so that the hardware abstraction layer performs hardware matching to send the display data of the third image to the image display driver of the kernel layer. The image display driver performs pre-image sending preparations after receiving the display data of the third image.

[0167] Then, the image display driver determines whether to start the frame chasing scheme. If the frame chasing scheme is not started, the image display driver directly waits for the next Vsync signal to execute the image sending. If the frame chasing scheme is turned on, at this time, the image display driver obtains the result detected by the frame chasing detection module, and the result is that the time for the third image to wait for the next Vsync signal after the display data preparation is completed is greater than 2.8ms (360Hz period). That is, the third image has the conditions to turn on the high-frequency TE 2.8ms in advance. At this time, the image display driver can immediately send an instruction 1 to control the start of the high-frequency TE to the display screen through the display module serial interface (DSI) that establishes a communication connection with the display screen, thereby controlling the display screen to respond to the instruction 1 and start the pre-set 360Hz-TE high-frequency synchronization scheme 2.8ms in advance, thereby increasing the frequency of the Vsync signal output by the display screen to 360Hz.

[0168] As shown in FIG15 , after the image display driver determines that the third image has the conditions for turning on the high-frequency TE 2.8ms in advance based on the results detected by the frame tracking detection module, it is again determined by the results detected by the frame tracking detection module whether the current turning on of the high-frequency TE will only be 2.8ms in advance. In other words, if the time the third image waits for the next Vsync signal after the display data preparation is completed is greater than or equal to 2 times of 2.8ms, then the image display driver sends an instruction 1 for controlling the turning on of the high-frequency TE to the display screen through the display module serial interface (DSI) that establishes a communication connection with the display screen. The instruction 1 includes the time for turning on the high-frequency TE only 2.8ms in advance compared to the original time of generating the next Vsync signal. Thus, the control display screen responds to the instruction 1 to turn on the pre-set 360Hz-TE high-frequency synchronization scheme 2.8ms in advance to increase the frequency of the Vsync signal output by the display screen to 360Hz. Therefore, when the time it takes for the third image to wait for the next Vsync signal after the display data preparation is completed is greater than or equal to 2 times of 2.8ms, the image display driver will not control the display screen to generate the Vsync signal with a higher frequency in advance by 2 or more cycles of 360hz, but will delay it to a moment only 2.8ms in advance to control the display screen to generate the Vsync signal with a higher frequency.

[0169] Among them, if the result detected by the frame tracking detection module determines that the current high-frequency TE is turned on only 2.8ms in advance, then the image display driver immediately sends an instruction 1 to control the turning on of the high-frequency TE to the display screen through the display module serial interface (DSI) that establishes a communication connection with the display screen, thereby controlling the display screen to respond to the instruction 1 and turn on the pre-set 360Hz-TE high-frequency synchronization scheme at a time of 2.8ms in advance, thereby increasing the frequency of the Vsync signal output by the display screen to 360Hz.

[0170] In some feasible embodiments, after the image display driver of the electronic device increases the frequency of the output Vsync signal, thereby driving the display screen to display an image in response to the Vsync signal with the increased frequency, in order to avoid the image display driver sending the next frame of the image for display in advance, thereby causing the display screen to only briefly display the image and then quickly display the next frame of the image, the electronic device can use the image display driver to not respond to the Vsync signal with the increased frequency output by the display screen within the display time of the display screen displaying the image, thereby forcing the display screen to display the image for an extended period of time.

[0171] In an embodiment of the present application, the electronic device can forcibly extend the duration of the display screen displaying the third image through steps S5 and S10 shown in FIG16 . After displaying the third image, the display screen executes step S5: feeding back a Vsync signal with a frequency increase. Upon receiving the Vsync signal with a frequency increase, if the third display duration of the third image displayed by the display screen has not yet equaled the first display duration, the image display driver executes step S6: stopping responding to the Vsync signal with a frequency increase. The display screen then continues to execute step S7: feeding back the Vsync signal with a frequency increase. Upon receiving the Vsync signal with a frequency increase, if the third display duration equals the first display duration, the image display driver executes step S8: resuming responding to the Vsync signal with a frequency increase. The display screen then executes step S9: feeding back the Vsync signal with a frequency increase. After receiving the Vsync signal, the image display driver executes step S10: writing display data for the next frame of the image to the display screen in response to the Vsync signal with a frequency increase. Thus, the display screen begins displaying the next frame of the image.

[0172] In an embodiment of the present application, after the image display driver of the electronic device writes the display data of the third image to the display screen to drive the display screen to display the third image, the image display driver stops responding to the Vsync signal with a frequency increase output by the display screen within the third display time duration when the display screen displays the third image, so as to refuse to write the display data of the next frame image of the third image to the display screen within the third display time duration.

[0173] Afterwards, when the third display time is equal to the first display time, the image display driver resumes responding to the Vsync signal with increased frequency output by the display screen, thereby writing the display data of the next frame of the third image to the display screen after the third display time reaches the first display time.

[0174] In the embodiment of the present application, the image display driver does not respond to the Vsync signal with a frequency increase triggered by the display screen during the third display duration of the display screen displaying the third image. This can prevent the image display driver from prematurely sending the next frame of the third image to the display screen during the display screen displaying the third image, causing the display screen to briefly display the third image. This further improves the stability of the electronic device in displaying the third image and subsequent images.

[0175] Please refer to Figure 17, which shows another control logic for an electronic device to display an image using the method provided in an embodiment of the present application. Assuming that the display screen of the electronic device supports a 360Hz base frequency, when the display screen displays an image according to the first Vsync period of 16.6ms corresponding to a 60Hz refresh rate, when the display screen displays the second image, the browser application APP of the electronic device system application layer also draws the third image of the next frame of the second image, and sends the display data of the third image that has been drawn but needs to be rendered to the image rendering service (SF) in the application framework layer. After the SF completes rendering the display data, if the display data needs to be further synthesized, the rendered display data is further sent to the image synthesis service (GPU). After the GPU synthesizes the display data, it is sent to the hardware abstraction layer as the display data of the third image to be displayed, so that the hardware abstraction layer performs hardware matching to send the display data of the third image to the image display driver of the kernel layer. The image display driver performs pre-image sending preparations after receiving the display data of the third image.

[0176] Then, the image display driver determines whether to enable the frame tracking scheme. If not, the image display driver directly waits for the next Vsync signal to send the image. If the frame tracking scheme is enabled, the image display driver obtains the result detected by the frame tracking detection module. The result is that the time the second image waits for the next Vsync signal after the display data is prepared exceeds the set time, which is 2.8ms (360Hz cycle).

[0177] At this point, the image display driver determines whether the time it takes for the third image to wait for the next Vsync signal after display data preparation is completed is greater than or equal to 2.8ms. If so, the third image meets the conditions for turning on the high-frequency TE 2.8ms in advance. At this point, the image display driver can immediately send a command 1 to control the turning on of the high-frequency TE to the display screen through the display module serial interface (DSI) that establishes a communication connection with the display screen. In response to the command 1, the display screen will turn on the pre-set 360Hz-TE high-frequency synchronization scheme 2.8ms in advance, thereby increasing the frequency of the display screen's output Vsync signal to 360Hz.

[0178] If the image display driver obtains the result detected by the frame tracking detection module that the time for the second image to wait for the next Vsync signal after the display data preparation is completed is less than 2.8ms, then the image display driver directly waits for the next Vsync signal to execute image transmission.

[0179] As shown in FIG17 , after the image display driver determines that the third image meets the conditions for turning on the high-frequency TE 2.8ms in advance based on the results detected by the frame tracking detection module, the frame tracking detection module is again used to determine whether the current high-frequency TE will be turned on only 2.8ms in advance. In other words, if the time the third image waits for the next Vsync signal after the display data preparation is completed is greater than or equal to 2 times of 2.8ms, then the image display driver sends a control instruction 1 for turning on the high-frequency TE to the display screen through the display module serial interface (DSI) that establishes a communication connection with the display screen. The instruction 1 includes the time for turning on the high-frequency TE only 2.8ms in advance of the original time for generating the next Vsync signal. Thus, the display screen is controlled to respond to the instruction 1 and turn on the pre-set 360Hz-TE high-frequency synchronization scheme 2.8ms in advance to increase the frequency of the Vsync signal output by the display screen to 360Hz. Therefore, when the time it takes for the third image to wait for the next Vsync signal after the display data preparation is completed is greater than 2 times or more of 2.8ms, the image display driver will not control the display screen to generate the Vsync signal with a higher frequency in advance by 2 or more 360hz cycles, but will delay it to a moment only 2.8ms in advance to control the display screen to generate the Vsync signal with a higher frequency.

[0180] Among them, if the result detected by the frame tracking detection module determines that the current high-frequency TE is turned on only 2.8ms in advance, then the image display driver immediately sends an instruction 1 to control the turning on of the high-frequency TE to the display screen through the display module serial interface (DSI) that establishes a communication connection with the display screen, thereby controlling the display screen to respond to the instruction 1 and turn on the pre-set 360Hz-TE high-frequency synchronization scheme at a time of 2.8ms in advance, thereby increasing the frequency of the Vsync signal output by the display screen to 360Hz.

[0181] In an embodiment of the present application, the time duration for the second image to wait for the next Vsync signal after the display data preparation is completed can be calculated by recording the timestamp when the second image starts waiting for the arrival of the next Vsync signal after the display data preparation is completed, and recording the timestamp when the next Vsync signal arrives and the image display driver writes the display data of the second image to the display screen.

[0182] Please refer to Figure 18, which shows a control logic provided by an embodiment of the present application for obtaining the length of time the second image waits for the next Vsync signal after display data preparation is completed. Assuming that the display screen of the electronic device supports a 360Hz base frequency, when the display screen displays an image according to the first Vsync period of 16.6ms corresponding to a 60Hz refresh rate, while the display screen displays the first image, the browser application APP of the electronic device system application layer also draws the second image of the next frame of the first image, and sends the display data of the second image that has been drawn but needs to be rendered to the image rendering service (SF) in the application framework layer. After the SF completes rendering the display data, if the display data needs to be further synthesized, the rendered display data is further sent to the image synthesis service (GPU). After the GPU synthesizes the display data, it is sent to the hardware abstraction layer as the display data of the second image to be displayed, so that the hardware abstraction layer performs hardware matching to send the display data of the second image to the image display driver of the kernel layer. The image display driver performs pre-image sending preparation after receiving the display data of the second image.

[0183] Then, the image display driver determines whether to start the frame chasing scheme. If the frame chasing scheme is not started, the image display driver directly waits for the next Vsync signal to send the image. If the frame chasing scheme is turned on, at this time, the image display driver starts to record the timestamp when the second image starts waiting for the next Vsync signal to arrive after the display data preparation is completed. Then, after waiting for the next Vsync signal, the image display driver performs the image sending operation, that is, writes the display data of the second image to the display screen. At this time, the image display driver will also determine whether to start the frame chasing scheme. If the frame chasing scheme is not started, the process ends. If the frame chasing scheme is turned on, at this time, the image display driver starts to record the timestamp when the next Vsync signal arrives and the image display driver executes the image sending. Therefore, through the two recorded timestamps, the length of time the two images wait for the next Vsync signal after the display data preparation is completed can be calculated.

[0184] Please refer to Figure 19, which shows a flow chart for configuring the frame chasing scheme. The SF module can write a node to turn on the frame chasing scheme through the Android Interface Definition Language (AIDL) interface and send the frame chasing start time value. The frame chasing start time value indicates the length of time the display outputs the VSync signal in advance. For example, the frame chasing start time value can be 2.8ms, or the frame chasing start time value can be indicated by a flag bit. For example, a flag bit of 1 can indicate that the frame chasing start time value is 2.8ms, and a flag bit of 2 can indicate that the frame chasing start time value is 5.5ms.

[0185] In some embodiments, embodiments of the present application provide an electronic device that implements the image display methods described in the above embodiments. This function can be implemented in hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions.

[0186] In some embodiments, an embodiment of the present application provides an electronic device, comprising: a processor and a memory; the memory is used to store computer program code, the computer program code includes computer execution instructions, and when the electronic device is running, the processor executes the computer execution instructions to enable the electronic device to perform the image display method described in the above embodiments.

[0187] In some embodiments, an embodiment of the present application provides an electronic device, comprising: a processor; the processor is used to couple with a memory, and after reading instructions in the memory, execute the image display method described in the above embodiments according to the instructions.

[0188] In some embodiments, an embodiment of the present application provides a computer-readable storage medium, including computer instructions. When the computer instructions are executed on an electronic device, the electronic device executes the wallpaper display method as described above.

[0189] In some embodiments, embodiments of the present application provide a computer program product. When the computer program product is run on an electronic device, the electronic device executes the image display method described in the above embodiments.

[0190] In some embodiments, the present application provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the image display methods described in the above embodiments.

[0191] In some embodiments, embodiments of the present application provide a device (e.g., a display system) that includes a processor configured to support an electronic device in implementing the image display methods described in the various embodiments above. In one possible design, the device also includes a memory configured to store program instructions and data necessary for the electronic device.

[0192] An embodiment of the present application also provides a chip system, as shown in Figure 20, the chip system 90 includes at least one processor 901 and at least one interface circuit 902. The processor 901 and the interface circuit 902 can be interconnected via lines. For example, the interface circuit 902 can be used to receive signals from other devices (such as the memory of an electronic device). For another example, the interface circuit 902 can be used to send signals to other devices (such as the processor 901). Exemplarily, the interface circuit 902 can read instructions stored in the memory and send the instructions to the processor 901. When the instructions are executed by the processor 901, the electronic device can perform the various steps in the above embodiments. Of course, the chip system can also include other discrete devices, which is not specifically limited in the embodiment of the present application.

[0193] Through the description of the above implementation methods, technical personnel in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0194] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place, or they may be distributed in multiple different places. Some or all of the units may be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

[0195] In addition, the functional units in the various embodiments of the present application can be integrated into a processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of a software functional unit. If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or in other words, the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a device (which can be a single-chip microcomputer, chip, etc.) or a processor to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program code, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0196] The above content is only a specific embodiment of this application, but the scope of protection of this application is not limited to this. Any changes or replacements within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. An image display method, characterized in that, Applied to an electronic device, the electronic device includes a display screen, and the method includes: At a first moment, the electronic device generates a first Vsync signal. In response to the first Vsync signal, starting to display a first image on the display screen, wherein the first Vsync signal corresponds to a first Vsync signal period, and a first display duration of displaying the first image is the same as a duration of the first Vsync signal period; At a second moment, the electronic device generates a second Vsync signal. In response to the second Vsync signal, starting to display a second image on the display screen, wherein the second Vsync signal corresponds to a second Vsync signal period, the second moment is after the first moment, and the second image is the next frame image of the first image; After starting to display the second image on the display screen, detecting whether display data of a third image is synthesized completely, wherein the third image is the next frame image of the second image; if the display data of the third image is synthesized completely, sending a control instruction to the display screen, and the control instruction is used to control a frequency of generating a Vsync signal.

2. The method according to claim 1, wherein The step that if the display data of the third image is synthesized completely, the image display driver sends a control instruction to the display screen includes: If a duration between a moment when the display data of the third image is synthesized completely and a moment when the electronic device is preset to generate a third Vsync signal is greater than or equal to a preset interval duration, sending a control instruction to the display screen.

3. The method according to claim 2, wherein The electronic device further includes an image display driver. If a duration between a moment when the display data of the third image is synthesized completely and a moment when the electronic device is preset to generate a third Vsync signal is greater than or equal to a preset interval duration, sending a control instruction to the display screen, specifically: If a duration between a moment when the display data of the third image is synthesized completely and a moment when the electronic device is preset to generate a third Vsync signal is greater than or equal to a preset interval duration, the image display driver sends a control instruction to the display screen, and the control instruction is used to control a frequency of generating a Vsync signal, so that a frequency of the display screen generating a Vsync signal is higher than a current frequency of the display screen generating a Vsync signal.

4. The method according to claim 2, wherein The preset interval duration is 2.8 ms.

5. The method according to any one of claims 1-4, characterized in that, After sending the control instruction to the display screen, the method further includes: At a third moment, the electronic device generates a third Vsync signal; wherein the third Vsync signal corresponds to a third Vsync signal period, the third moment is after the second moment, and the third Vsync signal period is less than the first Vsync signal period.

6. The method according to claim 5, characterized in that, The second Vsync signal period is less than the first Vsync signal period, and a second display duration of displaying the second image is less than the first display duration.

7. The method according to claim 6, characterized in that, The first Vsync signal period is 16.6 ms, and the third Vsync signal period is 2.8 ms.

8. The method according to claim 7, wherein The second Vsync signal period is 13.8 ms, and the second display duration is 13.8 ms.

9. The method according to claim 5, wherein The method further includes: At a fourth moment, the electronic device generates a fourth Vsync signal, and in response to the fourth Vsync signal, starts to display a fourth image on the display screen, where the fourth moment is after the third moment, the fourth Vsync signal corresponds to the fourth Vsync signal period, the fourth Vsync signal period is the same as the first Vsync period, and the fourth display duration for displaying the fourth image is the same as the first display duration.

10. The method according to claim 9, wherein The method further includes: before the fourth moment, sending a control instruction to the display screen, where the control instruction is used to control the frequency of generating the Vsync signal.

11. The method according to claim 10, wherein Before the fourth moment, sending a control instruction to the display screen, where the control instruction is used to control the frequency of generating the Vsync signal, specifically: The image display driver sends a control instruction to the display screen, where the control instruction is used to control the frequency of generating the Vsync signal, so that the frequency of generating the Vsync signal by the display screen is lower than the current frequency of generating the Vsync signal by the display screen.

12. An electronic device, characterized in that, The electronic device includes: a communication module, a display screen, a memory, and one or more processors; the communication module, the display screen, the memory, and the processor are coupled; the memory is used to store computer program code, and the computer program code includes computer instructions. When the computer instructions are executed by the electronic device, the electronic device executes the method according to any one of claims 1-11.

13. A computer-readable storage medium, characterized in that, Instructions are stored in the computer-readable storage medium. When the instructions run in the electronic device, the electronic device executes the method according to any one of claims 1 to 11.

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