Digital phase locked loop system and method for integral gain calibration

Abstract

A PLL system (200) and method for calibrating an integral gain of the PLL system (200). The PLL system (200) comprises a controlled oscillator (CO) (210), a digital phase detector (PD) (220), an accumulator (230), a first gain module (240), a second gain module (250) and a combiner (260). The PLL system (200) further comprises a first gain calibration module (270) configured to process an accumulated signal of the PD (220) to generate a periodicity measure for the accumulated signal of the PD (220), adjust the integral gain factor (Ki) based on the periodicity measure and provide the adjusted integral gain factor (Kiadj) to the first gain module (240).

Description

[0001] DIGITAL PHASE LOCKED LOOP SYSTEM AND METHOD FOR INTEGRAL GAIN CALIBRATION

[0002] TECHNICAL FIELD

[0003] Embodiments herein relate to Phase Locked Loop (PLL) system. In particular, they relate to PLL system, method for integral gain calibration of the PLL system, transceivers and electronic apparatus comprising the PLL system.

[0004] BACKGROUND

[0005] There is a need for accurate local oscillator (LO) signals in wireless transceivers. Typically, LO signals are generated using phase locked loops (PLLs). Traditionally analog PLLs have been used, but lately also digital ones. Currently both options are viable, with different pros and cons. A digital PLL (DPLL) has advantages in the absence of an analog loop filter with large area capacitors, and possibility to support advanced digital algorithms to, for instance, speed up frequency hops. An analog PLL on the other hand is much less complex to design and may have excellent performance regarding phase noise, in applications where the DPLL in-band phase noise is dominating error vector magnitude (EVM) and signal to noise ratio (SNR) of a transceiver.

[0006] DPLLs are becoming in performance equal to their analog counterparts thanks to complementary metal-oxide-semiconductor (CMOS) technology scaling. In the core of a DPLL is a time to digital converter (TDC), which converts phase difference between a reference signal and a feedback signal from a digitally controlled oscillator (DCO) output into digital codes.

[0007] A special flavor of the TDC is a Bang-Bang or binary phase detector (BBPD). The BBPD can only distinguish between leading or lagging phases and thus outputs only one single bit of phase information. The BBPD has an advantage that it may be implemented in a very simple fashion compared to multi-bit counterparts enabling extremely low noise PLLs. This has been demonstrated in S. Ek et al., "A Bang-Bang Digital PLL Covering 11.1-14.3 GHz and 14.7-18.7 GHz with sub-40 fs RMS Jitter in 7 nm FinFET Technology", 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC), 2022, pp. 237-240.

[0008] Among the drawbacks, apart from inability to generate information about the level of the phase error and thereby making high performance fractional-N operation impossible, the gain of the BBPD is largely unknown and input signal dependent. Fully digital algorithms observing the BBPD output sequence have been proposed to adjust the PLL loop gain such that the PLL output root mean square (RMS) jitter is minimized, e.g. in S. Jang et al., “An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang-Bang Phase- Frequency Detection”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 62, no. 9, pp. 836-840, 2015.

[0009] The PLL loop gain consists of proportional gain Kpand integral gain Kj. The existing solutions can perform full calibration of the proportional gain Kp. For integral gain Kj calibration, a predefined relationship between the proportional gain Kpand integral gain Kj is usually used. Such a relationship can be derived from simulations or during production testing and entered in a look-up table. However, the gain of a DCO in the PLL may show a variation over samples and operating conditions, and the BBPD gain may also vary due to varying input signal properties, such as a noisier reference clock or operating the DCO with a lower bias current to save power, using the calibration algorithm of the prior art to calibrate Kpand then using the predefined relationship between the proportional gain Kpand integral gain Kjto calibrate Kj may not be optimal.

[0010] SUMMARY

[0011] Therefor it is an object of embodiments herein to provide a PLL system with improved performance and an improved method for gain calibration of the PLL system.

[0012] According to a first aspect of embodiments herein, the object is achieved by a PLL system. The PLL system comprises a controlled oscillator (CO) configured to generate an output signal, and a digital phase detector (PD) configured to receive a reference signal and a feedback (FB) signal to generate an output signal representing a frequency or phase difference between the reference and feedback signals. The FB signal is based on the output signal from the CO.

[0013] The PLL system further comprises an accumulator configured to accumulate the output signal of the digital PD and generate an accumulated signal PDaccof the PD, a first gain module configured to apply an integral gain factor Kj to the accumulated signal PDacc, a second gain module configured to apply a proportional gain factor Kpto the output signal of the PD, a combiner configured to combine outputs of the first and second gain modules to generate a control signal Ctrl to the CO for controlling the frequency of the output signal.

[0014] The PLL system further comprises a first gain calibration module configured to process an accumulated signal of the PD to generate a periodicity measure for the accumulated signal of the PD, adjust the integral gain factor Kj based on the periodicity measure and provide the adjusted integral gain factor adj to the first gain module. According to a second of embodiments herein, the object is achieved by a method performed in a PLL system for generating an output signal.

[0015] The method comprises generating the output signal by a CO, generating a feedback (FB) signal based on the output signal from the CO, generating an output signal by a digital PD. The digital PD is configured to receive a reference signal and the FB signal, and the output signal of the digital PD represents a frequency or phase difference between the reference and feedback signals.

[0016] The method further comprises generating an accumulated signal PDaccof the output signal of the digital PD by an accumulator, applying an integral gain factor Kj to the accumulated signal of the PD by a first gain module, applying a proportional gain factor Kpto the output signal of the PD by a second gain module, and combining outputs of the first and second gain modules to generate a control signal Ctrl to the CO for controlling the frequency of the output signal.

[0017] The method further comprises processing by a first gain calibration module, the accumulated signal PDaccof the PD to generate a periodicity measure for the accumulated signal PDaccof the PD, generating by the first gain calibration module, an adjusted integral gain factor Kiadj based on the periodicity measure, providing by the first gain calibration module, the adjusted integral gain factor Kiadj to the first gain module, and applying by the first gain module, the adjusted integral gain factor adj to the accumulated signal PDaccof the PD.

[0018] According to a third aspect of embodiments herein, the object is achieved by a method for calibrating an integral gain of the digital PLL system described above.

[0019] The method comprises calculating an accumulated signal of the PD by an accumulator, applying an initial value of integral gain factor Ki by a first gain module to the accumulated signal of the PD, calculating an autocorrelation function of the accumulated signal of the PD by a first gain calibration module, processing the autocorrelation function by the first gain calibration module to generate a periodicity measure for the accumulated signal of the PD, comparing the periodicity measure with a predefined threshold by the first gain calibration module, adjusting the integral gain factor based on the comparing result by the first gain calibration module, providing the adjusted integral gain factor Kiadj to the first gain module by the first gain calibration module, and applying the adjusted integral gain factor Kiadj by the first gain module to the accumulated signal of the PD.

[0020] The digital PLL system according to some embodiments herein has a means to observe the PD output signal sequence. The accumulated signal of the PD output signal sequence is generated and may be processed for detecting peaking in phase noise and the closed loop transfer function by forming an autocorrelation function versus relative sample delay for the accumulated signal of the PD. The integral gain Kj may be calibrated and adjusted by sweeping Kj from low to high value and the target Kj may be the one that is on the limit of generating peaking in phase noise and the closed loop transfer function.

[0021] The PLL system and methods according to embodiment herein have some advantages. Compared to prior art solutions, a predefined relationship between Kj and Kpdoes not need to be defined. Furthermore, the CO gain may show a variation over samples and operating conditions. Using the proposed PLL system and method for calibrating the integral gain, it is possible to optimize the performance of the PLL system blindly and regardless of operating conditions. By optimizing and calibrating Kj, phase noise originating from the CO is reduced. Moreover, it may reduce production test time while making sure that the PLL system operates with a minimum amount of jitter generated for each bias current setting.

[0022] The method for calibrating the integral gain of the digital PLL system may run continuously in the background to keep the PLL system calibrated while operating conditions change. It may also be used for various types of digital PLLs although the clearest benefits are present for BB DPLLs where phase detector gain varies to a larger extent than when using linear phase detectors.

[0023] Therefore, the embodiments herein provide an improved method for gain calibration of the PLL system and an improved PLL system with regard to, e.g. loop stability, phase noise, production test time, changing operating conditions, etc.

[0024] BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Examples of embodiments herein are described in more detail with reference to attached drawings in which:

[0026] Figure 1 is a schematic block view of a Bang Bang digital PLL circuit according to prior art; Figure 2 is a schematic block view of a digital PLL system according to embodiments herein;

[0027] Figure 3 is a schematic block view of an integral gain calibration module according to embodiments herein;

[0028] Figure 4 (a) and (b) are diagrams illustrating examples of autocorrelation for BBPD output cumulative sum and the second derivative of the autocorrelation for a low Kj value; Figure 5 (a) and (b) are diagrams illustrating examples of autocorrelation for BBPD output cumulative sum and the second derivative of the autocorrelation for a high Kj value;

[0029] Figure 6 is a diagram illustrating the maximum value of the second derivative of the BBPD output cumulative sum versus ;

[0030] Figure 7 is a diagram illustrating an example periodicity measure according to embodiments herein;

[0031] Figure 8 is a diagram illustrating examples of autocorrelation for BBPD output cumulative sum for Kj from low value to high value;

[0032] Figure 9 is a diagram illustrating the second derivative of the autocorrelation for Kj from low value to high value;

[0033] Figure 10 (a) and (b) are flow charts illustrating a method performed by the PLL system for generating an output signal according to embodiments herein;

[0034] Figure 11 (a) and (b) are flow charts illustrating a method performed by the PLL system for calibrating the integral gain of the PLL system according to embodiments herein; and

[0035] Figure 12 is a block diagram illustrating an electronic device in which a PLL system according to embodiments herein may be implemented.

[0036] DETAILED DESCRIPTION

[0037] As part of developing embodiments herein, problems and limitations related to the prior art solutions will be first identified and discussed.

[0038] Figure 1 shows a main structure of a Bang Bang DPLL 100 according to prior art. The DPLL 100 comprises a proportional gain calibration unit 110 for Kpcalibration which observes the BBPD 120 output and uses an algorithm for Kpcalibration. The integral gain Kj is not calibrated.

[0039] The integrator part of the loop filter in the PLL makes sure that the DCO output accurately tracks the reference signal phase, so it may be utilized for suppression of the DCO 1 / f-noise. The amount of suppression is dependent of the integral gain Kj that could be allowed. A too high integral gain will introduce peaking in the closed loop transfer function and ultimately cause the loop to become unstable. On the other hand, if the integral gain is too low, the suppression of DCO noise will be limited. Therefor it is important to be able to adjust the integral gain Kj to a level that assures optimal performance. Currently known algorithms for gain calibration do not take the integral gain into special consideration. Some embodiments herein provide a digital PLL having a means to observe the PD output signal sequence. The accumulated signal of the PD output signal sequence is checked for correlation peaks by forming an autocorrelation function versus relative sample delay for the accumulated signal of the PD. The integral gain Kj is calibrated and adjusted by sweeping Kj from low to high value and the target Kj is the one that is on the limit of generating peaking in phase noise and the closed loop transfer function. Detecting the peaking may include filtering the autocorrelation function, differentiating, further filtering etc.

[0040] Figure 2 is a schematic block diagram showing a digital PLL system 200 according to embodiments herein. The digital PLL system 200 comprises a controlled oscillator CO 210 configured to generate an output signal CKV.

[0041] The digital PLL system 200 further comprises a digital phase detector PD 220 configured to receive a reference signal CKR and a feedback signal FB to generate an output signal PDOut representing a frequency or phase difference between the reference and feedback signals. The feedback signal FB is based on the output signal CKV from the CO 210. The feedback signal FB may be generated by dividing the output signal CKV from the CO 210 by a divider DIV 270 as shown in Figure 2.

[0042] The digital PLL system 200 further comprises an accumulator 230 configured to accumulate the output signal of the digital PD 220 and generate an accumulated signal PDacc of the PD 220.

[0043] The digital PLL system 200 further comprises a first gain module 240 configured to apply an integral gain factor Kj to the accumulated signal PDacc.

[0044] The digital PLL system 200 further comprises a second gain module 250 configured to apply a proportional gain factor Kpto the output signal of the PD 220.

[0045] The digital PLL system 200 further comprises a combiner 260 configured to combine outputs of the first and second gain modules 240, 250 to generate a control signal Ctrl to the CO 210 for controlling the frequency of the output signal CKV.

[0046] The digital PLL system 200 further comprises a first gain calibration module KjCalM 270 configured to process an accumulated signal of the PD 220 to generate a periodicity measure for the accumulated signal of the PD 220, adjust the integral gain factor Kj based on the periodicity measure and provide the adjusted integral gain factor Kjadj to the first gain module 240.

[0047] Although it is shown in Figure 2 that the first gain calibration module 270 receives and processes the accumulated signal PDaccfrom the accumulator 230, the first gain calibration module 270 may receive and process an output signal from a further accumulator (not shown) configured to accumulate the output signal of the PD 220. This further accumulator may be a separate accumulator outside the loop of the PLL system 200.

[0048] Figure 3 is a schematic block diagram showing the first gain calibration module KjCalM 270 according to embodiments herein.

[0049] The first gain calibration module 270 comprises a correlator module 271 configured to calculate an autocorrelation function of the accumulated signal PDaccof the PD 220.

[0050] The first gain calibration module 270 further comprises a memory module 272 configured to store the autocorrelation function.

[0051] The first gain calibration module 270 further comprises a processing module 273 configured to process the autocorrelation function to generate the periodicity measure for the accumulated PDaccsignal of the PD 220.

[0052] The first gain calibration module 270 further comprises a comparing module 274 configured to compare the periodicity measure with a predefined threshold Th.

[0053] The first gain calibration module 270 further comprises a register module 275 configured to store integral gain factor Kj and adjust the integral gain factor Kj stored in the register module 275 based on the comparing result and provide the adjusted integral gain factor Kiadj to the first gain module 240.

[0054] In the following, details of the algorithm and processing modules in the processing module 273 to generate different alternatives of the periodicity measures will be described.

[0055] It has been discussed in the beginning of the detailed description that a too high integral gain Kj will introduce peaking in the closed loop transfer function. Similarly, a too high integral gain will also introduce peaking in the phase noise. The peaking in the phase noise makes the PLL not fulfil the phase noise specification. On the other hand, if the integral gain is too low, the suppression of DCO noise will be limited. Therefore, there is a clear benefit with finding an optimal setting for the integral gain factor Kj. The principle for optimizing and calibrating the integral gain factor Kj is to identify the relatively higher energy around the peaking frequency through observation of the PD 220 output signal sequence. It is found that the cumulative sum of the PD 220 output signal sequence contains the information about the frequency contents at the PD 220 output. The cumulative sum is equivalent to the accumulated PD output. That means a signal already present in the loop filter of the PLL system can be used. During calibration, the integral gain Kj is swept from low to high value, and the target Kj is the one that is on the limit of generating peaking in the phase noise and closed loop transfer function. Since the signals observed are disturbed by noise, it is necessary to perform statistical analysis to find potential patterns or frequency contents in the accumulated PD output signal sequence. Autocorrelation is a powerful measure to find potential patterns or frequency contents of a signal sequence. The autocorrelation is the correlation of a signal with a delayed copy of itself as a function of the sample delay. To calculate the autocorrelation for different values of the sample delay or lag k, which may be defined as:

[0056] Where

[0057] Where, s0is the non-normalized autocorrelation when the sample delay is 0, , skis the non-normalized autocorrelation when the sample delay is k, y is the mean value of all samples and n is the number of samples of the signal sequence.

[0058] Some examples of the autocorrelation of the accumulated signal PDaccof the PD 220 are shown in Figures 4 and 5 for different measurements. In Figure 4, a relatively low Kj is used. The autocorrelation function versus sample delay, see Figure 4 (a), starts from a value close to 1 , and the larger the sample delay, the smaller the correlation between samples. This is a case when there is small periodicity in the signal observed, see Figure 4 (b) which shows the second derivative of the autocorrelation function. The rate at which the autocorrelation decays is different because of slower variations, mainly caused by low frequency phase noise of the reference clock that the PLL strives to track.

[0059] Increasing Kj, the phase margin will decrease, and frequency content will show up in the autocorrelation function as larger variations in the second derivative of the autocorrelation function, see Figure 5 (a) and (b). Another observation is that the initial values of the second derivative of the autocorrelation function for relative low sample delay, e.g. lower than 100, are always positive for the case of a higher Kj. Therefore, the larger and positive values in this range may be used to indicate that the Kj may be too high which leads to less phase margin.

[0060] The process of optimizing the Kj may be performed in several ways. A straightforward approach is to let the Kj increase from a value well below the point where the PLL system starts peaking and then detect where there is an indication of PLL peaking in the autocorrelation function. Measurement trials show that there is no very clear “knee” in any parameter of the autocorrelation function where the peaking takes off, but it is possible to fit an exponential function to the maximum of the second derivative of the autocorrelation function versus Kj. Examples of measurements and fitted curves are shown in Figure 6.

[0061] Having fitted an exponential function to the maximum of the second derivative of the autocorrelation function, the task remaining is to decide which periodicity measure and threshold to use for the optimal setting of the Kj. The threshold can be predefined from circuit measurements.

[0062] Therefore, according to some embodiments herein, for finding repeating patterns or frequency content in the accumulated PD 220 output signal sequence, the correlator module 271 calculates an autocorrelation function of the accumulated signal PDaccof the PD 220.

[0063] Turning back to Figure 3, to generate a periodicity measure from the autocorrelation function of the accumulated signal PDaccof the PD 220, the processing module 273 may comprise a first finite impulse response filter (FIR) module 31 configured to filter the autocorrelation function.

[0064] The processing module 273 may further comprise a first differentiation module 32 configured to calculate a first derivative of the filtered autocorrelation function to generate a first resulting sequence.

[0065] The processing module 273 may further comprise a periodicity measure generating module PMG 35 configured to generate the periodicity measure by calculating a difference between the first derivative value of the filtered autocorrelation function at a predefined low sample delay and the average decay rate of the whole autocorrelation function.

[0066] Figure 7 shows the autocorrelation functions plotted versus sample delays, for different values of Kj. The first derivatives of the filtered autocorrelation versus sample delay are formed at the beginning of the autocorrelation functions, in this example at sample delay 10, indicated by the shorter straight lines 701, 702, in the figure. Then the average decay rate of the autocorrelation functions between sample delay 0 and 500 are calculated, indicated by straight lines 703. The first derivative is compared to the average decay rate of the autocorrelation function, for each Kj curve. The periodicity measure is formed by the difference between the first derivative and the average decay rate. A significant difference indicates peaking and that Kj should be reduced

[0067] The periodicity measure generated by this embodiment has a reduced computational complexity in that the autocorrelation function for only a few initial lower sample delays and the maximum sample delay needs to be calculated.

[0068] One alternative method of finding the optimal Kj involves checking the second derivative of the autocorrelation function for low sample delays. A measurement trial proves the feasibility of the method, and the result is shown in Figures 8 and 9. The Kj is swept from a low value of 10 until a high value of 101, Figure 8 shows the autocorrelation function, Figure 9 shows the second derivative of the autocorrelation function. As can be seen the measurement is somewhat noisy, meaning that several iterations and averaging may need to be used.

[0069] Therefore, according to some embodiments herein, alternative periodicity measures may be generated by further filtering and differentiating the first derivative of the first filtered autocorrelation function, by a second finite impulse response filter module 33 and a second differentiation module34, as shown in Figure 3 with the dotted boxes which mean they are optional. That is, the processing module 273 may further comprise a second finite impulse response filter module 33 configured to filter the first derivative of the filtered autocorrelation function and a second differentiation module 34 configured to calculate a derivative of the filtered, first derivative of the filtered autocorrelation function to generate a second resulting sequence.

[0070] The periodicity measure generating module PMG 35 in this embodiment is configured to generate the periodicity measure by finding the maximum variation over the second resulting sequence or by finding the value for a predefined low sample delay in the second resulting sequence.

[0071] For example, Figure 9 shows the second derivative of the autocorrelation function, i.e. the second resulting sequence. As it can be seen, for Kj=70, the second derivative value for a low sample delay, e.g. 10 samples, is around 2.3x1 O'5, the generated periodicity measure may be 2.3x1 O'5in this case for Kj=70. For different Ki, the different periodicity measures can be generated. It can also be seen that the second derivative value for low sample delay, e.g. 10 samples, is much larger when Kj is large, e.g. when Kj=101 , the generated periodicity measure may be 3.7x1 O'5.

[0072] After the periodicity measure is generated, the first gain calibration module 270 is configured to generate an adjusted integral gain factor adj based on the periodicity measure by comparing the periodicity measure with a predefined threshold Th and adjust the integral gain factor Kj based on the comparing result. The predefined threshold Th may be a threshold range between a lower threshold value and an upper threshold value. For example, if the periodicity measure is lower than the lower threshold value, the integral gain factor Kj is increased, if the periodicity measure is higher than the upper threshold value, the integral gain factor Kj is decreased.

[0073] According to embodiments herein, a method performed in the digital PLL system 200 for generating an output signal will be described with reference to Figure 10 (a), (b). The method comprises the following actions which may be performed in any suitable order or simultaneously.

[0074] Action 1010

[0075] Generating the output signal CKV by the CO 210.

[0076] Action 1020

[0077] Generating a feedback signal FB based on the output signal CKV from the CO 210.

[0078] Action 1030

[0079] Generating an output signal PDout by a digital phase detector PD 220. The digital PD 220 is configured to receive a reference signal CKR and the feedback signal FB, and the output signal of the PD 220 represents a frequency or phase difference between the reference and feedback signals.

[0080] Action 1040

[0081] Generating an accumulated signal PDaccof the output signal of the digital PD 220 by an accumulator 230.

[0082] Action 1050

[0083] Applying an integral gain factor Kj to the accumulated signal of the PD 220 by a first gain module 240.

[0084] Action 1060

[0085] Applying a proportional gain factor Kpto the output signal of the PD 220 by a second gain module 250.

[0086] Action 1070

[0087] Combining outputs of the first and second gain modules to generate a control signal Ctrl to the CO 210 for controlling the frequency of the output signal CKV.

[0088] Action 1080

[0089] Processing by a first gain calibration module 270, the accumulated signal PDaccof the PD 220 to generate a periodicity measure for the accumulated signal PDaccof the PD 220.

[0090] Processing the accumulated signal of the PD 220 may comprise the following actions, see Figure 10 (b):

[0091] Action 1081

[0092] Calculating an autocorrelation function of the accumulated signal of the PD 220.

[0093] Action 1082

[0094] Processing the autocorrelation function to generate the periodicity measure.

[0095] To generate the periodicity measure, the autocorrelation function may be filtered, and a first resulting sequence may be generated by calculating a first derivative of the filtered autocorrelation function. Alternatively, the first derivative of the filtered autocorrelation function may be filtered once again and a second resulting sequence may be generated by calculating a derivative of the filtered, first derivative of the autocorrelation function. Therefore, the Action 1082 of processing the autocorrelation function to generate the periodicity measure may comprise the following actions:

[0096] Action 10821

[0097] Filtering the autocorrelation function by a first finite impulse response filter.

[0098] Action 10822

[0099] Calculating a first derivative of the filtered autocorrelation function to generate a first resulting sequence.

[0100] Action 10823

[0101] Filtering the first derivative of the filtered autocorrelation function by a second finite impulse response filter.

[0102] Action 10824

[0103] Calculating a derivative of the filtered, first derivative of the filtered autocorrelation function to generate a second resulting sequence.

[0104] Action 10825

[0105] Generating the periodicity measure based on the first resulting sequence by calculating a difference between the first derivative value of the filtered autocorrelation function at a predefined sample delay and the average decay rate of the whole autocorrelation function.

[0106] Action 10826

[0107] Generating the periodicity measure based on the second resulting sequence by finding the maximum variation over the second resulting sequence or by finding the value for a predefined sample delay in the second resulting sequence.

[0108] Action 1090

[0109] Generating by the first gain calibration module 270, an adjusted integral gain factor adj based on the periodicity measure.

[0110] Generating an adjusted integral gain factor adj based on the periodicity measure may comprise the following Actions, see Figure 10 (b):

[0111] Action 1091

[0112] Comparing the periodicity measure with a predefined threshold Th.

[0113] Action 1092

[0114] Adjusting the integral gain factor Kj based on the comparing result.

[0115] Action 10100

[0116] Providing by the first gain calibration module 270, the adjusted integral gain factor adj to the first gain module 240.

[0117] Action 10110 Applying by the first gain module 240, the adjusted integral gain factor Kiadj to the accumulated signal PDaccof the PD 220.

[0118] According to one embodiment herein, a method performed in the digital PLL system 200 shown in Figure 2 for calibrating an integral gain of the PLL system 200 will be described with reference to Figure 11 (a), (b). The method comprises the following actions which may be performed in any suitable order or simultaneously.

[0119] Action 1110

[0120] Calculating an accumulated signal PDacc of the output signal of the PD 220 by an accumulator 230.

[0121] Action 1120

[0122] Applying an initial value of integral gain factor Kj by the first gain module 240 to the accumulated signal PDacc of the PD 220.

[0123] Action 1130

[0124] Calculating an autocorrelation function of the accumulated signal of the PD 220 by the first gain calibration module 270.

[0125] Action 1140

[0126] Processing the autocorrelation function by the first gain calibration module 270 to generate a periodicity measure for the accumulated signal of the PD 220.

[0127] To generate the periodicity measure, the autocorrelation function may be filtered, and a first resulting sequence may be generated by calculating a first derivative of the filtered autocorrelation function. Alternatively, the first derivative of the filtered autocorrelation function may be filtered once again and a second resulting sequence may be generated by calculating a derivative of the filtered, first derivative of the autocorrelation function. Therefore, the Action 1140 of processing the autocorrelation function to generate the periodicity measure may comprise the following actions, see Figure 11 (b):

[0128] Action 1141

[0129] Filtering the autocorrelation function by a first finite impulse response filter.

[0130] Action 1142

[0131] Calculating a first derivative of the filtered autocorrelation function to generate a first resulting sequence.

[0132] Action 1143

[0133] Filtering the first derivative of the filtered autocorrelation function by a second finite impulse response filter.

[0134] Action 1144 Calculating a derivative of the filtered, first derivative of the filtered autocorrelation function to generate a second resulting sequence.

[0135] Action 1145

[0136] Generating the periodicity measure based on the first resulting sequence by calculating a difference between the first derivative value of the filtered autocorrelation function at a predefined sample delay and the average decay rate of the whole autocorrelation function.

[0137] Action 1146

[0138] Generating the periodicity measure based on the second resulting sequence by finding the maximum variation over the second resulting sequence or by finding the value for a predefined sample delay in the second resulting sequence.

[0139] Action 1150

[0140] Comparing the periodicity measure with a predefined threshold Th.

[0141] Action 1160

[0142] Adjusting the integral gain factor Kj based on the comparing result. The predefined threshold Th may be a threshold range within a lower threshold value and an upper threshold value. For example, if the periodicity measure is lower than the lower threshold value, the integral gain factor Kj is increased, if the periodicity measure is higher than the upper threshold value, the integral gain factor Kj is decreased.

[0143] Action 1170

[0144] Providing the adjusted integral gain factor Kiadj to the first gain module 240.

[0145] Action 1180

[0146] Applying the adjusted integral gain factor Kiadj by the first gain module 240 to the accumulated signal of the PD 220.

[0147] Actions 1130-1180 aim to search indications of PLL peaking in the PD 220 output signal sequence. If the level of the PLL peaking indication, i.e. the periodicity measure, is below a specified threshold, increase Ki. Repeating Actions 1130-1180 until the specified threshold is reached and a desired level of Ki is achieved. The method for calibrating the integral gain Ki of the digital PLL system 200 may run continuously in the background to keep the PLL system 200 calibrated while operating conditions change.

[0148] To summarize, a digital PLL system 200 and methods therein for generating an output signal and calibrating the integral gain of the digital PLL system 200 are provided. The digital PLL system 200 has a means to observe the PD output signal. The accumulated signal of the PD is processed to identify periodicity in the accumulated signal of the PD and generate periodicity measures. The periodicity measures are compared with predefined thresholds. One example of the predefined thresholds may be a threshold range between a lower threshold value and an upper threshold value. If the periodicity measure is lower than the lower threshold value, the integral gain factor Kj is increased, if the periodicity measure is higher than the upper threshold value, the integral gain factor Kj is decreased. The integral gain Kj can be calibrated by sweeping Kj from low to high value and the target Kj is the one that is on the limit of generating peaking in phase noise and the closed loop transfer function.

[0149] The PLL system 200 and methods according to embodiment herein have some advantages. Compared to prior art solutions, a predefined relationship between Kj and Kpdoes not need to be defined. With varying PD gain due to varying input signal properties, such as a noisier reference clock signal or the CO operating with a lower bias current to save power, the predefined values of Kj and Kpmay not be optimal.

[0150] Furthermore, the CO gain may show a variation over samples and operating conditions. Using the proposed PLL system 200 and method for calibrating the integral gain, it is possible to optimize the performance of the PLL system blindly and regardless of operating conditions. By optimizing and calibrating Kj, phase noise originating from the CO is reduced. Moreover, it may reduce production test time while making sure that the PLL system 200 operates with a minimum amount of jitter generated for each bias current setting.

[0151] The method for calibrating the integral gain of the digital PLL system 200 may run continuously in the background to keep the PLL system 200 calibrated while operating conditions change. It may also be used for various types of digital PLLs although it benefits most for BB DPLLs as shown in Figure 1 , where PD gain varies to a larger extent than when using linear phase detectors.

[0152] The digital PLL system 200 may be employed in various integrated circuits, electronic circuits, communication devices or apparatus. Figure 12 shows a block diagram for an electronic device 1200 in which the PLL system 200 according to embodiments herein may be implemented. The electronic device 1200 may comprise a receiver or a transmitter or both i.e. a transceiver TX / RX 1210 in which the PLL system 200 according to embodiments herein may be implemented. The electronic device 1200 may comprise other units, where a memory 1220, a processing unit 1230 are shown. The electronic device 1200 may be any one of a base station, a wireless communication device such as a user equipment or a mobile device for a cellular communication system.

[0153] The embodiments herein for calibrating the integral gain of the digital PLL system 200 may be implemented through one or more processors, such as the processing unit 1230 in the electronic device 1200, together with computer program code for performing the functions and actions of the embodiments herein. The program code mentioned above may also be provided as a computer program product 1240, for instance in the form of a data carrier carrying computer program code 1250 for performing the embodiments herein when being loaded into the electronic device 1200. One such carrier may be in the form of a CD ROM disc. It is however feasible with other data carriers such as a memory stick. The computer program code may furthermore be provided as pure program code on a server or cloud and downloaded to the electronic device 1200.

[0154] Therefore, according to some embodiments herein, it is provided a computer program product 1240 comprising program code 1250 which when the program is executed by a computer / processor in the the electronic device 1200, cause the computer / processor to carry out the method for calibrating the integral gain of the digital PLL system 200 according to embodiments herein.

[0155] The embodiments herein are not limited to the above described preferred embodiments. Various alternatives, modifications and equivalents may be used. Those skilled in the art will understand that the digital PLL system 200 according to embodiments herein may be implemented in any semiconductor technology, e.g., Complementary Metal Oxide Semiconductor (CMOS), Silicon on Insulator (SOI) CMOS, field-effect transistor (FET), MOSFET technology etc.

[0156] Those skilled in the art will also appreciate that the PD 220, the accumulator 230, the first and second gain module 240, 250, the combiner 260 and the first gain calibration module 270 in the digital PLL system 200 may be referred to as one circuit or one module, or one or more processors configured with software and / or firmware and / or any other digital hardware performing the function of each module. The correlator module 271 , the memory module 272, the processing module 273, the comparing module 274, the register module 275 comprised in the first gain calibration module 270 may also be referred to as one circuit or one module, or one or more processors configured with software and / or firmware and / or any other digital hardware performing the function of each module. The first and second finite impulse response filter modules 31 , 33, the first and second differentiation modules 32, 34 and the periodicity measure generating module 35 comprised in the processing module 273 may also be referred to as one circuit or one module, or one or more processors configured with software and / or firmware and / or any other digital hardware performing the function of each module. One or more of these processors, the combination of analog and digital circuits as well as the other digital hardware, may be included in a single application-specific integrated circuitry (ASIC), or several processors and various analog / digital hardware may be distributed among several separate components, whether individually packaged or assembled into a system-on-a-chip (SoC).

[0157] The word "comprise" or “comprising”, when used herein, shall be interpreted as non- limiting, i.e. meaning "consist at least of".

[0158] The embodiments herein are not limited to the above described preferred embodiments. Various alternatives, modifications and equivalents may be used. Therefore, the above embodiments should not be taken as limiting the scope of the invention, which is defined by the appended claims.

Claims

CLAIMS1. A digital Phase Locked Loop, PLL, system (200) comprising: a controlled oscillator, CO (210), configured to generate an output signal (CKV); a digital phase detector, PD (220), configured to receive a reference signal (CKR) and a feedback signal (FB) to generate an output signal representing a frequency or phase difference between the reference and feedback signals, wherein the feedback signal (FB) is based on the output signal (CKV) from the CO (210); an accumulator (230) configured to accumulate the output signal of the digital PD (220) and generate an accumulated signal (PDacc) of the PD (220); a first gain module (240) configured to apply an integral gain factor (Kj) to the accumulated signal (PDacc) of the PD (220); a second gain module (250) configured to apply a proportional gain factor (Kp) to the output signal of the PD (220); a combiner (260) configured to combine outputs of the first and second gain modules (240, 250) to generate a control signal (Ctrl) to the CO (210) for controlling a frequency of the output signal (CKV); characterized in that the PLL system (200) further comprises: a first gain calibration module (270) configured to process an accumulated signal of the PD (220) to generate a periodicity measure for the accumulated signal of the PD (220), adjust the integral gain factor (Kj) based on the periodicity measure and provide the adjusted integral gain factor ( adj) to the first gain module (240).

2. The PLL system (200) according to claim 1 , wherein the first gain calibration module (270) comprises: a correlator module (271) configured to calculate an autocorrelation function of the accumulated signal (PDacc) of the PD (220); a memory module (272) configured to store the autocorrelation function; a processing module (273) configured to process the autocorrelation function to generate the periodicity measure for the accumulated (PDacc) signal of the PD (220); a comparing module (274) configured to compare the periodicity measure with a predefined threshold (Th); a register module (275) configured to store integral gain factor (Kj) and adjust the integral gain factor (Kj) stored in the register module (275) based on thecomparing result and provide the adjusted integral gain factor ( adj) to the first gain module (240).

3. The PLL system (200) according to claim 2, wherein the processing module (272) comprises: a first finite impulse response filter module (31) configured to filter the autocorrelation function; a first differentiation module (32) configured to calculate a first derivative of the filtered autocorrelation function to generate a first resulting sequence; a periodicity measure generating module (35) configured to generate the periodicity measure by calculating a difference between the first derivative value of the filtered autocorrelation function at a predefined low sample delay and the average decay rate of the whole autocorrelation function.

4. The PLL system (200) according to claim 2, wherein the processing module (273) comprises: a first finite impulse response filter module (31) configured to filter the autocorrelation function; a first differentiation module (32) configured to calculate a first derivative of the filtered autocorrelation function; a second finite impulse response filter module (33) configured to filter the first derivative of the filtered autocorrelation function; a second differentiation module (34) configured to calculate a derivative of the filtered, first derivative of the filtered autocorrelation function to generate a second resulting sequence; a periodicity measure generating module (35) configured to generate the periodicity measure by finding the maximum variation over the second resulting sequence or by finding a value for a predefined low sample delay in the second resulting sequence.

5. A method performed in a digital PLL system (200) for calibrating an integral gain of the digital PLL system (200) according to any one of the claims 1-4, the method comprising: calculating (1110) an accumulated signal of the output signal of the PD (220) by an accumulator (230);applying (1120) an initial value of integral gain factor (Kj) by a first gain module (240) to the accumulated signal of the PD (220); calculating (1130) an autocorrelation function of the accumulated signal of the PD (220) by a first gain calibration module (270); processing (1140) the autocorrelation function by the first gain calibration module (270) to generate a periodicity measure for the accumulated signal of the PD (220); comparing (1150) the periodicity measure with a predefined threshold (Th), by the first gain calibration module; adjusting (1160) the integral gain factor (Kj) based on the comparing result, by the first gain calibration module; providing (1170) the adjusted integral gain factor ( adj) to the first gain module (240) by the first gain calibration module; and applying (1180) the adjusted integral gain factor ( adj) by the first gain module (240) to the accumulated signal of the PD (220).

6. The method according to claim 5, wherein processing (1140) the autocorrelation function by the first gain calibration module (270) comprises: filtering (1141) the autocorrelation function by a first finite impulse response filter; calculating (1142) a first derivative of the filtered autocorrelation function to generate a first resulting sequency; and generating (1145) a periodicity measure by calculating a difference between the first derivative value of the filtered autocorrelation function at a predefined low sample delay and the average decay rate of the whole autocorrelation function.

7. The method according to claim 5, wherein processing (440) the autocorrelation function by the first gain calibration module (270) comprises: filtering (1141) the autocorrelation function by a first finite impulse response filter; calculating (1142) a first derivative of the filtered autocorrelation function; filtering (1143) the first derivative of the filtered autocorrelation function by a second finite impulse response filter; calculating (1144) a derivative of the filtered, first derivative of the filtered autocorrelation function to generate a second resulting sequence;generating (1146) the periodicity measure by finding the maximum variation over the second resulting sequence or by finding a value for a predefined small sample delay in the second resulting sequence.

8. A method performed in a digital Phase Locked Loop, PLL, system (200) for generating an output signal (CKV), the method comprising: generating (1010) the output signal (CKV) by a controlled oscillator, CO (210); generating (1020) a feedback signal (FB) based on the output signal (CKV) from the CO (210); generating (1030) an output signal (PDout) by a digital phase detector, PD (220), wherein the digital PD (220) is configured to receive a reference signal (CKR) and the feedback signal (FB), and the output signal of the PD (220) represents a frequency or phase difference between the reference and feedback signals; generating (1040) an accumulated signal (PDacc) of the output signal of the digital PD (220) by an accumulator (230); applying (1050) an integral gain factor (Kj) to the accumulated signal of the PD (220) by a first gain module (240); applying (1060) a proportional gain factor (Kp) to the output signal of the PD (220) by a second gain module (250); combining (1070) outputs of the first and second gain modules to generate a control signal (Ctrl) to the CO (210) for controlling a frequency of the output signal (CKV); characterized by processing (1080) by a first gain calibration module (270), the accumulated signal (PDacc) of the PD (220) to generate a periodicity measure for the accumulated signal (PDacc) of the PD (220); generating (1090) by the first gain calibration module (270), an adjusted integral gain factor (Kadj) based on the periodicity measure; providing (10100) by the first gain calibration module (270), the adjusted integral gain factor ( adj) to the first gain module (240); and applying (10110) by the first gain module (240), the adjusted integral gain factor ( adj) to the accumulated signal (PDacc) of the PD (220).

9. The method according to claim 8, wherein processing (1080) by a first gain calibration module (270), the accumulated signal of the PD (220) comprising:calculating (1081) an autocorrelation function of the accumulated signal of the PD (220); processing (1082) the autocorrelation function to generate the periodicity measure.

10. The method according to claim 9, wherein processing (1082) the autocorrelation function to generate the periodicity measure comprises: filtering (10821) the autocorrelation function by a first finite impulse response filter; calculating (10822) a first derivative of the filtered autocorrelation function to generate a first resulting sequence; and generating (10825) the periodicity measure by calculating a difference between the first derivative value of the filtered autocorrelation function at a predefined low sample delay and the average decay rate of the whole autocorrelation function.

11. The method according to claim 9, wherein processing (1082) the autocorrelation function to generate the periodicity measure comprises: filtering (10821) the autocorrelation function by a first finite impulse response filter; calculating (10822) a first derivative of the filtered autocorrelation function; filtering (10823) the first derivative of the filtered autocorrelation function by a second finite impulse response filter; calculating (10824) a derivative of the filtered, first derivative of the filtered autocorrelation function to generate a second resulting sequence; generating (10826) the periodicity measure by finding the maximum variation over the second resulting sequence or by finding a value for a predefined sample delay in the second resulting sequence.

12. The method according to any one of claims 8-11 , wherein generating (1090) an adjusted integral gain factor ( adj) based on the periodicity measure comprises: comparing (1091) the periodicity measure with a predefined threshold (Th); adjusting (1092) the integral gain factor (Kj) based on the comparing result.

13. A transceiver (1210) comprising a digital PLL system (200) according to any one of claims 1-4.

14. An electronic apparatus (1200) comprising a digital PLL system (200) according to any one of claims 1-4.

15. The electronic apparatus (1200) according to claim 14, wherein the electronic apparatus is any one of a wireless communication device and a base station for a cellular communications system.

16. A computer program product (1240) comprising program code (1250) which when the program is executed by a computer / processor, causes the computer / processor to carry out the method according to any one of the claims 5-7.

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