PLL loop bandwidth adjusting circuit, control method and circuit board
By introducing a frequency and phase detector, a charge-sharing filter, and an adjustable voltage-controlled oscillator into the PLL loop, and adjusting the proportional path gain of the phase-locked loop, the noise-power consumption constraint problem of traditional PLL loop bandwidth control is solved, achieving highly flexible and low-power bandwidth adjustment, and reducing hardware complexity and circuit board area.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-21
- Publication Date
- 2026-05-05
AI Technical Summary
Traditional PLL loop bandwidth control is constrained by noise and power consumption. Increasing the bandwidth will reduce noise suppression capability and increase clock jitter, which contradicts the current approach to low-power design.
A frequency and phase detector, a charge-sharing filter, a phase-locked loop (PLL) proportional path module, and an adjustable voltage-controlled oscillator (VCO) are used. By changing the output frequency of the VCO, the gain of the PLL proportional path module is adjusted to achieve PLL loop bandwidth modulation. Combined with the charge-sharing filter, low-pass filtering and integral path functions are realized.
It achieves highly flexible and low-power PLL loop bandwidth adjustment, reducing hardware design complexity and circuit board area, and improving the flexibility and low power consumption of bandwidth adjustment.
Smart Images
Figure CN121984498A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the technical field of phase-locked loop sources, specifically to a PLL loop bandwidth adjustment circuit, control method, and circuit board. Background Technology
[0002] See Figure 1 , Figure 2 A PLL (Phase Locked Loop) is a circuit used to unify and integrate clock signals, ensuring the normal operation of high-frequency devices. The PLL loop bandwidth is equal to the integral of its closed-loop frequency response, reflecting the loop's noise suppression capability. A smaller noise bandwidth indicates a narrower loop and stronger noise suppression. Furthermore, the noise bandwidth is also related to the loop gain K, damping coefficient, and undamped oscillation frequency.
[0003] As can be seen from the above, traditional PLL loop bandwidth control is constrained by "noise-power consumption". Higher PLL loop bandwidth means lower lockout time. At the same time, increasing the PLL bandwidth will reduce the loop system's ability to suppress in-band noise, thereby introducing more clock jitter into the output clock signal.
[0004] Typically, in order to improve loop bandwidth without affecting noise performance, additional noise reduction measures are required, such as increasing the reference clock frequency, introducing auxiliary loops, and increasing the charge pump current. However, these methods are all contrary to low-power design, making it difficult to solve the "noise-power" constraint. Summary of the Invention
[0005] In view of this, it is necessary to provide a highly flexible and low-power PLL loop bandwidth adjustment circuit, control method, and circuit board to address the problem.
[0006] This invention provides a PLL loop bandwidth adjustment circuit, comprising: a frequency and phase detector, a charge-sharing filter, a phase-locked loop proportional path module, and an adjustable voltage-controlled oscillator;
[0007] The input terminal of the frequency and phase detector is connected to the reference signal;
[0008] The first output terminal of the frequency and phase detector is connected to the first input terminal of the adjustable voltage-controlled oscillator through a charge-sharing filter.
[0009] The second output terminal of the frequency and phase detector is connected to the second input terminal of the adjustable voltage-controlled oscillator through a phase-locked loop proportional path module.
[0010] Optionally, the charge-sharing filter includes: an integration path module and a low-pass filter module;
[0011] The first output terminal of the frequency and phase detector is connected to the first input terminal of the adjustable voltage-controlled oscillator through an integration path module and a low-pass filter module.
[0012] Optionally, the adjustable voltage-controlled oscillator is a variable VCO switched capacitor array.
[0013] Optionally, the variable VCO switched capacitor array includes a switching circuit module and a VCO circuit module, wherein the VCO circuit module is electrically disconnected or connected to the charge-sharing filter and the phase-locked loop proportional path module through the switching circuit module.
[0014] Optionally, the structure of the VCO circuit module includes: a first variable capacitor C1, a second variable capacitor C2, a first MOSFET Q1, a second MOSFET Q2, a third MOSFET Q3, a fourth MOSFET Q4, an inductor L1, and a variable capacitor array CV;
[0015] The first MOSFET Q1 and the second MOSFET Q2 form a first cross-coupled negative resistor, and the third MOSFET Q3 and the fourth MOSFET Q4 form a second cross-coupled negative resistor.
[0016] The first terminal of the first cross-coupled negative resistor is connected in parallel to the second terminal of the first cross-coupled negative resistor and then connected to the voltage terminal VDD.
[0017] The third terminal of the first cross-coupled negative resistor is connected to the first terminal of the inductor L1, the first terminal of the first variable capacitor C1, the first terminal of the variable capacitor array CV, and the first terminal of the second cross-coupled negative resistor, respectively.
[0018] The fourth terminal of the first cross-coupled negative resistor is connected to the second terminal of inductor L1, the first terminal of the second variable capacitor C2, the second terminal of the variable capacitor array CV, and the second terminal of the second cross-coupled negative resistor, respectively. The third terminal of the second cross-coupled negative resistor is connected in parallel to the fourth terminal of the first cross-coupled negative resistor and then grounded.
[0019] The second terminal of the first variable capacitor C1 is connected to the second terminal of the second variable capacitor C2;
[0020] The switching circuit module 401 is connected to the variable capacitor array CV.
[0021] Optionally, the feedback signal terminal of the adjustable voltage-controlled oscillator is connected to the feedback signal input terminal of the frequency and phase detector through a frequency divider.
[0022] This invention also provides a control method for a PLL loop bandwidth adjustment circuit, wherein the PLL loop bandwidth adjustment circuit adopts the PLL loop bandwidth adjustment circuit described above; the control method includes:
[0023] By changing the output frequency of the adjustable voltage-controlled oscillator, the proportional path gain value in the phase-locked loop proportional path module is adjusted, thereby modulating the PLL loop bandwidth.
[0024] The present invention also provides a circuit board for a PLL loop bandwidth adjustment circuit, comprising: the PLL loop bandwidth adjustment circuit as described above, and a substrate supporting the PLL loop bandwidth adjustment circuit.
[0025] The advantages of the technical solution provided in this application are:
[0026] 1. In this application, a charge-shared filter is used to achieve low-pass filtering and integration path functions, and the phase-locked loop proportional path module is directly connected to an adjustable voltage-controlled oscillator. In use, the bandwidth modulation of the PLL loop is achieved by changing the output frequency of the adjustable voltage-controlled oscillator and changing the gain coefficient of the phase-locked loop proportional path module. By dynamically adjusting the gain coefficient of the phase-locked loop proportional path, the modulation of the PLL loop bandwidth has the characteristics of flexibility and low power consumption.
[0027] 2. This application does not introduce additional hardware structures, which can reduce the complexity of hardware design and circuit board area. Attached Figure Description
[0028] To more clearly illustrate the technical solutions of the embodiments of the present invention or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0029] Figure 1 This is a schematic diagram of the structure of a PLL loop in the prior art;
[0030] Figure 2 This is a schematic diagram of the mathematical model of a PLL loop in the prior art;
[0031] Figure 3 This is a schematic diagram of the circuit structure of a PLL loop bandwidth adjustment circuit provided by the present invention;
[0032] Figure 4 This is a circuit diagram of the adjustable voltage-controlled oscillator provided by the present invention;
[0033] In the picture:
[0034] 10 is a frequency and phase detector, 20 is a charge-sharing filter, 30 is a phase-locked loop proportional path module, 40 is an adjustable voltage-controlled oscillator, and 50 is a frequency divider.
[0035] 201 is the integration path module, and 202 is the low-pass filter module;
[0036] 401 is the switch circuit module, and 402 is the VCO circuit module;
[0037] C1 is the first variable capacitor, and C2 is the second variable capacitor;
[0038] L1 is an inductor;
[0039] Q1 is the first MOSFET, Q2 is the second MOSFET, Q3 is the third MOSFET, and Q4 is the fourth MOSFET;
[0040] CV is a variable capacitor array;
[0041] VDD is the voltage terminal. Detailed Implementation
[0042] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.
[0043] In this invention, the use of terms such as "first," "second," etc., is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0044] Furthermore, the technical solutions of the various embodiments of the present invention can be combined with each other, but only if they are feasible to those skilled in the art. If the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.
[0045] The following section will further introduce the specific implementation method, as well as the technical difficulties and inventive points of this invention, using this design example as an example.
[0046] Example 1
[0047] See Figure 3 A PLL loop bandwidth adjustment circuit includes: a frequency and phase detector 10, a charge-sharing filter 20, a phase-locked loop proportional path module 30, and an adjustable voltage-controlled oscillator 40.
[0048] The input terminal of the frequency and phase detector 10 is connected to the reference signal;
[0049] The first output terminal of the frequency and phase detector 10 is connected to the first input terminal of the adjustable voltage-controlled oscillator 40 through the charge-sharing filter 20.
[0050] The second output terminal of the frequency and phase detector 10 is connected to the second input terminal of the adjustable voltage-controlled oscillator 40 through the phase-locked loop proportional path module 30.
[0051] It should be noted that the PLL loop bandwidth adjustment circuit proposed in this embodiment achieves low-pass filtering and integration path functions through a charge-sharing filter, and directly connects the phase-locked loop proportional path module to an adjustable voltage-controlled oscillator. In use, by changing the output frequency of the adjustable voltage-controlled oscillator, the gain coefficient of the phase-locked loop proportional path module is changed, thereby realizing the bandwidth modulation of the PLL loop. In this embodiment, no additional hardware structure is introduced, which can reduce the complexity of hardware design. At the same time, by dynamically adjusting the gain coefficient of the phase-locked loop proportional path, the modulation of the PLL loop bandwidth has the characteristics of flexibility and low power consumption.
[0052] In this embodiment, the charge-sharing filter 20 includes an integration path module 201 and a low-pass filter module 202; the first output terminal of the frequency and phase detector 10 is connected to the first input terminal of the adjustable voltage-controlled oscillator 40 through the integration path module 201 and the low-pass filter module 202.
[0053] It should be noted that in this embodiment, the loop filter in the traditional PLL loop structure is replaced by a charge-sharing filter and a phase-locked loop proportional path module. This allows for parameter settings of the charge-sharing filter and the phase-locked loop proportional path module separately during the adjustment of the PLL loop bandwidth, thus improving the flexibility of bandwidth adjustment.
[0054] In this embodiment, the adjustable voltage-controlled oscillator 40 is a variable VCO switched capacitor array.
[0055] See Figure 4 The variable VCO switched capacitor array includes a switching circuit module 401 and a VCO circuit module 402. The VCO circuit module 402 is electrically disconnected or connected to the charge-sharing filter 20 and the phase-locked loop proportional path module 30 through the switching circuit module 401.
[0056] In this embodiment, the structure of the VCO circuit module 402 includes: a first variable capacitor C1, a second variable capacitor C2, a first MOSFET Q1, a second MOSFET Q2, a third MOSFET Q3, a fourth MOSFET Q4, an inductor L1, and a variable capacitor array CV.
[0057] The first MOSFET Q1 and the second MOSFET Q2 form a first cross-coupled negative resistor, and the third MOSFET Q3 and the fourth MOSFET Q4 form a second cross-coupled negative resistor.
[0058] The first terminal of the first cross-coupled negative resistor is connected in parallel to the second terminal of the first cross-coupled negative resistor and then connected to the voltage terminal VDD.
[0059] The third terminal of the first cross-coupled negative resistor is connected to the first terminal of the inductor L1, the first terminal of the first variable capacitor C1, the first terminal of the variable capacitor array CV, and the first terminal of the second cross-coupled negative resistor, respectively.
[0060] The fourth terminal of the first cross-coupled negative resistor is connected to the second terminal of inductor L1, the first terminal of the second variable capacitor C2, the second terminal of the variable capacitor array CV, and the second terminal of the second cross-coupled negative resistor, respectively. The third terminal of the second cross-coupled negative resistor is connected in parallel to the fourth terminal of the first cross-coupled negative resistor and then grounded.
[0061] The second terminal of the first variable capacitor C1 is connected to the second terminal of the second variable capacitor C2;
[0062] The switching circuit module 401 is connected to the variable capacitor array CV.
[0063] It should be noted that in this embodiment, the phase-locked loop proportional path module is directly connected to the adjustable voltage-controlled oscillator. By changing the array access scale, the path gain coefficient is changed to achieve loop bandwidth modulation. This embodiment reduces the complexity of hardware design and the circuit board area without introducing additional hardware structures.
[0064] In this embodiment, the feedback signal terminal of the adjustable voltage-controlled oscillator 40 is connected to the feedback signal input terminal of the frequency and phase detector 10 through the frequency divider 50.
[0065] This application embodiment also provides a control method for a PLL loop bandwidth adjustment circuit, wherein the PLL loop bandwidth adjustment circuit adopts the PLL loop bandwidth adjustment circuit described above; the control method includes:
[0066] By changing the output frequency of the adjustable voltage-controlled oscillator, the proportional path gain value in the phase-locked loop proportional path module is adjusted, thereby modulating the PLL loop bandwidth.
[0067] This application embodiment also provides a circuit board for a PLL loop bandwidth adjustment circuit, including: the PLL loop bandwidth adjustment circuit as described above, and a substrate carrying the PLL loop bandwidth adjustment circuit.
[0068] It should be noted that in this embodiment, the phase-locked loop proportional path module is directly connected to the adjustable voltage-controlled oscillator, which can save circuit board area.
[0069] In this application, the phase-locked loop proportional path module ( Adjusting the PLL loop bandwidth has advantages such as high flexibility, high energy efficiency, low chip area occupation, and wide adjustment range. It has broad application prospects and development space in wired transmission, wireless transmission, 5G communication and audio processing.
[0070] In summary, this application achieves bandwidth modulation of the PLL loop by changing the output frequency of the adjustable voltage-controlled oscillator and altering the gain coefficient of the phase-locked loop proportional path module. This method features low power consumption, flexible adjustment, and high practicality.
[0071] Although one embodiment of the invention has been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to that embodiment. Therefore, the appended claims are intended to be interpreted as including the described embodiment as well as all changes and modifications falling within the scope of the invention.
[0072] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.
Claims
1. A PLL loop bandwidth adjustment circuit, characterized in that, include: Frequency and phase detector (10), charge-sharing filter (20), phase-locked loop proportional path module (30) and adjustable voltage-controlled oscillator (40); The input terminal of the frequency and phase detector (10) is connected to the reference signal; The first output terminal of the frequency and phase detector (10) is connected to the first input terminal of the adjustable voltage-controlled oscillator (40) through a charge-sharing filter (20); The second output terminal of the frequency and phase detector (10) is connected to the second input terminal of the adjustable voltage-controlled oscillator (40) through the phase-locked loop proportional path module (30).
2. The PLL loop bandwidth adjustment circuit according to claim 1, characterized in that, The charge-sharing filter (20) includes: an integration path module (201) and a low-pass filter module (202); The first output terminal of the frequency and phase detector (10) is connected to the first input terminal of the adjustable voltage-controlled oscillator (40) through the integration path module (201) and the low-pass filter module (202).
3. The PLL loop bandwidth adjustment circuit according to claim 1, characterized in that, The adjustable voltage-controlled oscillator (40) is a variable VCO switched capacitor array.
4. The PLL loop bandwidth adjustment circuit according to claim 2, characterized in that, The variable VCO switched capacitor array includes a switching circuit module (401) and a VCO circuit module (402), wherein the VCO circuit module (402) is electrically disconnected or connected to the charge-sharing filter (20) and the phase-locked loop proportional path module (30) through the switching circuit module (401).
5. The PLL loop bandwidth adjustment circuit according to claim 4, characterized in that, The structure of the VCO circuit module (402) is as follows: it includes a first variable capacitor C1, a second variable capacitor C2, a first MOSFET Q1, a second MOSFET Q2, a third MOSFET Q3, a fourth MOSFET Q4, an inductor L1, and a variable capacitor array CV. The first MOSFET Q1 and the second MOSFET Q2 form a first cross-coupled negative resistor, and the third MOSFET Q3 and the fourth MOSFET Q4 form a second cross-coupled negative resistor. The first terminal of the first cross-coupled negative resistor is connected in parallel to the second terminal of the first cross-coupled negative resistor and then connected to the voltage terminal VDD. The third terminal of the first cross-coupled negative resistor is connected to the first terminal of the inductor L1, the first terminal of the first variable capacitor C1, the first terminal of the variable capacitor array CV, and the first terminal of the second cross-coupled negative resistor, respectively. The fourth terminal of the first cross-coupled negative resistor is connected to the second terminal of inductor L1, the first terminal of the second variable capacitor C2, the second terminal of the variable capacitor array CV, and the second terminal of the second cross-coupled negative resistor, respectively. The third terminal of the second cross-coupled negative resistor is connected in parallel to the fourth terminal of the first cross-coupled negative resistor and then grounded. The second terminal of the first variable capacitor C1 is connected to the second terminal of the second variable capacitor C2; The switching circuit module (401) is connected to the variable capacitor array CV.
6. The PLL loop bandwidth adjustment circuit according to claim 1, characterized in that, The feedback signal terminal of the adjustable voltage-controlled oscillator (40) is connected to the feedback signal input terminal of the frequency and phase detector (10) through a frequency divider (50).
7. A control method for a PLL loop bandwidth adjustment circuit, characterized in that, The PLL loop bandwidth adjustment circuit adopts the PLL loop bandwidth adjustment circuit as described in any one of claims 1 to 6; the control method includes: By changing the output frequency of the adjustable voltage-controlled oscillator, the proportional path gain value in the phase-locked loop proportional path module is adjusted, thereby modulating the PLL loop bandwidth.
8. A circuit board for a PLL loop bandwidth adjustment circuit, characterized in that, include: The PLL loop bandwidth adjustment circuit as described in any one of claims 1 to 6, and the substrate carrying the PLL loop bandwidth adjustment circuit.