Phase frequency detector and phase locked loop circuit

Abstract

The application discloses a frequency discriminator and phase detector and a phase-locked loop circuit. The frequency discriminator and phase detector comprises a first digital circuit and a second digital circuit. The signal input end of the first digital circuit receives a first signal and is connected with the configuration end of the second digital circuit. The signal input end of the second digital circuit receives a second signal and is connected with the configuration end of the first digital circuit. The first digital circuit outputs a first level signal when the second signal appears a clock active edge. The first digital circuit outputs a second level signal when the first signal appears a clock active edge twice in succession during the period that the second signal appears a clock active edge twice in succession. The second digital circuit outputs the first level signal when the first signal appears a clock active edge. The second digital circuit outputs the second level signal when the second signal appears a clock active edge twice in succession during the period that the first signal appears a clock active edge twice in succession. For a charge pump type phase-locked loop circuit, the frequency discriminator and phase detector can reduce the matching requirement of the current source for the subsequent charge pump circuit.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a frequency and phase detector and a phase-locked loop circuit. Background Technology

[0002] A charge pump type phase-locked loop circuit includes a frequency and phase detector, a charge pump circuit, and a voltage-controlled oscillator (VCO). The frequency and phase detector detects the frequency and phase differences between the input and feedback signals and outputs an error signal related to both. The charge pump circuit converts the error signal output by the frequency and phase detector into an analog control voltage through charging and discharging. The VCO adjusts the frequency of its output signal according to the input control voltage.

[0003] In related technologies, the charge pump circuit includes a first current source, a second current source, a first switch, a second switch, and a capacitor. When the first switch is on, the first current source charges the capacitor; when the second switch is on, the capacitor discharges through the second current source. Furthermore, the two output terminals of the frequency and phase detector are connected to the control terminals of the first and second switches, respectively. When both output signals of the frequency and phase detector are continuously high, the first and second switches will be turned on simultaneously. If the currents from the first and second current sources do not match, it will cause voltage fluctuations across the capacitor, leading to a decrease in the accuracy of the control voltage output by the charge pump circuit and affecting the performance of the entire phase-locked loop circuit. Utility Model Content

[0004] The main technical problem addressed by this application is to provide a frequency and phase detector and a phase-locked loop circuit that can reduce the matching requirements of the current source after the frequency and phase detector.

[0005] To solve the above-mentioned technical problems, one technical solution adopted in this application is: providing a frequency and phase detector applied to a charge pump type phase-locked loop circuit; the frequency and phase detector includes a first digital circuit and a second digital circuit, the signal input terminal of the first digital circuit is used to receive a first signal, and the signal input terminal of the first digital circuit is connected to the configuration terminal of the second digital circuit, the signal input terminal of the second digital circuit is used to receive a second signal, and the signal input terminal of the second digital circuit is connected to the configuration terminal of the first digital circuit; when the second signal has a valid clock edge, the first digital circuit is configured to output a first level signal; and when the first signal has two consecutive valid clock edges during the period when the second signal has two consecutive valid clock edges, the first digital circuit is configured to output a second level signal; when the first signal has a valid clock edge, the second digital circuit is configured to output a first level signal; and when the second signal has two consecutive valid clock edges during the period when the first signal has two consecutive valid clock edges, the second digital circuit is configured to output a second level signal; wherein the level types of the first level signal and the second level signal are different.

[0006] Optionally, the first digital circuit is a target digital circuit, and the first signal and the second signal are respectively the first target signal and the second target signal; or, the second digital circuit is a target digital circuit, and the second signal and the first signal are respectively the first target signal and the second target signal; wherein, the target digital circuit includes a first trigger circuit and a second trigger circuit, the first configuration terminal of the first trigger circuit and the configuration terminal of the second trigger circuit are connected and serve as the configuration terminal of the target digital circuit, the clock input terminal of the first trigger circuit and the clock input terminal of the second trigger circuit are connected and serve as the signal input terminal of the target digital circuit, the second configuration terminal of the first trigger circuit is connected to the output terminal of the second trigger circuit, and the output terminal of the first trigger circuit is the output terminal of the target digital circuit; the first trigger circuit is used to count the number of consecutive clock effective edges of the first target signal, the first trigger circuit is configured to output a first level signal when a clock effective edge of the second target signal appears, and the first trigger circuit is configured to output a second level signal when the number of consecutive clock effective edges of the second target signal reaches two; and, when a clock effective edge of the second target signal appears during the period when the first target signal is a continuous second level signal, the second trigger circuit is configured to output a configuration signal to configure the first trigger circuit to count the clock effective edges of the second target signal.

[0007] Optionally, the first trigger circuit includes a first trigger sub-circuit and a second trigger sub-circuit; the set terminal of the first trigger sub-circuit and the reset terminal of the second trigger sub-circuit are connected and serve as the first configuration terminal of the first trigger circuit, the reset terminal of the first trigger sub-circuit is the second configuration terminal of the first trigger circuit, the clock input terminal of the first trigger sub-circuit and the clock input terminal of the second trigger sub-circuit are connected and serve as the clock input terminal of the first trigger circuit, the data input terminal of the first trigger sub-circuit is grounded, the inverting output terminal of the first trigger sub-circuit is connected to the data input terminal of the second trigger sub-circuit, and the output terminal of the second trigger sub-circuit is the output terminal of the first trigger circuit.

[0008] Optionally, at least one of the first trigger sub-circuit and the second trigger sub-circuit is a D flip-flop; or, at least one of the first trigger sub-circuit and the second trigger sub-circuit includes a first inverter and a first JK flip-flop, wherein the input terminal of the first inverter and the first input terminal of the first JK flip-flop are connected and serve as the data input terminal of the corresponding trigger sub-circuit, and the output terminal of the first inverter is connected to the second input terminal of the first JK flip-flop.

[0009] Optionally, the second trigger circuit includes a second inverter and a third trigger sub-circuit. The input terminal of the second inverter and the data input terminal of the third trigger sub-circuit are connected and serve as the configuration terminal of the second trigger circuit. The output terminal of the second inverter is connected to the reset terminal of the third trigger sub-circuit. The clock input terminal and the output terminal of the third trigger sub-circuit are, in turn, the clock input terminal and the clock output terminal of the second trigger circuit.

[0010] Optionally, the third trigger sub-circuit is a D flip-flop; or, the third trigger sub-circuit includes a third inverter and a second JK flip-flop, the input terminal of the third inverter and the first input terminal of the second JK flip-flop are connected and serve as the data input terminal of the third trigger sub-circuit, and the output terminal of the third inverter is connected to the second input terminal of the second JK flip-flop.

[0011] Optionally, the frequency and phase detector further includes a first delay circuit and a second delay circuit. The input terminal of the first delay circuit is connected to the output terminal of the first digital circuit, and the input terminal of the second delay circuit is connected to the output terminal of the second digital circuit. The first delay circuit is configured to output a second-level signal when the first digital circuit outputs a second-level signal before the first delay duration has elapsed, and to output a first-level signal when the first digital circuit outputs a second-level signal after the first delay duration has elapsed. The second delay circuit is configured to output a second-level signal when the second digital circuit outputs a second-level signal before the second delay duration has elapsed, and to output a first-level signal when the second digital circuit outputs a second-level signal after the second delay duration has elapsed.

[0012] Optionally, the target delay circuit is a first delay circuit or a second delay circuit. The target delay circuit includes a delay sub-circuit, a fourth inverter, and a NOR gate. The input terminal of the delay sub-circuit and the input terminal of the fourth inverter are connected and serve as the input terminal of the target delay circuit. The output terminal of the delay sub-circuit is connected to the first input terminal of the NOR gate. The output terminal of the fourth inverter is connected to the second input terminal of the NOR gate. The output terminal of the NOR gate serves as the output terminal of the target delay circuit.

[0013] To solve the above-mentioned technical problems, another technical solution adopted in this application is: to provide a phase-locked loop circuit, the phase-locked loop circuit including: the aforementioned frequency and phase detector; a charge pump circuit, the first terminal of the charge pump circuit being connected to the first output terminal of the frequency and phase detector, and the second terminal of the charge pump circuit being connected to the second output terminal of the frequency and phase detector; a voltage-controlled oscillator, the input terminal of the voltage-controlled oscillator being connected to the output terminal of the charge pump circuit, and the output terminal of the voltage-controlled oscillator being connected to a signal input terminal of the frequency and phase detector.

[0014] Optionally, the charge pump circuit includes: a first current source, a second current source, a first switch, a second switch, and a capacitor; the input terminal of the first current source is connected to a power supply, the output terminal of the first current source is connected to the first terminal of the first switch, the second terminal of the first switch is connected to the first terminal of the second switch and the first terminal of the capacitor, the second terminal of the second switch is connected to the input terminal of the second current source, the second terminal of the capacitor and the output terminal of the second current source are both grounded, the control terminal of the first switch and the control terminal of the second switch are respectively connected to the first output terminal and the second output terminal of the frequency and phase detector, and the first terminal of the capacitor is the output terminal of the charge pump circuit.

[0015] In the above scheme, the frequency and phase detector includes a first digital circuit and a second digital circuit. The signal input terminal of the first digital circuit receives a first signal and is connected to the configuration terminal of the second digital circuit. The signal input terminal of the second digital circuit receives a second signal and is connected to the configuration terminal of the first digital circuit. The first digital circuit outputs a second-level signal only when the first signal has two consecutive valid clock edges. When the first signal has a valid clock edge, the second digital circuit is configured to output the first-level signal. Similarly, the second digital circuit outputs a second-level signal only when the second signal has two consecutive valid clock edges. When the second signal has a valid clock edge, the first digital circuit is configured to output the first-level signal. Therefore, the first and second digital circuits will not output second-level signals simultaneously. For charge pump type phase-locked loop circuits, this frequency and phase detector prevents the two switches in the subsequent charge pump circuit from conducting simultaneously, thereby reducing the matching requirements of the current source for the subsequent charge pump circuit. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the circuit structure of an embodiment of the phase-locked loop circuit provided in this application;

[0017] Figure 2 This is a schematic diagram of the circuit structure of an embodiment of the frequency and phase detector provided in this application;

[0018] Figure 3 This is a schematic diagram of the circuit structure of an embodiment of the target digital circuit provided in this application;

[0019] Figure 4 This is a schematic diagram of the circuit structure of one embodiment of the target digital circuit provided in this application;

[0020] Figure 5 This is a schematic diagram of the circuit structure of another embodiment of the target digital circuit provided in this application;

[0021] Figure 6 This is a schematic diagram of the operating waveforms of the target digital circuit provided in this application;

[0022] Figure 7 This is a schematic diagram of the circuit structure of another embodiment of the frequency and phase detector provided in this application;

[0023] Figure 8 This is a schematic diagram of the circuit structure of one embodiment of the target delay circuit provided in this application. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0025] It should be noted that the terms "first" and "second" in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0026] Please see Figure 1 , Figure 1 This is a schematic diagram of the circuit structure of an embodiment of the phase-locked loop circuit provided in this application. Figure 1 As shown, the phase-locked loop circuit includes a frequency and phase detector, a charge pump circuit, and a voltage-controlled oscillator.

[0027] The frequency and phase detector includes a first signal input terminal, a second signal input terminal, a first output terminal, and a second output terminal. The first and second signal input terminals of the frequency and phase detector receive a first signal and a second signal, respectively. The first signal is a reference signal. For example, the first signal can be provided by a signal source such as a crystal oscillator. The second signal is a feedback signal. For example, the second signal can be obtained by dividing the output signal of a voltage-controlled oscillator. The first and second output terminals of the frequency and phase detector output a UP signal and a DN signal, respectively.

[0028] The frequency and phase detector further includes a first D flip-flop (corresponding to...) Figure 1 M1 in the middle), the second D flip-flop (corresponding to Figure 1 M2 in the middle) and AND gate (corresponding to Figure 1 The clock input of the first D flip-flop (M3 in the diagram) is the first signal input of the frequency and phase detector. The data input of the first D flip-flop is connected to the power supply. The data output of the first D flip-flop is connected to the first input of the AND gate and serves as the first output of the frequency and phase detector. The clock input of the second D flip-flop is the second signal input of the frequency and phase detector. The data input of the second D flip-flop is connected to the power supply. The data output of the second D flip-flop is connected to the second input of the AND gate and serves as the second output of the frequency and phase detector. The output of the AND gate is connected to the reset terminals of both the first and second D flip-flops.

[0029] The first terminal of the charge pump circuit is connected to the first output terminal of the frequency and phase detector, and the second terminal of the charge pump circuit is connected to the second output terminal of the frequency and phase detector.

[0030] The charge pump circuit further includes a first current source (corresponding to) Figure 1 I1 in the middle), the second current source (corresponding to) Figure 1 I2 in the middle), the first switch (corresponding to) Figure 1 S1 in the middle), the second switch (corresponding to Figure 1 S2) and capacitor (corresponding to Figure 1 (C) The input terminal of the first current source is connected to the power supply. The output terminal of the first current source is connected to the first terminal of the first switch. The second terminal of the first switch is connected to the first terminal of the second switch and the first terminal of the capacitor. The second terminal of the second switch is connected to the input terminal of the second current source. The second terminal of the capacitor and the output terminal of the second current source are both grounded. The control terminals of the first and second switches are respectively connected to the first and second output terminals of the frequency and phase detector, and the first terminal of the capacitor is the output terminal of the charge pump circuit. The first switch is turned on when the control terminal of the first switch is input with a high level, and the second switch is turned on when the control terminal of the second switch is input with a high level. For example, the first switch is a PMOS and the second switch is an NMOS. In this case, an inverter is also included between the first output terminal of the frequency and phase detector and the control terminal of the first switch. Figure 1 The inverter is not shown in the diagram.

[0031] The input terminal of the voltage-controlled oscillator is connected to the output terminal of the charge pump circuit, and the output terminal of the voltage-controlled oscillator is connected to the second signal input terminal of the frequency and phase detector.

[0032] The following is a brief introduction Figure 1 The working principle of the frequency and phase detector: Assume that initially, both the UP and DN signals are low, and both the first and second D flip-flops are triggered by the rising edge of the clock. When the first signal has a rising edge, the first D flip-flop is triggered, making the UP signal high. When the second signal has a rising edge, the second D flip-flop is triggered, making the DN signal high. When both the UP and DN signals are high simultaneously, an AND gate is triggered to reset the first and second D flip-flops, causing the UP and DN signals to return to low. If the first and second signals do not have simultaneous rising edges—for example, if the first signal rises first, the UP signal is high after the first rising edge begins, and then both the UP and DN signals are low after the second rising edge appears. Therefore, the duration for which the UP signal remains high reflects the time the first signal's rising edge leads the second signal, and the duration for which the DN signal remains high reflects the time the second signal's rising edge leads the first signal. Therefore, this frequency and phase detector can be used to detect the phase relationship between the first and second signals.

[0033] In practical applications, due to the different path delays from the AND gate to each D flip-flop, the resets of the first and second D flip-flops may not occur simultaneously. It's possible that even though the AND gate output is high, resetting the first D flip-flop, the second D flip-flop may not have had time to reset. In this case, the UP signal goes low, causing the AND gate output to go low again, leading to digital function errors. Therefore, a delay module is typically used to ensure that the UP and DN signals are simultaneously high for a period of time to solve this problem. Even without the aforementioned issue, due to the gate circuit delay, the UP and DN signals will always be high simultaneously for a period of time. During this period, the first and second switches in the charge pump circuit are simultaneously turned on. If the currents from the first and second current sources do not match, it will cause fluctuations in the voltage (Vo) across the capacitor, reducing the accuracy of the control voltage output by the charge pump circuit, thus affecting the performance of the entire phase-locked loop circuit.

[0034] Please see Figure 2 , Figure 2 This is a schematic diagram of the circuit structure of an embodiment of the frequency and phase detector provided in this application. Figure 2 As shown, the frequency and phase detector includes a first digital circuit and a second digital circuit. The signal input terminal of the first digital circuit is used to receive a first signal, and the signal input terminal of the first digital circuit is connected to the configuration terminal of the second digital circuit. The signal input terminal of the second digital circuit is used to receive a second signal, and the signal input terminal of the second digital circuit is connected to the configuration terminal of the first digital circuit. The signal input terminals of the first and second digital circuits are respectively the first and second signal input terminals of the frequency and phase detector. The output terminals of the first and second digital circuits are respectively the first and second output terminals of the frequency and phase detector. For details regarding the first and second signals, please refer to... Figure 1 The embodiments shown are not described in detail here.

[0035] When the second signal has a valid clock edge, the first digital circuit is configured to output a first-level signal. And, during the period between two consecutive valid clock edges of the second signal, when the first signal has two consecutive valid clock edges, the first digital circuit is configured to output a second-level signal. When the first digital circuit outputs the first-level signal, the corresponding first switch is not turned on; when the first digital circuit outputs the second-level signal, the corresponding first switch is turned on.

[0036] When the first signal has a valid clock edge, the second digital circuit is configured to output a first-level signal. And, during the period between two consecutive valid clock edges of the first signal, when the second signal has two consecutive valid clock edges, the second digital circuit is configured to output a second-level signal. When the second digital circuit outputs the first-level signal, the corresponding second switch is not turned on; when the second digital circuit outputs the second-level signal, the corresponding second switch is turned on.

[0037] The first level signal and the second level signal have different level types. For example, the first level signal is low and the second level signal is high.

[0038] In this embodiment, the frequency and phase detector includes a first digital circuit and a second digital circuit. The signal input terminal of the first digital circuit is used to receive a first signal, and the signal input terminal of the first digital circuit is connected to the configuration terminal of the second digital circuit. The signal input terminal of the second digital circuit is used to receive a second signal, and the signal input terminal of the second digital circuit is connected to the configuration terminal of the first digital circuit. The first digital circuit outputs a second-level signal only when the first signal has two consecutive valid clock edges. When the first signal has a valid clock edge, the second digital circuit is configured to output a first-level signal. Similarly, the second digital circuit outputs a second-level signal only when the second signal has two consecutive valid clock edges. When the second signal has a valid clock edge, the first digital circuit is configured to output a first-level signal. Therefore, the first and second digital circuits will not output second-level signals simultaneously. For charge pump type phase-locked loop circuits, using this frequency and phase detector will prevent the two switches in the subsequent charge pump circuit from being turned on simultaneously, thereby reducing the matching requirements of the current source for the subsequent charge pump circuit.

[0039] Since the first digital circuit and the second digital circuit have the same circuit structure, to reduce repetitive description, this identical circuit structure will be represented by the target digital circuit, and the circuit structure of the target digital circuit will be described in detail. It is understood that the target digital circuit is only half the circuit structure of the frequency and phase detector. Furthermore, in the following text, when the target digital circuit is the first digital circuit, the first signal and the second signal will be referred to as the first target signal and the second target signal, respectively; when the target digital circuit is the second digital circuit, the second signal and the first signal will be referred to as the first target signal and the second target signal, respectively.

[0040] Please see Figure 3 , Figure 3 This is a schematic diagram of the circuit structure of an embodiment of the target digital circuit provided in this application. Figure 3As shown, the target digital circuit includes a first trigger circuit 10 and a second trigger circuit 20. The first configuration terminal of the first trigger circuit 10 and the configuration terminal of the second trigger circuit 20 are connected and serve as the configuration terminal of the target digital circuit. The clock input terminal of the first trigger circuit 10 and the clock input terminal of the second trigger circuit 20 are connected and serve as the signal input terminal of the target digital circuit. The second configuration terminal of the first trigger circuit 10 is connected to the output terminal of the second trigger circuit 20, and the output terminal of the first trigger circuit 10 is the output terminal of the target digital circuit. In this embodiment, the signal input terminal of the target digital circuit is used to input a first target signal, and the configuration terminal of the target digital circuit is used to input a second target signal.

[0041] The first trigger circuit 10 is used to count the number of consecutive clock effective edges of the first target signal. When the second target signal has a clock effective edge, the first trigger circuit 10 is configured to output a first level signal. When the number of consecutive clock effective edges of the first target signal reaches two during the period when the second target signal has two consecutive clock effective edges, the first trigger circuit 10 is configured to output a second level signal.

[0042] Furthermore, considering that during the period when the second target signal has a valid clock edge and remains at the second level, the first target signal may also have a valid clock edge, while the first trigger circuit 10 still outputs the first level signal under the influence of the second target signal, thus failing to count correctly, a second trigger circuit 20 is added to ensure that the first trigger circuit 10 can still count the valid clock edges of the first target signal normally in this situation. When the second target signal has a valid clock edge during the period when the first target signal remains at the second level, the second trigger circuit 20 is configured to output a configuration signal to configure the first trigger circuit 10 to count the valid clock edges of the second target signal normally.

[0043] Figure 4 This is a schematic diagram of the circuit structure of one embodiment of the target digital circuit provided in this application. Figure 4 As shown, the target digital circuit includes a first trigger circuit 10 and a second trigger circuit 20.

[0044] The first trigger circuit 10 further includes a first trigger sub-circuit 11 and a second trigger sub-circuit 12. The set terminal of the first trigger sub-circuit 11 and the reset terminal of the second trigger sub-circuit 12 are connected and serve as the first configuration terminal of the first trigger circuit 10. The reset terminal of the first trigger sub-circuit 11 serves as the second configuration terminal of the first trigger circuit 10. The clock input terminal of the first trigger sub-circuit 11 and the clock input terminal of the second trigger sub-circuit 12 are connected and serve as the clock input terminal of the first trigger circuit 10. The data input terminal of the first trigger sub-circuit 11 is grounded. The inverting output terminal of the first trigger sub-circuit 11 is connected to the data input terminal of the second trigger sub-circuit 12. The output terminal of the second trigger sub-circuit 12 serves as the output terminal of the first trigger circuit 10.

[0045] The second trigger circuit 20 further includes a second inverter 21 and a third trigger sub-circuit 22. The input terminal of the second inverter 21 and the data input terminal of the third trigger sub-circuit 22 are connected and serve as the configuration terminal of the second trigger circuit 20. The output terminal of the second inverter 21 is connected to the reset terminal of the third trigger sub-circuit 22. The clock input terminal and the output terminal of the third trigger sub-circuit 22 are the clock input terminal and the clock output terminal of the second trigger circuit 20, respectively.

[0046] Figure 4 In this circuit, the first trigger sub-circuit 11, the second trigger sub-circuit 12, and the third trigger sub-circuit 22 are all D flip-flops.

[0047] For example, the first trigger sub-circuit 11, the second trigger sub-circuit 12 and the third trigger sub-circuit 22 are all triggered by the rising edge of the clock. That is, the rising edge of the first target signal is the valid edge of the clock. When the first target signal has a valid edge of the clock, each trigger sub-circuit updates the output data according to the input data.

[0048] Figure 5 This is a schematic diagram of the circuit structure of another embodiment of the target digital circuit provided in this application. For example... Figure 5 As shown, the target digital circuit includes a first trigger circuit 10 and a second trigger circuit 20. The first trigger circuit 10 further includes a first trigger sub-circuit 11 and a second trigger sub-circuit 12, and the second trigger circuit 20 further includes a second inverter 21 and a third trigger sub-circuit 22. Figure 4 Compared to the target digital circuit shown, Figure 5 Both the first trigger sub-circuit 11 and the second trigger sub-circuit 12 include a first inverter and a first JK flip-flop. Figure 5 The labels of the first inverter and the first JK flip-flop are not shown in the diagram. The third trigger sub-circuit 22 includes a third inverter and a second JK flip-flop. Figure 5(The labels for the third inverter and the second JK flip-flop are not shown). Specifically, the input terminal of the first inverter is connected to the first input terminal (J terminal) of the first JK flip-flop and serves as the data input terminal of the corresponding trigger sub-circuit. The output terminal of the first inverter is connected to the second input terminal (K terminal) of the first JK flip-flop. The input terminal of the third inverter is connected to the first input terminal (J terminal) of the second JK flip-flop and serves as the data input terminal of the third trigger sub-circuit 22. The output terminal of the third inverter is connected to the second input terminal (K terminal) of the second JK flip-flop.

[0049] It should be noted that, Figure 4 The example only illustrates that the first trigger sub-circuit 11, the second trigger sub-circuit 12, and the third trigger sub-circuit 22 are all D flip-flops. Figure 5 The example described herein is based solely on the first trigger sub-circuit 11 and the second trigger sub-circuit 12, both of which include a first inverter and a first JK flip-flop, and the third trigger sub-circuit 22, which includes a third inverter and a second JK flip-flop. Each trigger sub-circuit can be in the form of a D flip-flop, or it can be a combination of an inverter and a JK flip-flop that have the same function as a D flip-flop.

[0050] The following is about Figure 4 and Figure 5 A brief explanation of the working principle of the target digital circuit in the diagram is provided below:

[0051] It is important to note that in this embodiment, the set and reset terminals of the trigger sub-circuit have opposite functions. When the set terminal of the trigger sub-circuit is high, the output of the trigger sub-circuit is set to high, and the inverted output of the trigger sub-circuit is set to low; when the reset terminal of the trigger sub-circuit is high, the output of the trigger sub-circuit is set to low, and the inverted output of the trigger sub-circuit is set to high. Furthermore, the reset terminal of the trigger sub-circuit has a higher priority than the set terminal. That is, when both the reset and set terminals of the trigger sub-circuit are high, the reset terminal of the trigger sub-circuit takes effect.

[0052] For ease of description, the output signals of the third trigger sub-circuit 22, the first trigger sub-circuit 11, and the second trigger sub-circuit 12 will be referred to as S1, S2, and S3, respectively. Wherein, when the target digital circuit is the aforementioned first digital circuit, S3 is the aforementioned UP signal; when the target digital circuit is the aforementioned second digital circuit, S3 is the aforementioned DN signal.

[0053] Initially, S1, S2, and S3 are all low. When the first target signal has a rising edge (i.e., a valid clock edge) and the second target signal is low, the first trigger circuit 11 is triggered, causing S2 to go high. If the first target signal has another rising edge while S2 is already high, the second trigger circuit 12 is triggered, causing S3 to go high. In other words, S3 needs two consecutive rising edges from the first target signal to go high. If the rising edge of the second target signal arrives first when S2 is high, the set terminal of the first trigger circuit 11 and the reset terminal of the second trigger circuit 12 are triggered, causing both S2 and S3 to go low. Therefore, the second target signal can interrupt the transmission process of the first target signal with two consecutive rising edges. If the first and second target signals alternate rising edges, only S2 will go high, while S3 will not. If the duty cycle of the second target signal is relatively large, causing it to remain high for a prolonged period after a rising edge, the first trigger sub-circuit 11 and the second trigger sub-circuit 12 will continuously output low levels during this period. However, a rising edge may occur in the first target signal during this time, and according to logic requirements, S2 should become high. Therefore, a second trigger circuit 20 (including a second inverter 21 and a third trigger sub-circuit 22) is added. When the second target signal is high, the reset terminal of the third trigger sub-circuit 22 is low, preventing it from being in a reset state. Furthermore, the data input terminal of the third trigger sub-circuit 22 is high. If a rising edge occurs in the first target signal at this time, it will trigger the third trigger sub-circuit 22, causing S1 to become high, which can reset the first trigger sub-circuit 11, causing S2 to also become high.

[0054] Figure 6 This is a schematic diagram of the operating waveforms of the target digital circuit provided in this application, and... Figure 6 The CCP outlined four possible scenarios.

[0055] Case 1: The rising edges of the first target signal and the second target signal alternate. When the first target signal has a rising edge, S2 becomes high. However, the second target signal then has a rising edge, which sets S2 to low. Therefore, S3 is never high.

[0056] Case 2: The first target signal has two consecutive rising edges. After the first rising edge of the first target signal, S2 becomes high. After the first rising edge of the first target signal, S3 becomes high, and the high level of S3 continues until the second rising edge of the second target signal appears.

[0057] Case 3: During the period when the second target signal is continuously at a high level, the first target signal has a rising edge. At this time, S1 becomes high level, which makes S2 also become high level. When the next rising edge of the first target signal arrives, it can make S3 become high level.

[0058] Case 4: The rising edges of the first target signal and the second target signal alternate, but each rising edge of the first target signal occurs exactly during the period when the second target signal is continuously at a high level. Each time the first target signal has a rising edge, S1 and S2 will be at a high level. However, when the second target signal has a rising edge for the next time, S2 will be configured to a low level, so S3 will still not be at a high level.

[0059] Based on the foregoing analysis, it can be seen that in this embodiment, the target digital circuit only outputs a high level when the first target signal has two consecutive valid clock edges during the period when the second target signal has two consecutive valid clock edges. Specifically, when the target digital circuit is the first digital circuit, the first target signal is the first signal, and the second target signal is the second signal. The first digital circuit outputs a high level when the first signal has two consecutive valid clock edges during the period when the second signal has two consecutive valid clock edges. When the target digital circuit is the second digital circuit, the first target signal is the second signal, and the second target signal is the first signal. The second digital circuit outputs a high level when the second signal has two consecutive valid clock edges during the period when the first signal has two consecutive valid clock edges. Therefore, the first and second digital circuits will not output high levels simultaneously, preventing the two switches in the subsequent charge pump circuit from conducting simultaneously, thereby reducing the matching requirements for the current source after the frequency and phase detector.

[0060] In the aforementioned embodiments, the high-level output of the target digital circuit (i.e., the second-level signal) is limited to ending when the second target signal reaches a valid clock edge. In other embodiments, this limitation may not apply, meaning the high-level output of the target digital circuit can end at any time before the second target signal reaches a valid clock edge.

[0061] Please see Figure 7 , Figure 7 This is a schematic diagram of the circuit structure of another embodiment of the frequency and phase detector provided in this application. Figure 7 As shown, the frequency and phase detector includes a first digital circuit and a second digital circuit, as well as a first delay circuit and a second delay circuit. The input terminal of the first delay circuit is connected to the output terminal of the first digital circuit, and the input terminal of the second delay circuit is connected to the output terminal of the second digital circuit. In this embodiment, the output terminals of the first delay circuit and the second delay circuit are respectively the first output terminal and the second output terminal of the frequency and phase detector.

[0062] The first delay circuit is configured to output a second level signal when the first digital circuit outputs a second level signal before the first delay duration is reached, and to output a first level signal when the first digital circuit outputs a second level signal for the first delay duration is reached.

[0063] The second delay circuit is configured to output a second level signal when the second level signal output by the second digital circuit has not reached the second delay duration, and to output a first level signal when the second level signal output by the second digital circuit has reached the second delay duration.

[0064] For example, the first delay duration is the same as the second delay duration.

[0065] In a specific application, the first delay circuit and the second delay circuit have the same circuit structure. To reduce repetitive description, this identical circuit structure is represented by the target delay circuit 30 (the target delay circuit 30 is either the first delay circuit or the second delay circuit), and the circuit structure of the target delay circuit 30 is described in detail.

[0066] Figure 8 This is a schematic diagram of the circuit structure of one embodiment of the target delay circuit provided in this application. Figure 8 As shown, the target delay circuit 30 includes a delay sub-circuit 31, a fourth inverter 32, and a NOR gate 33. The input terminals of the delay sub-circuit 31 and the fourth inverter 32 are connected and serve as the input terminals of the target delay circuit 30. The output terminal of the delay sub-circuit 31 is connected to the first input terminal of the NOR gate 33, and the output terminal of the fourth inverter 32 is connected to the second input terminal of the NOR gate 33. The output terminal of the NOR gate 33 is the output terminal of the target delay circuit 30. The delay sub-circuit is used to delay the output of the signals input to its input terminals. The NOR gate 33 operates as follows: when all inputs are low, the output is high; otherwise, the output is low.

[0067] Assuming the target digital circuit initially outputs a low level, since the fourth inverter 32 outputs a high level, the NOR gate 33 outputs a low level. When the target digital circuit outputs a high level (i.e., outputs the second level signal), the delay sub-circuit 31 remains low until the corresponding delay duration is reached. Since the fourth inverter 32 also outputs a low level, the NOR gate 33 outputs a high level. After the delay sub-circuit 31 reaches the corresponding delay duration, its output becomes high. Since the fourth inverter 32 outputs a low level, the NOR gate 33 outputs a low level. In this way, the high level output by the target digital circuit can be automatically delayed for a period of time before becoming low, without waiting for the valid clock edge of the second target signal.

[0068] Figure 1In the frequency and phase detector shown, during the period when the UP signal and DN signal are continuously at a high level, the first switch and the second switch in the charge pump circuit are turned on simultaneously. If the current of the first current source and the current of the second current source do not match, it will cause fluctuations in the voltage (Vo) on the capacitor, which will reduce the accuracy of the control voltage output by the charge pump circuit, thereby affecting the performance of the entire phase-locked loop circuit.

[0069] In the frequency and phase detector of this application, the first digital circuit and the second digital circuit will not output high level at the same time. That is, the UP signal and the DN signal will not become high level at the same time, so that the two switches in the subsequent charge pump circuit will not be turned on at the same time, thereby reducing the matching requirements of the current source of the subsequent charge pump circuit.

[0070] Figure 1 In the frequency and phase detector shown, when the UP signal and the DN signal go high at the same time, the first switch and the second switch may not turn on at the same time due to the path delay and the different switch types. For example, if the second switch turns on first, the output voltage Vo on the capacitor will decrease, which is an incorrect reaction.

[0071] In the frequency and phase detector of this application, the first digital circuit and the second digital circuit will not output high level at the same time. That is, the UP signal and the DN signal will not become high level at the same time. There will be no switching delay problem caused by simultaneous conduction. Therefore, the delay requirement of the switch in the subsequent charge pump circuit can be reduced.

[0072] Figure 1 In the frequency and phase detector shown, each rising edge of the first and second signals causes fluctuations in the UP and DN signals, resulting in fluctuations in the output voltage Vo across the capacitor. Although the first and second signals have the same frequency, the jumping coupling capacitor and noise generated anywhere in the circuit affect the phase of the first and second signals. When the phase of the first and second signals changes, the circuit interprets the frequency as changing (even though the frequency may not have actually changed), causing a change in the output voltage Vo across the capacitor. This, in turn, affects subsequent circuitry, ultimately causing fluctuations in the steady-state operating frequency of the frequency and phase detector.

[0073] In the frequency and phase detector of this application, there will be no high-level output when the frequencies of the first signal and the second signal are the same. Even if there is circuit noise that causes a delay in one of the first signal and the second signal, as long as the first signal or the second signal does not have two consecutive rising edges after the delay, the frequency and phase detector will not generate an output. Therefore, after the frequency and phase detector of this application works stably, the phase change will not be reflected in the output, and the frequency will no longer fluctuate.

[0074] Furthermore, the frequency and phase detector of this application can also determine the frequency relationship between the first and second signals by judging whether there are two consecutive rising edges of the second signal between two consecutive rising edges of the first signal, or by judging whether there are two consecutive rising edges of the first signal between two consecutive rising edges of the second signal, thus realizing the frequency discrimination function of the frequency and phase detector. For example, if there are two consecutive rising edges of the second signal between two consecutive rising edges of the first signal, it means that the frequency of the first signal is higher than that of the second signal; if no two consecutive rising edges of the second signal are detected between two consecutive rising edges of the first signal, it means that the frequencies of the first and second signals are the same.

[0075] In this embodiment, it can be Figure 1 The frequency and phase detector in the shown phase-locked loop circuit is replaced with the frequency and phase detector in this application to obtain a new phase-locked loop circuit. It should be noted that, except... Figure 1 In addition to the charge pump type phase-locked loop circuit shown, the frequency and phase detector in this application can also be applied to other charge pump type phase-locked loop circuits.

[0076] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A frequency and phase detector, characterized in that, Applied to charge pump type phase-locked loop circuits; The frequency and phase detector includes a first digital circuit and a second digital circuit. The signal input terminal of the first digital circuit is used to receive a first signal and is connected to the configuration terminal of the second digital circuit. The signal input terminal of the second digital circuit is used to receive a second signal and is connected to the configuration terminal of the first digital circuit. When the second signal has a valid clock edge, the first digital circuit is configured to output a first level signal; And, during the period when the second signal occurs twice consecutively on the clock effective edge, when the first signal occurs twice consecutively on the clock effective edge, the first digital circuit is configured to output a second level signal; When the first signal has a valid clock edge, the second digital circuit is configured to output the first level signal; And, during the period when the first signal occurs twice consecutively on the clock effective edge, when the second signal occurs twice consecutively on the clock effective edge, the second digital circuit is configured to output the second level signal; The first level signal and the second level signal have different level types.

2. The frequency and phase detector according to claim 1, characterized in that, The first digital circuit is the target digital circuit, and the first signal and the second signal are respectively the first target signal and the second target signal; or, the second digital circuit is the target digital circuit, and the second signal and the first signal are respectively the first target signal and the second target signal. The target digital circuit includes a first trigger circuit and a second trigger circuit. The first configuration terminal of the first trigger circuit and the configuration terminal of the second trigger circuit are connected and serve as the configuration terminal of the target digital circuit. The clock input terminal of the first trigger circuit and the clock input terminal of the second trigger circuit are connected and serve as the signal input terminal of the target digital circuit. The second configuration terminal of the first trigger circuit is connected to the output terminal of the second trigger circuit, and the output terminal of the first trigger circuit is the output terminal of the target digital circuit. The first trigger circuit is configured to count the number of times the first target signal continuously occurs at the clock effective edge. When the second target signal occurs at the clock effective edge, the first trigger circuit is configured to output the first level signal. When the number of occurrences reaches two during the period when the second target signal continuously occurs at the clock effective edge, the first trigger circuit is configured to output the second level signal. And when the second target signal occurs at the clock effective edge during the period when the first target signal is continuously at the second level signal, the second trigger circuit is configured to output a configuration signal to configure the first trigger circuit to count the clock effective edges of the second target signal.

3. The frequency and phase detector according to claim 2, characterized in that, The first trigger circuit includes a first trigger sub-circuit and a second trigger sub-circuit; The set terminal of the first trigger sub-circuit and the reset terminal of the second trigger sub-circuit are connected and serve as the first configuration terminal of the first trigger circuit. The reset terminal of the first trigger sub-circuit is the second configuration terminal of the first trigger circuit. The clock input terminal of the first trigger sub-circuit and the clock input terminal of the second trigger sub-circuit are connected and serve as the clock input terminal of the first trigger circuit. The data input terminal of the first trigger sub-circuit is grounded. The inverting output terminal of the first trigger sub-circuit is connected to the data input terminal of the second trigger sub-circuit. The output terminal of the second trigger sub-circuit is the output terminal of the first trigger circuit.

4. The frequency and phase detector according to claim 3, characterized in that, At least one of the first trigger sub-circuit and the second trigger sub-circuit is a D flip-flop; or, At least one of the first trigger sub-circuit and the second trigger sub-circuit includes a first inverter and a first JK flip-flop. The input terminal of the first inverter and the first input terminal of the first JK flip-flop are connected and serve as the data input terminal of the corresponding trigger sub-circuit. The output terminal of the first inverter is connected to the second input terminal of the first JK flip-flop.

5. The frequency and phase detector according to claim 2, characterized in that, The second trigger circuit includes a second inverter and a third trigger sub-circuit. The input terminal of the second inverter and the data input terminal of the third trigger sub-circuit are connected and serve as the configuration terminal of the second trigger circuit. The output terminal of the second inverter is connected to the reset terminal of the third trigger sub-circuit. The clock input terminal and the output terminal of the third trigger sub-circuit are, in sequence, the clock input terminal and the clock output terminal of the second trigger circuit.

6. The frequency and phase detector according to claim 5, characterized in that, The third trigger sub-circuit is a D flip-flop; or... The third trigger sub-circuit includes a third inverter and a second JK flip-flop. The input terminal of the third inverter is connected to the first input terminal of the second JK flip-flop and serves as the data input terminal of the third trigger sub-circuit. The output terminal of the third inverter is connected to the second input terminal of the second JK flip-flop.

7. The frequency and phase detector according to claim 1, characterized in that, The frequency and phase detector further includes a first delay circuit and a second delay circuit, wherein the input terminal of the first delay circuit is connected to the output terminal of the first digital circuit, and the input terminal of the second delay circuit is connected to the output terminal of the second digital circuit. The first delay circuit is configured to output the second level signal when the output of the second level signal from the first digital circuit has not reached the first delay duration, and to output the first level signal when the output of the second level signal from the first digital circuit has reached the first delay duration; the second delay circuit is configured to output the second level signal when the output of the second level signal from the second digital circuit has not reached the second delay duration, and to output the first level signal when the output of the second level signal from the second digital circuit has reached the second delay duration.

8. The frequency and phase detector according to claim 7, characterized in that, The target delay circuit is either the first delay circuit or the second delay circuit. The target delay circuit includes a delay sub-circuit, a fourth inverter, and a NOR gate. The input terminal of the delay sub-circuit is connected to the input terminal of the fourth inverter and serves as the input terminal of the target delay circuit. The output terminal of the delay sub-circuit is connected to the first input terminal of the NOR gate. The output terminal of the fourth inverter is connected to the second input terminal of the NOR gate. The output terminal of the NOR gate serves as the output terminal of the target delay circuit.

9. A phase-locked loop circuit, characterized in that, The phase-locked loop circuit includes: The frequency and phase detector according to any one of claims 1 to 8; A charge pump circuit, wherein a first terminal of the charge pump circuit is connected to a first output terminal of the frequency-phase detector, and a second terminal of the charge pump circuit is connected to a second output terminal of the frequency-phase detector; A voltage-controlled oscillator (VCO) is provided, wherein the input terminal of the VCO is connected to the output terminal of the charge pump circuit, and the output terminal of the VCO is connected to one signal input terminal of the frequency and phase detector.

10. The phase-locked loop circuit according to claim 9, characterized in that, The charge pump circuit includes: a first current source, a second current source, a first switch, a second switch, and a capacitor; The input terminal of the first current source is connected to the power supply. The output terminal of the first current source is connected to the first terminal of the first switch. The second terminal of the first switch is connected to the first terminal of the second switch and the first terminal of the capacitor. The second terminal of the second switch is connected to the input terminal of the second current source. The second terminal of the capacitor and the output terminal of the second current source are both grounded. The control terminals of the first switch and the second switch are respectively connected to the first and second output terminals of the frequency and phase detector. The first terminal of the capacitor is the output terminal of the charge pump circuit.

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