Clock data recovery circuit and method of operation thereof

Abstract

The present invention relates to a clock data recovery circuit and method of operation thereof. The technology of the present invention is used to implement a clock data recovery circuit with improved tendencies, such as pull-up and / or pull-down tendencies. In various embodiments, the clock data recovery circuit includes a phase detector for receiving an input signal and outputting a reference clock signal. The phase detector then outputs two signals to a charge pump. The output of the charge pump drives an oscillator control voltage up or down depending on the current from the charge pump. A lock detector detects whether lock has occurred by comparing the oscillator control voltage to a preset threshold voltage. When the circuit has stabilized to a frequency substantially close to that of the input signal and the oscillator control voltage is substantially close to the threshold voltage, lock is said to have occurred. A controller circuit can control the scanning of the frequency range available to the circuit until lock occurs.

Description

Technical Field

[0001] This invention relates to analog circuit design, and more particularly to a clock data recovery circuit. Background Technology

[0002] To improve data transmission rates and reduce overhead, communication systems are constantly being improved. One common improvement is to transmit data without a reference clock. Therefore, the receiver must process data asynchronously to recover the clock and data in the absence of a reference clock. The receiver can perform asynchronous data processing using Clock and Data Recovery (CDR) circuitry. Typically, a CDR circuit uses a frequency detector to track the input data rate and match the frequency of a voltage-controlled oscillator to the input data rate. Furthermore, the CDR can use a phase detector to detect the phase difference between the input data rate and the generated clock, and lock the phase accordingly. In this way, the CDR can match the output signal frequency to the input signal. However, because the CDR operates at high frequencies, traditional frequency detectors consume a lot of power and place a heavy load on the system.

[0003] Therefore, the CDR circuit still needs to be improved so that the improved circuit can, for example, increase the frequency range while operating with lower power consumption. Summary of the Invention

[0004] The following description of the invention is provided for the reader's convenience, and various representative embodiments of the invention are illustrated.

[0005] A clock data recovery (CDR) circuit according to a representative embodiment can scan multiple frequency ranges in conjunction with an asymmetric charge pump operation without the need for a crystal and frequency detector. The representative embodiment may include a phase detector that can generate one or more charge pump control signals based on a phase difference between an input signal and an output clock signal. The representative embodiment may also include a charge pump comprising a first current source configured to pull an oscillator control signal up toward a preset voltage; and a second current source configured to pull the oscillator control signal down toward a second preset voltage. The charge pump responds to the one or more charge pump control signals by pulling the oscillator control signal up or down toward the first preset voltage or the second preset voltage. The first current source may be configured to generate a first drive current, and the second current source may be configured to generate a second drive current different from the first drive current.

[0006] A representative embodiment may also include a voltage-controlled oscillator (VCO) configured to generate an output clock signal based on an oscillator control signal, and a lock-in detector configured to detect a lock-in state based on a comparison between the oscillator control signal and a VCO reference voltage. Furthermore, a representative embodiment may include a controller configured to selectively switch a first lock-in range of the VCO to a second lock-in range based on the aforementioned lock-in state, wherein the first lock-in range of the VCO corresponds to a first range frequency associated with the output clock signal, and wherein the second lock-in range of the VCO corresponds to a second range frequency associated with the output clock signal but different from the first range. In some embodiments, the first and second current sources may have an amplitude difference of at least 20% in their respective drive currents.

[0007] In some embodiments, the charge pump is configured such that the VCO scans available frequencies within the first lockout range by moving from a first preset voltage to a second preset voltage via an oscillator control signal before switching to the second lockout range. The second lockout range may be the one with a start frequency closest to the start frequency of the first lockout range. Furthermore, in some embodiments, the current source within the charge pump may be configured to give the charge pump a pull-down tendency, and the initial lockout range may be the one with the highest start frequency among all available lockout ranges. In this case, the lockout detector may be configured to detect whether the circuit is locked when the circuit is stable and whether the oscillator control signal is higher than the VCO reference voltage. Furthermore, the highest available voltage level in each lockout range may be a first preset voltage, and the VCO reference voltage may be half of the first preset voltage.

[0008] In some embodiments, the current source can be configured to give the charge pump a pull-up tendency. In this case, the initial lockout range can be the one with the lowest start frequency among all available lockout ranges. A lockout detector can then detect whether the circuit is locked when it is stable, and whether the oscillator control signal is below the VCO reference voltage. The lowest available level for each lockout range can be a second preset voltage, and the VCO reference voltage is half of the first preset voltage.

[0009] In some variations, the total available locking range can represent the overall operating frequency range of the circuit. Furthermore, in several examples, the VCO reference voltage can be half of a first preset voltage. Additionally, the VCO reference voltage is adjustable. For example, the VCO reference voltage can be adjusted when the difference between the oscillator control signal and the VCO reference voltage exceeds a threshold value.

[0010] In some variations, the lock-on detector may include a comparator. In various examples, the controller may be configured to begin a frequency scan by stabilizing the VCO's first lock-on range to an initial lock-on range and stabilizing the oscillator control signal to a first preset voltage. The controller may also be configured to set the oscillator control signal back to the first preset voltage when the VCO switches to a second lock-on range. Furthermore, after scanning all available lock-on ranges, the controller may reset the VCO to the initial lock-on range to begin a second round of frequency scanning.

[0011] In some embodiments, the controller may be configured to detect whether the circuit has reached stability based on a comparison between the frequency of the output clock signal and the frequency of the input signal. Furthermore, the controller may determine that the circuit has reached stability when the frequency of the output clock signal is substantially equal to the frequency of the input signal. Attached Figure Description

[0012] The present invention is described by way of one or more embodiments, but is not limited to those shown in the accompanying drawings, in which similar components are represented by the same reference numerals, and the drawings are not necessarily drawn to scale.

[0013] Figure 1 This is a block diagram of a representative clock data recovery (CDR) circuit with an asymmetric charge pump.

[0014] Figure 2 This is the control flowchart of a CDR circuit with pull-down tendency.

[0015] Figure 3 The diagram illustrates an example of scanning the frequency band in a CDR circuit with pull-down bias.

[0016] Figure 4 This is the control flowchart of a CDR circuit with pull-up tendency.

[0017] Figure 5 The diagram illustrates an example of scanning the frequency band in a CDR circuit with pull-up tendency.

[0018] Figure 6 The diagram illustrates another example of band scanning in a CDR circuit with an alternative pull-up bias configuration, where the VCO's transfer curve is inversely proportional to its input control voltage. Detailed Implementation

[0019] In data communication, such as sequential communication of digital data, clock data recovery is required when data transmission lacks a reference clock signal. If the receiver lacks a reference clock signal, its sampling of the data may be oversampling or undersampling, potentially leading to bit errors. Despite the problems of oversampling and / or undersampling, transmitting data without a reference clock signal remains necessary. One reason is the limited space (e.g., bandwidth) for carrying data in a signal. Due to space constraints, to transmit more data at a faster rate, it is essential to reduce unnecessary data transmitted on the signal. This unnecessary data can be overhead data, such as the reference clock signal. In other words, the transmitted signal should not be filled with overhead data, but rather should strive to carry as much necessary data as possible.

[0020] Therefore, Clock Data Recovery (CDR) technology has become increasingly important and is now an essential component in many devices. Clock recovery refers to the process of extracting timing information (such as a reference clock signal) from a data stream so that the receiving circuitry can decode the received data. Clock recovery is a commonly used technique in systems that communicate via wired, fiber optic, or wireless methods.

[0021] When data is transmitted but a corresponding reference clock is missing, the receiver circuitry can perform clock data recovery (CDR). For example, the receiver circuitry may include a phase-locked loop (PLL) circuit to help recover the reference clock. The PLL circuitry generates a clock by roughly estimating the frequency of the received data and aligning the phase of the data stream with the phase of the output data stream. Other CDR examples include using a delay-locked loop (DLL) and / or oversampling the data stream. A DLL is similar to a PLL, except that it does not include a voltage-controlled oscillator but rather a delay line. A DLL is primarily a delay chain consisting of many delay gates connected in an input-output manner. The inputs of the DLL are connected to an internal clock. Due to the chain of delay gates between the inputs and the internal clock, the internal clock experiences a negative delay.

[0022] Since most devices receive data through one or more communication systems (such as optical communication, Ethernet, or wireless), CDR circuitry is a critical component in many devices. For example, a laptop computer can use CDR circuitry to process data received via an Ethernet connection. A laptop computer can receive data used to play video, and this data can be streamed over an Ethernet connection. If the transmitted data lacks a reference signal, the laptop computer may oversample or undersample the data stream, potentially causing the video to be displayed incorrectly (e.g., missing frames or reduced resolution). To avoid these problems, the laptop computer uses CDR circuitry to roughly estimate the frequency and phase of the input signal from the Ethernet connection. The laptop computer can then sample the data stream at the correct rate, minimizing bit errors.

[0023] As mentioned above, traditional CDR technology includes a frequency detector. The frequency detector needs to sample the received signal at high speed to better approximate the frequency, thus requiring high-frequency operation. However, high frequencies increase power consumption and burden the circuitry. For example, in the aforementioned laptop computer example, laptop manufacturers may need to increase standby time by reducing power consumption. In other words, power consumption is a primary consideration for many devices that use rechargeable batteries.

[0024] Another problem is that frequency detectors increase the load on the circuitry. Since frequency detectors operate at high frequencies, the data they acquire must be stored, at least during the transition period, to determine the signal frequency. This data needs to be stored on local memory, such as a CDR (Printed Circuit Board) (PCB). However, space on a PCB is limited and therefore particularly valuable, making this heavy data consumption a burden that needs to be addressed.

[0025] Accordingly, the present invention relates to a CDR circuit that uses components such as a charge pump with an asymmetric current source to lock the frequency of a signal. In particular, in some embodiments, it is not necessary to use a frequency detector or a reference clock (e.g., a crystal oscillator) to implement the CDR function.

[0026] The following description uses an example of a CDR circuit to illustrate various techniques that can be implemented using an asymmetric charge pump, but this example is for illustrative purposes only. For instance, even though one or more figures relating to the invention are illustrated for a particular CDR circuit configuration, in other embodiments, the invention can be applied in a similar manner to other CDR circuits configured differently. In another example, even though the technique can be applied to a CDR circuit with an asymmetric charge pump, other electrical components can be added or removed to maintain functionality.

[0027] Numerous specific details are set forth below to fully illustrate the invention. In other embodiments, the introduced techniques may be implemented without these specific details. In other instances, well-known features, such as known circuit design and assembly techniques, are not described in detail here so as not to obscure the focus of the invention. When references to "an embodiment," "an example," or similar terms are used in this specification, they mean that the specific feature, structure, material, or characteristic described is included in at least one embodiment of the invention. Therefore, the use of such terms in this specification does not necessarily refer to the same embodiment. On the other hand, such references are not necessarily mutually exclusive. Furthermore, in one or more embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner. And it should be understood that the various embodiments depicted in the drawings are illustrative in nature and are not necessarily drawn to scale.

[0028] To maintain clarity in the following description, layouts or procedures known and typically associated with CDR circuit systems and corresponding electrical components may not be described in detail, so as not to obscure certain important aspects of the invention. Furthermore, while the following description presents several embodiments of different aspects of the invention, many other embodiments may have different configurations or components than those described herein. Accordingly, the technology of the invention may include additional components or omit several components described herein in other embodiments.

[0029] CDR Circuit Overview

[0030] Figure 1 This is a block diagram of a representative CDR circuit 100. This CDR circuit 100 includes a phase detector (PD) 102, a charge pump (CP) 104, a latch-up detector (LD) 106, a controller 108, a loop filter (LF) 110, and a voltage-controlled oscillator (VCO) 112, as well as other components and nodes. PD 102 compares the phase difference between the Sin and Sout signals and generates corresponding charge pump control signals UP and DN. The generated signals, in Figure 1 The inputs are designated as UP and DN, and are sent to CP104. Upon receiving the UP or DN input signal from PD102, CP104 uses pull-up current source I1 or pull-down current source I2 to raise or lower the voltage at the CP104 output (i.e., the voltage at node N1), respectively. Figure 1 (The symbol is Vctrl). This oscillator control signal Vctrl, in turn, controls VCO112. VCO112 is operable to generate output signals Sout at different frequencies depending on the voltage level of Vctrl.

[0031] In some embodiments, the output signal Sout is directly input to PD102. In other embodiments, a frequency divider can be added between the output of VCO112 and PD102, so that the frequency of the output signal Sout is N times the frequency of the input signal Sin.

[0032] Generally speaking, the function of a CP is to drive its output voltage (e.g., Figure 1 The voltage (Vctrl) in the circuit rises or falls. This rise and fall of the output voltage can be achieved by utilizing different current sources in the circuit breaker (CP). In one embodiment, the CP may include a current source connected to the positive terminal of the voltage source and another current source connected to the negative terminal of the voltage source. The current source connected to the positive terminal may be called the "positive current source," and the current source connected to the negative terminal may be called the "negative current source." Figure 1 Taking the CDR circuit 100 as an example, CP104 includes two current sources I1 and I2. Current sources I1 and I2 can be connected in series and are controlled by current source control switches 1 (SW1) and 2 (SW2) connected in series. Current source I1 can be a current source designed to supply positive current through SW1 to pull the Vctrl voltage up towards a first voltage (e.g., a voltage source supplying the CDD voltage), and current source I2 can be a current source designed to be connected to ground, thus supplying negative current through SW2 to pull the Vctrl voltage down towards a second voltage (e.g., ground or a voltage source supplying the VSS voltage).

[0033] In some embodiments, current sources I1 and I2 can supply a preset amount of current. For example, CP104 can be designed so that the current generated by current source I1 is greater than the current generated by current source I2. In this case, the Vctrl voltage will increase from its initial voltage value toward a first voltage. In some embodiments, current sources I1 and I2 are adjustable current sources. For example, the current generated by current source I1 or the current generated by current source I2 can be dynamically increased or decreased depending on the situation. This is particularly useful when, for example, the Vctrl voltage rises or falls too slowly. To address the speed problem, current source I1 or I2 can be adjusted to speed up the process. For example, to speed up the rise of the Vctrl voltage, current source I1 can be increased or current source I2 can be decreased. Thus, the Vctrl voltage level can be controlled by adjusting current sources I1 and I2. Alternatively, other configurations can be used. For example, current sources I1 and I2 can each include multiple current sources. For example, current source I1 can include multiple current sources in parallel to supply positive current. Current source I2 can also include multiple current sources in parallel. In some embodiments, additional current sources can be added to current sources I1 and / or I2 to change the current supplied to node N1. For example, an additional current source can be connected in parallel with current source I1 to increase the positive current supplied to node N1. Alternatively or supplementarily, other electrical components can be added to adjust the supplied current. For example, a resistor can be connected (e.g., in parallel) to current sources I1 and / or I2 to change the current flowing to node N1. In one or more embodiments, the current drawdowns of current sources I1 and I2 can be configured via one or more corresponding registers.

[0034] Regardless of the polarity of the current source, the CP may cause the corresponding voltage (e.g., Vctrl) to rise or fall due to built-in (e.g., natural) bias. The cause of this built-in bias could be, for example, variations in manufacturing processes. However, it is conventionally better to employ a symmetrical drive configuration between the two current sources, as this allows both sources to provide nearly equal current drive. Symmetrical designs provide symmetrical pull-up and pull-down performance, which is generally considered an advantage. It should be noted that the terms "symmetric," "symmetrical," "asymmetrical," and "asymmetric" used to describe the current source design selection in a charge pump refer to the drive force of the current source (which can be reflected in the amount of current drawn, e.g., in amperes). These terms do not refer to the physical size of the current source. For example, it is known that different PMOS and NMOS transistors may have different drive forces due to differences in electron and hole mobility, and often the pull-up and pull-down current sources are designed differently to achieve pull-up and pull-down drive forces as close to symmetry as possible.

[0035] However, the technique introduced in this invention deliberately designs the pull-up and pull-down forces of the CP to be asymmetrical, thus creating a pull-up or pull-down tendency. This deliberately designed tendency may cause Vctrl to rise or fall naturally. In various embodiments of this invention, this designed Vctrl pull-up or pull-down tendency, together with the controller system and the implementation techniques detailed below, allows the CDR circuit of this invention to scan a frequency range until locking occurs. For example, see... Figure 1 Current source I1 can be a positive current source (e.g., connected to the positive terminal of the voltage supply), and current source I2 can be a negative current source (e.g., connected to the negative terminal of the voltage supply). In a "pull-up bias" configuration, the driving force of current source I1 is designed to be greater than that of current source I2 (e.g., more than 20% or more, or any other suitable parameter), wherein the voltage level of Vctrl gradually increases during the locking process of CDR circuit 100. In an alternative configuration, namely a "pull-down bias," current source I2 can be designed to have a greater current driving force than current source I1 (e.g., more than 20% or more, or any other suitable parameter). In this alternative, the voltage level of Vctrl gradually decreases to ground.

[0036] In some embodiments, the current sources can be designed to control the rate at which the tendency to affect the corresponding voltage (e.g., Vctrl). For example, an asymmetry of 20%, greater, or less can be intentionally created between the two current sources I1 and I2. This asymmetry may cause the corresponding voltage (e.g., Vctrl) to rise or fall. Figure 1 In a pull-up bias, current source I1 can provide a positive current that is 20% or more greater than the negative current of current source I2. In a pull-down bias, current source I2 can provide a negative current that is 20% or more greater than the positive current of current source I1. In both cases, since the multiple current sources are intentionally designed to have different currents, the voltage Vctrl can be increased or decreased. Therefore, the CP of the present invention intentionally designs the two current sources to be asymmetrical, thus generating a pull-up or pull-down bias.

[0037] Another component coupled between Vctrl and node N1 is LD106. LD106 is typically designed to detect the lockout state of CDR circuit 100, for example, when the phase and frequency of Sout match (e.g., are the same, or within the same threshold) the phase and frequency of Sin. According to one or more embodiments described herein, LD106 may also determine whether the lockout state is suitable for VCO conditions based on a comparison between Vctrl and a preset VCO reference voltage (i.e., a threshold voltage). In some implementations, the threshold voltage is half the supply voltage. In some examples, LD106 may include a comparator circuit that compares the voltage of Vctrl with a preset threshold (or reference) voltage.

[0038] Controller 108 can control the locking procedure of CDR circuit 100, for example, by using Figures 2 to 5 The described technology. Although in Figure 1 In this design, controller 108 is depicted as part of LD 106, but controller 108 may actually be implemented within or outside LD 106, as it may be implemented as a discrete circuit or combined with other suitable circuitry. Furthermore, in implementing the various control functions of this invention, controller 108 may be coupled to one or more suitable circuits, such as LD 106 and VCO 112, and may directly or indirectly control the voltage level of Vctrl (detailed below). To avoid visual complexity, Figure 1 The signal lines of controller 108 are not shown in the diagram.

[0039] Specifically, according to the embodiment described, the controller 108 can monitor the locking state, determine whether the locking is within a suitable Vctrl range, switch the VCO 112 to different frequency locking ranges, and control the voltage of Vctrl during frequency band scanning (as shown in the reference). Figure 3 , Figure 5 and Figure 6 (as detailed above), and control the overall state (e.g., setting all the above parameters during the initialization of CDR circuit 100 and in reset condition).

[0040] The oscillation frequency output of the VCO112 depends on the voltage controlled by its input. Specifically, as... Figure 1 As shown, VCO112 receives the Vctrl input and generates an output clock signal based on Vctrl. This output clock signal is then fed back to PD102. According to this embodiment, VCO112 can also be controlled by controller 108 to control the operating frequency band of VCO112. For example, initially, LD106 can determine whether CDR circuit 100 has reached stability, which in some embodiments is considered stable when the frequency and phase of the Sout signal match the frequency and phase of the Sin signal. However, it should be noted that depending on the application in different fields, some embodiments of this CDR circuit may include a frequency divider, and in this case, the frequency of Sout may be a multiple (or fraction) of Sin. Furthermore, as an alternative, the CDR circuit can be considered stable when the frequency and / or phase of the Sout signal is similar to (e.g., within an acceptable range) that of the Sin signal.

[0041] Once the CDR circuit 100 reaches stability, the controller 108 can determine whether the voltage of Vctrl is within a desired range (e.g., depending on the configuration, greater than or less than a threshold voltage) to ensure relatively stable operation of VCO 112 (e.g., with high frequency variation tolerance). The desired voltage range may depend on whether the CDR circuit 100 operates in a pull-up or pull-down bias and may be related to the threshold voltage, as will be detailed below.

[0042] If controller 108 determines that the voltage is within the desired range, controller 108 can display a lock and signal VCO 112 not to change the frequency band. On the other hand, if controller 108 determines that the voltage is not within the desired range, controller 108 can reset Vctrl to its initial value (e.g., supply voltage or ground voltage) and signal VCO to switch to the next frequency band. Accordingly, controller 108 and VCO 112 can interact to continuously switch frequency bands until a lock occurs and Vctrl operation is within the desired range. If the last frequency band is reached, VCO 112 can inform controller 108 of this situation, and controller 108 will then reset Vctrl and signal VCO 112 to operate within the frequency of that initial frequency band. Through this series of events, VCO 112 can set the frequency of Sout within a certain frequency band of the available frequency range until CDR circuit 100 reaches stability and Vctrl is within the desired range.

[0043] For example, in a pull-up bias configuration, Vctrl can be increased and the VCO can scan all frequencies in the available band (e.g., one by one), as described above. Once the LD 106 detects that the CDR has reached stability, the controller 108 can determine whether Vctrl is within the desired range. In this example, assuming Vctrl is not within the desired range, the controller 108 can reset the voltage to, for example, ground and signal the VCO 112 to switch to the next highest frequency band. The controller 108 and VCO 112 interact in this manner until locking occurs within the desired range or until VCO 112 reaches the last frequency band. In a pull-up bias configuration, the last frequency band can be the highest frequency in the available range. If VCO 112 reaches the highest frequency band, the controller 108 can signal VCO 112 to reset to a frequency band at the bottom of the available range. LD106, controller 108 and VCO112 can interact in this way to determine whether the CDR circuit has reached stability (e.g., the frequency and phase of the Sout signal are the same as the Sin signal) and when the CDR reaches stability, the VCO control input Vctrl is within the desired range (thus constituting what the present invention calls "locking").

[0044] Finally, as Figure 1As shown, the CDR circuit 100 also includes LF110. It should be noted that while LF110 provides useful functionality, it is not an essential component for implementing the present invention. LF110 may include a filter circuit, such as a resistor connected in series with a capacitor, for filtering and stabilizing the Vctrl signal. Furthermore, Figure 1 The CDR circuit 100 shown uses analog circuitry to implement CP104, LF110, and VCO112. In some other embodiments, CP104, LF110, and VCO112 can be implemented using digital circuitry to make the CDR circuit 100 an all-digital CDR.

[0045] Pull-down tendency

[0046] The following instructions are for reference only. Figure 1 The CDR circuit 100.

[0047] Figure 2 This is a flowchart 200 of a CDR control method, designed to exhibit a deliberately designed pull-down tendency when the negative current is intentionally greater than the positive current (e.g., 20% or more). In other words, in this tendency, Vctrl is pulled down towards ground because I2 is intentionally made greater than the current source I1. In block 202, the CDR circuit 100 can set VCO 112 to operate in the highest frequency range and set Vctrl to the highest voltage (e.g., VDD). The entire frequency range may depend on the capabilities of the CDR circuit 100. For example, the entire frequency range may be divided into several segments covering a 4 GHz range. Each frequency range may include a portion of the entire frequency range, thus dividing a predetermined number of ranges. For example, there may be a total of 64 partially overlapping frequency ranges (bands), each covering 4 GHz and each frequency range covering 100 MHz. For example, the voltage Vctrl may vary between a minimum value corresponding to the ground voltage and a maximum value corresponding to the supply voltage. Therefore, according to this example, in block 202, the VCO can be set to operate in the highest frequency band of the 4GHz range, and the voltage can be set as the supply voltage.

[0048] In block 204, the CDR circuit 100 can wait for the CDR to stabilize. Here, stabilization means that the frequency of the output signal Sout is substantially close to (e.g., within a frequency threshold determined by LD106) the frequency of the input data signal Sin, and the phase of the output signal Sout is substantially close to (e.g., within a frequency threshold determined by LD106) the phase of the input data signal Sin. The frequency of the output signal Sout generated by VCO112 is controlled based on Vctrl. As mentioned above, Vctrl can be changed based on the tendency caused by the currents provided by current sources I1 and I2. Here, in the pull-down tendency, current source I2 is intentionally made to be greater than current source I1, so Vctrl is pulled down towards the ground. In this way, the frequency of the output signal Sout will decrease until the frequency stabilizes to be substantially close to the frequency of the input signal Sin.

[0049] After the frequency and phase of Sout stabilize, in block 206, LD106 can determine whether VCO112 is operating under the desired conditions. In some implementations, VCO112 is determined to be operating under the desired conditions when Vctrl is within the desired range. For example, the desired range during the pull-down tendency period may be, for instance, greater than a threshold voltage. Therefore, LD106 can compare the voltage of Vctrl with a preset threshold voltage (e.g., Vth). In some implementations, Vth may be a preset value, such as half of the supply voltage or another value. In another example, LD106 can compare the voltage of Vctrl with the preset threshold voltage to determine the voltage difference. In block 208, if the voltage difference is within an acceptable value, LD106 can determine that lockout has occurred.

[0050] However, if LD106 determines that VCO112 is not operating under the desired conditions, then in block 210, controller 108 can determine whether the current frequency band is the lowest frequency band in that range. For example, if Vctrl is less than Vth when CDR circuit 100 is stable, LD106 can determine that VCO is not operating under the desired conditions. Based on this result, controller 108 can determine whether VCO112 is operating in the last frequency band. Then, if there is another available frequency band, controller 108 sends a signal requesting VCO112 to switch to the next frequency band. On the other hand, if VCO112 is already operating in the last frequency band, controller 108 can reset CDR circuit 100 to the initial stage in block 202. If the current frequency band is not in the lowest frequency band, controller 108 can switch to the next lower frequency band and set Vctrl to the highest voltage (e.g., the supply voltage). After this stage, the program can return to block 204.

[0051] Figure 3 Explained in chart form Figure 2The process. Chart 300 depicts the relationship between frequency ranges in the pull-down trend. In Chart 300, the x-axis represents the voltage of Vctrl, and the y-axis represents the voltage-controlled oscillator (e.g., Figure 1 The frequency of VCO112 in [the context]. For example, regarding [the context of VCO112]... Figure 2 As described in the description of block 202, V0 is the starting voltage. V0 is set to the maximum voltage. Here, the maximum voltage is VDD (e.g., the supply voltage), but it can also be other voltages (e.g., a fraction of the supply voltage). Furthermore, the VCO frequency can be set to operate in the highest frequency band (band 1).

[0052] As Vctrl is pulled down toward ground, the voltage decreases. In some embodiments, the rate of voltage decrease can be directly related to the current difference between multiple current sources I1 and I2. Since CP can be intentionally designed to have at least a 20% difference between the two current sources, the rate of voltage decrease can be indirectly controlled by this at least 20% difference. For example, as described above and Figure 3 As shown, because the difference between multiple current sources is intentionally designed, rather than a random variation that could potentially disrupt the performance of the CDR circuit, the voltage can drop in a stable manner. For example, the CP can be designed with a 25% current draw difference between multiple current sources, but this built-in bias is typically smaller than the design deviation. Accordingly, the designed 25% difference, along with any built-in bias, allows Vctrl to generate a corresponding and stable pull-up or pull-down. It should be noted that the 20% difference is only one example, and the difference between two current sources may also be less than 20%.

[0053] As the voltage of Vctrl decreases, the output frequency Sout of the VCO also decreases within frequency band 1. Once the voltage drops to a minimum value (e.g., within frequency band 1), the controller (e.g., Figure 1 The controller 108 can reset Vctrl to VDD and send a signal requesting the VCO to operate at the frequency of the next frequency band (band 2). Similarly, as the voltage of Vctrl decreases, the frequency of the VCO will also decrease within band 2. In band 2, such as... Figure 3 As shown, the frequency is stable at V1.

[0054] However, at point V1, Vctrl is less than a preset threshold. In some embodiments, such as... Figure 3As shown, the preset threshold can be half of the supply voltage VDD. Since Vctrl is less than half of VDD, the controller resets Vctrl to VDD and signals the VCO to operate within frequency band 3. In frequency band 3, the frequency is stable at V2. At point V2, Vctrl is greater than half of VDD. Therefore, the LD can determine that locking has occurred. In some embodiments, if locking has not occurred, the controller can continue to reset Vctrl and signal the VCO to continue scanning each frequency band in that frequency range. Once the VCO reaches the lowest frequency band, the controller can reset to operate within the highest frequency band (e.g., frequency band 1). In this way, the controller and VCO can interact to perform a linear scan of each frequency band in that frequency range until locking occurs.

[0055] Furthermore, once the frequency enters the reset zone, it is unlikely to stabilize. This is because the frequency bands in the reset zone operate at frequencies lower than the input signal. Therefore, the frequency may not stabilize in these bands. However, in some embodiments, the controller can scan the remaining frequency bands before resetting to band 1. For example, in a pull-down bias design using 64 frequency bands, the controller can scan all 64 frequency bands until a lock occurs. If no lock occurs, the controller can reset to operate at band 1 and scan all 64 frequency bands.

[0056] Upward tendency

[0057] Figure 4 This is flowchart 400 of the CDR control flow during pull-up tendency. The following is about... Figure 4 The explanation should also refer to Figure 1 The CDR circuit 100. Furthermore, the techniques described below can also utilize the techniques of the present invention described above (e.g., the "pull-down tendency" section). For the sake of brevity, all techniques described above will not be repeated below; however, these techniques can be applied to pull-up tendency in a similar manner. Figure 400 depicts the control state in pull-up tendency when the positive current is intentionally designed to be greater than the negative current (e.g., at least 20% greater than the negative current). In this case, Vctrl will decrease due to the influx of positive current from current source I1. As current source I1 increases, the frequency from VCO and the frequency of the output signal (Sout) also increase.

[0058] Figure 4 In block 402, the controller signals the VCO to operate within the lowest frequency range and sets Vctrl to the lowest voltage. The controller does this because during pull-up bias, the VCO frequency, along with its control voltage Vctrl, increases over time. Therefore, to scan the entire available frequency range, the VCO starts at the lowest frequency band, and the controller sets Vctrl to the lowest voltage value. Block 404 is similar. Figure 2In block 204, the controller circuit waits for the CDR to stabilize (e.g., the frequency and phase of the Sout signal equals the Sin signal). In block 406, during pull-up bias, the controller checks whether the VCO is operating under the desired conditions (e.g., Vctrl is below the threshold voltage Vth). If Vctrl is below the threshold voltage, the LD can determine that latch-up has occurred. If not, the controller can determine whether the current frequency band is the highest frequency band. If it is the highest frequency band, the controller can reset to the condition in block 402. If it is not the highest frequency band, the controller can signal the VCO to switch to the next higher frequency band and set Vctrl to the lowest range.

[0059] Figure 5 A pull-up tendency diagram is depicted. In Figure 500, due to the pull-up tendency, the voltage of Vctrl and the frequency of VCO increase within each frequency band. Initially, the controller sets Vctrl to V0. In some embodiments, V0 corresponds to the ground voltage VSS. However, other usable minimum values ​​may be, for example, a fraction of the supply voltage VDD. The threshold voltage Vth may be set to half of the supply voltage VDD.

[0060] As more positive current is supplied, Vctrl increases, causing the VCO frequency to rise accordingly. Once the upper limit of band 1 is reached, the controller can signal the VCO to change conditions and operate in a higher frequency band (e.g., band 2) until the frequency stabilizes. Figure 5 Initially, the frequency stabilizes at V1. However, at V1, Vctrl is above the threshold voltage, which is half of the supply voltage VDD. In some cases, a higher frequency band may include a stable frequency and a Vctrl voltage that is below but close to the threshold voltage. Therefore, the controller switches to frequency band 3, where the frequency stabilizes at V2 because V2 is below the threshold voltage.

[0061] However, if stability is not achieved in a higher frequency band, the controller and VCO can interact to scan the remaining frequency band. When the Sout frequency reaches the last frequency band, the controller can send a signal requesting the VCO to reset and operate within frequency band 1. Figure 5 As shown, the reset zone can be any frequency band that operates at least partially above the input signal frequency. This is because once the frequency increases above the input signal frequency, the frequency cannot reach stability.

[0062] Frequency band linear scanning alternative

[0063] Figure 6 Figure 600 illustrates another example of how to scan the frequency band in a CDR circuit, which is a pull-up bias configuration. Unlike... Figure 5 The configuration, in Figure 6In this configuration, the VCO's transfer curve is inversely proportional to the voltage of its control input, Vctrl. In some embodiments, the minimum voltage of Vctrl may be the ground voltage VSS, or a fraction of the supply voltage VDD. Figure 6 In the process, due to the inverse relationship in the VCO transfer function, the controller interacts with the VCO to scan the frequency band, starting from the highest frequency range band 1 and the lowest voltage VSS.

[0064] In frequency band 1, the frequency is not stable, and therefore, the controller signals the VCO to switch to the next lower frequency band, frequency band 2. In frequency band 2, the frequency stabilizes at V1. However, V1 is not close to the threshold voltage, which is half of VDD. In some embodiments, when the difference is higher than an allowable threshold, the controller may signal the VCO to switch to the next frequency band even if the CDR circuit is stable. Figure 6 In this case, V1 is higher than the preset threshold, which is half of VDD, so VCO jumps to the next frequency band.

[0065] Depending on the implementation, the controller may be configured to perform different checks after frequency stabilization to determine whether to jump to the next frequency band or whether the VCO is already operating under desired conditions. For example, in one embodiment, it may check whether Vctrl is below a threshold voltage (e.g., Figure 4 (Block 406 in the diagram). In an alternative embodiment, the check item could be to confirm whether the difference between the stable voltage and the threshold voltage is lower than a preset threshold. If the check passes, the LD determines that locking has occurred. However, if the check fails, the VCO can jump to the next frequency band. For example, in... Figure 6 In the test, V1 failed because V1 is above the threshold voltage.

[0066] In band 3, the CDR circuit stabilizes at V2, where the controller can perform another check (e.g., block 406) to determine if the VCO is operating under the desired conditions. If the controller determines that the VCO is not operating under the desired conditions, it can jump to band 4 and continue checking the remaining bands. Upon reaching the last band, the controller can reset to band 1 and restart the program. However, if the CDR circuit stabilizes at V2, such as Figure 6 As shown, if V2 is within the desired threshold range (e.g., less than half of VDD / 2 in this case), the controller determines that the CDR circuit has been locked.

[0067] Linear scanning alternatives for frequency bands

[0068] While the above description primarily focuses on linearly scanning each frequency band until a lock is detected or the last band is reset and linear scanning resumes, other techniques can also be applied. Generally, the CDR circuit can apply any suitable search algorithm to determine if a lock has occurred. For example, frequency bands can be grouped. Grouping can be based on, for example, the amount of frequency overlap between bands or the proximity of the bands. For instance, the first two bands can be grouped together, the next two bands can be grouped into another group, and so on. In this case, the controller can hop to only one band in each group. If the LD detects near-locking in one of the bands in a group, the controller can hop to another band in the same group. By narrowing down the frequency band range where a lock may occur, the locking time can be shortened.

[0069] Another alternative to linear scanning is a target-based approach. For example, the controller can receive a possible range of input signal frequencies via a smart input, which is smaller than the entire available frequency range of the CDR circuit. The controller can configure the CDR circuit to initially operate within frequency bands that partially overlap with the input data signal frequency. For example, if a frequency range has 64 bands, but according to the smart input, only 5 bands overlap with the input signal frequency, the controller can scan only those 5 bands. In some embodiments, the controller can determine which bands overlap with the signal frequency based on the start and end frequencies of each band. For example, if the start frequency is higher than the input signal frequency and the end frequency is lower than the input signal frequency, the controller can determine that this band does not overlap with the input signal frequency.

[0070] Another alternative is to perform a partial linear scan of the frequency band until the starting frequency of the subsequent band is higher or lower than the frequency of the input signal. In a pull-up bias, if the starting frequency of the subsequent band is higher than the frequency of the input signal, the controller can reset to the starting band (e.g., band 1). In a pull-down bias, if the starting frequency of the subsequent band is lower than the frequency of the input signal, the controller can reset to the starting band again.

[0071] In some embodiments, the controller may not reset to the starting frequency band, but instead rescan the most recently scanned frequency band. In some embodiments, the controller may perform a second scan in reverse order instead of resetting to the initial frequency band. For example, if the LD determines that a proximity lock occurs in frequency bands 2 and 3, but not in frequency band 4, the controller may rescan in reverse order, starting with frequency band 3, and then proceeding to frequency band 2 as needed. In one or more embodiments, one or more corresponding buffers may be used to change the current drawout configuration of current sources I1 and I2, thereby changing the scanning direction (e.g., from front to back, or vice versa).

[0072] in conclusion

[0073] In summary, it should be understood that the specific embodiments of the present invention described herein are illustrative in nature and various modifications can be made without departing from the present invention. In representative embodiments, the CDR circuit may have a different configuration than that described and depicted herein, including other electrical layouts. The various components and circuits described herein may have other configurations in other embodiments that can also produce the characteristics required by the present invention (e.g., pull-up or pull-down).

[0074] The specific forms described in the specific embodiments of the present invention may be combined with or excluded from other embodiments. Furthermore, while advantages of specific embodiments are mentioned in the description of the embodiments of the present invention, other embodiments may also have the same advantages, and not all embodiments must have such advantages to be within the scope of the present invention. Accordingly, the present invention may include other embodiments not explicitly depicted or described herein. For example, although programs or blocks are presented in a specific order, alternative embodiments may execute conventional programs with different blocks, or employ systems with blocks in different orders, and some programs or blocks may be deleted, moved, added, subdivided, combined, and / or modified to provide alternatives or sub-combinations. Each program or block may be implemented in many different ways. And, although programs or blocks may appear to be executed sequentially, these programs or blocks may instead be executed simultaneously, or may be executed at different times. Furthermore, any specific figures explicitly stated herein are merely examples: different values ​​or ranges may be used in alternative embodiments.

[0075] The terms used in this specification generally have the meaning that falls within the technical field of this invention and that are usually understood in the context in which they are used. Specific terms used to describe the invention in the foregoing or other parts of this specification are intended to provide additional guidance to practitioners regarding the description of the invention. For ease of reading, specific terms may be emphasized, for example, by using italics and / or quotation marks. Whether emphasized or not does not affect the scope and meaning of the term; in the same context, the scope and meaning of a term are the same regardless of whether it is emphasized. It should be understood that the same thing can be stated in more than one way.

[0076] Therefore, any one or more terms used herein may have alternative languages ​​and synonyms, but whether a term is detailed or discussed herein does not imply that the term is of particular importance. Synonyms for certain terms are provided herein. The listing of one or more synonyms is not intended to exclude the use of other synonyms. The use of examples in this specification, including any examples of terms discussed herein, is illustrative in nature and not intended to further limit the scope and meaning of the invention or the exemplary terms. Similarly, the invention is limited to the embodiments provided in this specification.

[0077] The foregoing provides examples of instruments, apparatus, methods, and results according to embodiments of the present invention, but these are not intended to further limit the scope of the invention. It should be understood that the headings or subheadings used in the examples are for ease of reading and should not in any way constitute a limitation on the scope of the invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art. In case of any conflict, the definitions included herein shall prevail.

[0078] As can be seen from the above description, the specific embodiments of the present invention provided are illustrative in nature, and various modifications can be made without departing from the scope of the invention. Therefore, the scope of the invention should be limited only by the claims.

Claims

1. A clock data recovery (CDR) circuit, characterized in that, The circuit includes: A phase detector configured to generate one or more charge pump control signals based on a phase difference between an input signal and an output clock signal; A charge pump includes a first current source configured to pull an oscillator control signal toward a first preset voltage; and a second current source configured to pull the oscillator control signal toward a second preset voltage, wherein the charge pump pulls the oscillator control signal toward the first preset voltage or the second preset voltage based on the one or more charge pump control signals, and wherein the first current source is configured to generate a first drive current and the second current source is configured to generate a second drive current of a different magnitude than the first drive current; A voltage-controlled oscillator (VCO) is configured to generate the output clock signal based on the oscillator control signal; A lock detector, configured to determine a lock state based on a comparison between the oscillator control signal and a voltage-controlled oscillator reference voltage; and A controller is configured to selectively switch a first locking range of a voltage-controlled oscillator to a second locking range based on the locking state, wherein the first locking range of the voltage-controlled oscillator corresponds to a first range frequency associated with the output clock signal, and wherein the second locking range of the voltage-controlled oscillator corresponds to a second range frequency associated with the output clock signal and different from the first range.

2. The clock data recovery circuit according to claim 1, wherein, The charge pump is configured such that the voltage-controlled oscillator scans the available frequencies in the first lock-up range before switching to the second lock-up range by driving the oscillator control signal from the first preset voltage to the second preset voltage.

3. The clock data recovery circuit according to claim 2, wherein, The second locking range is the locking range whose start frequency is closest to that of the first locking range among all available locking ranges.

4. The clock data recovery circuit according to claim 1, wherein, The controller is configured to begin frequency scanning by setting the first locking range of the voltage-controlled oscillator to an initial locking range and setting the oscillator control signal to the first preset voltage.

5. The clock data recovery circuit according to claim 4, wherein, The controller is configured such that when the voltage-controlled oscillator switches to the second locking range, the oscillator control signal is set back to the first preset voltage.

6. The clock data recovery circuit according to claim 5, wherein, The controller is configured to reset the voltage-controlled oscillator back to the initial lock range after scanning all available lock ranges to begin a second frequency scan.

7. The clock data recovery circuit according to claim 1, wherein, The configuration of the multiple current sources gives the charge pump a pull-down tendency, wherein the initial locking range is the locking range with the highest start frequency among all available locking ranges.

8. The clock data recovery circuit according to claim 7, wherein, The lockout detector is configured to determine whether the circuit is locked when the circuit reaches stability and the oscillator control signal is higher than the reference voltage of the voltage-controlled oscillator.

9. The clock data recovery circuit according to claim 8, wherein, The highest available voltage level of each of the plurality of available locking ranges is the first preset voltage, and the voltage-controlled oscillator reference voltage is half of the first preset voltage.

10. The clock data recovery circuit according to claim 1, wherein, The multiple current sources are configured such that the charge pump has a pull-up tendency, and wherein an initial locking range is the locking range with the lowest start frequency among all available locking ranges.

11. The clock data recovery circuit according to claim 10, wherein, The lockout detector is configured to determine whether the circuit is locked when the circuit reaches stability and the oscillator control signal is lower than the reference voltage of the voltage-controlled oscillator.

12. The clock data recovery circuit according to claim 11, wherein, The lowest available level of each of the plurality of available locking ranges is the second preset voltage, and the voltage-controlled oscillator reference voltage is half of the first preset voltage.

13. The clock data recovery circuit according to claim 1, wherein, The controller is configured to determine whether the circuit has reached stability based on a comparison between the frequency of the output clock signal and the frequency of the input signal.

14. The clock data recovery circuit according to claim 1, wherein, All available lockout ranges together represent the overall operating frequency range of the circuit.

15. The clock data recovery circuit according to claim 1, wherein, The first and second current sources have an amplitude difference of at least 20% in their drive current.

16. The clock data recovery circuit according to claim 1, wherein, The circuit further includes: A single-loop filter is coupled to the oscillator control signal to filter the oscillator control signal.

17. The clock data recovery circuit according to claim 1, wherein, This circuit does not require a crystal to operate.

18. The clock data recovery circuit according to claim 1, wherein, This circuit does not require a frequency detector to operate.

19. The clock data recovery circuit according to claim 1, wherein, The reference voltage of the voltage-controlled oscillator can be adjusted, and the reference voltage of the voltage-controlled oscillator is adjusted when the difference between the oscillator control signal and the reference voltage of the voltage-controlled oscillator is greater than a threshold.

20. A method for operating a clock data recovery (CDR) circuit, characterized in that, Include: An input signal and an output clock signal are received by a phase detector; The phase detector generates one or more charge pump control signals based on the phase difference between the input signal and the output clock signal; An oscillator control signal is generated by a charge pump, wherein the charge pump includes (i) a first current source configured to pull the oscillator control signal toward a first preset voltage; (ii) a second current source configured to pull down the oscillator control signal toward a second preset voltage, wherein the charge pump pulls up or down the oscillator control signal toward the first preset voltage or the second preset voltage based on the one or more charge pump control signals, and wherein the first current source is configured to generate a first drive current, and the second current source is configured to generate a second drive current of a different magnitude than the first drive current; The output clock signal is generated by a voltage-controlled oscillator (VCO) based on the oscillator control signal; The lock-in detector determines the lock-in state by comparing the oscillator control signal with a voltage-controlled oscillator reference signal; as well as A controller provides one or more control devices based on the locked state to selectively switch a first locked range of the voltage-controlled oscillator to a second locked range, wherein the first locked range of the voltage-controlled oscillator corresponds to a first range frequency related to the output clock signal, and wherein the second locked range of the voltage-controlled oscillator corresponds to a second range frequency related to the output clock signal and different from the first range.

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