Improved single-phase phase-locked loop based on generalized second-order integration and notch filter

Abstract

An improved single-phase phase-locked loop based on generalized second-order integration and a notch filter, the phase-locked loop comprising a phase detector, a notch filter, a loop filter and a voltage-controlled oscillator, which are sequentially electrically connected in series, wherein an input end of the phase detector is connected to a grid voltage sampling signal, and the phase detector processes the grid voltage sampling signal to obtain an error voltage signal; the phase detector inputs the error voltage signal into the notch filter for processing, so as to obtain a voltage signal; the notch filter inputs the voltage signal into the loop filter for processing, so as to obtain a control voltage signal; the loop filter inputs the control voltage signal into the voltage-controlled oscillator to obtain a phase-locked loop output signal; and the voltage-controlled oscillator inputs the phase-locked loop output signal into the phase detector. The improved phase-locked loop provided in the present invention can effectively solve the problem of a large phase-locked error at a low sampling frequency, thereby improving the performance and stability of a system, and avoiding the problems of relatively large errors and insufficient accuracy of existing phase-locked loops.

Description

An improved single-phase phase-locked loop based on generalized second-order integrator and notch filter.

[0001] This application claims priority to Chinese Patent Application No. 202411685317.3, filed on November 22, 2024, entitled "An Improved Single-Phase Phase-Locked Loop Based on Generalized Second-Order Integrator and Notch Filter", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of single-phase phase-locked loop (PLL) technology, and in particular to an improved single-phase PLL based on a generalized second-order integral and a notch filter. Background Technology

[0003] With the increasing prominence of energy and environmental issues, more and more distributed renewable energy generation inverters are being connected to the grid. As a key interface connecting distributed generation units and the main power grid, grid-connected inverters play a crucial role in converting DC power generated by various renewable energy sources into high-quality AC power that can be fed into the public grid. For grid-connected inverters, grid synchronization methods are a vital component for control, protection, and monitoring. These methods can quickly and accurately obtain the frequency and phase of the grid voltage at the point of common coupling (PCC) and provide a reference for the incoming current. Among various grid synchronization methods, the phase-locked loop (PLL) has been widely used due to its relatively simple structure, fast synchronization speed, and high tracking accuracy.

[0004] Among existing phase-locked loop (PLL) technologies, the Synchronous Reference Frame PLL (SRF-PLL) based on the dq synchronous rotating coordinate system has been widely used in power grid systems due to its advantages such as fast dynamic response and ease of software implementation. Its characteristic is that the three-phase voltages are first subjected to Clark transformation to obtain u in the two-phase stationary coordinate system. α and u β After undergoing the Park transformation, the voltage u in the synchronous rotating coordinate system is obtained. d and u q , with u q =0 is the control target to achieve phase-locked loop (PLL) functionality. However, in single-phase grid-connected systems, since there is only one voltage phasor, direct coordinate system transformation is not possible, making synchronous coordinate system rotation difficult. To solve this problem, a common approach is to use an orthogonal signal generator to produce a voltage phasor with the same amplitude and orthogonality to the input voltage, thereby completing the coordinate system transformation.

[0005] Currently, there are various methods for generating orthogonal signals, such as the delay method, all-pass filter (APF), Hilbert transform method, differentiation method, and second-order generalized integrator (SOGI). Among them, the second-order generalized integrator is more suitable for constructing two-phase virtual orthogonal signals due to its simple structure, certain filtering performance, and higher accuracy, and is widely used in single-phase phase-locked loops.

[0006] Current phase-locked loops (PLLs) based on generalized second-order integrals (SOGI-PLLs) typically require high sampling frequencies to obtain perfectly orthogonal virtual signals between two phases. However, in practical engineering, sampling frequencies of tens of kHz are often difficult to achieve. At low sampling frequencies, existing PLLs suffer from large errors and insufficient accuracy, negatively impacting system performance and stability. Therefore, we propose an improved single-phase PLL based on generalized second-order integrals and a notch filter (SOGI-Notch) to address the problem of large PLL errors at low sampling frequencies. This innovative improvement is expected to significantly enhance and improve the application of traditional PLLs at low sampling frequencies, making a positive contribution to the technological development of related fields. Summary of the Invention

[0007] The present invention aims to at least overcome the technical problems of existing phase-locked loops having large errors and insufficient accuracy at low sampling frequencies, which negatively affect the performance and stability of the system.

[0008] Therefore, one object of the present invention is to propose an improved single-phase phase-locked loop based on a generalized second-order integral and a notch filter, comprising a phase detector, a notch filter, a loop filter and a voltage-controlled oscillator connected in series.

[0009] The input terminal of the phase detector is connected to the mains voltage sampling signal u. g (t), the phase detector processes the grid voltage sampling signal to obtain the error voltage signal u. i (t); The phase detector inputs the error voltage signal into the notch filter for processing to obtain the voltage signal u. d (t); The notch filter inputs the voltage signal into the loop filter for processing to obtain the control voltage signal u. c (t); The loop filter inputs the control voltage signal into the voltage-controlled oscillator to obtain the phase-locked loop output signal u. o (t); The voltage-controlled oscillator inputs the phase-locked loop output signal into the phase detector.

[0010] Furthermore, the phase detector includes a second-order generalized integrator and a Park transform module connected to the output of the second-order generalized integrator; the input grid voltage sampling signal is passed through the second-order generalized integrator to obtain a two-phase quadrature signal, and then the voltage in the dq synchronous rotating coordinate system is obtained through the Park transform module. The error voltage signal is generated through the voltage in the dq synchronous rotating coordinate system.

[0011] Furthermore, the expression for the transfer function of the second-order generalized integrator is as follows:

[0012] In the formula: D(s) is the transfer function of the bandpass filter; Q(s) is the transfer function of the lowpass filter; ω′ is the frequency estimate of the phase-locked loop; k is the filter gain coefficient; s is the complex frequency variable; u α and u β These are the components along the α and β axes of the stationary coordinate system, respectively; u g This refers to the grid voltage.

[0013] The formula for calculating the grid voltage is: u g =U m cosθ′;

[0014] In the formula, θ′ is the angle between the grid voltage sampling signal and the α axis of the stationary coordinate system; U m This represents the amplitude of the input voltage.

[0015] Furthermore, the calculation formula for the Park transformation module is as follows:

[0016] Where θ is the output phase of the voltage-controlled oscillator; u d and u q These are the components on the d-axis and q-axis of the dq synchronous rotating coordinate system, respectively.

[0017] Furthermore, the formulas for calculating the components on the α and β axes of the stationary coordinate system are: u α =U m cosθ′; u β =U m sinθ′;

[0018] The formula for calculating the components on the q-axis of the dq synchronous rotating coordinate system is: u q =U m sinθ′cosθ-U m cosθ′sinθ=U m sin(θ′-θ); sin(θ′-θ)≈θ′-θ.

[0019] Furthermore, the transfer function of the notch filter is:

[0020] In the formula: k1 is the first notch coefficient, k2 is the second notch coefficient; ω n Y is the notch bandwidth, in rad / s; X is the input signal; n is the output signal; n is an integer representing the time index of the sample; T is the notch bandwidth. s This indicates the time interval for sampling during the discretization process.

[0021] Furthermore, the loop filter is implemented using a PI controller, and the PI controller includes a proportional element k. p and the integral stage k i The transfer function of a PI controller can be expressed as:

[0022] In the formula, s is a complex frequency variable, and G is the transfer function of the PI controller.

[0023] Furthermore, the voltage-controlled oscillator includes an adder and an integrator electrically connected to the adder. The frequency estimate of the phase-locked loop is obtained through the adder, and the output phase of the voltage-controlled oscillator is obtained through the integrator.

[0024] This invention discloses an improved single-phase phase-locked loop based on a generalized second-order integral and a notch filter, which has the following advantages:

[0025] This invention employs a generalized second-order integrator and a three-parameter notch filter structure, comprising a phase detector, a notch filter, a loop filter, and a voltage-controlled oscillator connected in series. By incorporating the notch filter, the negative-sequence component generated by the second-order generalized integrator due to insufficient sampling frequency can be filtered out. The improved phase-locked loop provided by this invention can effectively solve the problem of large phase-locked loop errors at low sampling frequencies, improve system performance and stability, and avoid the problems of large errors and insufficient accuracy in existing phase-locked loops. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 is a schematic diagram of an improved single-phase phase-locked loop based on a generalized second-order integral and a notch filter according to the present invention.

[0028] Figure 2 is a structural diagram of an improved single-phase phase-locked loop based on a generalized second-order integral and a notch filter according to the present invention.

[0029] Figure 3 is a model diagram of the present invention based on a generalized second-order integral and a notch filter.

[0030] Figure 4(a) shows the phase-locked loop results of a traditional phase-locked loop at a sampling frequency of 2k.

[0031] Figure 4(b) shows the phase-locked loop results of the improved single-phase phase-locked loop at a sampling frequency of 2k.

[0032] Figure 5(a) shows the phase-locked loop results of a traditional phase-locked loop at a sampling frequency of 1k.

[0033] Figure 5(b) shows the phase-locked loop results of the improved single-phase phase-locked loop at a sampling frequency of 1k. Detailed Implementation

[0034] Various aspects and features of the present invention are described herein with reference to the accompanying drawings.

[0035] It should be understood that various modifications can be made to the embodiments described herein. Therefore, the above description should not be considered as limiting, but merely as an example of embodiments. Other modifications within the scope and spirit of the invention will be apparent to those skilled in the art.

[0036] The accompanying drawings, which are included in and form part of this specification, illustrate embodiments of the invention and, together with the general description of the invention given above and the detailed description of the embodiments given below, serve to explain the principles of the invention.

[0037] These and other features of the invention will become apparent from the following description of preferred forms of embodiments given as non-limiting examples, with reference to the accompanying drawings.

[0038] It should also be understood that although the invention has been described with reference to some specific examples, those skilled in the art can certainly implement many other equivalent forms of the invention, which have the features described in the claims and are therefore all within the scope of protection defined herein.

[0039] The above and other aspects, features and advantages of the invention will become more apparent when taken in conjunction with the accompanying drawings and in view of the following detailed description.

[0040] Specific embodiments of the invention are described below with reference to the accompanying drawings; however, it should be understood that the claimed embodiments are merely examples of the invention, which can be implemented in various ways. Well-known and / or repeated functions and structures are not described in detail to avoid unnecessary or redundant details that could obscure the invention. Therefore, the specific structural and functional details claimed herein are not intended to be limiting, but merely to serve as the basis and representative basis for the claims to teach those skilled in the art to use the invention in various ways with substantially any suitable detailed structure.

[0041] In the description of this invention, references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0042] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

[0043] Example

[0044] As shown in Figures 1, 2 and 3, this embodiment provides an improved single-phase phase-locked loop based on a generalized second-order integral and a notch filter, including a phase detector (PD), a notch filter (NF), a loop filter (LF) and a voltage-controlled oscillator (VCO) connected in series.

[0045] The input terminal of the phase detector is connected to the mains voltage sampling signal u. g (t), whose angular frequency is ω g The phase detector processes the grid voltage sampling signal to obtain the error voltage signal u. i (t); The phase detector inputs the error voltage signal into the notch filter for processing to obtain the voltage signal u. d (t); The notch filter inputs the voltage signal into the loop filter for processing to obtain the control voltage signal u. c (t); The loop filter inputs the control voltage signal into the voltage-controlled oscillator to obtain the phase-locked loop output signal u. o (t); The voltage-controlled oscillator inputs the phase-locked loop output signal into the phase detector.

[0046] As shown in Figure 2, according to another specific embodiment of the present invention, based on the above embodiment, the phase detector includes a second-order generalized integrator and a Park transform module connected to the output of the second-order generalized integrator; the input grid voltage sampling signal is passed through the second-order generalized integrator to obtain a two-phase quadrature signal, and then the voltage in the dq synchronous rotating coordinate system is obtained through the Park transform module. The error voltage signal is generated through the voltage in the dq synchronous rotating coordinate system.

[0047] According to another specific embodiment of the present invention, based on the above embodiment, the expression of the transfer function of the second-order generalized integrator is as follows:

[0048] In the formula: D(s) is the transfer function of the bandpass filter; Q(s) is the transfer function of the lowpass filter; ω′ is the frequency estimate of the phase-locked loop; k is the filter gain coefficient; s is the complex frequency variable; u α and u β These are the components along the α and β axes of the stationary coordinate system, respectively; u g This refers to the grid voltage.

[0049] Specifically, the larger the value of k, the larger the bandwidth and the faster the system response. For harmonic signals in the input signal, the amplitude-frequency characteristics of the system show that the second-order generalized integrator (SOGI) has a good filtering capability for higher harmonics, while also reducing the interference of lower harmonics. When the value of k is larger, the filter's ability to suppress lower harmonics weakens. Therefore, the selection of the k value should consider both filtering effect and response time. Generally speaking, a k value of [value missing] is chosen.

[0050] The formula for calculating the grid voltage is: u g =U m cosθ′;

[0051] In the formula, θ′ is the angle between the grid voltage sampling signal and the α axis of the stationary coordinate system; U m This represents the amplitude of the input voltage.

[0052] According to another specific embodiment of the present invention, based on the above embodiments, the calculation formula of the Park transformation module is as follows:

[0053] Where θ is the output phase of the voltage-controlled oscillator; u d and u q These are the components on the d-axis and q-axis of the dq synchronous rotating coordinate system, respectively.

[0054] According to another specific embodiment of the present invention, based on the above embodiment, the calculation formulas for the components on the α-axis and β-axis of the stationary coordinate system are as follows: u α =U m cosθ′; u β =U m sinθ′;

[0055] The formula for calculating the components on the q-axis of the dq synchronous rotating coordinate system is: u q =U m sinθ′cosθ-U m cosθ′sinθ=U m sin(θ′-θ);

[0056] When the phase-locked loop is in the locked state, the error between the phase θ′ of the actual grid voltage and the output phase θ of the voltage-controlled oscillator is small, and can be approximated as: sin(θ′-θ)≈θ′-θ;

[0057] This enables the phase detector function.

[0058] Since a second-order generalized integrator (SOGI) is a nonlinear, adaptive filter that integrates and differentiates the input signal, insufficient sampling frequency can lead to performance degradation and the appearance of large negative-sequence components. This invention adds a three-parameter notch filter to the traditional phase-locked loop (PLL) to filter out the negative-sequence components generated by the SOGI due to insufficient sampling frequency.

[0059] The transfer function of the notch filter is:

[0060] The transfer function of the three-parameter notch filter is:

[0061] In the formula: k1 is the first notch coefficient, k2 is the second notch coefficient; ω n The bandwidth is the notch filter bandwidth, measured in rad / s, and is twice the output frequency of the voltage-controlled oscillator.

[0062] To discretize the above equation, a bilinear transformation is used, and the integral is approximated using the trapezoidal rule, resulting in:

[0063] Substituting equation (2) into equation (1), we get

[0064] Equation (3) can be obtained by replacing characters.

[0065] in,

[0066] By utilizing the signal lag characteristic of the z-transform, equation (4) can be transformed to obtain: a1Y(z) + a2z -1 Y(z)+a3z -2 Y(z)=b1X(z)+b2z -1 X(z)+b3z -2 X(z) (6) a1Y(z)+a2Y(z-1)+a3Y(z-2)=b1X(z)+b2X(z-1)+b3X(z-2) (7)

[0067] The discrete form of the three-parameter notch filter transfer function is finally obtained as follows:

[0068] In the formula: Y is the input signal; X is the output signal; n is an integer representing the time index of the sample; T s This indicates the time interval for sampling during the discretization process.

[0069] According to another specific embodiment of the present invention, based on the above embodiments, the loop filter is implemented using a PI controller, and the PI controller includes a proportional element k. p and the integral stage k i Essentially, it is a lead-lag filter. The proportional element primarily amplifies the amplitude of the input error signal linearly, outputting a control signal proportional to the input. The integral element gradually synchronizes the control system output with the input signal until a steady state is reached. The transfer function of the PI controller can be expressed as:

[0070] In the formula, s is a complex frequency variable, and G is the transfer function of the PI controller.

[0071] According to another specific embodiment of the present invention, based on the above embodiments, the voltage-controlled oscillator includes an adder and an integrator electrically connected to the adder. In the phase-locked loop, in order to accelerate the dynamic response time of the phase-locked loop, ω n The value is set to the rated frequency of the power grid. The frequency estimate of the phase-locked loop is obtained through an adder, and the output phase of the voltage-controlled oscillator is obtained through an integrator.

[0072] As shown in Figures 4 and 5, in order to test the phase-locked loop accuracy of the improved single-phase phase-locked loop and the traditional phase-locked loop at low sampling frequencies, this embodiment built the improved single-phase phase-locked loop and the traditional phase-locked loop models in MATLAB / Simulink, and tested the two phase-locked loops at different sampling frequencies.

[0073] The grid frequency is set to 50Hz. Figure 4(a) and (b) show the phase-locked loop results of the traditional phase-locked loop and the improved single-phase phase-locked loop at a sampling frequency of 2k, respectively. Figure 5(a) and (b) show the phase-locked loop results of the traditional phase-locked loop and the improved single-phase phase-locked loop at a sampling frequency of 1k, respectively.

[0074] The test results show that as the sampling frequency decreases, the phase-locked loop (PLL) error increases significantly, reaching ±0.7Hz at a sampling frequency of 1kHz. In contrast, the improved single-phase PLL maintains high phase-locked accuracy even at lower sampling frequencies.

[0075] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

[0076] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0077] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

[0078] The foregoing has provided a detailed description of several embodiments of this disclosure. However, this disclosure is not limited to these specific embodiments. Those skilled in the art can make various variations and modifications based on the concept of this disclosure, and all such variations and modifications should fall within the scope of protection claimed by this disclosure.

Claims

1. An improved single phase phase locked loop based on generalized second order integration and notch filter, characterized by, It includes a phase detector, a notch filter, a loop filter, and a voltage-controlled oscillator connected in series. The input end of the phase discriminator is connected with a grid voltage sampling signal u g (t), the phase discriminator processes the grid voltage sampling signal to obtain an error voltage signal u i (t); the phase discriminator inputs the error voltage signal into the notch filter to process to obtain a voltage signal u d (t); the notch filter inputs the voltage signal into the loop filter to process to obtain a control voltage signal u c (t); the loop filter inputs the control voltage signal into the voltage-controlled oscillator to obtain a phase-locked loop output signal u o (t); the voltage-controlled oscillator inputs the phase-locked loop output signal into the phase discriminator.

2. The improved single phase phase locked loop based on generalized 2nd order integrator and notch filter as claimed in claim 1 wherein, The phase detector includes a second-order generalized integrator and a Park transform module connected to the output of the second-order generalized integrator. The input grid voltage sampling signal is passed through the second-order generalized integrator to obtain a two-phase quadrature signal, which is then passed through the Park transform module to obtain the voltage in the dq synchronous rotating coordinate system. The error voltage signal is generated by the voltage in the dq synchronous rotating coordinate system.

3. The improved single phase phase locked loop based on generalized 2nd order integrator and notch filter as claimed in claim 2, wherein, The expression of the transfer function of the second-order generalized integrator is as follows: where: D(s) is the pass-band filter transfer function; Q(s) is the low-pass filter transfer function; ω' is the frequency estimate of the phase-locked loop; k is the filter gain coefficient; s is the complex frequency variable; u α and u β are the components on the stationary coordinate system α and β axes, respectively; u g is the grid voltage; The formula for calculating the grid voltage is as follows: u g = U m cos θ' In the formula, θ' is the angle between the grid voltage sampling signal and the α axis of the stationary coordinate system; U m is the amplitude of the input voltage.

4. The improved single phase phase locked loop based on generalized 2nd order integrator and notch filter as claimed in claim 3 wherein, The calculation formula of the Park transformation module is as follows: where θ is the phase of the voltage-controlled oscillator output; u d and u q are the components on the d-axis and q-axis of the d-q synchronous rotating coordinate system, respectively.

5. The improved single phase phase locked loop based on generalized 2nd order integrator and notch filter as claimed in claim 4 wherein, The calculation formula of the components on the α axis and the β axis of the stationary coordinate system is: u α = U m cos θ'; u β = U m sin θ'; The formula for calculating the components on the q-axis of the dq synchronous rotating coordinate system is: u q = U m sin θ' cos θ - U m cos θ' sin θ = U m sin (θ' - θ); sin(θ′-θ)≈θ′-θ.

6. The improved single phase phase locked loop based on generalized 2nd order integrator and notch filter as claimed in claim 1 wherein, The transfer function of the notch filter is: wherein: k1 is a first notch coefficient, k2 is a second notch coefficient; ω n is the notch bandwidth, in rad / s; Y is the input signal; X is the output signal; n is an integer representing the time index of the sample; T s denotes the time interval at which the samples are taken during the discretization process.

7. The improved single phase phase locked loop based on generalized 2nd order integrator and notch filter as claimed in claim 1 wherein, The loop filter includes a PI controller implementation, the PI controller including a proportional term k p and an integral term k i The transfer function of the PI controller can be represented as: In the formula, s is a complex frequency variable, and G is the transfer function of the PI controller.

8. The improved single phase phase locked loop based on generalized 2nd order integrator and notch filter as claimed in claim 1 wherein, The voltage-controlled oscillator includes an adder and an integrator electrically connected to the adder. The frequency estimate of the phase-locked loop is obtained through the adder, and the output phase of the voltage-controlled oscillator is obtained through the integrator.

Images