A phase detector and programmable logic device
By combining the comparison module and the multi-channel signal generation module, and utilizing multiple square wave signals of different phases with the counting and accumulation module, the problems of large size and high cost of phase detection circuits are solved, and high-precision phase detection effect is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- GUANGDONG DAPU TELECOM TECH CO LTD
- Filing Date
- 2026-02-27
- Publication Date
- 2026-06-05
Smart Images
Figure CN122159864A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of phase detection technology, and more particularly to a phase detection device and a programmable logic device. Background Technology
[0002] Time error measurement (also known as phase detection) is one of the key technologies in the field of clock synchronization. Clock synchronization technology is widely used in mobile communication networks, Internet time servers, and for synchronizing base stations, routers, switches, avionics, and other fields. Precise time synchronization and accurate data transmission are crucial for equipment operation. Clock signals are used to synchronize the operation of various components in the entire system, ensuring that each component works according to the correct time sequence, thereby guaranteeing the accuracy and stability of data transmission, processing, and control.
[0003] Currently, commonly used time error measurement techniques typically require dedicated TDC (Time-to-Digital Converter) chips for measurement. Dedicated TDC chips can achieve picosecond-level measurement accuracy, but they require additional chips and peripheral circuits, making them unsuitable for integration into miniaturized clock products and increasing costs, thus they are not an ideal choice. Summary of the Invention
[0004] This invention provides a phase detection device and a programmable logic device to solve the problems of large size and high cost of phase detection circuits.
[0005] According to one aspect of the present invention, a phase detection device is provided, comprising: The comparator module receives the test clock signal and the reference signal, and outputs a start-clear signal. The system includes a multi-channel signal generation module and a counting and accumulating module. The multi-channel signal generation module is used to start or stop according to the start-reset signal, and outputs at least four square wave signals with different phases and the same frequency to the counting and accumulating module when starting. The counting and accumulating module is used to calculate the total number of rising and falling edges of each of the square wave signals. The phase detection module is used to generate a phase detection value between the test clock signal and the reference signal based on the total number of times and the frequency and phase of each of the square wave signals.
[0006] Optionally, the comparison module includes: an XOR gate and an AND gate; The first input terminal of the XOR gate is used to receive the reference signal, and the second input terminal of the XOR gate is used to receive the test clock signal; the output terminal of the XOR gate is connected to the first input terminal of the AND gate. The second input terminal of the AND gate is used to receive the test clock signal, and the output terminal of the AND gate is connected to the multi-channel signal generation module.
[0007] Optionally, the multi-channel signal generation module includes: a first signal generation unit, a second signal generation unit, a third signal generation unit, and a fourth signal generation unit, all of which are connected to the counting and accumulating module; The first signal generation unit is used to generate and output a 0° phase-shifted square wave signal, the second signal generation unit is used to generate and output a 45° phase-shifted square wave signal, the third signal generation unit is used to generate and output a 90° phase-shifted square wave signal, and the fourth signal generation unit is used to generate and output a 135° phase-shifted square wave signal.
[0008] Optionally, the counting and accumulating module includes: a counting unit and an accumulating unit; The counting unit is connected to the multi-channel signal generation module and is used to count the number of rising and falling edges of each square wave signal. The accumulator unit is connected to the counter unit and is used to calculate the total number of times the counter unit counts.
[0009] Optionally, the counting unit includes: a first counter, a second counter, a third counter, and a fourth counter; The first counter is connected to the first signal generation unit and is used to count the number of rising and falling edges of the 0° phase-shifted square wave signal; The second counter is connected to the second signal generation unit and is used to count the number of rising and falling edges of the 45° phase-shifted square wave signal; The third counter is connected to the third signal generation unit and is used to count the number of rising and falling edges of the 90° phase-shifted square wave signal. The fourth counter is connected to the fourth signal generation unit and is used to count the number of rising and falling edges of the 135° phase-shifted square wave signal.
[0010] Optionally, the accumulation unit includes: a first accumulator; The first counter, the second counter, the third counter, and the fourth counter are all connected to the first accumulator, which is used to calculate the total number of counts by the first counter, the second counter, the third counter, and the fourth counter.
[0011] Optionally, the accumulation unit includes: a second accumulator, a third accumulator, and a fourth accumulator; both the first counter and the second counter are connected to the second accumulator, and the second accumulator is used to calculate the total number of counts by the first counter and the second counter; The third counter and the fourth counter are both connected to the third accumulator, and the third accumulator is used to calculate the total number of counts by the third counter and the fourth counter; The second accumulator and the third accumulator are both connected to the fourth accumulator, which is used to calculate the total number of calculations performed by the second accumulator and the third accumulator.
[0012] Optionally, the phase detection device further includes a display module connected to the phase detection module for displaying the phase detection value.
[0013] Optionally, the frequency of each of the square wave signals is 200MHz.
[0014] According to another aspect of the present invention, a programmable logic device is provided, comprising: the phase detection device described in any embodiment of the present invention.
[0015] The technical solution provided in this invention controls whether the phase detector starts phase detection by setting a start-reset signal output by the comparison module. Furthermore, this application eliminates the need for a single ultra-high frequency square wave signal for high-precision phase detection; instead, it utilizes multiple square wave signals with different phases, working in conjunction with a counting and accumulating module to achieve high-precision phase detection. The multi-channel signal generation module does not need to output ultra-high frequency square wave signals, reducing its design complexity and eliminating the need for a dedicated TDC chip, resulting in a smaller size and better phase detection performance.
[0016] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 This is a schematic diagram of a phase detection device according to an embodiment of the present invention; Figure 2 This is a schematic diagram of another phase detection device provided according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of another phase detection device provided according to an embodiment of the present invention; Figure 4 This is a waveform diagram of a phase detection device provided according to an embodiment of the present invention; Figure 5 This is a waveform diagram of a phase detection value provided according to an embodiment of the present invention. Detailed Implementation
[0019] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.
[0020] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0021] This invention provides a phase detection device. Figure 1 This is a schematic diagram of a phase detection device provided in an embodiment of the present invention. (Reference) Figure 1 The phase detection device includes: a comparison module 1, a multi-channel signal generation module 2, a counting and accumulating module 3, and a phase detection module 4. The comparison module 1 receives the test clock signal and a reference signal, and outputs a start / reset signal. The multi-channel signal generation module 2 starts or stops according to the start / reset signal, and outputs at least four square wave signals with different phases and the same frequency to the counting and accumulating module 3 during startup; the counting and accumulating module 3 calculates the total number of rising and falling edges of each square wave signal. The phase detection module 4 generates a phase detection value between the test clock signal and the reference signal based on the total number of edges and the frequency and phase of each square wave signal.
[0022] The phase detection device provided by this invention is used to detect the phase difference between a test clock signal and a reference signal. The test clock signal is the signal under test, and the reference signal is a standard signal. Both the test clock signal and the reference signal can be square wave signals. Therefore, the phase difference between the two signals can be obtained by detecting the time difference between two adjacent rising edges of the test clock signal and the reference signal. This phase difference is the phase detection value.
[0023] When the phase detector is running, the detection test clock signal and the reference signal are simultaneously transmitted to the comparison module 1. For example, when both the detection test clock signal and the reference signal are low, the reset signal can be low, and the multiplexer module 2 does not output a square wave signal. When the detection test clock signal flips to high and the reference signal is low, the reset signal flips to high, and the multiplexer module 2 outputs a square wave signal with a frequency lower than the reference signal. When both the detection test clock signal and the reference signal are high, the reset signal flips to low, and the multiplexer module 2 stops outputting the square wave signal.
[0024] Optionally, the frequency of each square wave signal is 200MHz.
[0025] When the multi-channel signal generation module 2 outputs four square wave signals with a 45° phase shift, the rising and falling edges of the four square wave signals can divide the cycle into eight equal parts within one period. The time of one part is 1 / 200MHz / 8 = 625 picoseconds, which means that the highest phase detection accuracy of the present invention is at the picosecond level.
[0026] When the counting and accumulating module 3 receives each square wave signal, it triggers counting based on the rising and falling edges of each square wave signal and calculates the total number of counts. Since the time between two trigger counts is fixed, the phase detection value between the test clock signal and the reference signal can be generated by multiplying the total number of counts by the time between the two trigger counts.
[0027] For example, when the time between two trigger counts is 625 picoseconds, and the total number of rising and falling edges of each square wave signal between the test clock signal and the reference signal is 2, then the phase detection value is 625 picoseconds × 2 times = 1250 picoseconds. When the test clock signal and the reference signal are transmitted to the comparison module 1 simultaneously, if the test clock signal flips to a high level first, it indicates that the test clock signal leads the reference signal by 1250 picoseconds; if the reference signal flips to a high level first, it indicates that the test clock signal lags the reference signal by 1250 picoseconds.
[0028] Compared to existing technologies that use a single square wave signal to count and measure the time error between two pulses, achieving a phase detection accuracy of 1 nanosecond requires a phase detection frequency of 1000MHz, which is difficult to achieve with conventional multi-channel signal generation modules. High-frequency signals also cause frequency interference and increase power consumption in the system, making them unsuitable for widespread application.
[0029] The technical solution provided in this invention controls whether the phase detector starts phase detection by setting a start-reset signal output by the comparison module. Furthermore, this application eliminates the need for a single ultra-high frequency square wave signal for high-precision phase detection; instead, it utilizes multiple square wave signals with different phases, working in conjunction with a counting and accumulating module to achieve high-precision phase detection. The multi-channel signal generation module does not need to output ultra-high frequency square wave signals, reducing its design complexity and eliminating the need for a dedicated TDC chip, resulting in a smaller size and better phase detection performance.
[0030] Figure 2 This is a schematic diagram of another phase detection device provided in an embodiment of the present invention. (Reference) Figure 2 Based on the above embodiments, optionally, the comparison module 1 includes: an XOR gate 11 and an AND gate 12. The first input terminal of the XOR gate 11 is used to receive a reference signal, and the second input terminal of the XOR gate 11 is used to receive a test clock signal; the output terminal of the XOR gate 11 is connected to the first input terminal of the AND gate 12. The second input terminal of the AND gate 12 is used to receive the test clock signal, and the output terminal of the AND gate 12 is connected to the multiplexed signal generation module 2.
[0031] When both the detection test clock signal and the reference signal are low, the XOR gate 11 outputs a low level, the AND gate 12 outputs a low-level start-up reset signal, and the multi-channel signal generation module 2 does not output a square wave signal.
[0032] When the detection clock signal is high and the reference signal is low, the XOR gate 11 outputs a high level, the AND gate 12 outputs a high-level start-up and reset signal, and the multi-channel signal generation module 2 outputs a square wave signal.
[0033] When the detection clock signal is low and the reference signal is high, the XOR gate 11 outputs a high level, and the AND gate 12 outputs a low-level start-up and reset signal. The multi-channel signal generation module 2 does not output a square wave signal.
[0034] When both the test clock signal and the reference signal are high, the XOR gate 11 outputs a low level, and the AND gate 12 outputs a low-level start-up reset signal. The multi-channel signal generation module 2 does not output a square wave signal.
[0035] For example, when the output of AND gate 12 is inverted from high level to low level, it indicates that the phase detector has completed one phase detection. At this time, the counting and accumulating module 3 clears the internally stored value to ensure the accuracy of the next phase detection.
[0036] Figure 3 This is a schematic diagram of another phase detection device provided in an embodiment of the present invention. (Reference) Figure 3Based on the above embodiments, optionally, the multi-channel signal generation module 3 includes: a first signal generation unit 21, a second signal generation unit 22, a third signal generation unit 23, and a fourth signal generation unit 24, all connected to the counting and accumulating module 3. The first signal generation unit 21 is used to generate and output a 0° phase-shifted square wave signal, the second signal generation unit 22 is used to generate and output a 45° phase-shifted square wave signal, the third signal generation unit 23 is used to generate and output a 90° phase-shifted square wave signal, and the fourth signal generation unit 24 is used to generate and output a 135° phase-shifted square wave signal.
[0037] Each square wave signal can be output to the first signal generation unit 21, the second signal generation unit 22, the third signal generation unit 23, and the fourth signal generation unit 24 through a phase-locked loop (PLL) in a complex programmable logic device (CPLD) or a field-programmable gate array (FPGA). CPLDs and FPGAs can also be collectively referred to as programmable logic devices. Each signal generation unit can be configured as a chip and connected to the comparator module 1 via pins R1 and R2. It also receives the square wave signal output from the PLL through a signal receiving terminal. For example, when the square wave signal is high, pins Q4, Q5, Q6, and Q7 transmit the square wave signal; when the square wave signal is low, pins Q0, Q1, Q2, and Q3 transmit the square wave signal.
[0038] Figure 4 This is a waveform diagram of a phase detection device provided in an embodiment of the present invention. (In conjunction with...) Figure 3 and Figure 4 Based on the above embodiments, optionally, the counting and accumulating module 3 includes a counting unit 31 and an accumulating unit 32. The counting unit 31 is connected to the multi-channel signal generation module 2 and is used to count the number of rising and falling edges of each square wave signal. The accumulating unit 32 is connected to the counting unit 31 and is used to calculate the total number of counts by the counting unit 31.
[0039] in, Figure 4A waveform diagram of a phase detection device is illustrated exemplarily. When the test clock signal reverses from low to high, the counting unit 31 starts counting and stops counting when the reference signal reverses from low to high. During the counting time, the rising and falling edges of the 0° phase-shifted square wave signal occur 3 times, the rising and falling edges of the 45° phase-shifted square wave signal occur 3 times, the rising and falling edges of the 90° phase-shifted square wave signal occur 3 times, and the rising and falling edges of the 135° phase-shifted square wave signal occur 2 times. The accumulation unit 32 receives and accumulates the counts from the counting unit 31, obtaining a total count of 11. By multiplying this total count by the time between two counts, the phase detection value between the test clock signal and the reference signal can be obtained.
[0040] The phase detection device provided in this embodiment of the invention utilizes a phase-locked loop (PLL) within a programmable logic device to output four square wave signals, logically dividing one clock cycle into eight equal parts. Furthermore, by employing a counting unit to count the rising and falling edges of each square wave signal, the counting accuracy is improved by eight times compared to counting only the rising edge of a single signal. When the frequency of the square wave signal is 200MHz, the phase detection accuracy can reach the picosecond level, exhibiting high precision.
[0041] Continue to combine Figure 3 and Figure 4 Based on the above embodiments, optionally, the counting unit 31 includes: a first counter 311, a second counter 312, a third counter 313, and a fourth counter 314. The first counter 311 is connected to the first signal generation unit 21 and is used to count the number of rising and falling edges of the 0° phase-shifted square wave signal. The second counter 312 is connected to the second signal generation unit 22 and is used to count the number of rising and falling edges of the 45° phase-shifted square wave signal. The third counter 313 is connected to the third signal generation unit 23 and is used to count the number of rising and falling edges of the 90° phase-shifted square wave signal. The fourth counter 314 is connected to the fourth signal generation unit 24 and is used to count the number of rising and falling edges of the 135° phase-shifted square wave signal.
[0042] The first counter 311, the second counter 312, the third counter 313, and the fourth counter 314 can be the same chip. The pin A3 of each counter is connected to the pin Q7 of the corresponding signal generation unit, the pin A2 of each counter is connected to the pin Q6 of the corresponding signal generation unit, the pin A1 of each counter is connected to the pin Q5 of the corresponding signal generation unit, and the pin A0 of each counter is connected to the pin Q4 of the corresponding signal generation unit.
[0043] For example, pins A3, A2, A1, and A0 can be used to receive a high-level square wave signal and count the rising edges using a counter.
[0044] Pin B3 of each counter is connected to pin Q3 of the corresponding signal generation unit, pin B2 of each counter is connected to pin Q2 of the corresponding signal generation unit, pin B1 of each counter is connected to pin Q1 of the corresponding signal generation unit, and pin B0 of each counter is connected to pin Q0 of the corresponding signal generation unit.
[0045] For example, pins B3, B2, B1, and B0 can be used to receive a low-level square wave signal and count the falling edges using a counter.
[0046] refer to Figure 4 The first counter 311 counts 3 times, the second counter 312 counts 3 times, the third counter 313 counts 3 times, and the fourth counter 314 counts 2 times.
[0047] Continue to refer to Figure 3 Based on the above embodiments, optionally, the accumulation unit 32 includes: a second accumulator 322, a third accumulator 323, and a fourth accumulator 324; the first counter 311 and the second counter 312 are both connected to the second accumulator 322, and the second accumulator 322 is used to calculate the total number of counts by the first counter 311 and the second counter 312. The third counter 313 and the fourth counter 314 are both connected to the third accumulator 323, and the third accumulator 323 is used to calculate the total number of counts by the third counter 313 and the fourth counter 314. The second accumulator 322 and the third accumulator 323 are both connected to the fourth accumulator 324, and the fourth accumulator 324 is used to calculate the total number of counts calculated by the second accumulator 322 and the third accumulator 323.
[0048] The second accumulator 322, the third accumulator 323, and the fourth accumulator 324 can be the same chip. Pin A3 of the second accumulator 322 is connected to pin 53 of the first counter 311; pin A2 of the second accumulator 322 is connected to pin 52 of the first counter 311; pin A1 of the second accumulator 322 is connected to pin 51 of the first counter 311; and pin A0 of the second accumulator 322 is connected to pin 50 of the first counter 311. Pin B3 of the second accumulator 322 is connected to pin 53 of the second counter 312; pin B2 of the second accumulator 322 is connected to pin 52 of the second counter 312; pin B1 of the second accumulator 322 is connected to pin 51 of the second counter 312; and pin B0 of the second accumulator 322 is connected to pin 50 of the second counter 312.
[0049] Pin A3 of the third accumulator 323 is connected to pin 53 of the third counter 313; pin A2 of the third accumulator 323 is connected to pin 52 of the third counter 313; pin A1 of the third accumulator 323 is connected to pin 51 of the third counter 313; and pin A0 of the third accumulator 323 is connected to pin 50 of the third counter 313. Pin B3 of the third accumulator 323 is connected to pin 53 of the fourth counter 314; pin B2 of the third accumulator 323 is connected to pin 52 of the fourth counter 314; pin B1 of the third accumulator 323 is connected to pin 51 of the fourth counter 314; and pin B0 of the third accumulator 323 is connected to pin 50 of the fourth counter 314.
[0050] Pin A3 of the fourth accumulator 324 is connected to pin 53 of the second accumulator 322; pin A2 of the fourth accumulator 324 is connected to pin 52 of the second accumulator 322; pin A1 of the fourth accumulator 324 is connected to pin 51 of the second accumulator 322; and pin A0 of the fourth accumulator 324 is connected to pin 50 of the second accumulator 322. Pin B3 of the fourth accumulator 324 is connected to pin 53 of the third accumulator 323; pin B2 of the fourth accumulator 324 is connected to pin 52 of the third accumulator 323; pin B1 of the fourth accumulator 324 is connected to pin 51 of the third accumulator 323; and pin B0 of the fourth accumulator 324 is connected to pin 50 of the third accumulator 323.
[0051] Pin 53 of the fourth accumulator 324 can be connected to pin 13 of the phase detector module 4, pin 52 of the fourth accumulator 324 can be connected to pin 12 of the phase detector module 4, pin 51 of the fourth accumulator 324 can be connected to pin 11 of the phase detector module 4, and pin 50 of the fourth accumulator 324 can be connected to pin 10 of the phase detector module 4. This is used to transmit the accumulated value to the phase detector module 4.
[0052] The method of cascading three accumulators can reduce the difficulty of selecting the second accumulator 322, the third accumulator 323, and the fourth accumulator 324.
[0053] Based on the above embodiments, optionally, the accumulation unit includes: a first accumulator. The first counter, the second counter, the third counter, and the fourth counter are all connected to the first accumulator, and the first accumulator is used to calculate the total number of counts by the first counter, the second counter, the third counter, and the fourth counter.
[0054] Alternatively, the second, third, and fourth accumulators can be combined into a single first accumulator. This first accumulator can have a higher bit depth and can directly accumulate all counts from the first, second, third, and fourth counters, resulting in a faster accumulation speed.
[0055] Figure 5 This is a waveform diagram of a phase detection value provided in an embodiment of the present invention. (Reference) Figure 5 The vertical axis represents the time deviation per second, and the horizontal axis represents the test time. Testing shows that the device achieves a minimum testing accuracy of 625 ps. Therefore, the phase detection device provided in this embodiment of the invention achieves the expected results. Picosecond-level phase detection accuracy is achieved without increasing the main frequency or adding extra overhead.
[0056] Continue to refer to Figure 3 Based on the above embodiments, optionally, the phase detection device further includes: a display module 5, connected to the phase detection module 4, for displaying the phase detection value.
[0057] Specifically, pin a of phase detection module 4 is connected to pin a of display module 5, pin b of phase detection module 4 is connected to pin b of display module 5, pin c of phase detection module 4 is connected to pin c of display module 5, pin d of phase detection module 4 is connected to pin d of display module 5, pin e of phase detection module 4 is connected to pin e of display module 5, pin f of phase detection module 4 is connected to pin f of display module 5, and pin g of phase detection module 4 is connected to pin g of display module 5.
[0058] This invention also provides a programmable logic device. The programmable logic device includes the phase detection device provided in any embodiment of this invention, which has similar beneficial effects to the phase detection device and will not be described in detail here.
[0059] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.
[0060] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.
Claims
1. A phase detection device, characterized in that, include: The comparator module receives the test clock signal and the reference signal, and outputs a start-clear signal. The system includes a multi-channel signal generation module and a counting and accumulating module. The multi-channel signal generation module is used to start or stop according to the start-reset signal, and outputs at least four square wave signals with different phases and the same frequency to the counting and accumulating module when starting. The counting and accumulating module is used to calculate the total number of rising and falling edges of each of the square wave signals. The phase detection module is used to generate a phase detection value between the test clock signal and the reference signal based on the total number of times and the frequency and phase of each of the square wave signals.
2. The phase detector according to claim 1, characterized in that, The comparison module includes: an XOR gate and an AND gate; The first input terminal of the XOR gate is used to receive the reference signal, and the second input terminal of the XOR gate is used to receive the test clock signal; the output terminal of the XOR gate is connected to the first input terminal of the AND gate. The second input terminal of the AND gate is used to receive the test clock signal, and the output terminal of the AND gate is connected to the multi-channel signal generation module.
3. The phase detector according to claim 1, characterized in that, The multi-channel signal generation module includes a first signal generation unit, a second signal generation unit, a third signal generation unit, and a fourth signal generation unit, all of which are connected to the counting and accumulating module. The first signal generation unit is used to generate and output a 0° phase-shifted square wave signal, the second signal generation unit is used to generate and output a 45° phase-shifted square wave signal, the third signal generation unit is used to generate and output a 90° phase-shifted square wave signal, and the fourth signal generation unit is used to generate and output a 135° phase-shifted square wave signal.
4. The phase detection device according to claim 3, characterized in that, The counting and accumulating module includes: a counting unit and an accumulating unit; The counting unit is connected to the multi-channel signal generation module and is used to count the number of rising and falling edges of each square wave signal. The accumulator unit is connected to the counter unit and is used to calculate the total number of times the counter unit counts.
5. The phase detection device according to claim 4, characterized in that, The counting unit includes: a first counter, a second counter, a third counter, and a fourth counter; The first counter is connected to the first signal generation unit and is used to count the number of rising and falling edges of the 0° phase-shifted square wave signal; The second counter is connected to the second signal generation unit and is used to count the number of rising and falling edges of the 45° phase-shifted square wave signal; The third counter is connected to the third signal generation unit and is used to count the number of rising and falling edges of the 90° phase-shifted square wave signal. The fourth counter is connected to the fourth signal generation unit and is used to count the number of rising and falling edges of the 135° phase-shifted square wave signal.
6. The phase detector according to claim 5, characterized in that, The accumulation unit includes: a first accumulator; The first counter, the second counter, the third counter, and the fourth counter are all connected to the first accumulator, which is used to calculate the total number of counts by the first counter, the second counter, the third counter, and the fourth counter.
7. The phase detector according to claim 5, characterized in that, The accumulation unit includes: a second accumulator, a third accumulator, and a fourth accumulator; the first counter and the second counter are both connected to the second accumulator, and the second accumulator is used to calculate the total number of counts by the first counter and the second counter; The third counter and the fourth counter are both connected to the third accumulator, and the third accumulator is used to calculate the total number of counts by the third counter and the fourth counter; The second accumulator and the third accumulator are both connected to the fourth accumulator, which is used to calculate the total number of calculations performed by the second accumulator and the third accumulator.
8. The phase detector according to claim 1, characterized in that, The phase detection device further includes a display module connected to the phase detection module for displaying the phase detection value.
9. The phase detector according to claim 1, characterized in that, The frequency of each of the square wave signals is 200MHz.
10. A programmable logic device, characterized in that, include: The phase detector according to any one of claims 1-9.