Equivalent sampling circuit and device, equivalent sampling method

Abstract

The application provides an equivalent sampling circuit and device, and an equivalent sampling method, and relates to the field of circuits.The equivalent sampling circuit comprises a frequency discriminator, a voltage-controlled oscillator, a first frequency divider, a second frequency divider and a sampling unit; wherein the frequency discriminator is used to obtain a reference signal and a first frequency division signal, compare the frequency and phase of the first frequency division signal and the reference signal respectively, and obtain the frequency difference and phase difference of the first frequency division signal and the reference signal; the voltage-controlled oscillator is used to generate a second oscillation signal based on the frequency difference and the phase difference; the second frequency divider is used to perform integer frequency division on the second oscillation signal by using an integer frequency division coefficient to generate a second frequency division signal; and the sampling unit is used to perform equivalent sampling on a to-be-tested signal based on the second frequency division signal.The equivalent sampling circuit in the application can greatly improve the time delay step of the second frequency division signal, does not increase the circuit cost, and ensures the accuracy of sampling.

Description

Technical Field

[0001] This application relates to the field of circuits, specifically to an equivalent sampling circuit and device, and an equivalent sampling method. Background Technology

[0002] Equivalent sampling is a technique that reconstructs the original signal waveform by sampling and recombining a signal multiple times. Its core lies in how to generate a sampling pulse with a stable step size relative to the original signal.

[0003] In related technologies, the pulse is mainly generated using delay chips. However, these delay chips are composed of independent delay circuits connected in series, and the delay step value of the sampling pulse is primarily determined by the number of delay circuits. To increase the delay step value of the sampling pulse, it is usually necessary to increase the number of delay circuits. This increases the circuit cost and size of the delay chip, and it also fails to meet the demand for significantly increasing the delay step value of the sampling pulse. Summary of the Invention

[0004] In view of this, embodiments of this application provide an equivalent sampling circuit and apparatus, and an equivalent sampling method.

[0005] In a first aspect, one embodiment of this application provides an equivalent sampling circuit, including: a frequency and phase detector, a voltage-controlled oscillator (VCO), a first frequency divider, a second frequency divider, and a sampling circuit; wherein, the output terminal of the frequency and phase detector is connected to the input terminal of the VCO, the output terminal of the VCO is connected to the input terminals of the first and second frequency dividers respectively, the output terminal of the first frequency divider is connected to the input terminal of the frequency and phase detector, the first input terminal of the sampling unit is used to receive the signal to be measured, and the second input terminal of the sampling unit is connected to the output terminal of the second frequency divider; the frequency and phase detector is used to acquire a reference signal and a first frequency-divided signal, and to perform sampling on the first frequency-divided signal. The frequencies and phases of the frequency-divided signal and the reference signal are compared respectively to obtain the frequency difference and phase difference between the first frequency-divided signal and the reference signal. The frequency and phase of the reference signal correspond to the frequency and phase of the signal under test. The first frequency-divided signal is obtained by dividing the first oscillation signal by a fractional frequency division coefficient. A voltage-controlled oscillator is used to generate a second oscillation signal based on the frequency difference and phase difference. A second frequency divider is used to divide the second oscillation signal by an integer frequency division coefficient to generate a second frequency-divided signal. A sampling unit is used to perform equivalent sampling of the signal under test based on the second frequency-divided signal.

[0006] In conjunction with the first aspect, in some implementations of the first aspect, the sampling unit is further configured to: calculate the target sampling rate based on the fractional frequency division coefficient corresponding to the first frequency division signal and the integer frequency division coefficient corresponding to the second frequency division signal; determine the target sampling period based on the signal period of the signal under test and the target sampling rate; determine the sampling interval based on the signal period of the signal under test and the target sampling period; and perform equivalent sampling on the signal under test using the second frequency division signal based on the sampling interval.

[0007] In conjunction with the first aspect, in some implementations of the first aspect, the sampling interval Where T represents the signal period of the signal under test, M represents the integer value of the fractional frequency division coefficient, a represents the numerator of the fractional frequency division coefficient after converting the decimal value into a fraction, b represents the denominator of the fractional frequency division coefficient after converting the decimal value into a fraction, and c represents the difference between the integer frequency division coefficient and the integer value of the fractional frequency division coefficient.

[0008] In conjunction with the first aspect, in some implementations of the first aspect, the fractional frequency division coefficient and the integer frequency division coefficient are determined based on the sampling interval of the signal under test. The fractional frequency division coefficient includes integer and fractional values, and the difference between the integer and fractional frequency division coefficients is equal to the target value.

[0009] In conjunction with the first aspect, in some implementations of the first aspect, the voltage-controlled oscillator is also used to generate an error signal based on the frequency difference and the phase difference; and to generate a second oscillation signal of a corresponding frequency based on the error signal.

[0010] In conjunction with the first aspect, in some implementations of the first aspect, the circuit further includes a trigger unit, the input of which is used to receive the signal to be tested, and the output of which is connected to the input of a frequency and phase detector: wherein the trigger unit is used to acquire the signal to be tested; to detect the signal to be tested and obtain a detection result; and if the detection result meets the target triggering condition, to generate a reference signal based on the frequency and phase of the signal to be tested.

[0011] Secondly, one embodiment of this application provides an equivalent sampling method applied to an equivalent sampling device. The equivalent sampling device includes an equivalent sampling circuit, which includes a frequency and phase detector, a voltage-controlled oscillator (VCO), a first frequency divider, a second frequency divider, and a sampling unit. The output terminal of the frequency and phase detector is connected to the input terminal of the VCO, the output terminal of the VCO is connected to the input terminals of the first and second frequency dividers, the output terminal of the first frequency divider is connected to the input terminal of the frequency and phase detector, the first input terminal of the sampling unit is used to receive the signal to be measured, and the second input terminal of the sampling unit is connected to the output terminal of the second frequency divider. The method includes: acquiring a reference signal using a frequency and phase detector, wherein the frequency and phase of the reference signal correspond to the frequency and phase of the signal under test; acquiring a first frequency-divided signal using the frequency and phase detector, wherein the first frequency-divided signal is obtained by dividing a first oscillation signal by a fractional frequency division coefficient using a first frequency divider; comparing the frequencies and phases of the first frequency-divided signal and the reference signal respectively using the frequency and phase detector to obtain the frequency difference and phase difference between the first frequency-divided signal and the reference signal; generating a second oscillation signal using a voltage-controlled oscillator based on the frequency difference and phase difference; dividing the second oscillation signal by an integer frequency division coefficient using a second frequency divider to generate a second frequency-divided signal; and performing equivalent sampling of the signal under test using a sampling unit based on the second frequency-divided signal.

[0012] In conjunction with the second aspect, in some implementations of the second aspect, the sampling unit performs equivalent sampling of the signal under test based on the second frequency division signal, including: calculating the target sampling rate based on the fractional frequency division coefficient corresponding to the first frequency division signal and the integer frequency division coefficient corresponding to the second frequency division signal using the sampling unit; determining the target sampling period based on the signal period of the signal under test and the target sampling rate; determining the sampling interval based on the signal period of the signal under test and the target sampling period; and performing equivalent sampling of the signal under test using the second frequency division signal based on the sampling interval.

[0013] In conjunction with the second aspect, in some implementations of the second aspect, the sampling interval Where T represents the signal period of the signal under test, M represents the integer value of the fractional frequency division coefficient, a represents the numerator of the fractional frequency division coefficient after converting the decimal value into a fraction, b represents the denominator of the fractional frequency division coefficient after converting the decimal value into a fraction, and c represents the difference between the integer frequency division coefficient and the integer value of the fractional frequency division coefficient.

[0014] Thirdly, one embodiment of this application provides an equivalent sampling device, including the equivalent sampling circuit as described in the first aspect above.

[0015] In the equivalent sampling circuit of this application, the first frequency divider first divides the first oscillation signal by a fractional frequency division coefficient to obtain the first frequency-divided signal. Then, the second frequency divider performs an integer frequency division on the first frequency-divided signal to obtain the second frequency-divided signal. This second frequency-divided signal is used as the sampling signal for equivalent sampling of the signal under test. Typically, the fractional frequency division coefficient has a high number of bits. Therefore, by adjusting the parameters in the fractional frequency division coefficient of the first frequency divider, the delay step of the second frequency-divided signal can be significantly increased without increasing circuit cost. Secondly, the integer frequency division coefficient of the second frequency divider ensures an integer multiple relationship between the frequency of the second frequency-divided signal and the frequency of the signal under test, thus accurately reflecting the waveform information of the signal under test during the sampling process.

[0016] Furthermore, if the frequency of the sampled signal is too high, a higher-performance equivalent sampling circuit is required to process the sampled data, which increases the complexity and cost of the circuit. Therefore, by dividing the second oscillation signal by an integer, the frequency of the second divided signal can be reduced, thereby reducing the complexity and cost of the equivalent sampling circuit. Moreover, the first frequency divider divides the first oscillation signal by a fractional number, which pushes the first oscillation signal to a higher frequency, but also introduces quantization noise and fractional spurious signals. Therefore, by dividing the second oscillation signal by an integer number based on the first divided signal, the quantization noise power can be evenly distributed across multiple sampling periods, thus significantly reducing the noise power in each sampling period. Furthermore, the frequency and phase discriminator, by comparing the frequency difference and phase difference between the first divided signal and the reference signal, can improve the accuracy and precision of sampling, providing a reliable basis for subsequent processing and analysis of the sampling results. Attached Figure Description

[0017] The above and other objects, features, and advantages of this application will become more apparent from the more detailed description of the embodiments of this application in conjunction with the accompanying drawings. The drawings are provided to further illustrate the embodiments of this application and form part of the specification. They are used together with the embodiments of this application to explain this application and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps.

[0018] Figure 1 The diagram shows the structure of the relevant circuit for equivalent sampling.

[0019] Figure 2 The diagram shown is a schematic diagram of the equivalent sampling circuit provided in an embodiment of this application.

[0020] Figure 3 The diagram shown is a schematic diagram of the equivalent sampling circuit provided in another embodiment of this application.

[0021] Figure 4 The diagram shown is a flowchart of an equivalent sampling method provided in an embodiment of this application. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0023] The core idea of ​​equivalent sampling technology is to achieve equivalent sampling of the signal under test through specific algorithms and circuit designs. That is, under certain conditions, it obtains the same result as a high sampling rate using a relatively low sampling rate. This technology can be applied to scenarios such as oscilloscopes, TDR (Time Domain Reflectometry) impedance measurement, and UWB (Ultra-Wideband) ranging. By performing equivalent sampling on the signal under test, its frequency, amplitude, phase, and other characteristics can be analyzed; it can also be used to calculate certain statistical indicators of the signal under test, such as average value and variance; or it can be quantized to convert the signal into a digital signal that can be further analyzed and processed; or it can be used to detect whether the corresponding system is working properly or whether there are any abnormalities.

[0024] Figure 1 The diagram shows the structural schematic of the circuit for equivalent sampling. In this technology, the controllable delay circuit is a key component of the equivalent sampling technique. It introduces a controllable delay, causing a temporal shift in the sampled signal. Thus, by changing the delay time, the state of the signal under test at different times can be simulated, thereby capturing the behavior of the signal at different moments. Specifically, during the equivalent sampling process, the trigger unit generates a trigger pulse at a specific location on the signal under test, and then the controllable delay circuit controls the sampling unit to sample within different periods of the signal under test. In this way, multiple samples can be taken within a longer period of the signal, and the sampling results can be appropriately processed and combined to obtain a signal reconstruction result equivalent to that obtained with a high sampling rate.

[0025] Equivalent sampling techniques can significantly reduce sampling rates and data storage rates, thereby reducing hardware burden and costs. Simultaneously, equivalent sampling techniques can further improve the accuracy and effectiveness of signal reconstruction by optimizing algorithms and circuit design, providing digital oscilloscopes with a more flexible, efficient, and accurate data acquisition and processing method. However, Figure 1The controllable delay circuit in the illustrated circuit structure is composed of independent delay units connected in series, and the delay step depends on the number of independent delay units. To improve sampling efficiency, the only solution is to increase the number of delay units. Furthermore, the delay step improvement achieved through delay units is typically only around 1K.

[0026] Based on the above, this application proposes another equivalent sampling circuit to overcome the defects existing in the related circuits. Specifically, Figure 2 The diagram shows a schematic of an equivalent sampling circuit provided in an embodiment of this application. The equivalent sampling circuit includes a frequency and phase detector 10, a voltage-controlled oscillator 20, a first frequency divider 40, a second frequency divider 30, and a sampling unit 50. The output of the frequency and phase detector 10 is connected to the input of the voltage-controlled oscillator 20. The output of the voltage-controlled oscillator 20 is connected to the inputs of the first frequency divider 40 and the second frequency divider 30. The output of the first frequency divider 40 is connected to the input of the frequency and phase detector 10. The first input of the sampling unit 50 is used to receive the signal to be measured, and the second input of the sampling unit 50 is connected to the output of the second frequency divider 30.

[0027] The frequency and phase detector 10 is used to acquire the reference signal and the first frequency-divided signal, and compare the frequency and phase of the first frequency-divided signal and the reference signal respectively to obtain the frequency difference and phase difference between the first frequency-divided signal and the reference signal. The voltage-controlled oscillator 20 is used to generate a second oscillation signal based on the frequency difference and phase difference. The second frequency divider 30 is used to divide the second oscillation signal by an integer frequency division coefficient to generate a second frequency-divided signal; the sampling unit 50 is used to perform equivalent sampling of the signal to be tested based on the second frequency-divided signal.

[0028] In this embodiment, the frequency and phase of the reference signal correspond to the frequency and phase of the signal under test. Specifically, this relationship refers to a direct correspondence between the frequency and phase of the reference signal and the frequency and phase of the signal under test, so as to accurately reflect the characteristics of the signal under test during the equivalent sampling process. For example, a correspondence can be established in terms of frequency tuning, phase adjustment, and amplitude matching to obtain more accurate results during the equivalent sampling process.

[0029] For example, an oscillator can be used to generate a reference signal corresponding to the signal under test. Specifically, the process involves changing the capacitance or inductance of the oscillator according to the frequency of the signal under test, thereby tuning the oscillator to generate a reference signal with a frequency that is the same as or a multiple of the frequency of the signal under test. In this embodiment, the reference signal can be used to generate sampling pulses and also to adjust the phase and frequency of the sampling pulses to ensure that the correlation between the sampling pulses and the signal under test generates useful information. Therefore, by adjusting the parameters of the reference signal, different sampling strategies for the signal under test can be implemented.

[0030] In this embodiment, the first frequency-divided signal is obtained by the first frequency divider 40 dividing the first oscillation signal by a fractional frequency division coefficient. Then, the second frequency divider 30 performs integer frequency division on the first frequency-divided signal to generate the second frequency-divided signal for the current moment. The principle of the first frequency divider 40 performing fractional frequency division is to calculate the average frequency division over a period of time by using different division ratios in different periods. For example, if a fractional frequency division coefficient of 40.5 is required, then a division ratio of 40 is generated in one period, and a division ratio of 41 is generated in the next period, resulting in a division ratio of 40.5 over these two periods.

[0031] In this embodiment, the frequency and phase detector 10 is an electronic component used to compare the frequency and phase differences of two signals. During equivalent sampling, the frequency and phase detector 10 receives two input signals: a first frequency division signal and a reference signal. It compares the frequency and phase of these two signals respectively and outputs their frequency difference and phase difference.

[0032] Furthermore, the voltage-controlled oscillator 20 generates a second oscillation signal based on the frequency difference and phase difference. The voltage-controlled oscillator 20 is an electronic component that generates an oscillation signal whose frequency is controlled by an external voltage. In the equivalent sampling circuit, the voltage-controlled oscillator 20 adjusts the frequency and phase of the second oscillation signal by receiving the frequency difference and phase difference output from the frequency and phase detector 10. During this process, the frequency difference and phase difference are converted into a control voltage suitable for the voltage-controlled oscillator 20. Then, the voltage-controlled oscillator 20 adjusts its internal parameters according to the control voltage, thereby changing the frequency and phase of the second oscillation signal.

[0033] The second frequency divider 30 performs integer frequency division on the second oscillation signal primarily through internal logic gates, such as AND gates, OR gates, and NOT gates, to perform logical operations on the input second oscillation signal, resulting in a second frequency-divided signal with a frequency of 1 / n (where n is a positive integer) of the second oscillation signal frequency. In other words, the second frequency divider 30 is an integer frequency divider. Since the frequency and phase detector 10 is a digital module and the oscillation signal frequency of the voltage-controlled oscillator 20 is relatively high, the second frequency divider 30 is needed to convert the frequency of its second oscillation signal to a lower frequency.

[0034] In this embodiment, the sampling unit 50 uses the second frequency-divided signal to perform equivalent sampling of the signal under test. Exemplarily, the sampling unit 50 compares the second frequency-divided signal and the signal under test using one or more flip-flops (such as comparators, logic gates, etc.). At the rising or falling edge of each second frequency-divided signal, the flip-flop compares the voltage values ​​of the second frequency-divided signal and the signal under test. If the voltage value of the signal under test is higher than the voltage value of the second frequency-divided signal, the flip-flop outputs a logic high level; if the voltage value of the signal under test is lower than the voltage value of the second frequency-divided signal, the flip-flop outputs a logic low level.

[0035] In this way, the sampling unit 50 performs equivalent sampling of the signal under test. Since the frequency of the second frequency division signal is an integer multiple of the frequency of the signal under test, the sampling unit 50 can accurately capture the state changes of the signal under test within each period of the second frequency division signal, thus achieving the effect of equivalent sampling.

[0036] In this embodiment, the equivalent sampling circuit first uses a first frequency divider 40 to divide the first oscillation signal by a fractional frequency to obtain a first divided frequency signal. Then, based on this first divided frequency signal, a second frequency divider 30 is used to divide it by an integer frequency to obtain a second divided frequency signal. This second divided frequency signal is used as the sampling signal for equivalent sampling of the signal under test. Typically, the fractional frequency division coefficient has a high number of bits. Therefore, by adjusting the division parameters in the first frequency divider 40, the delay step of the second divided frequency signal can be significantly increased without increasing circuit cost. Secondly, the second frequency divider 30 ensures an integer multiple relationship between the frequency of the second divided frequency signal and the frequency of the signal under test, thus accurately reflecting the waveform information of the signal under test during sampling. Furthermore, if the frequency of the sampling signal is too high, a higher-performance equivalent sampling circuit is needed to process the sampling data, which increases circuit complexity and cost. Therefore, the second frequency divider 30 can also reduce the frequency of the second divided frequency signal, thereby reducing the complexity and cost of the sampling circuit. Furthermore, after the first oscillation signal passes through the first frequency divider 40, it will push the first oscillation signal to a higher frequency. However, this also introduces problems such as quantization noise and fractional spurious signals. Therefore, based on the first frequency-divided signal, the second frequency divider 30 is used to perform integer frequency division on the second oscillation signal. This allows the quantization noise power to be evenly distributed across multiple sampling periods, thereby significantly reducing the noise power in each sampling period. Further, by comparing the frequency difference and phase difference between the first frequency-divided signal and the reference signal using the frequency and phase discriminator 10, the accuracy and precision of sampling can be improved, providing a reliable foundation for subsequent processing and analysis of the sampling results.

[0037] exist Figure 2 Based on the illustrated embodiment, the following extensions are made: Figure 3The illustrated embodiment. Specifically, Figure 3 The diagram shown is a schematic representation of an equivalent sampling circuit provided in another embodiment of this application. Figure 3 As shown, the circuit also includes a trigger unit 60. The input terminal of the trigger unit 60 receives the signal to be tested, and the output terminal of the trigger unit 60 is connected to the input terminal of the frequency and phase detector 10. That is, in this embodiment, the trigger unit 60 detects the signal to be tested, obtains the detection result, and generates a reference signal based on the frequency and phase of the signal to be tested when the detection result meets the target triggering condition.

[0038] For example, in this process, the triggering unit 60 measures and analyzes the amplitude, frequency, and phase of the signal under test. These measurement results can be used to determine the characteristics and attributes of the signal under test. Furthermore, the triggering conditions can be set based on the frequency, phase, amplitude, or other relevant parameters of the signal under test. For example, the triggering unit 60 generates a reference signal only when the frequency of the signal reaches or exceeds a certain preset value; or, the triggering unit 60 generates a reference signal only when the phase of the signal under test reaches or exceeds a certain preset value (such as a specific angle or time point); or, the triggering unit 60 generates a reference signal only when the frequency of the signal under test falls within a specific range and its phase meets specific conditions.

[0039] When the signal under test is detected to meet the triggering conditions, the triggering unit 60 generates a reference signal based on the signal under test. For example, this reference signal may be a signal obtained after some processing or transformation of the signal under test. Furthermore, after generating the reference signal, the triggering unit 60 can also adjust and optimize it as needed, for example, by fine-tuning the amplitude, frequency, or phase of the reference signal to ensure optimal matching between the reference signal and the signal under test.

[0040] In this embodiment, the trigger unit 60 detects the signal to be tested and generates a reference signal when the detection result meets the trigger conditions. By setting appropriate trigger conditions, the generation of the reference signal can be ensured to be more accurate and reliable, thereby improving sampling accuracy and reducing sampling error. Furthermore, in equivalent sampling, the output frequency of the voltage-controlled oscillator 20 is adjusted according to the input signal of the frequency and phase detector 10, and the error signal is obtained from the phase difference and frequency difference between the reference signal and the first frequency divider signal output by the first frequency divider 40. Therefore, the generation of the reference signal is crucial, ensuring the accuracy and reliability of the equivalent sampling circuit in this application during equivalent sampling.

[0041] In conjunction with the foregoing embodiments, in other embodiments of this application, the voltage-controlled oscillator 20 is further configured to generate an error signal based on the frequency difference and the phase difference; and generate a second oscillation signal of a corresponding frequency based on the error signal.

[0042] In this process, the error signal characterizes the difference in frequency and phase between the reference signal and the first frequency divider signal. This error signal is further transmitted to the voltage-controlled oscillator 20 to adjust its output frequency, thereby reducing the frequency and phase difference with the signal under test. Through this closed-loop feedback mechanism, the second oscillation signal output by the voltage-controlled oscillator 20 can be automatically adjusted to keep its frequency and phase consistent with the signal under test. This adjustment process is based on the error signal output by the frequency and phase detector 10.

[0043] In this embodiment, by comparing the frequency and phase differences between the reference signal and the first frequency-divided signal, the differences between them can be understood more accurately. This precise difference measurement can greatly improve the accuracy and precision of sampling. When the frequency and phase detector 10 detects a frequency or phase difference, it can immediately generate an error signal. This error signal can adjust the output of the voltage-controlled oscillator 20 in real time to ensure that it is consistent with the frequency and phase of the signal under test. This real-time adjustment mechanism helps improve the real-time performance and dynamic response of sampling. At the same time, the presence of the error signal enables the system to self-correct and remain in a stable state. Even in the presence of noise or interference, this error signal-based adjustment can ensure the stability and reliability of sampling.

[0044] In conjunction with the foregoing embodiments, in some other embodiments of this application, the sampling unit 50 is further configured to: calculate a target sampling rate based on the fractional frequency division coefficient corresponding to the first frequency division signal and the integer frequency division coefficient corresponding to the second frequency division signal; determine a target sampling period based on the signal period of the signal under test and the target sampling rate; determine a sampling interval based on the signal period of the signal under test and the target sampling period; and perform equivalent sampling on the signal under test using the second frequency division signal based on the sampling interval.

[0045] Specifically, if T represents the signal period of the signal to be measured, M represents the integer value of the fractional frequency division coefficient, a represents the numerator of the fractional frequency division coefficient after converting the decimal value into a fraction, b represents the denominator of the fractional frequency division coefficient after converting the decimal value into a fraction, and c represents the difference between the integer and integer values ​​of the fractional frequency division coefficient, then the fractional frequency division coefficient of the first frequency divider 40 is denoted as... The integer division coefficient of the second frequency divider 30 is denoted as (M+c), then the sampling period of the reference signal is... The sampling period of the second frequency division signal can be denoted as:

[0046] Furthermore, sampling interval

[0047] Based on the above, when performing equivalent sampling on the signal under test, the time delay step value

[0048] For example, a common fractional frequency divider can be 18-bit, which means that the values ​​of a and b can range from 1 to 2. 18 Therefore, N can easily reach the million level, thus meeting the application requirement of significantly increasing the time delay step value of the sampled signal (the second frequency division signal in this application is the sampled signal).

[0049] The aforementioned sampling unit 50 takes into account the periodicity and frequency of the signal under test, as well as the specific requirements of the target sampling rate. Therefore, it can more accurately capture and reproduce the characteristics of the signal under test. Furthermore, by changing the fractional division coefficient corresponding to the first frequency division signal and the integer division coefficient corresponding to the second frequency division signal, the target sampling rate can be easily adjusted to meet different application requirements. Moreover, this method is relatively simple to implement and does not require complex hardware or algorithms.

[0050] As mentioned above, the fractional frequency division coefficient and the integer frequency division coefficient are determined based on the sampling interval of the signal under test. The fractional frequency division coefficient includes integer and fractional values. The difference between the integer and fractional frequency division coefficients is equal to the target value. In this application, c represents the target value.

[0051] For example, when c is 1, then

[0052] Below, in Figure 2 Based on, combined Figure 4 This paper briefly describes the specific implementation process of using an equivalent sampling circuit to perform the equivalent sampling method.

[0053] Specifically, Figure 4 The diagram shown is a flowchart of an equivalent sampling method provided in an embodiment of this application. Exemplarily, this method is applied to an equivalent sampling circuit, which includes: a frequency and phase detector, a voltage-controlled oscillator (VCO), a first frequency divider, a second frequency divider, and a sampling unit. The output of the frequency and phase detector is connected to the input of the VCO, the output of the VCO is connected to the inputs of the first and second frequency dividers, the output of the first frequency divider is connected to the input of the frequency and phase detector, the first input of the sampling unit is used to receive the signal to be measured, and the second input of the sampling unit is connected to the output of the second frequency divider. Figure 4 As shown, the equivalent sampling provided in this embodiment includes the following steps.

[0054] Step S410: Obtain the reference signal using a frequency and phase detector.

[0055] The frequency and phase of the reference signal correspond to the frequency and phase of the signal under test. Specifically, this relationship refers to the direct correspondence between the frequency and phase of the reference signal and the frequency and phase of the signal under test, so as to accurately reflect the characteristics of the signal under test during the equivalent sampling process.

[0056] For example, a reference signal corresponding to the signal under test can be generated by an oscillator. The specific process is as follows: according to the frequency of the signal under test, the capacitance or inductance of the oscillator is changed, and the oscillator is tuned accordingly to generate a reference signal with the same frequency as or a multiple of the frequency of the signal under test.

[0057] Step S420: Obtain the first frequency division signal using a frequency and phase detector.

[0058] The first frequency divider signal is generated by the first frequency divider 40 dividing the second oscillation signal output by the voltage-controlled oscillator 20 at the previous moment by a fractional frequency. Then, the second frequency divider 30 further divides the first frequency divider signal by an integer frequency to generate the second frequency divider signal at the current moment.

[0059] Step S430: The frequency and phase of the first frequency division signal and the reference signal are compared by a frequency and phase detector to obtain the frequency difference and phase difference between the first frequency division signal and the reference signal.

[0060] Step S440: A second oscillation signal is generated using a voltage-controlled oscillator based on the frequency difference and phase difference.

[0061] In equivalent sampling, the voltage-controlled oscillator 20 adjusts the frequency and phase of the second oscillation signal by receiving the frequency difference and phase difference output from the frequency and phase detector 10. In this process, the frequency difference and phase difference are converted into a control voltage suitable for the voltage-controlled oscillator 20. Then, the voltage-controlled oscillator 20 adjusts its internal parameters according to the control voltage, thereby changing the frequency and phase of the second oscillation signal.

[0062] Step S450: The second frequency divider is used to divide the second oscillation signal by an integer frequency division coefficient to generate the second frequency divided signal.

[0063] In other words, the second frequency divider 30 is an integer frequency divider. Since the frequency and phase detector 10 is a digital module and the oscillation signal frequency of the voltage-controlled oscillator 20 is relatively high, the second frequency divider 30 is required to convert the frequency of its second oscillation signal to a low frequency.

[0064] Step S460: The sampling unit performs equivalent sampling of the signal under test based on the second frequency division signal.

[0065] Specifically, in this embodiment, the sampling unit 50 uses the second frequency division signal to perform equivalent sampling of the signal under test. Since the frequency of the second frequency division signal is an integer multiple of the frequency of the signal under test, the sampling unit 50 can accurately capture the state changes of the signal under test within each period of the second frequency division signal, thereby achieving the effect of equivalent sampling.

[0066] In this embodiment, the first oscillation signal is first divided by a fractional frequency division coefficient to obtain a first frequency-divided signal. Then, an integer frequency division is performed on this first frequency-divided signal to obtain a second frequency-divided signal. This second frequency-divided signal is used as a sampling signal for equivalent sampling of the signal under test. Typically, the fractional frequency division coefficient has a high number of bits. Therefore, by adjusting the parameters in the fractional frequency division coefficient, the time delay step of the second frequency-divided signal can be significantly increased without increasing circuit cost. Secondly, integer frequency division ensures an integer multiple relationship between the frequency of the second frequency-divided signal and the frequency of the signal under test, thus accurately reflecting the waveform information of the signal under test during sampling. Furthermore, if the frequency of the sampling signal is too high, a higher-performance sampling circuit is required to process the sampling data, which increases circuit complexity and cost. Therefore, by performing integer frequency division on the second oscillation signal, the frequency of the second frequency-divided signal can be reduced, thereby reducing the complexity and cost of the sampling circuit. Furthermore, dividing the first oscillation signal by a fractional frequency pushes it to a higher frequency, but also introduces quantization noise and fractional spurious signals. Therefore, dividing the second oscillation signal by an integer frequency based on the first divided signal allows the quantization noise power to be evenly distributed across multiple sampling periods, thus significantly reducing the noise power in each sampling period. Moreover, by comparing the frequency difference and phase difference between the first divided signal and the reference signal, the accuracy and precision of sampling can be improved, providing a reliable foundation for subsequent processing and analysis of the sampling results.

[0067] Combination Figure 4 In some other embodiments of this application, the sampling unit performs equivalent sampling of the signal under test based on the second frequency division signal, including: calculating the target sampling rate based on the fractional frequency division coefficient corresponding to the first frequency division signal and the integer frequency division coefficient corresponding to the second frequency division signal; determining the target sampling period based on the signal period of the signal under test and the target sampling rate; determining the sampling interval based on the signal period of the signal under test and the target sampling period; and performing equivalent sampling of the signal under test using the second frequency division signal based on the sampling interval.

[0068] Specifically, sampling interval Where T represents the signal period of the signal under test, M represents the integer value of the fractional frequency division coefficient, a represents the numerator of the fractional frequency division coefficient after converting the decimal value into a fraction, n represents the denominator of the fractional frequency division coefficient after converting the decimal value into a fraction, and c represents the difference between the integer frequency division coefficient and the integer value of the fractional frequency division coefficient.

[0069] The method in this embodiment considers the periodicity and frequency of the signal under test, as well as the specific requirements of the target sampling rate. Therefore, it can more accurately capture and reproduce the characteristics of the signal under test. Furthermore, by changing the fractional division coefficient corresponding to the first frequency division signal and the integer division coefficient corresponding to the second frequency division signal, the target sampling rate can be easily adjusted to meet different application requirements. Moreover, this method is relatively simple to implement and does not require complex hardware or algorithms.

[0070] One embodiment of this application also provides an equivalent sampling device, including any of the equivalent sampling circuits described in the foregoing embodiments. This circuit first uses a first frequency divider to perform fractional division on a first oscillation signal to obtain a first frequency-divided signal. Then, based on the first frequency-divided signal, it uses a second frequency divider to perform integer division on the same signal to obtain a second frequency-divided signal. This second frequency-divided signal is used as a sampling signal for equivalent sampling of the signal under test. Typically, the fractional division coefficient has a high number of bits. Therefore, by adjusting the division parameters in the first frequency divider, the delay step of the second frequency-divided signal can be significantly increased, and this method does not increase circuit cost. Secondly, the second frequency divider can ensure an integer multiple relationship between the frequency of the second frequency-divided signal and the frequency of the signal under test, thereby accurately reflecting the waveform information of the signal under test during the sampling process. Furthermore, if the frequency of the sampling signal is too high, a higher-performance sampling circuit is required to process the sampling data, which increases the complexity and cost of the circuit. Therefore, by using a second frequency divider, the frequency of the second frequency-divided signal can be reduced, thereby reducing the complexity and cost of the sampling circuit. Furthermore, after the first oscillation signal passes through the first frequency divider, it pushes the signal to a higher frequency, but this also introduces quantization noise and fractional spurious signals. Therefore, by using a second frequency divider to perform integer frequency division on the second oscillation signal based on the first frequency-divided signal, the quantization noise power can be evenly distributed across multiple sampling periods, thus significantly reducing the noise power in each sampling period. Moreover, by comparing the frequency difference and phase difference between the first frequency-divided signal and the reference signal using a frequency and phase discriminator, the accuracy and precision of the sampling can be improved, providing a reliable foundation for subsequent processing and analysis of the sampling results.

[0071] It is understood that the equivalent sampling method and equivalent sampling device in this application correspond to the operations and functions that can be realized by each unit in the equivalent sampling circuit in the foregoing embodiments. Therefore, for more detailed implementations of the equivalent sampling method and equivalent sampling device, please refer to the embodiments corresponding to the equivalent sampling circuit. To avoid repetition, they will not be described again here.

[0072] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the application to the necessity of employing the aforementioned specific details for implementation.

[0073] The block diagrams of devices, apparatuses, units, and circuits involved in this application are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, units, and circuits can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0074] It should also be noted that in the circuits, apparatuses, and methods of this application, the components or steps can be disassembled and / or recombined. These disassemblies and / or recombinations should be considered as equivalent solutions of this application.

[0075] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of this application. Therefore, this application is not intended to be limited to the aspects shown herein, but rather to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0076] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this application to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. An equivalent sampling circuit, characterized by, include: The system comprises a frequency and phase detector, a voltage-controlled oscillator (VCO), a first frequency divider, a second frequency divider, and a sampling unit; wherein the output of the frequency and phase detector is connected to the input of the VCO, the output of the VCO is connected to the inputs of the first and second frequency dividers respectively, the output of the first frequency divider is connected to the input of the frequency and phase detector, the first input of the sampling unit is used to receive the signal under test, and the second input of the sampling unit is connected to the output of the second frequency divider. The frequency and phase detector is used to acquire a reference signal and a first frequency division signal, and compare the frequency and phase of the first frequency division signal and the reference signal respectively to obtain the frequency difference and phase difference between the first frequency division signal and the reference signal. The frequency and phase of the reference signal have a corresponding relationship with the frequency and phase of the signal under test. The first frequency division signal is obtained by the first frequency divider using a fractional frequency division coefficient to divide the first oscillation signal into fractional frequencies. The voltage-controlled oscillator is used to generate a second oscillation signal based on the frequency difference and the phase difference; The second frequency divider is used to divide the second oscillation signal by an integer frequency division coefficient to generate a second frequency-divided signal; The sampling unit is configured to: calculate a target sampling rate based on the fractional frequency division coefficient corresponding to the first frequency division signal and the integer frequency division coefficient corresponding to the second frequency division signal; determine a target sampling period based on the signal period of the signal under test and the target sampling rate; determine a sampling interval based on the signal period of the signal under test and the target sampling period; and perform equivalent sampling on the signal under test using the second frequency division signal based on the sampling interval.

2. The equivalent sampling circuit according to claim 1, characterized in that, the sampling interval wherein denotes a signal period of the signal to be measured, denotes an integer value in the fractional division factor, denotes a value of a numerator after converting a fractional value in the fractional division factor into a fraction, denotes a value of a denominator after converting a fractional value in the fractional division factor into a fraction, and c denotes a difference between the integer division factor and the integer value in the fractional division factor.

3. The equivalent sampling circuit of claim 1 or 2, wherein, The fractional frequency division coefficient and the integer frequency division coefficient are determined based on the sampling interval of the signal under test. The fractional frequency division coefficient includes an integer value and a fractional value. The difference between the integer frequency division coefficient and the integer value of the fractional frequency division coefficient is equal to the target value.

4. The equivalent sampling circuit according to claim 1 or 2, characterized in that, The voltage-controlled oscillator is further configured to generate an error signal based on the frequency difference and the phase difference; and to generate a second oscillation signal of a corresponding frequency based on the error signal.

5. The equivalent sampling circuit according to claim 1 or 2, characterized in that, It also includes a trigger unit, the input of which is used to receive the signal to be tested, and the output of which is connected to the input of the frequency and phase detector. The triggering unit is used to acquire the signal to be tested; to detect the signal to be tested and obtain a detection result; and if the detection result meets the target triggering condition, to generate the reference signal based on the frequency and phase of the signal to be tested.

6. An equivalent sampling method, characterized in that, An equivalent sampling device is applied, the equivalent sampling device including an equivalent sampling circuit, the equivalent sampling circuit including: a frequency and phase detector, a voltage-controlled oscillator, a first frequency divider, a second frequency divider, and a sampling unit; wherein, the output terminal of the frequency and phase detector is connected to the input terminal of the voltage-controlled oscillator, the output terminal of the voltage-controlled oscillator is connected to the input terminals of the first frequency divider and the second frequency divider respectively, the output terminal of the first frequency divider is connected to the input terminal of the frequency and phase detector, the first input terminal of the sampling unit is used to receive the signal to be measured, and the second input terminal of the sampling unit is connected to the output terminal of the second frequency divider; the method includes: The frequency and phase detector is used to obtain a reference signal, the frequency and phase of which correspond to the frequency and phase of the signal under test. The first frequency division signal is obtained by using the frequency and phase detector, which is obtained by the first frequency divider dividing the first oscillation signal by a fractional frequency division coefficient. The frequency and phase of the first frequency-divided signal and the reference signal are compared using the frequency and phase detector respectively to obtain the frequency difference and phase difference between the first frequency-divided signal and the reference signal; The voltage-controlled oscillator generates a second oscillation signal based on the frequency difference and the phase difference. The second frequency divider is used to divide the second oscillation signal by an integer frequency division coefficient to generate a second frequency-divided signal. The sampling unit calculates the target sampling rate based on the fractional frequency division coefficient corresponding to the first frequency division signal and the integer frequency division coefficient corresponding to the second frequency division signal; determines the target sampling period based on the signal period of the signal under test and the target sampling rate; determines the sampling interval based on the signal period of the signal under test and the target sampling period; and performs equivalent sampling on the signal under test using the second frequency division signal based on the sampling interval.

7. The equivalent sampling method according to claim 6, characterized in that, The sampling interval ,in, This indicates the signal period of the signal under test. This represents the integer value of the fractional frequency division coefficient. This indicates that the decimal values ​​in the fractional frequency division coefficients are converted into the numerator values ​​of the fractions. This represents the value of the denominator after converting the decimal value in the fractional frequency division coefficient into a fraction, and c represents the difference between the integer value and the integer value in the decimal frequency division coefficient.

8. An equivalent sampling device, characterized in that, Includes the equivalent sampling circuit described in any one of claims 1 to 5.

Images