Multilayer ceramic capacitor and method for manufacturing multilayer ceramic capacitor

Abstract

The present invention provides a multilayer ceramic electronic component capable of suppressing a decrease in reliability.　A multilayer ceramic capacitor 10 comprises: a laminate 12 having a plurality of ceramic layers 14 and a plurality of internal electrode layers 16; and an external electrode 30 connected to the plurality of internal electrode layers 16. A base electrode layer 32 of the external electrode 30 includes a conductive metal and glasses 40 containing Si and Ba. The glasses 40 include a first glass 41. The first glass 41 includes a surface layer 41a having a compound in which Ba and P are bonded in a portion exposed from a surface 33 of the base electrode layer 32, and a surface layer vicinity region 41b that is located on the inner side relative to the surface layer 41a and / or on the laminate 12 side relative to the surface layer 41a, and that is located in the vicinity of the surface layer 41a. The content of the compound in the surface layer vicinity region 41b is less than the content of the compound in the surface layer 41a.

Description

Multilayer ceramic capacitor and method of manufacturing the same

[0001] The present invention relates to a multilayer ceramic capacitor and a method for manufacturing a multilayer ceramic capacitor.

[0002] Significant demand is expected for multilayer ceramic capacitors (MLCCs) as electronic components mounted on automobiles, electronic components for mobile phones, etc. Multilayer ceramic capacitors include a laminate having internal electrode layers and ceramic layers, and external electrodes.

[0003] Such a typical multilayer ceramic capacitor includes a laminate in which multiple ceramic layers and multiple internal electrode layers are stacked, and external electrodes are formed on the outer surfaces of the laminate. The internal electrode layers are extended to the end faces or side faces of the laminate and connected to the external electrodes. The external electrodes are composed of, for example, a base electrode layer formed by applying a conductive paste to the laminate and firing it, and a plating layer formed on the outer surface of the base electrode layer. The plating layer may be composed of multiple layers as necessary.

[0004] For example, Patent Document 1 discloses a conductive paste for base electrodes that can prevent the intrusion of plating solution and form external electrodes (including base electrode layers) that have excellent connectivity with internal electrode layers. The conductive paste for base electrodes in Patent Document 1 contains metal powder, and the particle size of this metal powder is adjusted. This improves the packing density of the metal powder and forms a dense sintered body. This prevents the intrusion of plating solution and improves the reliability of multilayer ceramic capacitors. Furthermore, limiting the amount of glass powder in the conductive paste to a predetermined range also prevents the intrusion of plating solution and improves the reliability of multilayer ceramic capacitors.

[0005] Japanese Patent Application Laid-Open No. 2007-294633

[0006] As described above, in Patent Document 1, the reliability of a multilayer ceramic capacitor is improved by adjusting the particle size of the metal powder and the amount of glass powder in the conductive paste. However, there is also a need to improve the reliability of a multilayer ceramic capacitor by using a configuration different from that of Patent Document 1. Here, the present inventors have discovered a new configuration different from that of Patent Document 1 that suppresses the intrusion of a plating solution and improves the reliability of a multilayer ceramic capacitor.

[0007] SUMMARY OF THE INVENTION Therefore, a primary object of the present invention is to provide a multilayer ceramic capacitor and a method for manufacturing the same that can improve reliability.

[0008] A multilayer ceramic capacitor according to the present invention comprises: a laminate including a plurality of ceramic layers and a plurality of internal electrode layers; and an external electrode connected to the plurality of internal electrode layers at portions where the plurality of internal electrode layers are exposed in the laminate; wherein the external electrode includes a base electrode layer and a plating layer disposed on the base electrode layer; the base electrode layer includes a conductive metal and glass containing Si and Ba; the glass includes a first glass; and the first glass includes a surface layer having a compound in which Ba and P are bonded at a portion exposed from the surface of the base electrode layer; and a surface-layer-neighboring region located at least either inside the surface layer or on the laminate side of the surface layer, and located near the surface layer, wherein the content of the compound in the surface-layer-neighboring region is lower than the content of the compound in the surface layer.

[0009] In the multilayer ceramic capacitor according to the present invention, the Ba-P bonded compound contained in the surface layer of the first glass prevents the first glass from dissolving in the plating solution. Therefore, the surface layer functions as a barrier film against the plating solution. This prevents the first glass from being corroded by the plating solution, preventing the plating solution from penetrating into the interior of the multilayer ceramic capacitor (the interior or inner portion of the multilayer ceramic capacitor). This improves the reliability of the multilayer ceramic capacitor.

[0010] A method for manufacturing a multilayer ceramic capacitor according to the present invention includes the steps of: preparing a laminate including a plurality of ceramic layers and a plurality of internal electrode layers; forming a base electrode layer including a conductive metal and glass on the laminate; immersing the laminate on which the base electrode layer has been formed in a solution containing P, thereby configuring the glass to include a first glass; and forming a plating layer on the base electrode layer, thereby forming an external electrode in which the base electrode layer and the plating layer are laminated, wherein the first glass includes a surface layer having a compound in which Ba and P are bonded in a portion exposed from the surface of the base electrode layer, and a surface-layer-neighboring region located at least either inside the surface layer or on the laminate side of the surface layer, and located in the vicinity of the surface layer, and the content of the compound in the surface-layer-neighboring region is lower than the content of the compound in the surface layer.

[0011] In a multilayer ceramic capacitor formed by the manufacturing method of the present invention, the Ba-P bonded compound contained in the surface layer of the first glass prevents the first glass from dissolving in the plating solution. Therefore, the surface layer functions as a barrier film against the plating solution. This prevents the first glass from being corroded by the plating solution and the plating solution from penetrating into the interior (middle and inner portions) of the multilayer ceramic capacitor. This improves the reliability of the multilayer ceramic capacitor.

[0012] According to the present invention, it is possible to provide a multilayer ceramic capacitor and a method for manufacturing a multilayer ceramic capacitor that can improve reliability.

[0013] The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

[0014] 1 is an external perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention; 2 is a cross-sectional view taken along line II-II in FIG. 1; 3 is a cross-sectional view taken along line III-III in FIG. 1; 4 is a partially enlarged cross-sectional view of a first external electrode; 5 (a) to (d) are partially enlarged cross-sectional views showing an example of the positional relationship of each region in a first glass; 6 (a) is a schematic diagram showing how a surface layer is formed in the first glass, and 7 (b) is a schematic diagram showing how a surface layer vicinity region and an internal region are formed in the first glass.

[0015] EMBODIMENTS 1. Multilayer Ceramic Capacitor A multilayer ceramic capacitor will be described as an example of a multilayer ceramic electronic component according to an embodiment of the present invention. In this embodiment, the multilayer ceramic capacitor is a two-terminal multilayer ceramic capacitor.

[0016] Fig. 1 is an external perspective view showing an example of a multilayer ceramic capacitor as a multilayer ceramic electronic component according to an embodiment of the present invention. Fig. 2 is a cross-sectional view taken along line II-II in Fig. 1. Fig. 3 is a cross-sectional view taken along line III-III in Fig. 1. Fig. 4 is a partially enlarged cross-sectional view of a first external electrode.

[0017] As shown in FIGS. 1 to 4, the multilayer ceramic capacitor 10 includes a rectangular parallelepiped laminate 12 and external electrodes 30 disposed on both ends of the laminate 12 .

[0018] (1) Laminate The laminate 12 has a first main surface 12a and a second main surface 12b that face each other in a height direction x (stacking direction), a first side surface 12c and a second side surface 12d that face each other in a width direction y that is perpendicular to the height direction x, and a first end surface 12e and a second end surface 12f that face each other in a length direction z that is perpendicular to the height direction x and the width direction y. The laminate 12 of this embodiment has rounded corners and ridges. Note that the corners refer to the intersections of three adjacent surfaces of the laminate 12, and the ridges refer to the intersections of two adjacent surfaces of the laminate 12. In addition, unevenness or the like may be formed on some or all of the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f.

[0019] The laminate 12 includes an outer layer portion 14a composed of multiple ceramic layers 14 and an inner layer portion 14b composed of one or more ceramic layers 14 and multiple internal electrode layers 16 disposed thereon. The outer layer portion 14a is located on the first main surface 12a side and the second main surface 12b side of the laminate 12. The outer layer portion 14a is an assembly of multiple ceramic layers 14 (first outer layer portion) located between the first main surface 12a and the internal electrode layer 16 closest to the first main surface 12a, and multiple ceramic layers 14 (second outer layer portion) located between the second main surface 12b and the internal electrode layer 16 closest to the second main surface 12b. The region sandwiched between the two outer layer portions 14a is the inner layer portion 14b. In the inner layer portion 14b, the ceramic layers 14 and the internal electrode layers 16 are alternately stacked in the height direction x.

[0020] The portion of the laminate 12 sandwiched between the first outer layer portion and the second outer layer portion, where a first internal electrode layer 16a (described later) and a second internal electrode layer 16b (described later) face each other, is referred to as a facing portion (effective layer portion). The portions between the facing portion and the first side surface 12c and between the facing portion and the second side surface 12d are also referred to as W gaps or side gaps. The portions between the facing portion and the first end surface 12e and between the facing portion and the second end surface 12f, which include the lead electrode portion of either the first internal electrode layer 16a or the second internal electrode layer 16b, are also referred to as L gaps or end gaps.

[0021] The dimensions of the laminate 12 are not particularly limited, but it is preferable that the dimension in the length direction z is 0.39 mm or more and 3.30 mm or less, the dimension in the height direction x is 0.21 mm or more and 2.70 mm or less, and the dimension in the width direction y is 0.21 mm or more and 2.70 mm or less.

[0022] The dielectric material for forming the ceramic layer 14 may be, for example, a dielectric ceramic containing a component such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3. When the dielectric material contains the above-mentioned dielectric material as a main component, a component containing a minor component such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound in a smaller amount than the main component may be added depending on the desired properties of the laminate 12.

[0023] The thickness of the ceramic layers 14 after firing is preferably 0.2 μm or more and 2 μm or less. The number of laminated ceramic layers 14 is preferably 15 to 1,000, and more preferably 0.2 μm or more and 0.55 μm or less. This makes it possible to increase the number of laminated layers, contributing to higher capacity. Note that the number of ceramic layers 14 is the total number of ceramic layers 14 in the inner layer portion 14b and the outer layer portion 14a on the first main surface 12a side and the outer layer portion 14a on the second main surface 12b side.

[0024] The laminate 12 has, as the multiple internal electrode layers 16, multiple first internal electrode layers 16a extended to the first end face 12e and multiple second internal electrode layers 16b extended to the second end face 12f. The multiple first internal electrode layers 16a and multiple second internal electrode layers 16b are embedded in the inner layer portion 14b so as to be alternately arranged at equal intervals with the ceramic layers 14 sandwiched between them along the height direction x of the laminate 12. The surfaces of the multiple first internal electrode layers 16a and the multiple second internal electrode layers 16b are generally parallel to the first main surface 12a and the second main surface 12b, and are, for example, substantially rectangular in plan view.

[0025] The first internal electrode layer 16a is disposed on the plurality of ceramic layers 14 and is located inside the laminate 12 (in the central portion of the laminate 12). The first internal electrode layer 16a has a first opposing electrode portion 26a facing the second internal electrode layer 16b and a first lead electrode portion 28a located on one end side of the first internal electrode layer 16a and extending from the first opposing electrode portion 26a to the first end face 12e of the laminate 12. The end of the first lead electrode portion 28a is extended to the surface of the first end face 12e and exposed from the laminate 12. In other words, the first lead electrode portion 28a is not exposed on the first main surface 12a, the second main surface 12b, the first side face 12c, the second side face 12d, or the second end face 12f. The end of the first opposing electrode portion 26a is located receding in the width direction from the surface of the second end face 12f.

[0026] The shape of the first opposing electrode portion 26a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the first opposing electrode portion 26a may be tapered in plan view, with a slope increasing in either direction.

[0027] The shape of the first lead electrode portion 28a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the first lead electrode portion 28a may be tapered in plan view, with a slope increasing in either direction.

[0028] The width of the first opposing electrode portion 26a of the first internal electrode layer 16a and the width of the first extraction electrode portion 28a of the first internal electrode layer 16a may be formed to be the same width, or one of the widths may be formed to be narrower.

[0029] The second internal electrode layer 16b is disposed on the plurality of ceramic layers 14 and is located inside (inside) the laminate 12. The second internal electrode layer 16b has a second opposing electrode portion 26b facing the first internal electrode layer 16a and a second lead electrode portion 28b located on one end side of the second internal electrode layer 16b and extending from the second opposing electrode portion 26b to the second end face 12f of the laminate 12. The end of the second lead electrode portion 28b is extended to the surface of the second end face 12f and exposed from the laminate 12. In other words, the second lead electrode portion 28b is not exposed on the first main surface 12a, the second main surface 12b, the first side face 12c, the second side face 12d, or the first end face 12e. The end of the second opposing electrode portion 26b is located receding in the width direction from the surface of the first end face 12e.

[0030] The shape of the second opposing electrode portion 26b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the second opposing electrode portion 26b may be tapered in plan view, with a slope increasing in either direction.

[0031] The shape of the second lead electrode portion 28b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the second lead electrode portion 28b may be tapered in plan view, with a slope increasing in either direction.

[0032] The width of the second opposing electrode portion 26b of the second internal electrode layer 16b and the width of the second extraction electrode portion 28b of the second internal electrode layer 16b may be formed to be the same width, or one of the widths may be formed to be narrower.

[0033] The first internal electrode layer 16a and the second internal electrode layer 16b can be made of an appropriate conductive material, for example, a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy. When the laminate 12 including the internal electrode layer 16 and an integrated body including the external electrode 30 on the surface of the laminate 12 are simultaneously fired, the metal constituting the internal electrode layer 16 forms a compound with the metal contained in the external electrode 30.

[0034] The thickness of each of the internal electrode layers 16, i.e., the first internal electrode layers 16a and the second internal electrode layers 16b, is preferably 0.2 μm or more and 2.0 μm or less. It is more preferably 0.2 μm or more and 0.5 μm or less. The total number of the first internal electrode layers 16a and the second internal electrode layers 16b is preferably 15 or more and 1000 or less.

[0035] (2) External Electrodes As shown in FIGS. 1 to 3, external electrodes 30 are disposed on the first end face 12e side and the second end face 12f side of the laminate 12.

[0036] The external electrode 30 includes a first external electrode 30a and a second external electrode 30b.

[0037] The first external electrode 30a is connected to the first internal electrode layer 16a and is disposed on at least the surface of the first end face 12e. In this case, the first external electrode 30a is electrically connected to the first lead electrode portion 28a of the first internal electrode layer 16a. In this embodiment, the first external electrode 30a extends from the first end face 12e and is disposed on a part of the first main surface 12a, a part of the second main surface 12b, and a part of the first side surface 12c, and a part of the second side surface 12d.

[0038] The second external electrode 30b is connected to the second internal electrode layer 16b and is disposed on at least the surface of the second end face 12f. In this case, the second external electrode 30b is electrically connected to the second lead electrode portion 28b of the second internal electrode layer 16b. In this embodiment, the second external electrode 30b extends from the second end face 12f and is disposed on a part of the first main surface 12a and a part of the second main surface 12b, as well as a part of the first side surface 12c and a part of the second side surface 12d.

[0039] In the laminate 12, capacitance is formed by the first opposing electrode portion 26a of the first internal electrode layer 16a and the second opposing electrode portion 26b of the second internal electrode layer 16b facing each other via the ceramic layer 14. Therefore, capacitance can be obtained between the first external electrode 30a connected to the first internal electrode layer 16a and the second external electrode 30b connected to the second internal electrode layer 16b, and the characteristics of a capacitor are exhibited.

[0040] The external electrode 30 is preferably composed of a base electrode layer 32 and a plating layer 34. In this embodiment, the external electrode 30 includes a base electrode layer 32 and a plating layer 34 disposed on the base electrode layer 32. The plating layer 34 includes a first plating layer 34a and a second plating layer 34b. The first external electrode 30a includes a first base electrode layer 32a, a first lower plating layer 34a1 disposed on the first base electrode layer 32a, and a first upper plating layer 34a2 disposed on the first lower plating layer 34a1. The second external electrode 30b includes a second base electrode layer 32b, a second lower plating layer 34b1 disposed on the second base electrode layer 32b, and a second upper plating layer 34b2 disposed on the second lower plating layer 34b1.

[0041] (2-1) Base Electrode Layer The first base electrode layer 32a is connected to the first internal electrode layer 16a and is disposed on the surface of the first end face 12e. In this case, the first base electrode layer 32a is electrically connected to the first lead electrode portion 28a of the first internal electrode layer 16a. In this embodiment, the first base electrode layer 32a extends from the first end face 12e and is disposed on a part of the first main surface 12a, a part of the second main surface 12b, and a part of the first side surface 12c, and a part of the second side surface 12d.

[0042] The second base electrode layer 32b is connected to the second internal electrode layer 16b and is disposed on the surface of the second end face 12f. In this case, the second base electrode layer 32b is electrically connected to the second lead electrode portion 28b of the second internal electrode layer 16b. In this embodiment, the second base electrode layer 32b extends from the second end face 12f and is disposed on a part of the first main surface 12a, a part of the second main surface 12b, a part of the first side surface 12c, and a part of the second side surface 12d.

[0043] The base electrode layer 32 includes a conductive metal and glass. The conductive metal of the base electrode layer 32 includes, for example, at least one selected from Cu, Ni, Ag, Pb, an Ag—Pb alloy, Au, and the like. In this embodiment, the conductive metal is primarily Cu. The glass of the base electrode layer 32 includes primarily Si and Ba. Preferably, the glass of the base electrode layer 32 includes at least one selected from Al, B, Pd, Mg, Li, and the like. The glass of this embodiment includes primarily Si, Ba, and Al. In this embodiment, the glass 40 is configured to suppress elution of the glass 40 during a plating process for the base electrode layer 32. Specifically, as described below, the glass 40 includes a first glass 41. The first glass 41 includes a compound in which Ba and P, which are insoluble in a plating solution during a plating process, are bonded. Therefore, in this embodiment, the first glass 41 contains P as well as Si, Ba, and Al as its components.

[0044] The base electrode layer 32 may be a multi-layer structure. The base electrode layer 32 is formed by applying a conductive paste containing a metal powder and a glass powder to the laminate 12 and baking it, and may be fired simultaneously with the ceramic layers 14 and the internal electrode layers 16, or may be fired after the ceramic layers 14 and the internal electrode layers 16 have been baked. Note that the inclusion of glass in the base electrode layer 32 can improve the adhesion between the laminate 12 and the base electrode layer 32.

[0045] The thicknesses of the first and second baked layers at the center in the height direction x of the first and second base electrode layers 32 a, 32 b located on the first end face 12 e and the second end face 12 f are preferably, for example, about 3 μm to 20 μm. Furthermore, when the base electrode layer 32 is provided on the first and second main faces 12 a, 12 b and the first and second side faces 12 c, 12 d, the thicknesses of the first and second baked layers at the center in the length direction z of the first and second base electrode layers 32 a, 32 b located on the first and second main faces 12 a, 12 b and the first and second side faces 12 c, 12 d are preferably, for example, about 1 μm to 20 μm.

[0046] Next, the glass 40 included in the base electrode layer 32 will be further described. As shown in Fig. 4 , the glass 40 includes a first glass 41 and a second glass 42. A portion of the first glass 41 is exposed on the surface 33 of the base electrode layer 32. On the other hand, the second glass 42 is located closer to the laminate 12 than the surface 33 of the base electrode layer 32, and is not exposed on the surface 33 of the base electrode layer 32.

[0047] In the present embodiment, the first glass 41 contains Si, Ba, and Al as components, as well as P. The first glass 41 includes a surface layer 41a, a surface layer vicinity region 41b, and an internal region 41c.

[0048] The surface layer 41 a is a portion of the first glass 41 that is exposed from the surface 33 of the base electrode layer 32. In other words, the surface layer 41 a is a layer located on the surface of the first glass 41 that is exposed from the surface 33 of the base electrode layer 32.

[0049] The surface layer vicinity region 41b is located at least either inside the surface layer 41a or on the laminate 12 side of the surface layer 41a, and is located near the surface layer 41a. Here, "the surface layer vicinity region 41b is located inside the surface layer 41a" means that the surface layer vicinity region 41b is covered by the surface layer 41a in a state where it is in contact with the surface layer 41a or in a state where it is not in contact with the surface layer 41a. Here, "covered" does not mean that the entire periphery of the surface layer vicinity region 41b is covered by the surface layer 41a, but rather that only the portion of the surface layer vicinity region 41b that protrudes from the surface 33 of the base electrode layer 32 is covered.

[0050] The position where the surface layer neighboring region 41b is formed will be described with reference to Fig. 5. In Fig. 5, (a) to (d) are partially enlarged cross-sectional views showing an example of the positional relationship of each region in the first glass.

[0051] An example of the positional relationship between the surface layer neighborhood 41b and the surface layer 41a is shown in FIG. 5( a). In FIG. 5( a), a portion of the surface layer neighborhood 41b protrudes from the surface 33 of the base electrode layer 32. That is, the surface layer neighborhood 41b is configured by a continuous combination of a portion protruding from the surface 33 of the base electrode layer 32 and a portion located closer to the laminate 12 than the surface 33 of the base electrode layer 32. The protruding portion of the surface layer neighborhood 41b is covered by the surface layer 41a with the surface 41b1 of the protruding portion in contact with the surface layer 41a, and is located inside the surface layer 41a. The portion of the surface layer neighborhood 41b located closer to the laminate 12 than the surface 33 of the base electrode layer 32 is the portion of the surface layer neighborhood 41b other than the portion protruding from the surface 33 of the base electrode layer 32. Note that another layer may be interposed between the surface layer neighborhood 41b and the surface layer 41a, so that the surface 41b1 is not in contact with the surface layer 41a.

[0052] Further, an example of the positional relationship between the surface layer neighborhood 41b and the surface layer 41a is the state shown in FIG. 5(b). In FIG. 5(b), the entire surface layer neighborhood 41b protrudes from the surface 33 of the base electrode layer 32. The entire surface layer neighborhood 41b is covered by the surface layer 41a with its surface 41b1 in contact with the surface layer 41a, and is located inside the surface layer 41a. It is preferable that the back surface 41b2 of the surface layer neighborhood 41b on the laminate 12 side is generally flush with the surface 33 of the base electrode layer 32. Another layer may be interposed between the surface layer neighborhood 41b and the surface layer 41a, and the surface 41b1 may be in a state of not contacting the surface layer 41a.

[0053] 5C, the surface layer near-region 41b is generally flush with the surface 33 of the base electrode layer 32, and the entire surface layer near-region 41b is in contact with the surface layer 41a, with the surface 41b being in contact with the surface layer 41a, and the entire surface layer near-region 41b being located on the laminate 12 side of the surface layer 41a.

[0054] 5(d) is an example of the positional relationship between the surface layer near region 41b and the surface layer 41a. In FIG. 5(d), the entire surface layer near region 41b is located closer to the laminate 12 than the surface 33 of the base electrode layer 32. Another layer is interposed between the surface layer near region 41b and the surface layer 41a, and the entire surface layer near region 41b is located closer to the laminate 12 than the surface layer 41a, with the surface 41b not in contact with the surface layer 41a.

[0055] The term "surface layer vicinity region 41b is located in the vicinity of surface layer 41a" includes both the surface layer vicinity region 41b being in contact with surface layer 41a and the surface layer vicinity region 41b being located near but not in contact with surface layer 41a.

[0056] The internal region 41c is located inside the base electrode layer 32 (inside the base electrode layer 32), and is located closer to the surface layer neighborhood region 41b on the laminate 12 side than the surface layer neighborhood region 41b. Note that the internal region 41c being located close to the surface layer neighborhood region 41b means that the internal region 41c is in contact with the surface layer neighborhood region 41b, and also means that the internal region 41c is located close to but not in contact with the surface layer neighborhood region 41b.

[0057] The surface layer 41a contains a compound in which Ba and P are bonded. The compound in which Ba and P are bonded contained in the surface layer 41a suppresses dissolution of the first glass 41 in a plating solution. In other words, when a plating layer 34 is formed on the base electrode layer 32 using a plating solution, the surface layer 41a of the first glass 41 exposed at the base electrode layer 32 contains a compound in which Ba and P are bonded, which is difficult to dissolve in a plating solution. Therefore, the surface layer 41a functions as a barrier film against the plating solution. This suppresses erosion of the first glass 41 by the plating solution.

[0058] If the glass 40 is dissolved by the plating solution, the following problems may occur. For example, the base electrode layer 32 may be eroded by the plating solution, resulting in a decrease in the flatness of the surface 33 of the base electrode layer 32; the base electrode layer 32 may be eroded by the plating solution, resulting in a disconnection; or the plating solution may penetrate into the interior (inside) of the multilayer ceramic capacitor 10 through the eroded portion. However, in the multilayer ceramic capacitor 10 configured as described above, the first glass 41 is contained in the base electrode layer 32, thereby preventing the above-mentioned problems. That is, since the first glass 41 is prevented from being eroded by the plating solution, it is possible to prevent the decrease in flatness of the surface 33 of the base electrode layer 32 due to the erosion by the plating solution, prevent the disconnection of the base electrode layer 32 due to the erosion by the plating solution, and prevent the penetration of the plating solution into the interior (inside) of the multilayer ceramic capacitor 10.

[0059] As a result, when plating is performed on the base electrode layer 32, it is possible to achieve improved reliability, such as suppressing poor plating on the base electrode layer 32, suppressing a decrease in the conductivity of the base electrode layer 32, and suppressing a decrease in the moisture resistance reliability of the multilayer ceramic capacitor 10.

[0060] In the present embodiment, the compound in which Ba and P are bonded in the surface layer 41 a is barium pyrophosphate 2.35 hydrate, which is a substance insoluble in water and can prevent the first glass 41 from dissolving into the plating solution.

[0061] Furthermore, the content of compounds in which Ba and P are bonded in the surface layer vicinity region 41b is lower than the content of compounds in which Ba and P are bonded in the surface layer 41a. Alternatively, compounds in which Ba and P are bonded are almost or completely absent in the surface layer vicinity region 41b. The content of Ba not bonded to P in the surface layer vicinity region 41b is higher than the content of Ba not bonded to P in the surface layer 41a. For example, all of the Ba present in the surface layer vicinity region 41b is not bonded to P, or even if Ba in a state bonded to P is present in the surface layer vicinity region 41b, the amount of Ba bonded to P is less than in the surface layer 41a. Therefore, Ba not bonded to P can exist in the surface layer vicinity region 41b as, for example, Ba oxide, which can improve the adhesion between the internal electrode layer 16 and the base electrode layer 32.

[0062] The Si content in the surface layer vicinity region 41 b is greater than the Si content in the surface layer 41 a. Although the Si content in the surface layer 41 a is small, by ensuring the Si content in the surface layer vicinity region 41 b, it is possible to improve the adhesion between the internal electrode layer 16 and the base electrode layer 32.

[0063] Furthermore, the Al content in the surface layer vicinity region 41b is greater than the Al content in the surface layer 41a. Although the Al content is low in the surface layer 41a, the Al content can be ensured in the surface layer vicinity region 41b. This Al may exist as Al oxide. The presence of this Al oxide improves the chemical durability of the first glass 41 and prevents the thermal expansion coefficient from becoming too large. Furthermore, the Al content in the surface layer vicinity region 41b is greater than the Al content in the internal region 41c.

[0064] The Si content in the surface layer vicinity region 41b is greater than the Si content in the internal region 41c. Furthermore, the Ba content not bonded to P in the surface layer vicinity region 41b is less than the Ba content not bonded to P in the internal region 41c. Because the Ba content not bonded to P in the surface layer vicinity region 41b is less than that in the internal region 41c, the surface layer vicinity region 41b exists as a region with less Ba that is likely to dissolve in the plating solution. Therefore, dissolution of the first glass 41 can be suppressed.

[0065] In this embodiment, the second glass 42 contains Si, Ba, and Al as components. Unlike the first glass 41, the second glass 42 does not contain a compound in which Ba and P are bonded. The second glass 42 is located closer to the laminate 12 than the surface 33 of the base electrode layer 32. That is, the second glass 42 is not exposed to the surface 33 of the base electrode layer 32. Because the second glass 42 is not exposed to the surface 33 of the base electrode layer 32, it is not exposed to the plating solution used to form a plating layer on the base electrode layer 32. Therefore, there is no need to form a layer on the second glass 42 to suppress corrosion by the plating solution, and no treatment for this purpose is required. Therefore, the second glass 42 does not include a surface layer 41a that is insoluble in the plating solution, as does the first glass 41. Furthermore, the second glass 42 does not include a surface layer vicinity region 41b. In other words, the second glass 42 is composed of layers that are generally equivalent to those in the internal region 41c of the first glass 41. Due to the presence of Si, Ba, Al, etc., the second glass 42 can contribute to improving the adhesion between the internal electrode layer 16 and the base electrode layer 32 more than the first glass 41.

[0066] (2-2) Plating Layer Next, the first plating layer 34a and the second plating layer 34b, which are the plating layers 34 disposed on the base electrode layer 32, will be described with reference to FIGS.

[0067] The first plating layer 34a is disposed so as to cover the first base electrode layer 32a on the first end face 12e side. Furthermore, the first plating layer 34a may be disposed so as to cover the first base electrode layer 32a on the first main surface 12a, the second main surface 12b, the first side surface 12c, and the second side surface 12d side. However, the first plating layer 34a may be disposed only on the first base electrode layer 32a on the first end face 12e side.

[0068] The second plating layer 34b is disposed so as to cover the second base electrode layer 32b on the second end face 12f side. Furthermore, the second plating layer 34b may be disposed so as to cover the second base electrode layer 32b on the first principal surface 12a, the second principal surface 12b, the first side surface 12c, and the second side surface 12d side. However, the second plating layer 34b may be disposed only on the second base electrode layer 32b on the second end face 12f side.

[0069] The first plating layer 34a and the second plating layer 34b contain at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, an Ag--Pd alloy, Au, and the like.

[0070] The plating layer 34 may be formed of multiple layers. For example, the first plating layer 34a has a two-layer structure consisting of a first lower-layer plating layer 34a1 and a first upper-layer plating layer 34a2 covering the first lower-layer plating layer 34a1, and the second plating layer 34b has a two-layer structure consisting of a second lower-layer plating layer 34b1 and a second upper-layer plating layer 34b2 covering the second lower-layer plating layer 34b1. It is preferable that the first lower-layer plating layer 34a1 and the second lower-layer plating layer 34b1 are Ni plating layers, and the first upper-layer plating layer 34a2 and the second upper-layer plating layer 34b2 are Sn plating layers.

[0071] The first and second lower plating layers 34a1, 34b1 made of Ni plating are used to prevent the base electrode layer 32 from being eroded by solder when mounting the multilayer ceramic capacitor 10. The first and second upper plating layers 34a2, 34b2 made of Sn plating are used to improve the wettability of the solder when mounting the multilayer ceramic capacitor 10, thereby facilitating mounting.

[0072] The first and second lower plating layers 34a1, 34b1 made of Ni plating layers are preferably 1 μm or more and 15 μm or less, and the first and second upper plating layers 34a2, 34b2 made of Sn plating layers are preferably 1 μm or more and 15 μm or less.

[0073] The first and second upper plating layers 34a, 34b may be omitted. In addition, the plating layer 34 may have the first and second upper plating layers 34a, 34b as the outermost layers, or other plating electrodes may be formed on the surfaces of the first and second upper plating layers 34a, 34b.

[0074] (3) Dimensions of the Multilayer Ceramic Capacitor The dimension in the length direction z of the multilayer ceramic capacitor 10 including the laminate 12, the first external electrode 30a, and the second external electrode 30b is defined as dimension L, the dimension in the height direction x of the multilayer ceramic capacitor 10 including the laminate 12, the first external electrode 30a, and the second external electrode 30b is defined as dimension T, and the dimension in the width direction y of the multilayer ceramic capacitor 10 including the laminate 12, the first external electrode 30a, and the second external electrode 30b is defined as dimension W. The dimensions of the multilayer ceramic capacitor 10 are as follows: L in the length direction z is 0.2 mm to 1.8 mm, W in the width direction y is 0.1 mm to 1.0 mm, and T in the height direction x is 0.1 mm to 1.0 mm. The dimensions of the multilayer ceramic capacitor 10 can be measured using a microscope.

[0075] 2. Method for Manufacturing a Multilayer Ceramic Capacitor Next, a method for manufacturing a multilayer ceramic capacitor will be described.

[0076] (Step 1) First, a dielectric sheet for the ceramic layer and a conductive paste for the internal electrode layer are prepared. The dielectric sheet and the conductive paste for the internal electrode layer contain a binder and a solvent. The binder and the solvent may be known.

[0077] (Step 2) Then, a conductive paste for the internal electrode layers is printed in a predetermined pattern on the dielectric sheet by, for example, screen printing, gravure printing, etc. In this way, a dielectric sheet on which the pattern of the first internal electrode layer is formed, and a dielectric sheet on which the pattern of the second internal electrode layer is formed are prepared.

[0078] Furthermore, with regard to the dielectric sheets, outer layer dielectric sheets on which no internal electrode layer patterns are printed are also prepared.

[0079] A predetermined number of dielectric sheets for outer layers, on which no pattern of internal electrode layers is printed, are laminated. A dielectric sheet on which a pattern of a first internal electrode layer is printed and a dielectric sheet on which a pattern of a second internal electrode layer is printed are sequentially laminated on top of the dielectric sheets to form a portion that will become the inner layer portion 14b. A predetermined number of dielectric sheets for outer layers, on which no pattern of internal electrode layers is printed, are laminated on top of the portion that will become the inner layer portion 14b. This forms a laminate sheet having the inner layer portion 14b and the outer layer portion.

[0080] (Step 4) Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0081] (Step 5) The laminated block is then cut to a predetermined size to obtain laminated chips. At this time, the corners and ridges of the laminated chips may be rounded by barrel polishing or the like.

[0082] (Step 6) Next, the laminated chip is fired to produce the laminate 12. The firing temperature depends on the materials of the ceramic layers, which are dielectrics, and the internal electrode layers, but is preferably 900°C or higher and 1400°C or lower. Steps 1 to 6 constitute the laminate formation process.

[0083] (Step 7) Next, the first external electrode 30a and the second external electrode 30b are formed on the first end face 12e and the second end face 12f of the laminate 12. That is, first, a base electrode layer paste is applied to the first end face 12e and the second end face 12f of the laminate 12 and baked to form the first base electrode layer 32a of the first external electrode 30a and the second base electrode layer 32b of the second external electrode 30b. The baking temperature is preferably 700°C or higher and 900°C or lower. The base electrode layer paste contains a metal powder whose main component is Cu and a glass powder containing Si, Ba, and Al as components. The metal powder and glass powder in the base electrode paste are contained as conductive metal and glass 40 in the base electrode layer 32 by the above-mentioned baking.

[0084] (Step 8) Next, the glass 40 exposed on the surface of the base electrode layer 32 is treated. As a result, the base electrode layer 32 includes the glass 40 including the first glass 41 and the second glass 42. This will be described in detail below.

[0085] The laminate 12 on which the base electrode layer 32 is formed is immersed in a pyrophosphate-based Cu plating solution in a non-energized state. The pyrophosphate-based Cu plating solution has a pyrophosphate concentration of 0.02 mol / L to 3 mol / L and a Cu concentration (Cu ion concentration) of 0.01 mol / L to 1.5 mol / L. More preferably, the pyrophosphate concentration is 0.1 mol / L to 2 mol / L and a Cu concentration (Cu ion concentration) of 0.05 mol / L to 1 mol / L. The pyrophosphate-based Cu plating solution is preferably stirred while the laminate 12 on which the base electrode layer 32 is formed is immersed. This allows the glass 40 of the base electrode layer 32 exposed on the surface 33 of the base electrode layer 32 to be treated with the pyrophosphate-based Cu plating solution, facilitating the production of the first glass 41. When the temperature of the plating solution is, for example, about 40° C. or higher and 95° C. or lower, the first glass 41 is likely to be produced.

[0086] When the laminate 12 on which the base electrode layer 32 is formed is immersed in a pyrophosphate-based Cu plating solution, the first glass 41 is thought to be formed as follows: In Fig. 6, (a) is a schematic diagram showing how a surface layer is formed on the first glass, and (b) is a schematic diagram showing how a surface layer vicinity region and an internal region are formed on the first glass.

[0087] First, when the laminate 12 on which the base electrode layer 32 is formed is immersed in a pyrophosphate-based Cu plating solution 45 in an unenergized state, the exposed portion 40a of the glass 40, which is exposed on the surface 33 of the base electrode layer 32, reacts with the pyrophosphate-based Cu plating solution 45. At this time, as shown in FIG. 6A , Ba near the exposed portion 40a of the glass 40 is eluted into the pyrophosphate-based Cu plating solution 45. The eluted Ba reacts with P in the pyrophosphate-based Cu plating solution 45, and a compound in which Ba and P are bonded, i.e., barium pyrophosphate 2.35 hydrate in this embodiment, is formed on the surface of the exposed portion 40a of the glass 40. This forms a first glass 41 having a surface layer 41a containing barium pyrophosphate 2.35 hydrate.

[0088] Furthermore, Ba near the exposed portion 40a is eluted into the pyrophosphate-based Cu plating solution 45, thereby forming a Ba-deficient area inside the surface layer 41a, as shown in FIG. 6( a). Si, Al, and the like migrate to this Ba-deficient area. For example, Si and Al migrate from the area including the Ba-deficient area, or from an area closer to the laminate 12 than the Ba-deficient area. As a result, a surface layer vicinity region 41b is formed in the first glass 41, where Si, Al, and the like migrate to the Ba-deficient area, and an internal region 41c is formed closer to the laminate 12 than the surface layer vicinity region 41b.

[0089] The respective contents of Al, Si, Ba, and P in the surface layer 41a, the surface-near region 41b, and the internal region 41c are, for example, as follows:

[0090]

[0091] The sum of the mass percentages of Al, Si, Ba, and P in the surface layer 41a, the surface-near region 41b, and the internal region 41c does not necessarily have to be 100%, and other elements may be included. Examples of other elements include at least one of Li, Na, K, Be, Mg, Ca, Sr, Bi, Zn, Ga, Pb, Ti, Zr, Sn, Cu, Mn, Co, Ni, Fe, Nb, La, V, C, N, O, S, F, and Cl. The surface layer 41a is primarily composed of barium pyrophosphate hydrate. Therefore, Al and Si are almost absent in the surface layer 41a, with Al and Si each being, for example, 5% by mass or less. The total mass percentage of the two elements Ba and P in the surface layer 41a is 60% by mass or more. The remainder of the surface layer 41a is filled with oxygen, hydrates, and trace amounts of other elements. Furthermore, each component contained in the glass 40 exists as an oxide, and the aforementioned oxygen includes oxygen derived from Ba and P. Furthermore, the Al, Si, and Ba in the surface layer vicinity region 41b and the internal region 41c have the following relationships (i) and (ii): (i) Al and Si in the surface layer vicinity region 41b > Al and Si in the internal region 41c (ii) Ba in the surface layer vicinity region 41b < Ba in the internal region 41c Furthermore, it is not necessary for at least one of Al, Si, and Ba to have the highest mass% in the surface layer vicinity region 41b and the internal region 41c; for example, B may have the highest mass% depending on the type of glass.

[0092] 6( b), the thickness of each layer in the first glass 41 is defined as follows: the distance from the surface of the surface layer 41a to the surface of the surface-layer-neighborhood region 41b is defined as the thickness ta of the surface layer 41a; the distance from the surface of the surface-layer-neighborhood region 41b to the surface of the internal region 41c is defined as the thickness tb of the surface-layer-neighborhood region 41b; and the distance from the surface of the internal region 41c to the back surface of the first glass 41. The ratio of the thicknesses of the layers is, for example, ta:tb:tc = 1 to 33.3:1 to 33.3:33.3 to 98. Here, the surface refers to the surface on which the base electrode layer 32 is exposed, and the back surface refers to the surface opposite to the side on which the base electrode layer 32 is exposed.

[0093] (Step 9) Next, the plating layer 34 is formed. In this embodiment, the plating layer 34 is formed on the surface 33 of the base electrode layer 32. More specifically, a Ni plating layer and a Sn plating layer are formed on the base electrode layer 32. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is usually preferable to use electrolytic plating. As the plating method, barrel plating is preferably used.

[0094] In the manner described above, the multilayer ceramic capacitor 10 according to this embodiment is manufactured.

[0095] (1) In the above embodiment, the first glass 41 is conveniently divided into three regions: the surface layer 41a, the surface-near-layer region 41b, and the internal region 41c. However, except for the fact that a compound in which Ba and P are bonded is formed on the surface of the first glass 41, the first glass 41 may be composed of any number of layers. For example, the first glass 41 may be divided into any number of layers depending on the content of Si, Al, Ba, etc.

[0096] (2) In the above embodiment, the glass 40 includes the second glass 42 in addition to the first glass 41. However, the glass may include only the first glass. However, if the glass 40 includes the second glass, it is preferable because the adhesion between the base electrode layer and the internal electrode layer can be further improved.

[0097] (3) In the above embodiment, a two-terminal multilayer ceramic capacitor having two terminals, a first external electrode 30a and a second external electrode 30b, has been described as a multilayer ceramic electronic component. However, the present invention is not limited to a two-terminal multilayer ceramic capacitor and can be applied to multilayer ceramic electronic components having external electrodes. For example, the present invention may be applied to a three-terminal multilayer ceramic capacitor. A three-terminal multilayer ceramic capacitor includes a laminate 12 similar to the above embodiment and first to fourth external electrodes. The internal electrode layers 16 include a first internal electrode layer extending to the first end face 12e and the second end face 12f, and a second internal electrode layer extending to the first side face 12c and the second side face 12d. A first external electrode is disposed on the first end face 12e of the laminate 12. The first external electrode is electrically connected to the first internal electrode layer exposed at the first end face 12e of the laminate 12. A second external electrode is disposed on the second end face 12f of the laminate 12. The second external electrode is electrically connected to the first internal electrode layer exposed at the second end face 12f of the laminate 12. A third external electrode is disposed on the first side face 12c of the laminate 12. The third external electrode is electrically connected to the second internal electrode layer exposed at the first side face 12c of the laminate 12. A fourth external electrode is disposed on the second side face 12d of the laminate 12. The fourth external electrode is electrically connected to the second internal electrode layer exposed at the second side face 12d of the laminate 12.

[0098] Each of the first to fourth external electrodes is formed by sequentially laminating a base electrode layer, a resin electrode layer, and a plating layer, as in the above-described embodiment. The resin electrode layer contains a conductive filler and a resin.

[0099] <1> A multilayer ceramic capacitor comprising: a laminate including a plurality of ceramic layers and a plurality of internal electrode layers; and external electrodes connected to the plurality of internal electrode layers at portions where the plurality of internal electrode layers are exposed in the laminate, wherein the external electrodes include a base electrode layer and a plating layer disposed on the base electrode layer, the base electrode layer including a conductive metal and glass containing Si and Ba, the glass including a first glass, the first glass including: a surface layer having a compound in which Ba and P are bonded in a portion exposed from a surface of the base electrode layer; and a surface-layer-neighboring region located at least either inside the surface layer or on the laminate side of the surface layer, and located in the vicinity of the surface layer, wherein a content of the compound in the surface-layer-neighboring region is lower than a content of the compound in the surface layer.

[0100] <2> The multilayer ceramic capacitor according to <1>, wherein the content of Ba not bonded to P in the surface layer vicinity region is greater than the content of Ba not bonded to P in the surface layer.

[0101] <3> The multilayer ceramic capacitor according to <1> or <2>, wherein the Si content in the surface layer vicinity region is higher than the Si content in the surface layer.

[0102] <4> The multilayer ceramic capacitor according to any one of <1> to <3>, wherein the glass further contains Al, and the Al content in the surface layer vicinity region is higher than the Al content in the surface layer.

[0103] <5> The multilayer ceramic capacitor according to any one of <1> to <4>, wherein the first glass is located inside the base electrode layer, and further includes an internal region located closer to the laminate than the surface layer vicinity region and closer to the surface layer vicinity region, wherein the surface layer vicinity region has a higher Si content than the internal region, and wherein the surface layer vicinity region has a lower Ba content than the Ba content that is not bonded to P than the internal region.

[0104] <6> The multilayer ceramic capacitor according to <5>, wherein the glass further contains Al, and the Al content in the surface layer vicinity region is higher than the Al content in the inner region.

[0105] <7> The multilayer ceramic capacitor according to any one of <1> to <6>, wherein the glass is located closer to the laminate than the surface of the base electrode layer and further includes a second glass that does not contain the compound.

[0106] <8> The multilayer ceramic capacitor according to any one of <1> to <7>, wherein the compound is barium pyrophosphate 2.35 hydrate.

[0107] <9> The multilayer ceramic capacitor according to any one of <1> to <8>, wherein the plating layer includes a lower-layer plating layer and an upper-layer plating layer formed on a surface of the lower-layer plating layer, the lower-layer plating layer being a Ni plating layer, and the upper-layer plating layer being a Sn plating layer.

[0108] <10> A method for manufacturing a multilayer ceramic capacitor, comprising: a step of preparing a laminate including a plurality of ceramic layers and a plurality of internal electrode layers; a step of forming a base electrode layer including a conductive metal and glass on the laminate; a step of configuring the glass to include a first glass by immersing the laminate on which the base electrode layer has been formed in a solution containing P; and a step of forming a plating layer on the base electrode layer to form an external electrode in which the base electrode layer and the plating layer are laminated, wherein the first glass includes a surface layer having a compound in which Ba and P are bonded in a portion exposed from a surface of the base electrode layer, and a surface-layer-neighboring region located at least either inside the surface layer or on the laminate side of the surface layer and in the vicinity of the surface layer, and a content of the compound in the surface-layer-neighboring region is lower than a content of the compound in the surface layer.

[0109] <11> The method for manufacturing a multilayer ceramic capacitor according to <10>, wherein the base electrode layer contains Cu as the conductive metal.

[0110] <12> The method for producing a multilayer ceramic capacitor according to <10> or <11>, wherein the solution containing P is a pyrophosphate-based Cu plating solution.

[0111] REFERENCE SIGNS LIST 10: Multilayer ceramic capacitor 12: Laminate 12a: First main surface 12b: Second main surface 12c: First side surface 12d: Second side surface 12e: First end surface 12f: Second end surface 14: Ceramic layer 14a, 14b: Outer layer portion, inner layer portion 16: Internal electrode layer 16a, 16b: First and second internal electrode layers 26a, 26b: First and second opposing electrode portions 28a, 28b: First and second extraction electrode portions 30: External electrodes 30a, 30b: First and second external electrodes 32: Base electrode layer 32a, 32b: First and second base electrode layer 34: Plating layer 34a: First plating layer 34b : second plating layer 34a1, 34b1: first and second lower plating layers 34a2, 34b2: first and second upper plating layers 40: glass 40a: exposed portion 41: first glass 41a: surface layer 41b: surface layer vicinity region 41c: internal region 42: second glass x: height direction y: width direction z: length direction

Claims

1. A multilayer ceramic capacitor including a laminate including a plurality of ceramic layers and a plurality of internal electrode layers, and an external electrode connected to the plurality of internal electrode layers at a portion where the plurality of internal electrode layers are exposed in the laminate, wherein the external electrode includes a base electrode layer and a plating layer disposed on the base electrode layer, the base electrode layer includes a conductive metal and a glass having Si and Ba, the glass includes a first glass, the first glass includes a surface layer having a compound in which Ba and P are bonded at a portion exposed from the surface of the base electrode layer, and a surface layer vicinity region located at least on either the inner side with respect to the surface layer or the laminate side with respect to the surface layer and in the vicinity of the surface layer, and the content of the compound in the surface layer vicinity region is less than the content of the compound in the surface layer.

2. The multilayer ceramic capacitor according to claim 1, wherein the content of Ba not bonded to P in the surface layer vicinity region is greater than the content of Ba not bonded to P in the surface layer.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein the content of Si in the surface layer vicinity region is greater than the content of Si in the surface layer.

4. The glass further contains Al, and the content of Al in the surface layer vicinity region is greater than the content of Al in the surface layer. The multilayer ceramic capacitor according to any one of claims 1 to 3.

5. The first glass is located inside the base electrode layer, further includes an internal region located closer to the laminate side than the surface layer vicinity region and in the vicinity of the surface layer vicinity region, the content of Si in the surface layer vicinity region is greater than the content of Si in the internal region, and the content of Ba not bonded to P in the surface layer vicinity region is less than the content of Ba not bonded to P in the internal region. The multilayer ceramic capacitor according to any one of claims 1 to 4.

6. The glass further contains Al, and the content of Al in the surface layer vicinity region is greater than the content of Al in the internal region. The multilayer ceramic capacitor according to claim 5.

7. The laminated ceramic capacitor according to any one of claims 1 to 6, wherein the glass is located on the laminate side with respect to the surface of the base electrode layer and further includes a second glass that does not contain the compound.

8. The laminated ceramic capacitor according to any one of claims 1 to 7, wherein the compound is barium pyrophosphate dihydrate.

9. The laminated ceramic capacitor according to any one of claims 1 to 8, wherein the plating layer includes a lower plating layer and an upper plating layer formed on the surface of the lower plating layer, the lower plating layer is a Ni plating layer, and the upper plating layer is a Sn plating layer.

10. A method for manufacturing a laminated ceramic capacitor, comprising: preparing a laminate including a plurality of ceramic layers and a plurality of internal electrode layers; forming a base electrode layer including a conductive metal and glass on the laminate; immersing the laminate having the base electrode layer formed therein in a solution containing P so that the glass is configured to include a first glass; forming a plating layer on the base electrode layer to form an external electrode in which the base electrode layer and the plating layer are laminated, wherein the first glass includes a surface layer having a compound in which Ba and P are bonded at a portion exposed from the surface of the base electrode layer, and a surface layer vicinity region that is located at least either inside the surface layer or on the laminate side with respect to the surface layer and is located in the vicinity of the surface layer, and the content of the compound in the surface layer vicinity region is less than the content of the compound in the surface layer.

11. The method for manufacturing a laminated ceramic capacitor according to claim 10, wherein the base electrode layer includes Cu as the conductive metal.

12. The method for manufacturing a laminated ceramic capacitor according to claim 10 or 11, wherein the solution containing P is a pyrophosphate-based Cu plating solution.

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