Back-contact cell with specific front-side passivation structure, and preparation method therefor and application thereof

Abstract

The present application belongs to the technical field of back-contact cells, and specifically relates to a back-contact cell with a specific front-side passivation structure, and a preparation method therefor and the application thereof. The back-contact cell comprises a silicon wafer having a front side and a back side, a first semiconductor layer and a second semiconductor layer which are both disposed on the back side of the silicon wafer, and a third semiconductor layer and an antireflective layer which are sequentially disposed outwardly on the front side of the silicon wafer, wherein the third semiconductor layer includes a first intrinsic hydrogenated amorphous silicon layer and an intrinsic oxygen-doped microcrystalline silicon layer which are sequentially disposed outwardly, and the antireflective layer includes a phosphorus-doped silicon nitride layer, a non-phosphorus-doped silicon nitride layer and an oxide layer which are sequentially disposed outwardly. The back-contact cell of the present application can reduce investment in a plate-type PECVD chamber while ensuring a front-side passivation effect, such that investment in devices is reduced, the process flow is simplified, and both the cell density and cell conversion efficiency are improved while the manufacturing costs are reduced.

Description

Back contact battery with specific front passivation structure and preparation method and application thereof

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 2024100578369 filed with the Patent Office of China on January 16, 2024, entitled “Back contact battery with specific front passivation structure, preparation method and application thereof”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application belongs to the technical field of back-contact batteries, and specifically relates to a back-contact battery with a specific front passivation structure, and a preparation method and application thereof. Background Art

[0004] At present, the first semiconductor layer and the second semiconductor layer in the back-contact battery are distributed on the back of the battery silicon wafer. The front is generally provided with a field passivation layer and an anti-reflection layer. The field passivation layer often uses an intrinsic amorphous silicon layer superimposed with a doped (N-type) amorphous / microcrystalline silicon layer as the third semiconductor layer. The intrinsic amorphous silicon layer, the doped amorphous / microcrystalline silicon layer and the anti-reflection layer are generally formed by coating separately in three or four chambers of plate-type PECVD (the two middle chambers are used to deposit the N layer).

[0005] However, plate-type PECVD equipment is very expensive, and the three or four chambers of plate-type PECVD (the two middle chambers deposit the N-type doping layer) are coated separately, resulting in a long cycle time. Therefore, the current back-contact battery has problems such as long process flow and high equipment investment.

[0006] It should be noted that this part of the content of this application only provides background technology related to this application, and does not necessarily constitute prior art or public knowledge.

[0007] Summary of the Invention

[0008] The purpose of this application is to overcome the defects of the back-contact battery structure in the prior art, which has a long process flow and high equipment investment while ensuring the battery conversion efficiency, and to provide a back-contact battery with a specific front passivation structure and its preparation method and application. The back-contact battery can reduce the investment in one chamber of plate-type PECVD while ensuring the front passivation effect, thereby reducing the equipment investment, simplifying the process flow, and reducing the production cost while taking into account the improvement of battery density and battery conversion efficiency.

[0009] In order to achieve the above-mentioned objectives, in a first aspect, the present application provides a back-contact battery with a specific front passivation structure, comprising a silicon wafer having a front and a back, a first semiconductor layer and a second semiconductor layer respectively arranged on the back of the silicon wafer, and a third semiconductor layer and an anti-reflection layer arranged outward in sequence on the front of the silicon wafer, wherein the third semiconductor layer comprises a first intrinsic hydrogenated amorphous silicon layer and an intrinsic oxygen-doped microcrystalline silicon layer arranged outward in sequence, and the anti-reflection layer comprises a phosphorus-doped silicon nitride layer, a non-phosphorus-doped silicon nitride layer and an oxide layer arranged outward in sequence.

[0010] In some preferred embodiments of the present application, the band gap width of the first intrinsic hydrogenated amorphous silicon layer is between 1.6-1.9 eV, and the band gap width of the intrinsic oxygen-doped microcrystalline silicon layer is between 1.9-2.2 eV.

[0011] In some preferred embodiments of the present application, the ratio of the band gaps of the first intrinsic hydrogenated amorphous silicon layer and the intrinsic oxygen-doped microcrystalline silicon layer is 1:(1-1.375).

[0012] In some preferred embodiments of the present application, the oxygen doping concentration of the intrinsic oxygen-doped microcrystalline silicon layer is between 1018 cm-3 and 1019 cm-3.

[0013] In some preferred embodiments of the present application, the thickness of the first intrinsic hydrogenated amorphous silicon layer is 1-2 nm, and the thickness of the intrinsic oxygen-doped microcrystalline silicon layer is 2-6 nm.

[0014] In some preferred embodiments of the present application, the thickness ratio of the first intrinsic hydrogenated amorphous silicon layer to the intrinsic oxygen-doped microcrystalline silicon layer is 1:(1-6).

[0015] In some preferred embodiments of the present application, the thickness ratio of the phosphorus-doped silicon nitride layer, the non-phosphorus-doped silicon nitride layer and the oxide layer is 1:(0.8-1.5):(20-37).

[0016] In some preferred embodiments of the present application, the thickness of the phosphorus-doped silicon nitride layer is 30-85 nm.

[0017] In some preferred embodiments of the present application, the refractive index of the phosphorus-doped silicon nitride layer is between 1.85 and 2.0, the refractive index of the non-phosphorus-doped silicon nitride layer is between 2.05 and 2.15, and the refractive index of the oxide layer is between 1.4 and 1.6.

[0018] In some preferred embodiments of the present application, the phosphorus doping concentration of the phosphorus-doped silicon nitride layer is between 1018 cm-3 and 1021 cm-3, and / or the phosphorus doping concentration of the phosphorus-doped silicon nitride layer first increases and then decreases.

[0019] In some preferred embodiments of the present application, the phosphorus doping concentration of the phosphorus-doped silicon nitride layer first increases and then decreases, and in the outward direction perpendicular to the silicon wafer, for the region where the unit thickness of the phosphorus-doped silicon nitride layer is located, the ratio of the phosphorus doping concentration of the adjacent latter region to the phosphorus doping concentration of the previous region is between 0.1-10, wherein the unit thickness of the phosphorus-doped silicon nitride layer is any value between 3-10nm.

[0020] In some preferred embodiments of the present application, when the phosphorus doping concentration of the phosphorus-doped silicon nitride layer increases, the ratio of the phosphorus doping concentration of the adjacent subsequent region to the phosphorus doping concentration of the previous region is between 1.5-6; when the phosphorus doping concentration of the phosphorus-doped silicon nitride layer decreases, the ratio of the phosphorus doping concentration of the adjacent subsequent region to the phosphorus doping concentration of the previous region is between 0.1-0.6.

[0021] In some preferred embodiments of the present application, the sum of the thicknesses of the phosphorus-doped silicon nitride layer when the phosphorus doping concentration increases is less than the sum of the thicknesses when the phosphorus doping concentration decreases.

[0022] In some preferred embodiments of the present application, the first semiconductor layer includes a tunneling silicon oxide layer and a first doped polysilicon layer, the second semiconductor layer includes a second intrinsic hydrogenated amorphous silicon layer and a second doped silicon layer, and one of the first doped polysilicon layer and the second doped silicon layer is N-type and the other is P-type.

[0023] Preferably, the thickness ratio of the first intrinsic hydrogenated amorphous silicon layer, the intrinsic oxygen-doped microcrystalline silicon layer and the tunneling silicon oxide layer is 1:(1-6):(0.5-2).

[0024] In some preferred embodiments of the present application, the first semiconductor layer and the second semiconductor layer are alternately arranged along the width direction of the back side of the silicon wafer, and the two ends of the second semiconductor layer extend to the outer surface of the end of the adjacent first semiconductor layer to form a stacking transition region; and the back-contact battery with a specific front passivation structure also includes a conductive film layer and a metal electrode, the conductive film layer is laid on the outer surface of the first semiconductor layer and the second semiconductor layer, and an insulating groove is provided on the part of the conductive film layer located in the stacking transition region, and the metal electrode is located on the outer surface of the part of the conductive film layer that is not in the stacking transition region and corresponds to the corresponding semiconductor layer.

[0025] In the second aspect, the present application provides a method for preparing a back-contact cell, which is the back-contact cell with a specific front passivation structure as described in the first aspect, and its preparation method includes: forming a first semiconductor layer and a second semiconductor layer in sequence on the back side of a silicon wafer, and forming a third semiconductor layer and an anti-reflection layer in sequence on the front side of the silicon wafer.

[0026] In some preferred embodiments of the present application, the first intrinsic hydrogenated amorphous silicon layer, the intrinsic oxygen-doped microcrystalline silicon layer, the phosphorus-doped silicon nitride layer, the non-phosphorus-doped silicon nitride layer and the oxide layer are all formed by plate-type PECVD.

[0027] Preferably, the formation conditions of the phosphorus-doped silicon nitride layer include: a deposition temperature of 200-300° C., a mass flow rate of silane of 100-1000 sccm during deposition, a mass flow rate of a mixture of hydrogen and phosphine of 300-1000 sccm, a mass flow rate of nitrogen of 5000-20000 sccm, a mass flow rate of ammonia of 100-1000 sccm, a pressure of 100-300 Pa, a power supply of 2-10 kW, and a deposition time of 200-400 s.

[0028] In some preferred embodiments of the present application, during the formation of the phosphorus-doped silicon nitride layer, the phosphorus doping concentration of the phosphorus-doped silicon nitride layer is controlled to first increase and then decrease by adjusting the mass flow parameter of phosphine.

[0029] In some preferred embodiments of the present application, the band gap width is adjusted to the target value by adjusting the mass flow rate and power supply of hydrogen and silane in the formation of the first intrinsic hydrogenated amorphous silicon layer; the band gap width and refractive index are adjusted to the target values ​​by adjusting the mass flow rate and power supply of hydrogen, carbon dioxide and silane in the formation of the intrinsic oxygen-doped microcrystalline silicon layer; the band gap width and refractive index are adjusted to the target values ​​by adjusting the mass flow rate and power supply of silane and ammonia in the formation of the non-phosphorus-doped silicon nitride layer; the refractive index is adjusted to the target value by adjusting the mass flow rate and power supply of silane and nitrous oxide in the formation of the oxide layer.

[0030] In some preferred embodiments of the present application, the process of sequentially forming the first semiconductor layer and the second semiconductor layer on the back side of the silicon wafer includes:

[0031] S1, provide double-sided polished silicon wafers;

[0032] S2, forming a first semiconductor layer and a mask layer on the back side of the silicon wafer;

[0033] S3, performing a first etching on a portion of the first semiconductor layer and its mask layer in a preset area on the back side of the silicon wafer obtained in S2 to form a second semiconductor opening area;

[0034] S4, performing texturing and cleaning on the second semiconductor opening areas on the front and back sides of the silicon wafer obtained in S3, and removing all mask layers on the back side of the silicon wafer;

[0035] S5, forming a second semiconductor layer on the back side of the silicon wafer obtained in S4;

[0036] S6, then sequentially forming a third semiconductor layer and an anti-reflection layer on the front side of the silicon wafer;

[0037] S7. Perform a second etching on a portion of the second semiconductor layer in a preset area on the back side of the silicon wafer obtained in S6 to form a first semiconductor opening region spaced apart from the second semiconductor opening region.

[0038] In some preferred embodiments of the present application, the method for preparing the back contact battery further comprises:

[0039] S8, depositing a conductive film layer on the back side of the silicon wafer obtained in S7;

[0040] S9, performing a third etching on a portion of the conductive film layer in a predetermined area on the back side of the silicon wafer obtained in S8 to form an insulating groove;

[0041] S10, forming metal electrodes on the outer surfaces of the first semiconductor opening region and the second semiconductor opening region on the back side of the silicon wafer obtained in S9.

[0042] In a third aspect, the present application provides a battery assembly comprising the back-contact battery with the specific front passivation structure described in the first aspect. Beneficial effects:

[0043] The present application, through the above-mentioned technical solution, especially the third semiconductor layer and anti-reflection layer with a special structure on the front side, can reduce the investment of one chamber of plate-type PECVD while ensuring the passivation effect on the front side, reduce the investment in equipment, simplify the process, and take into account the improvement of current density and the improvement of battery conversion efficiency. Specifically, the present application can replace the traditional intrinsic amorphous silicon superimposed doped silicon layer (i.e., doped amorphous silicon or doped microcrystalline silicon film layer) with only intrinsic silicon (i.e., the third semiconductor layer containing the first intrinsic hydrogenated amorphous silicon layer and the intrinsic oxygen-doped microcrystalline silicon layer). The intrinsic oxygen-doped microcrystalline silicon layer used in particular is conducive to improving the passivation effect and increasing the band gap width. This is because the oxygen-doped microcrystalline film layer used has a higher crystallization rate and enhanced density than the amorphous silicon film layer, and the field passivation effect is improved. At the same time, oxygen doping increases the band gap width of the film layer and reduces the refractive index; in combination with phosphorus-doped nitride The anti-reflection layer of the silicon layer, the non-phosphorus-doped silicon nitride layer, and the oxide layer replaces the traditional silicon nitride anti-reflection layer. The phosphorus-doped silicon nitride layer in the specific anti-reflection layer of the present application makes up for the problem of weakened field passivation effect caused by only setting an intrinsic layer in the third semiconductor layer without setting a traditional doped silicon layer. The phosphorus-doped silicon nitride layer has increased phosphorus doping compared to the general silicon nitride, which is beneficial to improving the passivation effect of the film layer without losing the anti-reflection effect of the silicon nitride itself. In combination with the structure of the non-phosphorus-doped silicon nitride layer and the oxide layer, it ensures that the front side has a sufficiently strong field passivation effect, thereby improving the battery conversion efficiency. At the same time, since the first intrinsic hydrogenated amorphous silicon layer and the intrinsic oxygen-doped microcrystalline silicon layer can be formed in one chamber, there is no need to set a traditional doped silicon layer (which and the intrinsic silicon layer need to use a different chamber), reducing the investment in one chamber of the plate-type PECVD, reducing the investment in equipment, and simplifying the process.

[0044] In a further preferred embodiment, the first intrinsic hydrogenated amorphous silicon layer and the intrinsic oxygen-doped microcrystalline silicon layer in the present application can be thinner as a whole, and the overall thickness is more than 50% thinner than the total thickness of the traditional intrinsic amorphous silicon superimposed doped silicon layer, which is more conducive to reducing the parasitic absorption of the film layer itself and increasing the current density.

[0045] In a further preferred embodiment, the present application controls the band gap width of the first intrinsic hydrogenated amorphous silicon layer and the intrinsic oxygen-doped microcrystalline silicon layer, matches the refractive index of the phosphorus-doped silicon nitride layer, the non-phosphorus-doped silicon nitride layer and the oxide layer, and can construct a trend in which the refractive index gradually decreases from the inside to the outside, which is beneficial to reducing optical absorption and further increasing the current density. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0047] FIG1 is a schematic structural diagram of a back-contact battery of the present application.

[0048] Description of Reference Numerals

[0049] 1. Silicon wafer, 2. First semiconductor layer, 2.1. Tunneling silicon oxide layer, 2.2. First doped polycrystalline silicon layer, 4. Second intrinsic hydrogenated amorphous silicon layer, 5. Second doped amorphous silicon layer, 6. Third semiconductor layer, 6.1. First intrinsic hydrogenated amorphous silicon layer, 6.2. Intrinsic oxygen-doped microcrystalline silicon layer, 7. Anti-reflection layer, 7.1. Phosphorus-doped silicon nitride layer, 7.2. Non-phosphorus-doped silicon nitride layer, 7.3. Oxide layer, 8. Conductive film layer, 9. Metal electrode. DETAILED DESCRIPTION

[0050] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0051] In this application, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0052] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein. Among them, the terms "optional" and "optional" all mean that they may be included or not (or may be present or not).

[0053] In this application, the area close to the silicon wafer is considered as the inside, and the area far from the silicon wafer is considered as the outside.

[0054] The test methods used in this application are as follows:

[0055] Bandgap: It is obtained by testing with an ellipsometer at the corresponding film thickness.

[0056] Refractive index: It is obtained by testing with an ellipsometer at corresponding film thickness.

[0057] In the first aspect, the present application provides a back-contact battery with a specific front passivation structure, comprising a silicon wafer having a front and a back, a first semiconductor layer and a second semiconductor layer respectively arranged on the back of the silicon wafer, and a third semiconductor layer and an anti-reflection layer arranged outward in sequence on the front of the silicon wafer, wherein the third semiconductor layer comprises a first intrinsic hydrogenated amorphous silicon layer and an intrinsic oxygen-doped microcrystalline silicon layer arranged outward in sequence, and the anti-reflection layer comprises a phosphorus-doped silicon nitride layer, a non-phosphorus-doped silicon nitride layer and an oxide layer arranged outward in sequence.

[0058] In some preferred embodiments of the present application, the first intrinsic hydrogenated amorphous silicon layer has a bandgap of 1.6-1.9 eV, and the intrinsic oxygen-doped microcrystalline silicon layer has a bandgap of 1.9-2.2 eV. This preferred embodiment provides suitable bandgap widths, which can reduce optical absorption of the film layers and further improve current density and battery conversion efficiency.

[0059] In some preferred embodiments of the present application, the ratio of the bandgap widths of the first intrinsic hydrogenated amorphous silicon layer to the intrinsic oxygen-doped microcrystalline silicon layer is 1:(1-1.375), preferably 1:(1.05-1.3), and further preferably 1:(1.1-1.3). In this preferred embodiment, the ratio of the bandgap widths of the first intrinsic hydrogenated amorphous silicon layer to the intrinsic oxygen-doped microcrystalline silicon layer is appropriate, achieving both passivation and anti-reflection effects, further helping to reduce optical absorption of the film layer and increase current density.

[0060] In some preferred embodiments of the present application, the oxygen doping concentration of the intrinsic oxygen-doped microcrystalline silicon layer is between 1018cm-3 and 1019cm-3, preferably between 2×1018cm-3 and 1019cm-3. In this preferred embodiment, the intrinsic oxygen-doped microcrystalline silicon layer adopts an appropriate oxygen doping concentration to construct a suitable film band gap width, which is more conducive to balancing passivation and optical effects, thereby further improving the current density and conversion efficiency of the battery.

[0061] In some preferred embodiments of the present application, the thickness of the first intrinsic hydrogenated amorphous silicon layer is 1-2 nm, and the thickness of the intrinsic oxygen-doped microcrystalline silicon layer is 2-6 nm.

[0062] In some preferred embodiments of the present application, the thickness ratio of the first intrinsic hydrogenated amorphous silicon layer to the intrinsic oxygen-doped microcrystalline silicon layer is 1:(1-6), preferably 1:(3-6). With the preferred embodiment of the present application, the thickness ratio of the first intrinsic hydrogenated amorphous silicon layer to the intrinsic oxygen-doped microcrystalline silicon layer is appropriate, which can ensure a good passivation effect and is more conducive to improving the open circuit voltage of the battery.

[0063] In some preferred embodiments of the present application, the thickness ratio of the phosphorus-doped silicon nitride layer, the non-phosphorus-doped silicon nitride layer, and the oxide layer is 1:(0.8-1.5):(20-37), preferably 1:(0.8-1.3):(20-30). In this preferred embodiment, the thickness ratio of the phosphorus-doped silicon nitride layer, the non-phosphorus-doped silicon nitride layer, and the oxide layer is appropriate, which can achieve both passivation and reduced film absorption, and is more conducive to increasing current density.

[0064] In some preferred embodiments of the present application, the thickness of the phosphorus-doped silicon nitride layer is 30-85 nm, preferably 30-70 nm, and further preferably 45-70 nm, which is more conducive to improving the field passivation effect and increasing the open circuit voltage of the battery.

[0065] In some preferred embodiments of the present application, the refractive index of the phosphorus-doped silicon nitride layer is between 1.85 and 2.0, preferably 1.9 and 2.0, the refractive index of the non-phosphorus-doped silicon nitride layer is between 2.05 and 2.15, preferably 2.05 and 2.12, and the refractive index of the oxide layer is between 1.4 and 1.6, preferably 1.4 and 1.5. In this preferred embodiment, the refractive index ranges of the phosphorus-doped silicon nitride layer, the non-phosphorus-doped silicon nitride layer, and the oxide layer are suitable, which can significantly improve the anti-reflection effect of the stacked film layer and is more conducive to improving current density and conversion efficiency.

[0066] The oxide layer is preferably silicon oxide.

[0067] In some preferred embodiments of the present application, the phosphorus doping concentration of the phosphorus-doped silicon nitride layer is between 1018 cm-3 and 1021 cm-3.

[0068] In a preferred embodiment of the present application, the phosphorus doping concentration of the phosphorus-doped silicon nitride layer first increases and then decreases. The phosphorus doping concentration first increases and then decreases, and can be increased or decreased continuously in sequence, or can be increased or decreased in a step-like manner. The step-like increase or decrease can be such as changing after a certain phosphorus doping concentration reaches a certain thickness.

[0069] In some preferred embodiments of the present application, the phosphorus doping concentration of the phosphorus-doped silicon nitride layer first increases and then decreases, and in the outward direction perpendicular to the silicon wafer, for the region where the unit thickness of the phosphorus-doped silicon nitride layer is located, the ratio of the phosphorus doping concentration of the adjacent latter region to the phosphorus doping concentration of the previous region is between 0.1-10, wherein the unit thickness of the phosphorus-doped silicon nitride layer is any value between 3-10nm.

[0070] The phosphorus doping concentration of the phosphorus-doped silicon nitride layer first increases and then decreases, and in the outward direction perpendicular to the silicon wafer, for the unit thickness region of the phosphorus-doped silicon nitride layer, the ratio of the phosphorus doping concentration of the adjacent rear region to the phosphorus doping concentration of the preceding region is satisfied, that is, whether the phosphorus doping concentration increases or decreases, it meets the following conditions: the ratio of the phosphorus doping concentration of the unit thickness region at the rear (i.e., in the direction away from the silicon wafer) to the phosphorus doping concentration of the unit thickness region at the front (i.e., in the direction close to the silicon wafer), and the phosphorus doping concentrations of any two adjacent unit thicknesses meet this ratio range. For example, when the phosphorus-doped silicon nitride layer has a thickness of 30 nm and a unit thickness of 10 nm, the phosphorus doping concentrations of the phosphorus-doped silicon nitride layer are different and are divided into three concentrations A, B, and C. Then B / A and C / B are both within the above ratio range, where A corresponds to the phosphorus doping concentration of the first 10 nm thickness, B corresponds to the phosphorus doping concentration of the second 10 nm thickness, and C corresponds to the phosphorus doping concentration of the third 10 nm thickness.

[0071] In some preferred embodiments of the present application, when the phosphorus doping concentration of the phosphorus-doped silicon nitride layer increases, the ratio of the phosphorus doping concentration of the adjacent subsequent region to the phosphorus doping concentration of the preceding region is between 1.5 and 6; and when the phosphorus doping concentration of the phosphorus-doped silicon nitride layer decreases, the ratio of the phosphorus doping concentration of the adjacent subsequent region to the phosphorus doping concentration of the preceding region is between 0.1 and 0.6. This preferred solution is more conducive to ensuring the overall field passivation effect of the film layer while avoiding the possibility of excessive phosphorus source doping damaging the quality of the film layer.

[0072] In some preferred embodiments of the present application, the sum of the thicknesses of the phosphorus-doped silicon nitride layer when the phosphorus doping concentration increases is less than the sum of the thicknesses when the phosphorus doping concentration decreases. This preferred solution is more conducive to taking into account both the passivation effect and the optical effect.

[0073] The silicon wafer described in the present application may be, for example, an N-type single crystal silicon wafer, specifically, a Czochralski single crystal silicon wafer or a cast single crystal silicon wafer. Those skilled in the art may select one according to their needs, and all of them may be applicable to the present application.

[0074] In some preferred embodiments of the present application, the first semiconductor layer comprises a tunneling silicon oxide layer and a first doped polysilicon layer, and the second semiconductor layer comprises a second intrinsic hydrogenated amorphous silicon layer and a second doped silicon layer, wherein one of the first doped polysilicon layer and the second doped silicon layer is N-type and the other is P-type. In this preferred embodiment, the back contact cell of the present application is a combined passivation back contact cell. Its combined passivation structure, combined with the third semiconductor layer and anti-reflection layer of a specific structure, achieves optimal passivation effect and good film density, which is more conducive to improving the open circuit voltage and current density, thereby improving the conversion efficiency of the cell.

[0075] Preferably, the thickness ratio of the first intrinsic hydrogenated amorphous silicon layer, the intrinsic oxygen-doped microcrystalline silicon layer, and the tunneling silicon oxide layer is 1:(1-6):(0.5-2), preferably 1:(1-6):(0.5-1.7). Adopting the preferred embodiment of the present application, the thickness ratio is appropriate, which is more conducive to ensuring the passivation effect and improving the minority carrier lifetime and open circuit voltage of the battery.

[0076] One of the first doped polysilicon layer and the second doped silicon layer is N-type and the other is P-type. It is understood that when the first doped polysilicon layer is N-type, the second doped silicon layer is P-type; and when the first doped polysilicon layer is P-type, the second doped silicon layer is N-type. The second doped silicon layer may be, for example, a doped amorphous layer or a doped microcrystalline layer.

[0077] The thickness of the tunneling silicon oxide layer and the thickness and doping concentration of the first doped polysilicon layer described in this application can refer to any corresponding range in the prior art. For example, the thickness of the tunneling silicon oxide layer is preferably 1-2 nm, the thickness of the first doped polysilicon layer is preferably 70-120 nm, and the effective doping concentration is preferably 1018 cm-3-1021 cm-3.

[0078] The thickness of the second intrinsic hydrogenated amorphous silicon layer and the thickness and doping concentration of the second doped silicon layer in the present application can refer to any corresponding range in the prior art. For example, the thickness of the second intrinsic hydrogenated amorphous silicon layer can be 4-8nm, the thickness of the second doped silicon layer can be 6-12nm, and the effective doping concentration can be 1018cm-3-1020cm-3.

[0079] In some preferred embodiments of the present application, the first and second semiconductor layers are alternately arranged along the width of the back side of the silicon wafer, with the ends of the second semiconductor layers extending to the outer surfaces of the ends of the adjacent first semiconductor layers, forming a stacked transition region. In this preferred embodiment, the back-contact cell of the present application has an interdigitated structure, which, combined with the specific front-side passivation structure of the present application, further enhances cell performance.

[0080] The back-contact cell of the present application may also include conventional necessary film layers and electrodes, which may be prepared in accordance with prior art. Preferably, the back-contact cell with a specific front-side passivation structure further includes a conductive film layer and a metal electrode, wherein the conductive film layer is laid on the outer surfaces of the first semiconductor layer and the second semiconductor layer, and an insulating groove is provided on the portion of the conductive film layer located in the stacking transition region. The metal electrode is located on the outer surface of the portion of the conductive film layer located in the non-stacking transition region and corresponds to the corresponding semiconductor layer.

[0081] The thickness and material of the conductive film layer, as well as the width of the insulating trench, can all refer to any corresponding range in the prior art. For example, the conductive film layer can be 40-80 nm thick and can be an indium oxide-based film doped with at least one of tin, tungsten, titanium, and zinc, or a zinc oxide-based film doped with aluminum and / or boron. For example, the insulating trench width W3 can be 20-100 μm, and the resistance between the first and second semiconductor layers after etching is greater than 1 kΩ.

[0082] In a second aspect, the present application provides a method for preparing a back-contact solar cell having a specific front-side passivation structure as described in the first aspect, comprising: sequentially forming a first semiconductor layer and a second semiconductor layer on the back side of a silicon wafer, and sequentially forming a third semiconductor layer and an anti-reflection layer on the front side of the silicon wafer. The third semiconductor layer and the anti-reflection layer have the same composition and structure as the corresponding layers in the first aspect.

[0083] In some preferred embodiments of the present application, the first intrinsic hydrogenated amorphous silicon layer, the intrinsic oxygen-doped microcrystalline silicon layer, the phosphorus-doped silicon nitride layer, the non-phosphorus-doped silicon nitride layer, and the oxide layer are all formed by slab-PECVD. The first intrinsic hydrogenated amorphous silicon layer and the intrinsic oxygen-doped microcrystalline silicon layer are formed in a single slab-PECVD chamber, while the phosphorus-doped silicon nitride layer, the non-phosphorus-doped silicon nitride layer, and the oxide layer are formed in a separate slab-PECVD chamber.

[0084] The formation methods and conditions of the first intrinsic hydrogenated amorphous silicon layer, intrinsic oxygen-doped microcrystalline silicon layer, phosphorus-doped silicon nitride layer, non-phosphorus-doped silicon nitride layer and oxide layer of the present application can be carried out according to the methods and conditions for forming the corresponding layers in the prior art, as long as a film layer with the required structure and required parameters is obtained.

[0085] In some embodiments, the formation conditions of the phosphorus-doped silicon nitride layer include: a deposition temperature of 200-300°C, a mass flow rate of silane of 100-1000 sccm during deposition, a mass flow rate of a mixture of hydrogen and phosphine of 300-1000 sccm, a mass flow rate of nitrogen of 5000-20000 sccm, a mass flow rate of ammonia of 100-1000 sccm, a pressure of 100-300 Pa, a power supply of 2-10 kW, and a deposition time of 200-400 s. The flow ratio of phosphine to hydrogen in the mixture of hydrogen and phosphine can be, for example, 1:40-60. The refractive index of the phosphorus-doped silicon nitride layer can be adjusted by controlling the mass flow ratio of silane, ammonia, and nitrogen, and the phosphorus doping concentration of the phosphorus-doped silicon nitride layer can be controlled to first increase and then decrease by adjusting the mass flow rate of phosphine.

[0086] In some preferred embodiments of the present application, the formation conditions of the non-phosphorus-doped silicon nitride layer include: formation by plate-type PECVD, a deposition temperature of 200-300°C, a silane mass flow rate of 100-1000 sccm, a nitrogen mass flow rate of 5000-20000 sccm, an ammonia mass flow rate of 100-1000 sccm, a pressure of 100-300 Pa, a power supply of 2-10 kW, and a deposition time of 100-300 s. The refractive index of the non-phosphorus-doped silicon nitride layer can be adjusted by the mass flow rate ratio of silane, ammonia, and nitrogen.

[0087] In some preferred embodiments of the present application, the oxide layer is formed using plate-type PECVD, with a deposition temperature of 200-300°C, a silane mass flow rate of 50-500 sccm, a nitrous oxide mass flow rate of 1000-10000 sccm, a pressure of 50-300 Pa, a power supply of 0.1-5 kW, and a deposition time of 100-300 s. The refractive index of the oxide layer can be adjusted by adjusting the mass flow rate ratio of silane to nitrous oxide.

[0088] In some preferred embodiments of the present application, the formation conditions of the first intrinsic hydrogenated amorphous silicon layer include: formation by plate-type PECVD, a deposition temperature of 200-300°C, a silane mass flow rate of 100-1000 sccm, a hydrogen mass flow rate of 1000-10000 sccm, a pressure of 50-500 Pa, a power supply of 0.1-5 kW, and a deposition time of 100-300 seconds. The bandgap width of the first intrinsic hydrogenated amorphous silicon layer can be adjusted by varying the mass flow ratio of silane to hydrogen and the power supply.

[0089] In some preferred embodiments of the present application, the formation conditions of the intrinsic oxygen-doped microcrystalline silicon layer include: formation by plate-type PECVD, a deposition temperature of 200-300°C, a silane mass flow rate of 100-1000 sccm, a carbon dioxide mass flow rate of 30-500 sccm, a hydrogen mass flow rate of 3000-30000 sccm, a pressure of 50-600 Pa, a power supply of 0.1-20 kW, and a deposition time of 100-300 s. The band gap of the intrinsic oxygen-doped microcrystalline silicon layer can be adjusted by changing the mass flow ratio of silane, carbon dioxide, and hydrogen and the power supply, and the oxygen concentration of the intrinsic oxygen-doped microcrystalline silicon layer can be adjusted by changing the mass flow rate and power of carbon dioxide.

[0090] In the preparation method of the present application, the composition and structure of the first semiconductor layer and the second semiconductor layer are the same as those of the corresponding layers in the first aspect, and will not be repeated here.

[0091] In some preferred embodiments of the present application, the process of sequentially forming the first semiconductor layer and the second semiconductor layer on the back side of the silicon wafer includes:

[0092] S1, provide double-sided polished silicon wafers;

[0093] S2, forming a first semiconductor layer and a mask layer on the back side of the silicon wafer;

[0094] S3, performing a first etching on a portion of the first semiconductor layer and its mask layer in a preset area on the back side of the silicon wafer obtained in S2 to form a second semiconductor opening area;

[0095] S4, performing texturing and cleaning on the second semiconductor opening areas on the front and back sides of the silicon wafer obtained in S3, and removing all mask layers on the back side of the silicon wafer;

[0096] S5, forming a second semiconductor layer on the back side of the silicon wafer obtained in S4;

[0097] S6, then sequentially forming a third semiconductor layer and an anti-reflection layer on the front side of the silicon wafer;

[0098] S7, performing a second etching on a portion of the second semiconductor layer in a preset area on the back side of the silicon wafer obtained in S6, to form a first semiconductor opening area spaced apart from the second semiconductor opening area. In this preferred solution, a post-texturing process is used to further reduce the process flow.

[0099] In the double-sided polishing process described in S1, after polishing, other conventional steps, such as cleaning, may be performed.

[0100] The type and thickness of the mask layer in S2 can be any type or thickness range of mask layers known in the art. For example, the mask layer can be at least one of silicon nitride, silicon oxide, silicon oxynitride, or nitrogen-containing polysilicon, preferably silicon nitride. For example, the mask layer can have a thickness of 40-90 nm.

[0101] The method for forming the first semiconductor layer and the mask layer in S2 and the method for forming the second semiconductor layer in S5 can be selected from a variety of methods in the prior art. For example, in the preferred embodiment in which the first semiconductor layer comprises a tunneling silicon oxide layer and a first doped polysilicon layer, and the second semiconductor layer comprises a second intrinsic hydrogenated amorphous silicon layer and a second doped silicon layer, the tunneling silicon oxide layer, the first doped polysilicon layer, and the mask layer can all be deposited in sequence in a tubular polysilicon deposition furnace and annealed at high temperature, with the deposition temperature preferably being 400-500°C. Further preferably, when depositing the tunneling silicon oxide layer, nitrous oxide is introduced and the nitrous oxide mass flow rate is controlled to be 8000-12000 sccm, the pressure is 100-200 Pa, the power is 3-20 kW, and the time is 20-100 s. Further preferably, when depositing the first doped polysilicon layer, the mass flow rate of silane introduced is 1000-3000 sccm, the mass flow rate of hydrogen is 7000-9000 sccm, and a mixed gas of hydrogen and a doping element source is introduced, and the power supply is controlled to be 5-20 kW, and the time is 800-1300 s. Preferably, when the doping element source is a phosphorus source, the mass flow rate of the mixed gas is 1000-2500 sccm, and the pressure is controlled to be 400-500 Pa; when the doping element source is a boron source, the mass flow rate of the mixed gas is 2000-4000 sccm, and the pressure is controlled to be 200-800 Pa. Further preferably, when depositing the mask layer, the mass flow rate of silane introduced is controlled to be 1000-2000 sccm, the mass flow rate of nitrogen is 2000-5000 sccm, the pressure is 200-300 Pa, the power supply is controlled to be 3-20 kW, and the time is 300-800 s. Further preferably, nitrogen gas needs to be introduced during the high temperature annealing process, the mass flow rate of nitrogen gas is 5000-15000 sccm, the annealing temperature is 850-950° C., the pressure is 1000-10000 Pa, and the time is 40-60 min.

[0102] For example, in the preferred solution in which the second semiconductor layer includes a second intrinsic hydrogenated amorphous silicon layer and a second doped silicon layer, the second semiconductor layer is formed by plate-type CVD. For details, please refer to the prior art and will not be described again here.

[0103] The first etching described in S3 of this application can be performed by laser or mask etching, as long as the second semiconductor opening region is formed. The laser can be an ultraviolet or green laser with a pulse width of less than 10ns. The width of the formed second semiconductor opening region can be, for example, 400-800 μm.

[0104] The texturing and cleaning process described in S4 of the present application can be carried out with reference to the prior art. For example, the process may include first using a texturing liquid for texturing, and then cleaning with a cleaning solution, while removing the mask layer on the back of the silicon wafer. Further preferably, the texturing liquid is a mixture of alkali (such as potassium hydroxide and / or sodium hydroxide), a texturing additive (such as a commercially available product) and water, wherein the mass percentage of the alkali is 1%-5%, and the mass percentage of the texturing additive is 0.5%-1%. The texturing time is 8-30min, and the texturing temperature is 75℃-85℃. Further preferably, the cleaning solution can be an acid solution containing HF, the mass percentage of HF is 0.5%-5%, the mass percentage of water (preferably deionized water) is 95%-99.5%, the processing temperature is 20℃-30℃, and the removal time is 60-300s.

[0105] The second etching described in S7 of this application can be performed by laser or mask etching, as long as the second semiconductor layer above the first semiconductor layer is etched away to form the first semiconductor opening region. The laser can be an ultraviolet or green laser with a pulse width of less than 10ns. The width W2 of the formed second semiconductor opening region is preferably 100-250μm.

[0106] In some preferred embodiments of the present application, the method for preparing the back-contact battery further includes: S8, depositing a conductive film layer on the back of the silicon wafer obtained in S7; S9, performing a third etching on a portion of the conductive film layer in a preset area on the back of the silicon wafer obtained in S8 to form an insulating groove.

[0107] In some preferred embodiments of the present application, the method for preparing the back-contact battery further includes: S10, forming metal electrodes on the outer surfaces of the first semiconductor opening area and the second semiconductor opening area on the back of the silicon wafer obtained in S9.

[0108] In the preparation method of the present application, the composition and structure of the conductive film layer and the metal electrode are the same as those of the corresponding layers in the first aspect, and will not be repeated here.

[0109] The conductive film layer and metal electrode described in this application can be prepared by referring to any corresponding method in the prior art. For example, the conductive film layer can be deposited using physical vapor deposition (PVD) or activated plasma deposition (RPD). For example, the metal electrode can be formed using screen printing technology.

[0110] The insulating groove described in S9 of the present application may be formed by, for example, mask etching or laser.

[0111] In a third aspect, the present application provides a battery assembly comprising the back-contact battery with the specific front passivation structure described in the first aspect.

[0112] The embodiments of the present application are described in detail below. These embodiments are exemplary and are only configured to explain the present application, but should not be construed as limiting the present application.

[0113] Example 1

[0114] A back contact battery, the structure of which is shown in FIG1 , is prepared according to the following preparation method:

[0115] S1, double-sided polishing of silicon wafer 1:

[0116] The double-sided polishing and cleaning of an N-type single crystal silicon wafer 1 is performed, wherein the silicon wafer 1 is a Czochralski single crystal silicon wafer.

[0117] S2. Forming a first semiconductor layer 2 and a mask layer on the back side of the silicon wafer 1:

[0118] The first semiconductor layer 2 comprises a tunneling silicon oxide layer 2.1 and an N-type first doped polysilicon layer 2.2. The mask layer is made of silicon nitride. The tunneling silicon oxide layer 2.1 is 1.5 nm thick, and the first doped polysilicon layer 2.2 is 80 nm thick with an effective doping concentration of 2×1020 cm-3. The mask layer is also 80 nm thick. The tunneling silicon oxide layer 2.1, the first doped polysilicon layer 2.2, and the mask layer are sequentially deposited in a tubular polysilicon deposition furnace and annealed at high temperature at a deposition temperature of 450°C. During the deposition of the tunneling silicon oxide layer 2.1, the nitrous oxide mass flow rate is 9000 sccm, the pressure is 150 Pa, the power supply is 10 kW, and the deposition time is 50 seconds. When depositing the first doped polysilicon layer 2.2, the mass flow rate of silane is 1000 sccm, the mass flow rate of the hydrogen-phosphine mixed gas (flow ratio is 2% PH3 / 98% H2) is 2000 sccm, the mass flow rate of hydrogen is 8000 sccm, the pressure is 450 Pa, the power supply is 10 kW, and the time is 1000 s. When depositing silicon nitride 3, the mass flow rate of silane is 1500 sccm, the mass flow rate of ammonia is 9500 sccm, the pressure is 250 Pa, the power supply is 10 kW, and the time is 500 s. The high-temperature annealing requires the introduction of nitrogen, the mass flow rate of nitrogen is 8000 sccm, the annealing temperature is 850°C, the pressure is 3000 Pa, and the time is 50 min.

[0119] S3, performing a first etching on the back side of the silicon wafer 1 to form a second semiconductor opening region;

[0120] The first etching is performed using a laser method, wherein the laser is an ultraviolet laser with a pulse width of 5 ps. The width W1 of the formed second semiconductor opening region is 500 μm.

[0121] S4, texturing and cleaning the second semiconductor opening areas on the front and back sides of the silicon wafer 1:

[0122] The second semiconductor opening areas on the front and back sides of the silicon wafer 1 were cleaned and texturized using a texturizing solution comprising a mixture of potassium hydroxide, a texturizing additive, and water, with the potassium hydroxide content being 2% by weight and the texturizing additive content being 0.5% by weight. The texturizing process lasted 10 minutes at a temperature of 80°C. Following texturization, the wafer was then rinsed with a cleaning solution to remove any silicon nitride mask layer from the back side of the wafer. The cleaning solution used to remove the mask layer was HF acid (0.5% by weight) and deionized water (99.5% by weight). The treatment temperature was 25°C, and the removal time was 100 seconds.

[0123] S5, forming a second semiconductor layer on the back side of the silicon wafer 1;

[0124] The second semiconductor layer comprises a second intrinsic hydrogenated amorphous silicon layer 4 and a second P-type doped amorphous silicon layer 5. The second semiconductor layer is formed by plate-type CVD. The second intrinsic hydrogenated amorphous silicon layer 4 is 5 nm thick, and the second doped amorphous silicon layer 5 is 10 nm thick with an effective doping concentration of 1019 cm-3.

[0125] S6, forming a third semiconductor layer 6 and an anti-reflection layer 7 on the front surface of the silicon wafer 1;

[0126] The third semiconductor layer 6 comprises a first intrinsic hydrogenated amorphous silicon layer 6.1 and an intrinsic oxygen-doped microcrystalline silicon layer 6.2, formed sequentially. The third semiconductor layer 6 is formed by plate-type PECVD. The specific formation process for the first intrinsic hydrogenated amorphous silicon layer 6.1 is as follows: a deposition temperature of 200°C, a silane mass flow rate of 300 sccm, a hydrogen mass flow rate of 1000 sccm, a pressure of 250 Pa, a power supply of 0.8 kW, and a deposition time of 200 s. The specific formation process for the intrinsic oxygen-doped microcrystalline silicon layer 6.2 is as follows: a deposition temperature of 210°C, a silane mass flow rate of 100 sccm, a carbon dioxide mass flow rate of 150 sccm, a hydrogen mass flow rate of 10,000 sccm, a pressure of 400 Pa, a power supply of 20 kW, and a deposition time of 250 s.

[0127] The first intrinsic hydrogenated amorphous silicon layer 6.1 has a thickness of 1 nm, and the intrinsic oxygen-doped microcrystalline silicon layer 6.2 has a thickness of 4 nm and an oxygen concentration of 1019 cm-3. The band gap of the first intrinsic hydrogenated amorphous silicon layer 6.1 is controlled at 1.65 eV, and the band gap of the intrinsic oxygen-doped microcrystalline silicon layer 6.2 is controlled at 2.0 eV.

[0128] The anti-reflection layer 7 is composed of a phosphorus-doped silicon nitride layer 7.1, a non-phosphorus-doped silicon nitride layer 7.2, and an oxide layer 7.3 (specifically, silicon oxide) formed in sequence. The formation conditions of the phosphorus-doped silicon nitride layer 7.1 include: during deposition, the mass flow rate of silane is controlled to be 700 sccm, the mass flow rate of a mixture of hydrogen and phosphine (with a flow ratio of 2% PH3 / 98% H2) is controlled to be 300-1000 sccm, the mass flow rate of nitrogen is controlled to be 5000 sccm, the mass flow rate of ammonia is controlled to be 1000 sccm, the pressure is controlled to be 150 Pa, the power supply is controlled to be 4 kW, the deposition temperature is controlled to be 220° C., and the deposition time is controlled to be 200 s. The phosphorus doping concentration of the phosphorus-doped silicon nitride layer 7.1 gradually increases and then gradually decreases from the inside to the outside of the silicon wafer 1, and the phosphorus doping concentration of the phosphorus-doped silicon nitride layer 7.1 is controlled to be one doping concentration per 10 nm. It is first 5×1019cm-3, 1×1020cm-3, 5×1020cm-3, 1×1020cm-3, 5×1019cm-3, 1×1019cm-3, 5×1018cm-3, where each doping concentration corresponds to a unit thickness of 10nm. When gradually increasing, the doping concentration is increased by one layer per 10nm, and when decreasing, the doping concentration is reduced by one layer per 10nm. The thickness of the phosphorus-doped silicon nitride layer 7.1 is controlled at 70nm.

[0129] The formation conditions of the non-phosphorus-doped silicon nitride layer 7.2 include: a deposition temperature of 220° C., a mass flow rate of silane of 700 sccm, a mass flow rate of nitrogen of 5000 sccm, a mass flow rate of ammonia of 1000 sccm, a pressure of 150 Pa, a power supply of 4 kW, and a deposition time of 150 s; the formation conditions of the oxide layer 7.3 include: a deposition temperature of 250° C., a mass flow rate of silane of 500 sccm, a mass flow rate of nitrous oxide of 10000 sccm, a pressure of 100 Pa, a power supply of 0.9 kW, and a deposition time of 300 s.

[0130] The thickness ratio of the phosphorus-doped silicon nitride layer 7.1, the non-phosphorus-doped silicon nitride layer 7.2, and the oxide layer 7.3 is 1:0.8:21. The refractive index of the phosphorus-doped silicon nitride layer 7.1 is controlled at 1.96, the refractive index of the non-phosphorus-doped silicon nitride layer 7.2 is controlled at 2.08, and the refractive index of the oxide layer 7.3 is controlled at 1.47.

[0131] S7, etching the back side of the silicon wafer 1 a second time to form a first semiconductor opening region;

[0132] The second etching is performed using a laser, which is an ultraviolet laser with a pulse width of 5 ps. The width W2 of the formed second semiconductor opening region is 200 μm.

[0133] S8, depositing a transparent conductive film layer 8 on the back side of the silicon wafer 1;

[0134] A conductive film layer 8 is deposited on the back of the silicon wafer 1 by physical vapor deposition (PVD). The conductive film layer 8 has a thickness of 50 nm. The material of the transparent conductive film layer 8 is a tin-doped indium oxide-based thin film.

[0135] S9, etching the back side of the silicon wafer 1 for the third time to form an insulating trench;

[0136] An opening is etched on the back of the silicon wafer 1 by mask etching to form an insulating trench between the first semiconductor and the second semiconductor. The insulating trench width W3 is 50 μm. After etching, the resistance between the first semiconductor and the second semiconductor is greater than 1 kΩ.

[0137] S10, forming metal electrodes 9 at the first semiconductor opening region and the second semiconductor opening region on the back side of the silicon wafer 1 respectively:

[0138] Metal electrodes 9 are formed on the surfaces of the first semiconductor opening region and the second semiconductor opening region on the back side of the silicon wafer 1 by using screen printing technology.

[0139] Example 2

[0140] The method of Example 1 is referred to, except that the band gap width of the intrinsic oxygen-doped microcrystalline silicon layer is adjusted to 2.2eV in S6. To meet this condition, the process parameters need to be adjusted accordingly: when preparing the intrinsic oxygen-doped microcrystalline silicon layer, compared with Example 1, the silicon dioxide flow rate is increased by 80% and the deposition power is increased by 100%. At this time, the ratio of the band gap widths of the first intrinsic hydrogenated amorphous silicon layer and the intrinsic oxygen-doped microcrystalline silicon layer is 1:1.33.

[0141] Example 3

[0142] The method of Example 1 is referred to, except that in S6, the band gap width of the first intrinsic hydrogenated amorphous silicon layer is adjusted to 1.85eV. To meet this condition, the process parameters need to be adjusted accordingly: when preparing the first intrinsic hydrogenated amorphous silicon layer, compared with Example 1, the mass flow rate of hydrogen is increased by 65% ​​and the deposition power is increased by 80%. At this time, the ratio of the band gap widths of the first intrinsic hydrogenated amorphous silicon layer and the intrinsic oxygen-doped microcrystalline silicon layer is 1:1.08.

[0143] Example 4

[0144] The method of Example 1 is referred to, except that in S6, the oxygen concentration of the intrinsic oxygen-doped microcrystalline silicon layer is adjusted to 1018cm-3. To meet this condition, the process parameters during preparation need to be adjusted accordingly: compared with Example 1, the mass flow rate of carbon dioxide is reduced by 60%.

[0145] Example 5

[0146] The method of Example 1 is referred to, except that the thickness of the intrinsic oxygen-doped microcrystalline silicon layer is adjusted to 2 nm in S6. To meet this condition, the process parameters during preparation need to be adjusted accordingly: compared with Example 1, the deposition time is reduced by 50%. At this time, the thickness ratio of the first intrinsic hydrogenated amorphous silicon layer to the intrinsic oxygen-doped microcrystalline silicon layer is 1:2.

[0147] Example 6

[0148] The method of Example 1 is referred to, except that in S6, the refractive index of the phosphorus-doped silicon nitride layer is adjusted to 1.85. To meet this condition, the process parameters during preparation need to be adjusted accordingly: compared with Example 1, the mass flow rate of silane is reduced by 46%.

[0149] Example 7

[0150] The method of Example 1 is referred to, except that in S6, the thickness of the phosphorus-doped silicon nitride layer is adjusted to 40 nm. To meet this condition, the process parameters during its preparation need to be adjusted accordingly: compared with Example 1, the deposition time is uniformly shortened by 44% at each doping concentration, and the thickness ratio of the phosphorus-doped silicon nitride layer, the non-phosphorus-doped silicon nitride layer and the oxide layer is 1:1.4:36.8.

[0151] Example 8

[0152] The method of Example 1 is followed, except that the phosphorus doping concentration of the phosphorus-doped silicon nitride layer is adjusted differently in S6. Specifically, the phosphorus doping concentration is kept constant at the initial value of Example 1. In this solution, the refractive index of the phosphorus-doped silicon nitride layer is 2.0.

[0153] Example 9

[0154] The method of Example 1 is referred to, except that in S6, the sum of the thicknesses of the phosphorus-doped silicon nitride layer when the phosphorus doping concentration is increased is adjusted to 45 nm (the thickness of each corresponding layer is 15 nm), which is greater than the sum of the thicknesses when the phosphorus doping concentration is decreased (which is the same as in Example 1). To meet this condition, the process parameters during preparation need to be adjusted accordingly: the sum of the deposition time when the phosphorus doping concentration is increased is greater than the sum of the deposition time when the phosphorus doping concentration is decreased.

[0155] Example 10

[0156] The method of Example 1 is referred to, except that in S6, the phosphorus doping concentration of the phosphorus-doped silicon nitride layer is adjusted to a decreasing distribution, specifically: one doping concentration is controlled every 10 nm, specifically 5×1020 cm-3, 1×1020 cm-3, 5×1019 cm-3, 1×1019 cm-3, 5×1018 cm-3, where each doping concentration corresponds to a unit thickness of 10 nm, and the doping concentration is reduced by one layer every 10 nm when decreasing, and the thickness of the phosphorus-doped silicon nitride layer is controlled at 50 nm.

[0157] Example 11

[0158] The method of Example 1 is referred to, except that in S6, the phosphorus doping concentration of the phosphorus-doped silicon nitride layer is adjusted to an increasing distribution, specifically: one doping concentration is controlled every 10 nm, specifically 5×1019 cm-3, 1×1020 cm-3, 5×1020 cm-3, where each doping concentration corresponds to a unit thickness of 10 nm, and the doping concentration is increased by one layer every 10 nm when gradually increasing, and the thickness of the phosphorus-doped silicon nitride layer is controlled at 30 nm.

[0159] Example 12

[0160] The method of Example 1 is referred to, except that in S6, the refractive index of the non-phosphorus-doped silicon nitride layer in the anti-reflection layer is adjusted to 2.15. To meet this condition, the process parameters during preparation need to be adjusted accordingly: compared with Example 1, the mass flow rate of silane is increased by 30%.

[0161] Example 13

[0162] The method of Example 1 is carried out, except that the refractive index of the oxide layer in the anti-reflection layer is adjusted to 1.6 in S6. To meet this condition, the process parameters during its preparation need to be adjusted accordingly: compared with Example 1, the mass flow rate of nitrous oxide is increased by 60%.

[0163] Example 14

[0164] The method of Example 1 is referred to, except that in S2, the thickness of the tunneling silicon oxide layer is adjusted to 2, so that the ratio of the thickness of the first intrinsic hydrogenated amorphous silicon layer to the tunneling silicon oxide layer is 1:2.

[0165] Comparative Example 1

[0166] The method of Example 1 is referred to, except that the third semiconductor layer and the anti-reflection layer both adopt traditional structures. Specifically, the third semiconductor layer is composed of an intrinsic amorphous silicon layer and an N-type doped amorphous silicon film layer (not doped with oxygen) arranged in sequence outward, the thickness of the intrinsic amorphous silicon layer is 6nm, the band gap width is 1.6ev, the thickness of the N-type doped amorphous silicon film layer is 8nm, the doping concentration is 1020cm-3, and the band gap width is 1.73ev; the anti-reflection layer is silicon nitride with a thickness of 120nm and a refractive index of 2.08ev.

[0167] Comparative Example 2

[0168] The method of Example 1 is referred to, except that no phosphorus-doped silicon nitride layer is provided in S6.

[0169] Comparative Example 3

[0170] The method of Example 1 is referred to, except that no phosphorus-free silicon nitride layer is provided in S6.

[0171] Comparative Example 4

[0172] The method of Example 1 is referred to, except that no oxide layer is provided in the anti-reflection layer in S6.

[0173] Comparative Example 5

[0174] The method of Example 1 is referred to, except that no intrinsic oxygen-doped microcrystalline silicon layer is provided in S6.

[0175] Comparative Example 6

[0176] The method of Example 1 is referred to, except that no intrinsic hydrogenated amorphous silicon layer is provided in S6.

[0177] Test Case

[0178] The back-contact cells obtained in the above examples and comparative examples were subjected to performance tests, and the results are shown in Table 1. The corresponding data of the other examples and comparative examples were converted relative to the benchmark of Example 1, wherein the benchmarks of the data of Example 1 were normalized to 1.

[0179] Table 1

[0180] From the above results, it can be seen that, compared with the comparative example, the embodiment scheme of the present application can take into account both good conversion efficiency and production cost, which is beneficial to improving the market competitiveness of the battery; while the comparative example scheme cannot achieve both conversion efficiency and cost.

[0181] Furthermore, according to Examples 1 and 2-14, it can be seen that the preferred first intrinsic hydrogenated amorphous silicon layer superimposed on the intrinsic oxygen-doped microcrystalline silicon layer of the present application is used to match the preferred structure of the phosphorus-doped silicon nitride layer, the non-phosphorus-doped silicon nitride layer and the oxide layer scheme, which can ensure good passivation and high current density, and is more conducive to further improving the conversion efficiency of the battery while maintaining a suitable low production cost.

[0182] The preferred embodiments of the present application are described in detail above, but the present application is not limited thereto. Within the technical concept of the present application, various simple modifications can be made to the technical solution of the present application, including combining the various technical features in any other appropriate manner. These simple modifications and combinations should also be regarded as the contents disclosed in the present application and fall within the scope of protection of the present application. Industrial Applicability

[0183] In the above scheme, the back-contact cell includes a silicon wafer having a front side and a back side, a first semiconductor layer and a second semiconductor layer disposed on the back side of the wafer, respectively, and a third semiconductor layer and an anti-reflection layer disposed outwardly from the front side of the wafer. The third semiconductor layer comprises a first intrinsic hydrogenated amorphous silicon layer and an intrinsic oxygen-doped microcrystalline silicon layer disposed outwardly in sequence, and the anti-reflection layer comprises a phosphorus-doped silicon nitride layer, a non-phosphorus-doped silicon nitride layer, and an oxide layer disposed outwardly in sequence. This allows the back-contact cell to maintain front-side passivation while reducing the investment in a single plate-type PECVD chamber, thereby reducing equipment investment, simplifying the process, and lowering production costs while simultaneously improving cell density and conversion efficiency.

Claims

1. A back-contact battery with a specific front passivation structure, comprising a silicon wafer having a front side and a back side, a first semiconductor layer and a second semiconductor layer respectively disposed on the back side of the silicon wafer, and a third semiconductor layer and an anti-reflection layer sequentially disposed outward on the front side of the silicon wafer, characterized in that, The third semiconductor layer includes a first intrinsic hydrogenated amorphous silicon layer and an intrinsic oxygen-doped microcrystalline silicon layer arranged successively outward, and the antireflection layer includes a phosphorus-doped silicon nitride layer, an undoped phosphorus silicon nitride layer, and an oxide layer arranged successively outward.

2. The back-contact battery with a specific front passivation structure according to claim 1, characterized in that, The band gap of the first intrinsic hydrogenated amorphous silicon layer is between 1.6 - 1.9 eV, and the band gap of the intrinsic oxygen-doped microcrystalline silicon layer is between 1.9 - 2.2 eV; and / or, the ratio of the band gaps of the first intrinsic hydrogenated amorphous silicon layer and the intrinsic oxygen-doped microcrystalline silicon layer is 1:(1 - 1.375).

3. The back-contact battery with a specific front passivation structure according to claim 1, characterized in that, The oxygen doping concentration of the intrinsic oxygen-doped microcrystalline silicon layer is between 10^18 cm^-3 - 10^19 cm^-3.

4. The back-contact battery with a specific front passivation structure according to claim 1 or 2, characterized in that, The thickness of the first intrinsic hydrogenated amorphous silicon layer is 1 - 2 nm, and the thickness of the intrinsic oxygen-doped microcrystalline silicon layer is 2 - 6 nm; and / or, the thickness ratio of the first intrinsic hydrogenated amorphous silicon layer and the intrinsic oxygen-doped microcrystalline silicon layer is 1:(1 - 6).

5. The back-contact battery with a specific front passivation structure according to claim 1, characterized in that, The thickness ratio of the phosphorus-doped silicon nitride layer, the undoped phosphorus silicon nitride layer, and the oxide layer is 1:(0.8 - 1.5):(20 - 37); and / or, the thickness of the phosphorus-doped silicon nitride layer is 30 - 85 nm.

6. The back contact battery with a specific front passivation structure according to claim 1 or 2, characterized in that, The refractive index of the phosphorus-doped silicon nitride layer is between 1.85 - 2.0, the refractive index of the undoped phosphorus silicon nitride layer is between 2.05 - 2.15, and the refractive index of the oxide layer is between 1.4 - 1.

6.

7. The back contact battery with a specific front passivation structure according to claim 1, characterized in that, The phosphorus doping concentration of the phosphorus-doped silicon nitride layer is between 10^18 cm^-3 - 10^21 cm^-3, and / or, the phosphorus doping concentration of the phosphorus-doped silicon nitride layer first increases and then decreases.

8. The back-contact battery with a specific front passivation structure according to claim 1, characterized in that, The phosphorus doping concentration of the phosphorus-doped silicon nitride layer first increases and then decreases, and in the outward direction perpendicular to the silicon wafer, for the region where the unit thickness of the phosphorus-doped silicon nitride layer is located, the ratio of the phosphorus doping concentration of the adjacent latter region to the phosphorus doping concentration of the previous region is between 0.1 - 10, where the unit thickness of the phosphorus-doped silicon nitride layer is any value between 3 - 10 nm.

9. The back contact battery with a specific front passivation structure according to claim 8, characterized in that, When the phosphorus doping concentration of the phosphorus-doped silicon nitride layer increases, the ratio of the phosphorus doping concentration of the adjacent latter region to the phosphorus doping concentration of the previous region is between 1.5 - 6; when the phosphorus doping concentration of the phosphorus-doped silicon nitride layer decreases, the ratio of the phosphorus doping concentration of the adjacent latter region to the phosphorus doping concentration of the previous region is between 0.1 - 0.

6.

10. The back contact battery with a specific front passivation structure according to claim 8, characterized in that, The sum of the thicknesses of the phosphorus-doped silicon nitride layer when its phosphorus doping concentration increases is less than the sum of its thicknesses when it decreases.

11. The back contact battery with a specific front passivation structure according to claim 1, characterized in that, The first semiconductor layer includes a tunneling silicon oxide layer and a first doped polysilicon layer, the second semiconductor layer includes a second intrinsic hydrogenated amorphous silicon layer and a second doped silicon layer, and one of the first doped polysilicon layer and the second doped silicon layer is N-type and the other is P-type; wherein, the thickness ratio of the first intrinsic hydrogenated amorphous silicon layer, the intrinsic oxygen-doped microcrystalline silicon layer, and the tunneling silicon oxide layer is 1:(1 - 6):(0.5 - 2); and / or, The first semiconductor layer and the second semiconductor layer are arranged alternately along the width direction of the back surface of the silicon wafer, and both ends of the second semiconductor layer extend to the outer surfaces of the ends of the adjacent first semiconductor layers to form a stacked transition region; and the back contact battery with the specific front passivation structure further includes a conductive film layer and a metal electrode. The conductive film layer is laid on the outer surfaces of the first semiconductor layer and the second semiconductor layer, and an insulating groove is formed in a part of the conductive film layer located at the stacked transition region. The metal electrode is located on the outer surface of the part of the conductive film layer that is not in the stacked transition region and corresponds to the corresponding semiconductor layer.

12. A method for preparing a back-contact battery, characterized in that, The back contact battery is the back contact battery with the specific front passivation structure as described in any one of claims 1-11, and its manufacturing method includes: sequentially forming a first semiconductor layer and a second semiconductor layer on the back surface of the silicon wafer, and sequentially forming a third semiconductor layer and an antireflection layer on the front surface of the silicon wafer.

13. The method for preparing a back-contact battery according to claim 12, wherein The first intrinsic hydrogenated amorphous silicon layer, the intrinsic oxygen-doped microcrystalline silicon layer, the phosphorus-doped silicon nitride layer, the non-phosphorus-doped silicon nitride layer, and the oxide layer are all formed by the plate-type PECVD method, wherein The formation conditions of the first intrinsic hydrogenated amorphous silicon layer include: the deposition temperature is 200-300 °C, the mass flow rate of silane during deposition is 100-1000 sccm, the mass flow rate of hydrogen is 1000-10000 sccm, the pressure is 50-500 Pa, the power of the power supply is 0.1-5 kW, and the deposition time is 100-300 s; The formation conditions of the intrinsic oxygen-doped microcrystalline silicon layer include: the deposition temperature is 200-300 °C, the mass flow rate of silane during deposition is 100-1000 sccm, the mass flow rate of carbon dioxide is 30-500 sccm, the mass flow rate of hydrogen is 3000-30000 sccm, the pressure is 50-600 Pa, the power of the power supply is 0.1-20 kW, and the deposition time is 100-300 s; The formation conditions of the phosphorus-doped silicon nitride layer include: controlling the mass flow rate of silane introduced during deposition to be 100-1000 sccm, the mass flow rate of the mixed gas of hydrogen carrying phosphine to be 300-1000 sccm, the mass flow rate of nitrogen to be 5000-20000 sccm, the mass flow rate of ammonia to be 100-1000 sccm, and controlling the pressure to be 100-300 Pa, the power of the power supply to be 2-10 kW, the deposition temperature to be 200-300 °C, and the deposition time to be 200-400 s; The formation conditions of the non-phosphorus-doped silicon nitride layer include: the deposition temperature is 200-300 °C, the mass flow rate of silane during deposition is 100-1000 sccm, the mass flow rate of nitrogen is 5000-20000 sccm, the mass flow rate of ammonia is 100-1000 sccm, the pressure is 100-300 Pa, the power of the power supply is 2-10 kW, and the deposition time is 100-300 s; The formation conditions of the oxide layer include: the deposition temperature is 200 - 300 °C, the mass flow rate of silane during deposition is 50 - 500 sccm, the mass flow rate of nitrous oxide is 1000 - 10000 sccm, the pressure is 50 - 300 Pa, the power of the power supply is 0.1 - 5 kW, and the deposition time is 100 - 300 s.

14. The method for preparing a back-contact battery according to claim 12, wherein The process of sequentially forming a first semiconductor layer and a second semiconductor layer on the back surface of the silicon wafer includes: S1. Provide a double-sided polished silicon wafer; S2. Form a first semiconductor layer and a mask layer on the back surface of the silicon wafer; S3. Perform a first etching on a part of the first semiconductor layer and its mask layer in a preset area on the back surface of the silicon wafer obtained in S2 to form a second semiconductor opening area; S4. Perform texturing cleaning on the second semiconductor opening areas on the front and back surfaces of the silicon wafer obtained in S3, and at the same time remove all the mask layers on the back surface of the silicon wafer; S5. Form a second semiconductor layer on the back surface of the silicon wafer obtained in S4; S6. Then perform the process of sequentially forming a third semiconductor layer and an antireflection layer on the front surface of the silicon wafer; S7. Perform a second etching on a part of the second semiconductor layer in a preset area on the back surface of the silicon wafer obtained in S6 to form a first semiconductor opening area spaced apart from the second semiconductor opening area; And the preparation method of the back contact battery further includes: S8. Deposit a conductive film layer on the back surface of the silicon wafer obtained in S7; S9. Perform a third etching on a part of the conductive film layer in a preset area on the back surface of the silicon wafer obtained in S8 to form an insulating groove; S10. Form metal electrodes on the outer surfaces of the areas where the first semiconductor opening area and the second semiconductor opening area are located on the back surface of the silicon wafer obtained in S9 respectively.

15. A battery assembly, characterized in that, It includes a back contact battery having a specific front passivation structure as described in any one of claims 1 - 11.

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