Hybrid passivated back contact cell and preparation method therefor, and cell module

Abstract

The present application relates to the technical field of hybrid passivated back contact cells, and in particular to a hybrid passivated back contact cell and a preparation method therefor, and a cell module. In the hybrid passivated back contact cell, a gap region is provided or not provided between a first semiconductor opening region and a second semiconductor opening region; the gap region is a stack structure formed by an edge of a second semiconductor layer extending to an outer surface of a neighboring first semiconductor layer in a Z-axis direction; and in an X-axis direction, an isolation trench spans the gap region and continues to extend to separately span into the second semiconductor opening region and the first semiconductor opening region. According to the hybrid passivated back contact cell of the present application, the gap between the second semiconductor opening region and the first semiconductor opening region is greatly reduced or completely eliminated, thereby increasing the proportion of the contact area between a conductive film layer and a corresponding semiconductor opening region, reducing the transverse transport distance of carriers, and reducing parasitic absorption on the back of the cell, and thus increasing the cell current and improving the cell conversion efficiency.

Description

A combined passivated back contact battery and its preparation method and battery assembly

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application number 2024100775070 filed with the Patent Office of China on January 19, 2024, entitled “A Combined Passivated Back Contact Battery, Preparation Method and Battery Assembly Thereof,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application belongs to the technical field of combined passivated back contact batteries, and specifically relates to a combined passivated back contact battery, a preparation method thereof, and a battery assembly. Background Art

[0004] At present, the process flow of back-contact heterojunction solar cells is generally as follows: S11, double-sided polishing of silicon wafers; S12, coating the back of the silicon wafer with a first mask layer for protection; S13, texturing and cleaning the silicon wafer to form a pyramid texturing surface opposite to the first mask layer, and then removing the first mask layer to form a silicon wafer with a single-sided texturing and single-sided polishing structure; S14, sequentially coating the back of the silicon wafer with a first semiconductor layer and a second mask layer, the first semiconductor layer comprising an intrinsic amorphous or microcrystalline silicon layer and an N-type or P-type doped amorphous or microcrystalline silicon layer, and the second mask layer is generally silicon nitride; S15, laser or etch an opening on the back of the silicon wafer, remove the second mask layer and part of the first semiconductor layer to form a second semiconductor opening area; S16, cleaning the silicon wafer to remove the first semiconductor layer in the second semiconductor opening area; S17, the front of the silicon wafer An amorphous layer and an anti-reflection layer are sequentially formed on the front surface, and a second semiconductor layer is formed on the back surface. The second semiconductor layer comprises an intrinsic amorphous or microcrystalline silicon layer and a P-type or N-type doped amorphous or microcrystalline silicon layer (when the first semiconductor layer is N-type, the second semiconductor layer is P-type, and when the first semiconductor layer is P-type, the second semiconductor layer is N-type). S18: Laser or etching openings are formed on the back surface of the silicon wafer to form first semiconductor opening regions that are arranged alternately with second semiconductor opening regions. S19: The silicon wafer is cleaned to remove the second mask layer within the first semiconductor opening regions. S20: A conductive film layer is deposited on the back surface of the silicon wafer. S21: An isolation trench is formed between the first and second semiconductor opening regions by laser or etching. S22: Metal electrodes are formed on the first and second semiconductor opening regions of the silicon wafer. Back-contact cells also have a combined passivation structure, in which the first semiconductor layer comprises a tunneling oxide layer and a first doped polysilicon layer.

[0005] However, in existing back-contact cells, a spacer is required between the first and second semiconductor opening regions. The spacer refers to the region where the first and second semiconductor layers overlap in the Z-axis direction. In HBC cells, the isolation trench must be located within the spacer. Therefore, the width of the isolation trench in conventional HBC cells is smaller than the spacer. The width of the spacer between the first and second semiconductor opening regions is typically 100-200 μm. The cell conversion efficiency of back-contact cells with this structure needs to be further improved.

[0006] Summary of the Invention

[0007] Research has found that in the back-contact battery of the prior art, the spacer area needs to occupy a larger width. At the same time, the setting of the spacer area reduces the contact area ratio between the conductive film layer and the first semiconductor opening area and the second semiconductor opening area, which is not conducive to reducing the arrangement period of the PN junction, increases the contact area of ​​the spacer area, and at the same time increases the contact resistance between the conductive film layer and the first semiconductor opening area and the second semiconductor opening area, increases the transmission distance of the carriers, and thus increases the series resistance of the battery; in addition, the spacer area is a stacked structure of the first semiconductor layer and the second semiconductor layer, which increases the parasitic absorption on the back side of the battery, thereby reducing the battery current, and further reducing the battery conversion efficiency and battery production yield.

[0008] The purpose of this application is to overcome the defects of the prior art that the battery conversion efficiency and battery production yield need to be further improved, and to provide a combined passivated back contact battery and its preparation method and battery assembly. The combined passivated back contact battery greatly reduces or completely eliminates the distance between the second semiconductor opening area and the first semiconductor opening area, which is beneficial to increase the contact area ratio between the conductive film layer and the corresponding semiconductor opening area, reduce the lateral transmission distance of the carriers, and reduce the parasitic absorption on the back of the battery, thereby increasing the battery current, improving the battery conversion efficiency, and taking into account the improvement of the battery production yield.

[0009] In order to achieve the above-mentioned objectives, in a first aspect, the present application provides a combined passivation back contact battery, comprising a silicon wafer having a front side and a back side, a first semiconductor layer and a second semiconductor layer alternately arranged along the X-axis direction of the back side of the silicon wafer, and a conductive film layer arranged on the outer surface of the first semiconductor layer and the second semiconductor layer in the Z-axis direction of the back side, an isolation groove is opened on the conductive film layer, a first semiconductor opening region is formed between adjacent second semiconductor layers, and a second semiconductor opening region is provided on the outer surface of the second semiconductor layer; wherein, the first semiconductor layer comprises a tunneling oxide layer and a first doped polysilicon layer, the second semiconductor layer comprises an intrinsic silicon layer and a second doped silicon layer, and the first semiconductor layer comprises a second doped silicon layer. A spacer region is set or not set between the first semiconductor opening region and the second semiconductor opening region. The spacer region is a stacked structure formed by extending the edge of the second semiconductor layer to the Z-axis direction outer surface of the adjacent first semiconductor layer. The width Wa11 of the spacer region in the X-axis direction is 0-50μm, and in the X-axis direction, the isolation groove spans the spacer region and continues to extend across the second semiconductor opening region and the first semiconductor opening region respectively. The width Wa of the isolation groove is 20-120μm, and on the same plane parallel to the silicon wafer, the sum of the contact areas of the conductive film layer and its corresponding semiconductor opening region accounts for 70%-95% of the total area of ​​the silicon wafer.

[0010] In some preferred embodiments of the present application, the edge of the second semiconductor layer only extends to the outer surface of the side surface in the X-axis direction of the adjacent first semiconductor layer, and no spacing region is provided between the first semiconductor opening region and the second semiconductor opening region.

[0011] In some preferred embodiments of the present application, the sum of the corresponding widths of the conductive film layers in their corresponding semiconductor opening regions accounts for 70%-95% of the overall width of the silicon wafer.

[0012] In some preferred embodiments of the present application, the ratio of the width Wa11 of the spacer region to the width Wa of the isolation trench is 0-0.9:1.

[0013] In some preferred embodiments of the present application, the ratio of the cross width Wa2 of the isolation trench in the second semiconductor opening region to the cross width Wa1 of the isolation trench in the first semiconductor opening region is 0.3-3:1.

[0014] In some preferred embodiments of the present application, the cross width Wa1 of the isolation trench in the first semiconductor opening region is 10%-90% of the width Wa of the isolation trench.

[0015] In some preferred embodiments of the present application, a cross width Wa2 of the isolation trench in the second semiconductor opening region is 10-60 μm, and a cross width Wa1 of the isolation trench in the first semiconductor opening region is 10-60 μm.

[0016] In some preferred embodiments of the present application, in the X-axis direction, the width W11 of the first semiconductor opening region is ≤ the width W1 of the first semiconductor layer and the difference is 0-0.1 mm.

[0017] In some preferred embodiments of the present application, the width W1 of the first semiconductor layer is 0.20-0.70 mm.

[0018] In some preferred embodiments of the present application, the width of the second semiconductor layer is 0.3-0.8 mm.

[0019] Preferably, the width W2 of the second semiconductor opening region is 0.3-0.8 mm.

[0020] Preferably, the width W11 of the first semiconductor opening region is 0.20-0.70 mm.

[0021] In some preferred embodiments of the present application, the sum of the width W1 of the first semiconductor layer and the width W2 of the second semiconductor opening area is between 0.7-1.3 mm, and the width of the arrangement period of the PN junction formed by the first semiconductor layer and the second semiconductor layer is the sum of W1 and W2.

[0022] In some preferred embodiments of the present application, the back side of the portion of the silicon wafer where the first semiconductor layer is located is a polished surface, and the back side of the portion of the silicon wafer where the second semiconductor layer is located is a textured surface.

[0023] In some preferred embodiments of the present application, the combined passivation back contact cell has at least one of the following structures:

[0024] Structure 1: The tunneling oxide layer has a thickness of 1-2 nm, the first doped polysilicon layer has a thickness of 50-130 nm and an effective doping concentration of 1e19 cm-3-9e20 cm-3, the intrinsic silicon layer has a thickness of 3-8 nm, and the second doped silicon layer has a thickness of 8-20 nm and an effective doping concentration of 1e19 cm-3-1e20 cm-3;

[0025] Structure 2: The thickness of the conductive film layer is 30-120 nm.

[0026] Structure 3: A mask layer is provided between the first semiconductor layer and the second semiconductor layer in the stacked structure, or no mask layer is provided, and the thickness of the mask layer is 0-40 nm;

[0027] Structure 4: The combined passivation back contact battery also includes a metal electrode and a front passivation layer and an anti-reflection layer sequentially arranged on the front side of the silicon wafer. The metal electrode is arranged on the outer surface of the conductive film layer and corresponds to the first semiconductor opening area and the second semiconductor opening area respectively.

[0028] In a second aspect, the present application provides a method for preparing a combined passivated back contact cell, which is configured to prepare the combined passivated back contact cell described in the first aspect.

[0029] The preparation method of the combined passivation back contact battery includes the following steps:

[0030] S101, providing silicon wafers;

[0031] S102, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer;

[0032] S103, removing a portion of the first semiconductor layer and its corresponding mask layer in the first preset area on the back side obtained in S102, to form a second semiconductor opening area;

[0033] S104, then forming a textured surface on the front side and the second semiconductor opening area on the back side of the silicon wafer by texturing and cleaning, and simultaneously etching away 50%-100% of the thickness of the mask layer;

[0034] S105, forming a second semiconductor layer on the back surface obtained in S104;

[0035] S106, removing a portion of the second semiconductor layer and the corresponding mask layer in the second preset area on the back surface obtained in S105, to form a first semiconductor opening area spaced apart from the second semiconductor opening area, with the area between the first semiconductor opening area and the second semiconductor opening area being a spacer area;

[0036] S107, forming a conductive film layer on the back surface obtained in S106;

[0037] S108 , performing etching to open the third predetermined area on the back surface obtained in S107 to form an isolation trench.

[0038] In some preferred embodiments of the present application, the thickness of the mask layer formed in S102 is 40-80 nm.

[0039] In some preferred embodiments of the present application, the method for preparing the combined passivation back contact cell further comprises at least one of the following methods:

[0040] Method 1, S105 also includes the step of forming a front passivation layer and an anti-reflection layer on the front side of the silicon wafer;

[0041] Method 2, S109, forming metal electrodes on the outer surfaces of the conductive film layer on the back side obtained in S108;

[0042] Method 3: The second semiconductor opening region and the first semiconductor opening region are formed by laser etching respectively, and the laser etching uses a picosecond or femtosecond laser, and the laser is a green laser or an ultraviolet laser.

[0043] In a third aspect, the present application provides a battery assembly comprising the combined passivated back contact battery described in the first aspect. Beneficial effects:

[0044] The present application adopts the above-mentioned technical solution, especially not setting a spacing area or setting a spacing area of ​​narrower width, and controlling the isolation groove of specific width and specific structure to reduce the width of the stacked structure of the first semiconductor layer and the second semiconductor layer, greatly reduce or completely eliminate the spacing between the second semiconductor opening area and the first semiconductor opening area, thereby facilitating increasing the contact area ratio between the conductive film layer and the corresponding semiconductor opening area, reducing the lateral transmission distance of carriers, reducing the parasitic absorption on the back side of the battery, thereby increasing the battery current and improving the battery conversion efficiency, while not easily causing problems such as micro-short circuits, and taking into account improving the battery production yield; and cooperating with controlling the contact area ratio of the conductive film layer within a suitable large range, on the one hand, it is suitable for increasing the contact area ratio between the conductive film layer and the first semiconductor opening area and the second semiconductor opening area, thereby reducing the contact resistance; on the other hand, it reduces the arrangement period of the battery PN junction, reduces the carrier transmission distance, reduces the series resistance, and promotes the improvement of the battery conversion efficiency.

[0045] Moreover, the specific structure of the above-mentioned spacer, isolation groove and conductive film layer of the present application, combined with the combined passivation structure, its first semiconductor layer includes a tunneling oxide layer and a first doped polysilicon layer. The structure of the first semiconductor layer has strong weather resistance, so that a wider isolation groove and a narrower spacer or no spacer can be used to increase the contact area ratio of the conductive film layer, thereby helping to improve the battery conversion efficiency. In the prior art, the first semiconductor layer of the conventional back-contact heterojunction battery is a stacked structure of intrinsic amorphous and doped amorphous layers. The intrinsic amorphous and doped amorphous layers have poor acid and alkali resistance (furthermore, the thickness of the stacked structure of intrinsic amorphous and doped amorphous layers is generally very thin, generally less than 20nm, which is much lower than the thickness of the first semiconductor layer of the present application). It cannot withstand long-term isolation groove etching and can only adopt a narrower isolation groove width formed in the spacer.

[0046] In the preparation method of the present application, laser etching is preferably used to form the first semiconductor opening region, and a short-pulse laser, such as a picosecond green light or ultraviolet laser, or a femtosecond green light or ultraviolet laser, is used, which is more conducive to reducing the thermal impact of the laser on the second semiconductor opening region and its second semiconductor layer which are closer (this is because the second semiconductor layer is deposited at low temperature and is relatively more sensitive to the thermal impact of the laser), thereby helping to maintain the passivation effect of the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0048] FIG1 is a schematic diagram of a silicon wafer structure provided in an example of an embodiment of the present application;

[0049] FIG2 is a schematic structural diagram of forming a tunneling oxide layer, a first doped polysilicon layer, and a mask layer on the back side of a silicon wafer according to an embodiment of the present application;

[0050] FIG3 is a schematic structural diagram of forming a second semiconductor opening region on the back side of a silicon wafer in an example of an embodiment of the present application;

[0051] FIG4 is a schematic diagram of the structure of an embodiment of the present application after texturing and cleaning;

[0052] FIG5 is a schematic structural diagram of an embodiment of an embodiment of the present application in which a front passivation layer and an anti-reflection layer are formed on the front side of a silicon wafer, and a second semiconductor layer is formed on the back side;

[0053] FIG6 is a schematic structural diagram of forming a first semiconductor opening region on the back side of a silicon wafer in an example of an embodiment of the present application;

[0054] FIG7 is a schematic structural diagram of forming a conductive film layer on the back side of a silicon wafer in an example of an embodiment of the present application;

[0055] FIG8 is a schematic structural diagram of an example of an embodiment of the present application in which an isolation trench is formed on the back side of a silicon wafer;

[0056] FIG9 is a schematic diagram of a structure in which a metal electrode is formed on the back side of a silicon wafer according to an embodiment of the present application.

[0057] FIG10 is a schematic structural diagram of a conventional back-contact battery of Comparative Example 1.

[0058] Description of Reference Numerals

[0059] 1. Silicon wafer, 2. Tunneling oxide layer, 3. First doped polysilicon layer, 4. Mask layer, 5. Intrinsic amorphous silicon layer, 6. Second doped amorphous silicon layer, 7. Front passivation layer, 8. Anti-reflection layer, 9. Conductive film layer, 10. Metal electrode. DETAILED DESCRIPTION

[0060] In this application, unless otherwise specified, directional words such as "up, down, left, right" generally refer to the directions shown in the drawings and actual applications, and "inside and outside" refer to the inside and outside of the outline of the component.

[0061] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0062] In this application, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0063] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein. Among them, the terms "optional" and "optional" all mean that they may be included or not (or may be present or not).

[0064] In this application, the direction close to the silicon wafer is referred to as the inside, and the direction away from the silicon wafer is referred to as the outside.

[0065] In a first aspect, the present application provides a combined passivation back contact battery, comprising a silicon wafer having a front side and a back side, a first semiconductor layer and a second semiconductor layer alternately arranged along the X-axis direction of the back side of the silicon wafer, and a conductive film layer arranged on the outer surface of the first semiconductor layer and the second semiconductor layer in the Z-axis direction of the back side, wherein an isolation groove is provided on the conductive film layer, a first semiconductor opening region is formed between adjacent second semiconductor layers, and a second semiconductor opening region is provided on the outer surface of the second semiconductor layer; wherein the first semiconductor layer comprises a tunneling oxide layer and a first doped polysilicon layer, the second semiconductor layer comprises an intrinsic silicon layer and a second doped silicon layer, and the first semiconductor opening region is provided on the outer surface of the first semiconductor layer. A spacer region may or may not be set between the opening region and the second semiconductor opening region. The spacer region is a stacked structure formed by extending the edge of the second semiconductor layer to the outer surface of the adjacent first semiconductor layer in the Z-axis direction. The width Wa11 of the spacer region in the X-axis direction is 0-50 μm, and in the X-axis direction, the isolation groove spans the spacer region and continues to extend across the second semiconductor opening region and the first semiconductor opening region respectively. The width Wa of the isolation groove is 20-120 μm, and on the same plane parallel to the silicon wafer, the sum of the contact areas of the conductive film layer and its corresponding semiconductor opening region accounts for 70%-95% of the total area of ​​the silicon wafer.

[0066] In this application, the sum of the contact areas of the conductive film layer and its corresponding semiconductor opening region refers to the sum of "the sum of the contact areas of the conductive film layer and the first semiconductor opening region where it is located" and "the sum of the contact areas of the conductive film layer and the second semiconductor opening region where it is located".

[0067] In some specific embodiments, the width Wa of the isolation trench is 20-50 μm.

[0068] In some preferred embodiments of the present application, the ratio of the width Wa11 of the spacer region to the width Wa of the isolation trench is 0-0.9:1.

[0069] When setting the spacer area (i.e., the width of the spacer area is not 0), in some preferred embodiments of the present application, the ratio of the width Wa11 of the spacer area to the width Wa of the isolation groove is 0.1-0.8:1, which can ensure that the contact area of ​​the conductive film layer in the corresponding semiconductor opening area accounts for as high a proportion as possible, and at the same time is not prone to problems such as micro short circuits, which is more conducive to improving the battery production yield.

[0070] In some preferred embodiments of the present application, the edge of the second semiconductor layer extends only to the outer surface of the side surface of the adjacent first semiconductor layer in the X-axis direction, and no spacer is provided between the first semiconductor opening region and the second semiconductor opening region. The absence of a spacer, with a width of zero, means that there is no stacked structure in the Z-axis direction. This can minimize the width of the stacked structure of the first and second semiconductor layers, completely eliminate the spacing between the spacer between the second semiconductor opening region and the first semiconductor opening region, and further increase the contact area ratio between the conductive film layer and the corresponding semiconductor opening region through coordinated control, thereby reducing the lateral carrier transmission distance and reducing parasitic absorption on the back side of the battery, thereby further increasing the battery current, reducing the series resistance, and further improving the battery conversion efficiency.

[0071] On the basis of ensuring that the ratio of the contact area of ​​the conductive film layer with its corresponding semiconductor opening region to the area of ​​the corresponding semiconductor opening region is within the aforementioned range, those skilled in the art may adjust the width of the conductive film layer. In some preferred embodiments of the present application, the sum of the corresponding widths of the conductive film layer within its corresponding semiconductor opening region accounts for 70%-95% of the overall width of the silicon wafer. This appropriate width ratio can ensure that the contact area ratio of the conductive film layer to the corresponding semiconductor opening region is as high as possible, while being less likely to cause problems such as micro-short circuits, and is more conducive to improving the yield rate of battery production.

[0072] In the X-axis direction, the isolation trench crosses the spacing region and continues to extend into the second semiconductor opening region and the first semiconductor opening region, respectively, indicating that the width Wa of the isolation trench is greater than the width of the spacing region.

[0073] In some preferred embodiments of the present application, the ratio of the cross-width Wa2 of the isolation groove in the second semiconductor opening area to its cross-width Wa1 in the first semiconductor opening area is 0.3-3:1. The cross-width ratio is appropriate, which can ensure that the contact area ratio of the conductive film layer in the semiconductor opening area is as high as possible. At the same time, it is not easy to cause problems such as micro short circuits, and is more conducive to improving the battery production yield.

[0074] More preferably, Wa2 is the same as Wa1.

[0075] It can be understood that the width of the isolation trench not only includes the widths Wa1 and Wa2 , but also includes the width Wa11 of the spacer region located in the stacking region of the first semiconductor layer and the second semiconductor layer.

[0076] In some preferred embodiments of the present application, the isolation trench has a width Wa1 within the first semiconductor opening region that is 10%-90%, preferably 30%-90%, of the isolation trench's width Wa. Using the preferred Wa1 / Wa is more conducive to reducing micro-short circuits and improving parallel resistance.

[0077] In some preferred embodiments of the present application, a cross width Wa2 of the isolation trench in the second semiconductor opening region is 10-60 μm.

[0078] Preferably, the isolation trench has a cross width Wa1 in the first semiconductor opening region of 10-60 μm.

[0079] In some preferred embodiments of the present application, in the X-axis direction, the width W11 of the first semiconductor opening region is ≤ the width W1 of the first semiconductor layer and the difference is 0-0.1 mm, preferably 0-0.5 mm.

[0080] In the present application, the tunnel oxide layer and the first doped polysilicon layer are sequentially arranged from the inside to the outside along the Z-axis direction, and the intrinsic silicon layer and the second doped silicon layer are sequentially arranged from the inside to the outside along the Z-axis direction.

[0081] In some preferred embodiments of the present application, the width W1 of the first semiconductor layer is 0.20-0.70 mm.

[0082] Preferably, the width W11 of the first semiconductor opening region is 0.20-0.70 mm, more preferably 0.20-0.40 mm.

[0083] In some preferred embodiments of the present application, the width of the second semiconductor layer is 0.3-0.8 mm.

[0084] Preferably, the width W2 of the second semiconductor opening region is 0.3-0.8 mm.

[0085] In some preferred embodiments of the present application, the sum of the width W1 of the first semiconductor layer and the width W2 of the second semiconductor opening region is between 0.7 and 1.3 mm, preferably between 0.7 and 0.9 mm. The width of the arrangement period of the PN junction formed by the first and second semiconductor layers is the sum of W1 and W2. Using an appropriately short arrangement period is more conducive to shortening the lateral transport distance of carriers, thereby reducing series resistance.

[0086] It can be understood that there are two isolation grooves in each arrangement period.

[0087] In some preferred embodiments of the present application, the back side of the portion of the silicon wafer where the first semiconductor layer is located is a polished surface, and the back side of the portion of the silicon wafer where the second semiconductor layer is located is a textured surface.

[0088] In some preferred embodiments of the present application, the thickness of the tunnel oxide layer is 1-2 nm, the thickness of the first doped polysilicon layer is 50-130 nm, and the effective doping concentration is 1e19 cm-3-9e20 cm-3.

[0089] Preferably in the present application, the thickness of the intrinsic silicon layer is 3-8 nm, the thickness of the second doped silicon layer is 8-20 nm, and the effective doping concentration is 1e19 cm-3-1e20 cm-3.

[0090] In the present application, one of the first doped polysilicon layer and the second doped silicon layer is N-type and the other is P-type. The intrinsic silicon layer can be an intrinsic amorphous silicon layer or an intrinsic microcrystalline silicon layer, and the second doped silicon layer can be a second doped amorphous silicon layer or a second doped microcrystalline silicon layer.

[0091] The silicon wafer described in this application can be an N-type or P-type silicon wafer.

[0092] Preferably in the present application, the thickness of the conductive film layer is 30-120 nm, preferably 40-80 nm.

[0093] The material of the conductive film layer can refer to the corresponding types in the prior art. For example, the material of the conductive film layer can be an indium oxide-based thin film doped with at least one of tin, zinc, tungsten, and titanium.

[0094] Preferably, in the present application, a mask layer is provided between the first semiconductor layer and the second semiconductor layer in the stacked structure, or no mask layer is provided.

[0095] Furthermore, the thickness of the mask layer is 0-40 nm.

[0096] The mask layer is a silicon dielectric layer, such as a combination of one or more of silicon nitride, silicon oxynitride, silicon oxide, intrinsic silicon, and silicon carbide.

[0097] It can be understood that the first semiconductor layer, the second semiconductor layer, the conductive film layer and the optional mask layer are respectively extended along another axial direction perpendicular to the X-axis direction and perpendicular to the Z-axis direction, that is, they are extended along the length direction of the first semiconductor opening area and the second semiconductor opening area, and preferably their lengths are the same.

[0098] In some preferred embodiments of the present application, the combined passivated back-contact cell further includes a metal electrode, a front passivation layer, and an optional anti-reflection layer sequentially disposed on the front surface of the silicon wafer. The metal electrode is disposed on the outer surface of the conductive film layer and corresponds to the first semiconductor opening region and the second semiconductor opening region, respectively. The anti-reflection layer may or may not be disposed on the outer surface of the front passivation layer, depending on actual needs.

[0099] The types and thicknesses of the front passivation layer and the anti-reflection layer described in this application can be set with reference to any corresponding range in the prior art. Exemplarily, the front passivation layer can be an intrinsic amorphous layer, a composite layer of an intrinsic amorphous layer and an N-type microcrystalline layer, a silicon dioxide layer, or a composite layer of silicon dioxide and an N-type polycrystalline composite layer, an aluminum oxide layer, and at least one of any other passivation materials. Exemplarily, the anti-reflection layer can be a combination of one or more of silicon nitride, silicon oxynitride, and silicon oxide. Exemplarily, the thickness of the front passivation layer can be 3-12 nm, and the thickness of the anti-reflection layer can be 60-100 nm.

[0100] In a second aspect, the present application provides a method for preparing a combined passivated back contact cell, which is configured to prepare the combined passivated back contact cell described in the first aspect.

[0101] A preparation method of a combined passivated back contact cell of the present application comprises the following steps:

[0102] S101, providing silicon wafers;

[0103] S102, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer;

[0104] S103, removing a portion of the first semiconductor layer and its corresponding mask layer in the first preset area on the back side obtained in S102, to form a second semiconductor opening area;

[0105] S104, then forming a textured surface on the front side and the second semiconductor opening area on the back side of the silicon wafer by texturing and cleaning, and simultaneously etching away 50%-100% of the thickness of the mask layer;

[0106] S105, forming a second semiconductor layer on the back surface obtained in S104;

[0107] S106, removing a portion of the second semiconductor layer and the corresponding mask layer in the second preset area on the back surface obtained in S105, to form a first semiconductor opening area spaced apart from the second semiconductor opening area, with the area between the first semiconductor opening area and the second semiconductor opening area being a spacer area;

[0108] S107, forming a conductive film layer on the back surface obtained in S106;

[0109] S108 , performing etching to open the third predetermined area on the back surface obtained in S107 to form an isolation trench.

[0110] The present application adopts a post-texturing method of thinning the mask layer to prepare a combined passivated back contact battery of the aforementioned structure, which can remove the mask layer residue in the texturing side erosion area and is more conducive to improving the battery passivation effect.

[0111] In some preferred embodiments of the present application, the thickness of the mask layer formed in S102 is 40-80 nm.

[0112] In S102 of the present application, the method of forming the first semiconductor layer and the mask layer can refer to any corresponding method in the prior art. For example, the tunneling oxide layer can be formed by wet oxidation, thermal oxidation, plasma oxidation, etc., and the first doped polysilicon layer and the mask layer can be formed by chemical vapor deposition (CVD) process followed by annealing crystallization, low-pressure CVD (LPCVD) post-diffusion, sputtering followed by annealing crystallization, and any other existing technology.

[0113] The method of removing the corresponding semiconductor layer and the corresponding mask layer to form the corresponding first semiconductor opening region or the second semiconductor opening region in S103 and S106 can be formed by laser etching, chemical etching or any other required technology.

[0114] In some preferred embodiments of the present application, the method for preparing the combined passivation back contact cell further includes: S105 also includes the step of forming a front passivation layer and an optional anti-reflection layer on the front side of the silicon wafer.

[0115] The step of forming the front passivation layer and the optional anti-reflection layer can be performed before or after forming the second semiconductor layer.

[0116] In the present application, the second semiconductor opening regions and the first semiconductor opening regions are alternately arranged. The second semiconductor opening regions and the first semiconductor opening regions can be formed by laser etching or mask etching. In some preferred embodiments of the present application, the method for preparing a combined passivated back contact cell further includes: forming the second semiconductor opening regions and the first semiconductor opening regions by laser etching, respectively. Laser etching is used to form the corresponding semiconductor opening regions.

[0117] Furthermore, the laser etching uses a picosecond or femtosecond laser, and the laser is a green laser or an ultraviolet laser.

[0118] In some specific embodiments, the second semiconductor opening region is formed by picosecond green laser etching.

[0119] The method for forming the conductive film layer in S107 can refer to the corresponding method in the prior art. For example, the conductive film layer can be formed by magnetron sputtering, evaporation, ion beam evaporation, activated plasma vapor deposition and any other required technology.

[0120] The isolation groove in S108 can be formed by, for example, laser, ink etching, mask etching, or any other desired technology.

[0121] In some preferred embodiments of the present application, the method for preparing a combined passivated back contact cell further comprises S109, forming metal electrodes on the outer surfaces of the conductive film layer on the back obtained in S108. The metal electrodes can be formed by printing, transfer printing, electroplating, etc.

[0122] In a third aspect, the present application provides a battery assembly comprising the combined passivated back contact battery described in the first aspect.

[0123] The following describes embodiments of the present application in detail, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only configured to explain the present application and are not to be construed as limiting the present application.

[0124] Example 1

[0125] A combined passivation back contact cell, as shown in FIG9 , is prepared as follows:

[0126] S101, as shown in FIG1 , providing a silicon wafer 1, wherein the silicon wafer 1 is an N-type silicon wafer;

[0127] S102. As shown in Figure 2, a first semiconductor layer is formed on the back side of the silicon wafer 1, wherein the first semiconductor layer includes a tunneling oxide layer 2, an N-type first doped polysilicon layer 3, and a mask layer 4. The tunneling oxide layer 2 has a thickness of 1.6 nm, the first doped polysilicon layer 3 has a thickness of 100 nm, and the effective doping concentration is 1e20 cm-3, the mask layer 4 has a thickness of 60 nm, and the mask layer 4 is silicon nitride; the tunneling oxide layer 2 and the first doped polysilicon layer 3 are formed by LPCVD post-diffusion, and the mask layer 4 is formed using a chemical vapor deposition (CVD) process.

[0128] S103, as shown in Figure 3, forming a second semiconductor opening region on the back side of the silicon wafer 1. The second semiconductor opening region is completed by picosecond green laser etching.

[0129] S104. As shown in FIG4 , a texturing process is performed to form a textured surface in the second semiconductor opening regions on the front and back sides of the silicon wafer 1. Simultaneously, 80% of the thickness of the mask layer 4 is removed by etching. After texturing, the width W2 of the second semiconductor opening region is 0.5 mm, the width W1 of the first semiconductor layer is 0.3 mm, and the width of the arrangement period of the PN junction formed by the first and second semiconductor layers is the sum of W1 and W2.

[0130] S105. As shown in FIG5 , a second semiconductor layer is formed on the back side of the silicon wafer 1, and a front passivation layer 7 and an anti-reflection layer 8 are formed on the front side of the silicon wafer 1. The second semiconductor layer comprises an intrinsic amorphous silicon layer 5 and a P-type second doped amorphous silicon layer 6. The intrinsic amorphous silicon layer 5 is 6 nm thick, and the second doped amorphous silicon layer 6 is 10 nm thick with an effective doping concentration of 4e19 cm⁻³. The front passivation layer 7 is an intrinsic amorphous layer with a thickness of 7 nm. The anti-reflection layer 8 is silicon nitride with a thickness of 75 nm.

[0131] S106. A first semiconductor opening region is formed by etching an opening in a second predetermined area on the back side of the silicon wafer 1. The width W11 of the first semiconductor opening region is 0.3 mm, and the width W11 of the first semiconductor opening region is the same as the width W1 of the first semiconductor layer. The opening in the first semiconductor opening region is etched by laser etching using a 5 picosecond green laser.

[0132] S107. As shown in FIG7 , a 60 nm thick conductive film layer 9 is formed on the back side of the silicon wafer 1. The conductive film layer 9 is a tin-doped indium oxide-based thin film and is formed by magnetron sputtering. The first semiconductor layer, the second semiconductor layer, the conductive film layer, and the mask layer are all arranged along the length of the first semiconductor opening region and the second semiconductor opening region, respectively, and have the same length. The ratio of the sum of the contact areas of the conductive film layer 9 and its corresponding semiconductor opening region to the total area of ​​the silicon wafer 1 (referred to as the conductive film layer area ratio) = (800 - 40 × 2) / 800 = 90%, as shown in Table 1.

[0133] S108. As shown in FIG8 , an isolation trench is formed in conductive film layer 9 on the back side of silicon wafer 1. The isolation trench is etched simultaneously across a portion of the first semiconductor opening region and the second semiconductor opening region. The isolation trench width Wa is 40 μm, with a width Wa1 across the first semiconductor opening region being 20 μm and a width Wa2 across the second semiconductor opening region being 20 μm. The isolation trench is formed by etching ink.

[0134] S109 , as shown in FIG9 , forming a metal electrode 10 on the back side of the silicon wafer 1 , wherein the metal electrode 10 is formed by printing.

[0135] Example 2

[0136] Proceed with reference to Example 1, except that:

[0137] S106, as shown in FIG6, the width W11 of the first semiconductor opening region is 0.26 mm;

[0138] S108 , the width Wa of the isolation trench is 60 μm, the cross width Wa1 etched to the first semiconductor opening region is 20 μm, the cross width Wa2 etched to the second semiconductor opening region is 20 μm, and the spacing region width is as shown in Table 1.

[0139] Example 3

[0140] Proceed with reference to Example 1, except that:

[0141] S104 , the width W1 of the first semiconductor layer is 0.4 mm, and the width of the arrangement period is 0.9 mm.

[0142] S106, the width W11 of the first semiconductor opening region is 0.36 mm;

[0143] S108 , the width Wa of the isolation trench is 60 μm, the cross width Wa1 etched to the first semiconductor opening region is 20 μm, the width Wa2 etched to the second semiconductor opening region is 20 μm, and the width of the spacer region is as shown in Table 1.

[0144] Example 4

[0145] Proceed with reference to Example 1, except that:

[0146] S104 , the width W1 of the first semiconductor layer is 0.5 mm, and the width of the arrangement period is 1 mm.

[0147] S106, the width W11 of the first semiconductor opening region is 0.46 mm;

[0148] S108 , the width Wa of the isolation trench is 60 μm, the cross width Wa1 etched to the first semiconductor opening region is 20 μm, the width Wa2 etched to the second semiconductor opening region is 20 μm, and the width of the spacer region is as shown in Table 1.

[0149] Example 5

[0150] Refer to Example 2, except that: the width W11 of the first semiconductor opening area in S106 is adjusted to 0.24 mm, so that W11 is smaller than the width W1 of the first semiconductor layer and the difference is 0.06 mm; and the isolation groove width, the spacing area width, and the area ratio of the conductive film layer are adjusted as shown in Table 1.

[0151] Example 6

[0152] The process is carried out in accordance with Example 2, except that the width Wa of the isolation trench in S108 is adjusted to 100 μm, Wa1 and Wa2 remain unchanged, so that Wa1 is 20% of the width Wa of the isolation trench; and the width of the spacer region and the area ratio of the conductive film layer are adjusted as shown in Table 1.

[0153] Example 7

[0154] The process is carried out in accordance with Example 2, except that the thickness of the mask layer is adjusted to be 100% removed by etching in S104, that is, the mask layer is completely removed.

[0155] Comparative Example 1

[0156] The same procedure is carried out with reference to Example 1, except that, as shown in FIG10 :

[0157] S106, the width W11 of the first semiconductor opening region is 0.1 mm; the arrangement period width is as shown in Table 1;

[0158] S108. The isolation groove width Wa is 60 μm, and is etched in the spacer region between the first semiconductor opening region and the second semiconductor opening region (not spanning the corresponding semiconductor opening regions on both sides). The width of the spacer region is shown in Table 1. The isolation groove width Wa is smaller than the width of the spacer region.

[0159] Comparative Example 2

[0160] The same procedure is carried out with reference to Example 3, except that, as shown in FIG10 :

[0161] S106, the width W11 of the first semiconductor opening region is 0.2 mm;

[0162] S108. The isolation groove width Wa is 60 μm, and is etched in the spacer region between the first semiconductor opening region and the second semiconductor opening region (not spanning the corresponding semiconductor opening regions on both sides). The width of the spacer region is shown in Table 1. The isolation groove width Wa is smaller than the width of the spacer region.

[0163] Comparative Example 3

[0164] The same procedure is carried out with reference to Example 4, except that, as shown in FIG10 :

[0165] S106, the width W11 of the first semiconductor opening region is 0.3 mm;

[0166] S108. The isolation groove width Wa is 60 μm, and is etched in the spacer region between the first semiconductor opening region and the second semiconductor opening region (not spanning the corresponding semiconductor opening regions on both sides). The width of the spacer region is shown in Table 1. The isolation groove width Wa is smaller than the width of the spacer region.

[0167] Test Case

[0168] The back-contact cells obtained in the above examples and comparative examples were subjected to performance testing, and the results are shown in Table 1. The cell current and series resistance were normalized to the values ​​of Example 1, with a value of "1" as the benchmark. For example, the cell current of Example 2 was 99.90% of the corresponding data of Example 1, and the series resistance of Example 2 was 100.1% of the corresponding data of Example 1.

[0169] Table 1

[0170] It can be seen from the above results that, compared with the comparative example, the combined passivation back contact battery of the embodiment of the present application can reduce the width of the stacked structure of the first semiconductor layer and the second semiconductor layer, greatly reduce or completely eliminate the spacing between the second semiconductor opening area and the first semiconductor opening area, and cooperate with the control to increase the contact area ratio between the conductive film layer and the corresponding semiconductor opening area, reduce the lateral transmission distance of the carriers, and reduce the parasitic absorption on the back side of the battery, thereby increasing the battery current, reducing the series resistance, and improving the battery conversion efficiency, while taking into account the improvement of the battery production yield.

[0171] Furthermore, according to the comparison between Example 1 and Examples 2-6 of the present application, it can be seen that the combined passivated back contact battery with the preferred structural parameters of the present application is more conducive to increasing the battery current, reducing the series resistance, and improving the battery conversion efficiency, while also taking into account the improvement of the battery production yield.

[0172] The preferred embodiments of the present application are described in detail above, but the present application is not limited thereto. Within the technical concept of the present application, various simple modifications can be made to the technical solution of the present application, including combining the various technical features in any other appropriate manner. These simple modifications and combinations should also be regarded as the contents disclosed in the present application and fall within the scope of protection of the present application. Industrial Applicability

[0173] In the combined passivated back contact battery of the above scheme, a spacer region is provided or not provided between the first semiconductor opening region and the second semiconductor opening region. The spacer region is a stacked structure formed by extending the edge of the second semiconductor layer to the outer surface of the adjacent first semiconductor layer in the Z-axis direction, and in the X-axis direction, the isolation trench spans the spacer region and continues to extend across the second semiconductor opening region and the first semiconductor opening region, respectively. The combined passivated back contact battery of the present application significantly reduces or completely eliminates the spacing between the second semiconductor opening region and the first semiconductor opening region, thereby facilitating an increase in the contact area ratio between the conductive film layer and the corresponding semiconductor opening region, reducing the lateral carrier transmission distance, and reducing parasitic absorption on the back of the battery, thereby increasing the battery current and improving the battery conversion efficiency.

Claims

1. A combined passivated back contact battery, comprising a silicon wafer having a front side and a back side, a first semiconductor layer and a second semiconductor layer alternately arranged along the X-axis direction of the back side of the silicon wafer, and a conductive film layer disposed on the outer surfaces of the first semiconductor layer and the second semiconductor layer in the Z-axis direction of the back side, an isolation groove is formed on the conductive film layer, a first semiconductor opening region is formed between adjacent second semiconductor layers, and a second semiconductor opening region is provided on the outer surface of the second semiconductor layer; wherein, The first semiconductor layer includes a tunneling oxide layer and a first doped polysilicon layer, and the second semiconductor layer includes an intrinsic silicon layer and a second doped silicon layer. It is characterized in that a spacer region is provided or not provided between the first semiconductor opening region and the second semiconductor opening region. The spacer region is a stacked structure formed by the edge of the second semiconductor layer extending to the outer surface of the adjacent first semiconductor layer in the Z-axis direction. The width Wa11 of the spacer region in the X-axis direction is 0 - 50 μm, and in the X-axis direction, the isolation groove straddles the spacer region and continues to extend and straddle into the second semiconductor opening region and the first semiconductor opening region respectively. The width Wa of the isolation groove is 20 - 120 μm, and on the same plane parallel to the silicon wafer, the sum of the contact areas of the conductive film layer with its corresponding semiconductor opening regions accounts for 70% - 95% of the overall area of the silicon wafer.

2. The passivated back-contact cell according to claim 1, wherein The edge of the second semiconductor layer only extends to the outer surface of the side surface of the adjacent first semiconductor layer in the X-axis direction, and no spacer region is provided between the first semiconductor opening region and the second semiconductor opening region; and / or, The sum of the corresponding widths of the conductive film layer in its corresponding semiconductor opening regions accounts for 70% - 95% of the overall width of the silicon wafer.

3. The passivated back contact cell according to claim 1, wherein The across-width Wa1 of the isolation groove in the first semiconductor opening region is 10% - 90% of the width Wa of the isolation groove; and / or, The ratio of the width Wa11 of the spacer region to the width Wa of the isolation groove is 0 - 0.9:

1.

4. The passivated back contact cell according to claim 1, wherein In the X-axis direction, the width W11 of the first semiconductor opening region ≤ the width W1 of the first semiconductor layer, and the difference is 0 - 0.1 mm; and / or, The width W1 of the first semiconductor layer is 0.20 - 0.70 mm, and the width W11 of the first semiconductor opening region is 0.20 - 0.70 mm.

5. The passivated back-contact cell according to claim 1 or 4, characterized in that, The width of the second semiconductor layer is 0.3 - 0.8 mm, and the width W2 of the second semiconductor opening region is 0.3 - 0.8 mm; and / or, The sum of the width W1 of the first semiconductor layer and the width W2 of the second semiconductor opening region is between 0.7 - 1.3 mm, and the width of the arrangement period of the PN junctions formed by the first semiconductor layer and the second semiconductor layer is the sum of W1 and W2.

6. The passivated back contact cell according to claim 1, characterized in that, The ratio of the across-width Wa2 of the isolation groove in the second semiconductor opening region to the across-width Wa1 of the isolation groove in the first semiconductor opening region is 0.3 - 3:1; the across-width Wa2 of the isolation groove in the second semiconductor opening region is 10 - 60 μm, and the across-width Wa1 of the isolation groove in the first semiconductor opening region is 10 - 60 μm; and / or, The back surface of the part of the silicon wafer where the first semiconductor layer is located is a polished surface, and the back surface of the part of the silicon wafer where the second semiconductor layer is located is a textured surface.

7. The passivated back contact cell according to claim 1, characterized in that, The combined passivated back contact battery has at least one of the following structures: Structure 1: The thickness of the tunneling oxide layer is 1 - 2 nm, the thickness of the first doped polysilicon layer is 50 - 130 nm, the effective doping concentration is 1e19 cm-3 - 9e20 cm-3, the thickness of the intrinsic silicon layer is 3 - 8 nm, and the thickness of the second doped silicon layer is 8 - 20 nm, with an effective doping concentration of 1e19 cm-3 - 1e20 cm-3; Structure 2: The thickness of the conductive film layer is 30 - 120 nm; Structure 3: In the stacked structure, a mask layer is provided or not provided between the first semiconductor layer and the second semiconductor layer, and the thickness of the mask layer is 0 - 40 nm; Structure 4: The combined passivated back contact cell further includes metal electrodes and a front passivation layer and an antireflection layer sequentially provided on the front of the silicon wafer. The metal electrodes are provided on the outer surface of the conductive film layer and correspond to the first semiconductor opening region and the second semiconductor opening region respectively.

8. A preparation method of a passivated back contact cell, characterized in that, It is configured to prepare the combined passivated back contact cell according to any one of claims 1 - 7, and the preparation method of the combined passivated back contact cell includes the following steps: S101. Provide a silicon wafer; S102. Sequentially form a first semiconductor layer and a mask layer on the back of the silicon wafer; S103. Remove a part of the first semiconductor layer and its corresponding mask layer in a first preset area on the back obtained in S102 to form a second semiconductor opening region; S104. Then, through texturing and cleaning, form a textured surface on the front of the silicon wafer and in the second semiconductor opening region on the back, and at the same time etch away 50% - 100% of the thickness of the mask layer; S105. Form a second semiconductor layer on the back obtained in S104; S106. Remove a part of the second semiconductor layer and its corresponding mask layer in a second preset area on the back obtained in S105 to form a first semiconductor opening region arranged at intervals with the second semiconductor opening region, and the region between the first semiconductor opening region and the second semiconductor opening region is the spacer region; S107. Form a conductive film layer on the back obtained in S106; S108. Etch an opening in a third preset area on the back obtained in S107 to form an isolation groove.

9. The preparation method of the jointly passivated back contact battery according to claim 8, wherein, The thickness of the mask layer formed in S102 is 40 - 80 nm; And / or, the preparation method of the combined passivated back contact cell further includes at least one of the following methods: Method 1: S105 further includes the step of forming a front passivation layer and an antireflection layer on the front of the silicon wafer; Method 2: S109. Form metal electrodes on the outer surface of the conductive film layer on the back obtained in S108 respectively; Method 3: The formation of the second semiconductor opening region and the first semiconductor opening region respectively uses laser etching, and the laser etching uses picosecond or femtosecond laser, and the laser is green laser or ultraviolet laser.

10. A battery assembly, characterized in that, It includes the combined passivated back contact cell according to any one of claims 1 - 7.

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