Hybrid passivated back contact battery based on p-type silicon wafer, preparation thereof, and photovoltaic module comprising same

Abstract

The present disclosure relates to a hybrid passivated back contact battery based on a P-type silicon wafer, preparation thereof, and a photovoltaic module comprising same. The hybrid passivated back contact battery comprises a silicon wafer, a first semiconductor layer and a second semiconductor layer which are provided on the back surface of the silicon wafer, and a front passivation layer and an anti-reflection layer which are provided on the front surface of the silicon wafer; the first semiconductor layer comprises a tunnel oxide layer and a first doped polycrystalline silicon layer; the second semiconductor layer comprises an intrinsic silicon crystal layer and a second doped microcrystalline silicon layer; the silicon wafer is of P-type, a boron-doped region is provided on the front surface of the silicon wafer, and the front passivation layer and the anti-reflection layer are sequentially arranged on the surface of the boron-doped region; the ratio of the thickness of the boron-doped region to the thickness of the tunnel oxide layer is (30-150): 1, and the ratio of the surface doping index of the boron-doped region to the surface doping index of the first doped polycrystalline silicon layer is (0.03-0.3): 1; the surface doping index is the ratio of the effective doping concentration of a corresponding doped layer to the thickness of the doped layer; the front passivation layer is made of aluminum oxide and has a thickness of 50-60 nm; and the ratio of the thickness of the boron-doped region to the thickness of the front passivation layer is (1-4): 1. The short-circuit current, the open-circuit voltage and the battery conversion efficiency of the present disclosure are obviously improved, and are higher than those of a conventional battery based on an N-type silicon wafer.

Description

Combined passivated back contact cell based on P-type silicon wafer, its preparation and photovoltaic module

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The present disclosure claims priority to Chinese patent application number 2024100642223 filed with the Patent Office of China on January 17, 2024, entitled “Jointly passivated back contact cell based on P-type silicon wafer, its preparation and photovoltaic module”, the entire contents of which are incorporated by reference into the present disclosure. Technical Field

[0003] The present disclosure belongs to the technical field of back-contact cells, and in particular relates to a combined passivation back-contact cell based on a P-type silicon wafer, its preparation, and a photovoltaic module. Background Art

[0004] Back-contact cells are a type of solar cell structure characterized by placing the positive and negative metal contacts on the back of the cell, thereby improving the cell's conversion efficiency and reliability. However, back-contact cells generally use N-type silicon wafers. This is because N-type silicon wafers can achieve high passivation levels using hydrogenated amorphous silicon passivation or tunneling polycrystalline passivation. However, depositing amorphous silicon or polycrystalline silicon on the front of the cell will affect its short-circuit current. Using P-type silicon wafers will result in lower passivation levels and low short-circuit current, resulting in lower cell conversion efficiency.

[0005] Therefore, there is an urgent need in the prior art for a tunneling-type back-contact cell structure based on P-type silicon wafers, so that P-type silicon wafers can also be configured into a back-contact heterojunction solar cell structure, while achieving the excellent combined effects of high short-circuit current and high open-circuit voltage.

[0006] It should be noted that this part of the present disclosure only provides background technology related to the present disclosure and does not necessarily constitute prior art or public known technology.

[0007] Summary of the Invention

[0008] The purpose of the present disclosure is to overcome the defects of the prior art in that the short-circuit current and battery conversion efficiency of back-contact batteries based on P-type silicon wafers are at a low level, and to provide a combined passivated back-contact battery based on P-type silicon wafers, its preparation, and photovoltaic module. The short-circuit current, open-circuit voltage and battery conversion efficiency of the combined passivated back-contact battery based on P-type silicon wafers are significantly improved, which are higher than those of conventional N-type silicon wafer batteries.

[0009] To achieve the above objectives, in a first aspect, the present disclosure provides a combined passivation back contact cell based on a P-type silicon wafer, comprising a silicon wafer, a first semiconductor layer and a second semiconductor layer arranged on the back side of the silicon wafer, and a front passivation layer and an anti-reflection layer arranged on the front side of the silicon wafer, wherein the first semiconductor layer comprises a tunneling oxide layer and a first doped polycrystalline silicon layer, and the second semiconductor layer comprises an intrinsic silicon crystal layer and a second doped microcrystalline silicon layer. The silicon wafer is P-type, and a boron-doped region is provided on the front side of the silicon wafer. The front passivation layer and the anti-reflection layer are sequentially arranged on the surface of the boron-doped region, and the thickness ratio of the boron-doped region to the tunneling oxide layer is (30-150):1, and the ratio of the surface doping index of the boron-doped region to the first doped polycrystalline silicon layer is (0.03-0.3):1, wherein the surface doping index is the ratio of the effective doping concentration of the corresponding doping layer to the thickness of the doping layer; and the front passivation layer is aluminum oxide with a thickness of 50-60 nm, and the thickness ratio of the boron-doped region to the front passivation layer is (1-4):1.

[0010] In some optional embodiments of the present disclosure, the anti-reflection layer is at least one of silicon nitride, silicon dioxide, and silicon oxynitride.

[0011] In some optional embodiments of the present disclosure, the anti-reflection layer is composed of two layers of silicon nitride and silicon dioxide, with the silicon nitride located between the silicon dioxide and aluminum oxide. More preferably, the thickness of the silicon nitride is 50-100 nm, and the thickness of the silicon dioxide is 5-20 nm.

[0012] In some optional embodiments of the present disclosure, the anti-reflection layer is silicon nitride and has a thickness of 50-100 nm.

[0013] In some optional embodiments of the present disclosure, a ratio of the surface doping index of the boron-doped region to the second doped microcrystalline silicon layer and the first doped polycrystalline silicon layer is (0.03-0.3):(0.1-0.6):1.

[0014] In some optional embodiments of the present disclosure, the thickness of the boron doped region is 50-200 nm and the effective doping concentration is 1e18 cm －3 -1e19cm －3 .

[0015] In some optional embodiments of the present disclosure, the thickness of the tunnel oxide layer is 1.2-2.0 nm, the thickness of the first doped polysilicon layer is 80-200 nm, and the effective doping concentration is 1e20 cm －3 -5e21cm －3 .

[0016] In some optional embodiments of the present disclosure, the thickness of the intrinsic silicon crystal layer is 3-8 nm, the thickness of the second doped microcrystalline silicon layer is 10-20 nm, and the effective doping concentration is 1e18 cm －3 -1e20cm －3 .

[0017] In some optional embodiments of the present disclosure, the crystallization rate of the second doped microcrystalline silicon layer is greater than 30%.

[0018] In some optional embodiments of the present disclosure, the first semiconductor layers are arranged at intervals in a direction parallel to the back surface, and the intervals are second semiconductor opening areas; and the second semiconductor layer is arranged on the surface of the first semiconductor layer and extends to cover the surface of the second semiconductor opening areas, and a first semiconductor opening area exposing the first semiconductor layer is opened on a portion of the second semiconductor layer located between adjacent second semiconductor opening areas; the front side of the silicon wafer is a textured surface, the portion of the back side of the silicon wafer located at the second semiconductor opening area is a textured surface, and the remaining portion is a polished surface.

[0019] In some optional embodiments of the present disclosure, the combined passivation back contact cell based on a P-type silicon wafer further includes: a conductive film layer, which is arranged on the surface of the second semiconductor layer and the surface of the first semiconductor layer exposed at the first semiconductor opening area, and an isolation groove exposing the second semiconductor layer is opened on the conductive film layer between the first semiconductor opening area and the second semiconductor opening area.

[0020] In some optional embodiments of the present disclosure, the combined passivation back contact cell based on a P-type silicon wafer further includes: a gate line electrode, which is respectively arranged on the surfaces of the first semiconductor opening region and the second semiconductor opening region.

[0021] In a second aspect, the present disclosure provides a method for preparing a combined passivated back contact cell based on a P-type silicon wafer, which is configured to prepare the combined passivated back contact cell based on a P-type silicon wafer described in the first aspect.

[0022] The method for preparing the combined passivation back contact cell based on a P-type silicon wafer comprises the following steps:

[0023] S1, forming a first semiconductor layer on the back side of a double-sided polished P-type silicon wafer;

[0024] S3, then forming a boron-doped region on the front side of the silicon wafer;

[0025] S4, forming a front passivation layer and an anti-reflection layer in sequence on the surface of the boron-doped region;

[0026] S5. Then, a second semiconductor layer is deposited on the back side.

[0027] In some optional embodiments of the present disclosure, the boron-doped region is formed by a boron diffusion method or an ion implantation method, and the boron implantation dose used in the ion implantation method is 1e16 ions / cm 2 -4e17ions / cm 2 .

[0028] In some optional embodiments of the present disclosure, the front passivation layer in the anti-reflection layer is formed in S4 by an atomic layer deposition process, and the conditions of the atomic layer deposition process include: controlling the process temperature at 150-180°C, first preheating the silicon wafer at a constant temperature for 300-450s, and then introducing a process gas for reaction, the flow rate of trimethylaluminum introduced into the process gas is 2000-4000sccm, the flow rate of ozone is 6000-9000sccm, and the reaction time is 70-150min.

[0029] In some optional embodiments of the present disclosure, the method for preparing a combined passivated back contact battery based on a P-type silicon wafer further includes: S2, growing a mask layer on the surface of the first semiconductor layer; and removing a portion of the first semiconductor layer and a portion of the mask layer thereon in a preset area on the back side to form a second semiconductor opening area; then performing texturing and cleaning, during which all mask layers are removed; and then performing S3.

[0030] In some optional embodiments of the present disclosure, S6, after depositing the second semiconductor layer, removing the second semiconductor layer in the preset area on the back side to form a first semiconductor opening region between adjacent second semiconductor opening regions exposing the first semiconductor layer.

[0031] In some optional embodiments of the present disclosure, S7, a conductive film layer is then deposited on the back side of the obtained silicon wafer.

[0032] In some optional embodiments of the present disclosure, S8 , an isolation trench is opened on the conductive film layer between the first semiconductor opening region and the second semiconductor opening region.

[0033] In some optional embodiments of the present disclosure, S9, screen printing or electroplating is used to form gate line electrodes at the first semiconductor opening area and the second semiconductor opening area respectively, wherein when the screen printing process is used, low-temperature sintering of no more than 350°C is performed after printing.

[0034] In a third aspect, the present disclosure provides a photovoltaic module comprising the P-type silicon wafer-based combined passivated back contact cell according to the first aspect. Beneficial effects:

[0035] The present invention, based on the use of P-type silicon wafers, ensures a high level of passivation by setting a boron-doped region with a specific thickness ratio and surface doping index on the front side of the silicon wafer, eliminating the need for electron transfer and increasing the open circuit voltage through field passivation. The use of aluminum oxide thickened to an appropriate range as a front passivation layer can improve the passivation level, and the combined passivation structure set on the back side can ensure that the optical loss of the front film layer is minimized under high passivation. As a result, compared to the back contact cell using an N-type silicon wafer and an amorphous passivation layer structure used on the front side in the prior art, the short-circuit current of the combined passivation back contact cell based on the P-type silicon wafer disclosed in the present invention is significantly improved, while also taking into account the improvement of the cell conversion efficiency. Moreover, as the thickness of aluminum oxide increases to an appropriate range, the annealing temperature required to activate the aluminum oxide field effect will be significantly reduced. The present invention can meet this requirement by relying on the subsequent conventional screen printing process and low-temperature sintering. Traditional TOPCON cells require openings in the front aluminum oxide to make electrodes, so there are requirements for the thickness of the aluminum oxide (generally below 25nm). If the aluminum oxide is too thick, laser opening cannot be performed.

[0036] Through a large number of experiments, it was found that in the combined passivation battery structure based on P-type silicon wafers, the thickness of the aluminum oxide film layer, the ratio of the thickness of the boron-doped region to the tunneling oxide layer, the ratio of the surface doping index of the boron-doped region to the first doped polysilicon layer, and the ratio of the thickness of the boron-doped region to the front passivation layer have a great influence on the short-circuit current and battery conversion efficiency of the back-contact battery. One possible guess is that the appropriate film layer ratio can minimize the optical loss of the front film layer, while maximizing the field passivation effect of aluminum oxide, ensuring a high level of passivation on the front side, thereby significantly improving the battery short-circuit current and open-circuit voltage as well as the battery conversion efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present disclosure and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0038] FIG1 is a schematic diagram of the structure of a silicon wafer after polishing and cleaning according to Example 1 of the present disclosure;

[0039] FIG2 is a schematic structural diagram of forming a first semiconductor layer and a mask layer on the back side of a silicon wafer in accordance with Embodiment 1 of the present disclosure;

[0040] FIG3 is a schematic diagram of the structure of the embodiment 1 of the present disclosure after the second semiconductor opening region is formed and then texturing and cleaning are performed;

[0041] FIG4 is a schematic structural diagram of a third semiconductor layer and an anti-reflection layer formed on the front side of a silicon wafer according to Example 1 of the present disclosure;

[0042] FIG5 is a schematic structural diagram of forming a second semiconductor layer and a first semiconductor opening region on the back side of a silicon wafer in accordance with Embodiment 1 of the present disclosure;

[0043] FIG6 is a schematic diagram of the structure of depositing a conductive film layer and an isolation trench on the back side of a silicon wafer according to Embodiment 1 of the present disclosure;

[0044] FIG7 is a schematic structural diagram of a gate line electrode formed on the back side of a silicon wafer in accordance with the first embodiment of the present disclosure.

[0045] Explanation of the accompanying symbols: 1. Silicon wafer, 2. Tunneling oxide layer, 3. First doped polysilicon layer, 4. Mask layer, 5. Boron-doped region, 6. Front passivation layer, 7. Silicon nitride, 8. Silicon dioxide, 9. Intrinsic microcrystalline silicon layer, 10. Second doped microcrystalline layer, 11. Conductive film layer, 12. Gate line electrode; 101. First semiconductor opening region, 102. Second semiconductor opening region, 103. Isolation trench. DETAILED DESCRIPTION

[0046] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein. Among them, the terms "optional" and "optional" all mean that they may be included or not (or may be present or not).

[0047] In the first aspect, the present disclosure provides a combined passivation back contact cell based on a P-type silicon wafer, comprising a silicon wafer, a first semiconductor layer and a second semiconductor layer arranged on the back of the silicon wafer, and a front passivation layer and an anti-reflection layer arranged on the front of the silicon wafer, wherein the first semiconductor layer comprises a tunneling oxide layer and a first doped polycrystalline silicon layer, and the second semiconductor layer comprises an intrinsic silicon crystal layer and a second doped microcrystalline silicon layer.

[0048] In the present disclosure, the silicon wafer is P-type, and a boron-doped region is provided on the front side of the silicon wafer, the front passivation layer and the anti-reflection layer are sequentially provided on the surface of the boron-doped region, and the thickness ratio of the boron-doped region to the tunneling oxide layer is (30-150):1, optionally (50-150):1, and the ratio of the surface doping index of the boron-doped region to the first doped polysilicon layer is (0.03-0.3):1, optionally (0.06-0.1):1, wherein the surface doping index is the ratio of the effective doping concentration of the corresponding doping layer to the thickness of the doping layer; and the front passivation layer is aluminum oxide with a thickness of 50-60 nm, and the thickness ratio of the boron-doped region to the front passivation layer is (1-4):1, optionally (2-4):1.

[0049] The silicon wafer disclosed in the present invention is P-type, and can be a P-type single crystal silicon wafer, or a P-type cast single crystal silicon wafer or a polycrystalline silicon wafer, and can optionally be a P-type single crystal silicon wafer.

[0050] In some optional embodiments of the present disclosure, the anti-reflection layer is at least one of silicon nitride, silicon dioxide, and silicon oxynitride.

[0051] In some optional embodiments of the present disclosure, the anti-reflection layer is composed of a stack of silicon nitride and silicon dioxide, with the silicon nitride positioned between the silicon dioxide and aluminum oxide. More preferably, the silicon nitride has a thickness of 50-100 nm, and the silicon dioxide has a thickness of 5-20 nm. This option allows the anti-reflection layer to be optimally coordinated with the front passivation layer, reducing optical losses in the front film and further improving the battery's short-circuit current.

[0052] In some optional embodiments of the present disclosure, the anti-reflection layer is silicon nitride and has a thickness of 50-100 nm.

[0053] In some optional embodiments of the present disclosure, a ratio of the surface doping index of the boron-doped region to the second doped microcrystalline silicon layer and the first doped polycrystalline silicon layer is (0.03-0.3):(0.1-0.6):1.

[0054] On the basis of satisfying the required thickness ratio and surface doping index ratio of the boron-doped region to other layers in the present disclosure, the range of thickness and effective doping concentration of the boron-doped region in the present disclosure is relatively wide. In some optional embodiments of the present disclosure, the thickness of the boron-doped region is 50-200nm, optionally 100-200nm, and the effective doping concentration is 1e18cm －3 -1e19cm －3 .

[0055] On the basis of satisfying the required thickness ratio of the boron-doped region to other layers and the ratio of the surface doping index disclosed herein, those skilled in the art can select the thickness of the tunnel oxide layer and the thickness and effective doping concentration of the first doped polysilicon layer from the prior art. In some optional embodiments of the present disclosure, the thickness of the tunnel oxide layer is 1.2-2.5nm, optionally 1.2-2.0nm, the thickness of the first doped polysilicon layer is 80-200nm and the effective doping concentration is 1e20cm －3 -5e21cm －3 .

[0056] In some optional embodiments of the present disclosure, the thickness of the intrinsic silicon crystal layer is 3-8 nm, optionally 6-8 nm, and the thickness of the second doped microcrystalline silicon layer is 10-20 nm and the effective doping concentration is 1e18 cm －3 -1e20cm －3 , optional 1e19-1e20cm －3 .

[0057] The intrinsic silicon crystal layer can be an intrinsic amorphous silicon layer or an intrinsic microcrystalline silicon layer, wherein the crystallization rate of the intrinsic microcrystalline silicon layer is greater than 30%. The intrinsic silicon crystal layer can be formed by a method known in the art, such as deposition by PECVD. During the deposition process, the silane concentration is controlled to be lower than the hydrogen concentration, for example, the volume flow ratio of silane to hydrogen is 1:200-600.

[0058] In some optional embodiments of the present disclosure, the crystallization rate of the second doped microcrystalline silicon layer is greater than 30%. This optional solution can improve the passivation level of the second doped microcrystalline silicon layer, which is more conducive to increasing the open circuit voltage of the battery.

[0059] In the present disclosure, the combined passivation back contact cell based on a P-type silicon wafer may also include other conventional structures. In some optional embodiments of the present disclosure, the first semiconductor layers are arranged at intervals along a direction parallel to the back surface, and the intervals are second semiconductor opening regions; the second semiconductor layer is arranged on the surface of the first semiconductor layer and extends to cover the surface of the second semiconductor opening regions, and a first semiconductor opening region is opened on a portion of the second semiconductor layer located between adjacent second semiconductor opening regions to expose the first semiconductor layer; the front side of the silicon wafer is a textured surface, the portion of the back side of the silicon wafer located at the second semiconductor opening region is a textured surface, and the remaining portion is a polished surface.

[0060] In some optional embodiments of the present disclosure, the combined passivation back contact cell based on a P-type silicon wafer further includes: a conductive film layer, which is arranged on the surface of the second semiconductor layer and the surface of the first semiconductor layer exposed at the first semiconductor opening area, and an isolation groove exposing the second semiconductor layer is opened on the conductive film layer between the first semiconductor opening area and the second semiconductor opening area.

[0061] In some optional embodiments of the present disclosure, the combined passivation back contact cell based on a P-type silicon wafer further includes: a gate line electrode, which is respectively arranged on the surfaces of the first semiconductor opening region and the second semiconductor opening region.

[0062] In the present disclosure, the thickness of the conductive film layer and the gate line electrode, as well as the widths of the first semiconductor opening region, the second semiconductor opening region, and the isolation trench can be selected with reference to the ranges in the prior art, and will not be described in detail in the present disclosure.

[0063] In a second aspect, the present disclosure provides a method for preparing a combined passivated back contact cell based on a P-type silicon wafer, which is configured to prepare the combined passivated back contact cell based on a P-type silicon wafer described in the first aspect.

[0064] The method for preparing the combined passivation back contact cell based on a P-type silicon wafer comprises the following steps:

[0065] S1, forming a first semiconductor layer on the back side of a double-sided polished P-type silicon wafer;

[0066] S3, then forming a boron-doped region on the front side of the silicon wafer;

[0067] S4, forming a front passivation layer and an anti-reflection layer in sequence on the surface of the boron-doped region;

[0068] S5. Then, a second semiconductor layer is deposited on the back side.

[0069] In S1, the present disclosure does not limit the double-sided polishing process of P-type silicon wafers, and methods in the prior art can be used. For example, in an optional solution, the double-sided polishing process includes: cleaning the silicon wafer with an alkaline solution to remove the wire-cut damage layer on the surface of the silicon wafer, and then removing the alkaline solution remaining on the surface of the silicon wafer by the RCA standard cleaning method. More optionally, the alkaline solution can be an aqueous solution of potassium hydroxide, sodium hydroxide, or a mixture of the two, with a concentration of 2-6wt%, and the reaction temperature of the alkaline solution cleaning is controlled to be 65°C-90°C, the reaction time is 1-15 minutes, and the single-sided removal thickness is controlled to be 1-20μm.

[0070] In S1, the method for forming the first semiconductor layer can adopt any method in the prior art, as long as the first semiconductor layer of the desired composition structure can be obtained. For example, the tunnel oxide layer and the intrinsic polysilicon layer can be formed by LPCVD and then phosphorus diffusion can be performed. Alternatively, the in-situ doping deposition and subsequent annealing can be performed by tubular PECVD. After the first semiconductor layer is formed in S1, a conventional re-cleaning step can also be included. Typically, there is phosphosilicate glass formed by phosphorus diffusion reaction on the surface of the first semiconductor layer. Optionally, the solution used for the re-cleaning is an aqueous HF acid solution with a mass concentration of HF acid of 2% to 8%. The silicon wafer is treated in the HF acid aqueous solution for 1 to 10 minutes at a temperature of 10 to 30°C.

[0071] In an optional embodiment of the present disclosure, the LPCVD method includes: thermal oxidation at 550-650°C for a preset time (e.g., 20-40 minutes) to form a tunneling oxide layer of desired thickness; growing an intrinsic polysilicon layer on the tunneling oxide layer; and then subjecting the intrinsic polysilicon layer to high-temperature phosphorus diffusion. Optionally, the conditions for growing the intrinsic polysilicon layer include: controlling the temperature between 550-650°C, the pressure between 5-10,000 Pa, the silane flow rate between 50 sccm and 300 sccm, and the reaction time between 600s and 3,000s. Optionally, the high-temperature phosphorus diffusion adopts the phosphorus oxychloride diffusion method, including a first-stage diffusion and a second-stage high-temperature advancement process. During the first-stage diffusion process, POCl3, O2, and N2 are introduced, the POCl3 gas flow rate is 50sccm-500sccm, the O2 gas flow rate is 100sccm-1000sccm, the N2 gas flow rate is 100sccm-1000sccm, the diffusion temperature is 700℃-850℃, the diffusion time is controlled at 5min-30min, and the furnace tube pressure is 50mbar-300mbar; during the high-temperature advancement process, O2 and N2 are introduced, the O2 gas flow rate is 1000sccm-2000sccm, and the N2 gas flow rate is 1000sccm-5000sccm; the high-temperature advancement temperature is 850℃-950℃, the furnace tube pressure is 100mbar-500mbar, and the high-temperature advancement time is controlled at 30min-60min.

[0072] In an optional embodiment of the present disclosure, the tubular PECVD method includes: using nitrous oxide (NO2) to react and generate a tunneling oxide layer, the nitrous oxide flow rate is 1000sccm-3000sccm, the deposition power is 1000W-3000W, the RF path on-off ratio is 2ms:10-20ms, the reaction temperature is 400℃-450℃, the reaction pressure is 100-2000mtorr, and the reaction time is 60-150s; then, a phosphorus-doped amorphous silicon film is deposited on the tunneling oxide layer, the reaction temperature is 400℃-500℃, and SiH4, H2, and PH3 gases are introduced. The phosphorus-doped amorphous silicon film is subjected to high-temperature crystallization annealing to generate a phosphorus-doped first doped polycrystalline silicon layer, the high-temperature crystallization annealing temperature is 800°C-900°C, and the high-temperature crystallization annealing time is 20min-40min.

[0073] In some optional embodiments of the present disclosure, the method for preparing a combined passivated back contact battery based on a P-type silicon wafer further includes: S2, growing a mask layer on the surface of the first semiconductor layer; and removing a portion of the first semiconductor layer and a portion of the mask layer thereon in a preset area on the back side to form a second semiconductor opening area; then performing texturing and cleaning, during which all mask layers are removed; and then performing S3.

[0074] The type and thickness of the mask layer and its growth process in the present disclosure can be selected from the prior art according to actual needs. Optionally, the mask layer can be at least one of silicon nitride, silicon dioxide and silicon oxynitride, and more preferably silicon nitride.

[0075] Optionally, the thickness of the mask layer may be 50-200 nm.

[0076] In S2, the removal of part of the first semiconductor layer and part of the mask layer thereon can be performed by laser ablation. The laser used is a pulsed laser with a pulse width of less than 20 nanoseconds, and more preferably less than 100 picoseconds. The laser can more preferably be a low energy density green light with a wavelength of about 560nm.

[0077] The texturing cleaning process can, on the one hand, form a silicon wafer with a textured front surface and a partially polished and partially textured back surface, thereby reducing reflectivity. On the other hand, to ensure that the second semiconductor opening region is fully open and free of film residue, the texturing cleaning process can optionally be performed for 8-40 minutes at a temperature of 65°C-85°C. The texturing cleaning process uses an alkaline mixed solution, which can be a mixture of potassium hydroxide, a texturing additive (which can be a commercially available product), and water, wherein the mass percentage of potassium hydroxide is 1%-5%, and the mass percentage of the texturing additive is 0.5%-1%.

[0078] In some optional embodiments of the present disclosure, the boron doped region is formed by boron diffusion or ion implantation in step S3. Optionally, the boron implantation dose used in the ion implantation is 1e16 ions / cm 2 -4e17ions / cm 2 The boron diffusion method may adopt an existing boron doping method, for example, a boron tribromide liquid source high temperature diffusion method.

[0079] In some optional embodiments of the present disclosure, the front passivation layer in the anti-reflection layer is formed in S4 by an atomic layer deposition process, and the conditions of the atomic layer deposition process include: controlling the process temperature at 150-180°C, first preheating the silicon wafer at a constant temperature for 300-450s, and then introducing a process gas for reaction, the flow rate of trimethylaluminum introduced into the process gas is 2000-4000sccm, the flow rate of ozone is 6000-9000sccm, and the reaction time is 70-150min.

[0080] The method for depositing the second semiconductor layer in S5 can be any method in the prior art. For example, a boron-containing dopant can be doped during the deposition of microcrystalline silicon using LPCVD or PECVD. The boron-containing dopant can be, for example, silane, borane, or hydrogen. PECVD can be used for deposition. During the deposition process, the silane concentration is low, and the flow ratio of silane:borane:hydrogen is 1:(2-5):(300-1000).

[0081] In some optional embodiments of the present disclosure, S6, after depositing the second semiconductor layer, the second semiconductor layer within the predetermined rear surface region is removed to form a first semiconductor opening region located between adjacent second semiconductor opening regions, exposing the first semiconductor layer. Removal of the second semiconductor layer within the predetermined rear surface region can be performed using methods such as laser ablation, which is conventional and will not be further described herein.

[0082] The present disclosure S6 may also include other conventional steps, such as cleaning and removing the oxide layer generated in the first semiconductor opening region due to the high temperature of the laser, for example, by using HF acid cleaning.

[0083] In some optional embodiments of the present disclosure, S7, a conductive film layer is then deposited on the back side of the obtained silicon wafer.

[0084] The conductive film layer described in this disclosure can be deposited using a method, type, and thickness selected from existing technologies. For example, it can be deposited using magnetron sputtering PVD, with an optional sputtering target voltage range of 220V-300V. The conductive film layer can be made of at least one of tin-doped indium oxide (ITO) and aluminum-doped zinc oxide (AZO). Optionally, the conductive film layer has a thickness of 50-150nm.

[0085] In some optional embodiments of the present disclosure, S8: An isolation trench is formed in the conductive film layer between the first semiconductor opening region and the second semiconductor opening region. The isolation trench can be formed by laser or etching. The width of the isolation trench can be, for example, 30-200 μm. The width of the first semiconductor opening region can be, for example, 100-150 μm. The width of the second semiconductor opening region can be, for example, 400-550 μm.

[0086] In some optional embodiments of the present disclosure, S9, a screen printing process or an electroplating method is used to form gate line electrodes at the first semiconductor opening area and the second semiconductor opening area respectively, wherein when the screen printing process is used, a low-temperature sintering of not more than 350°C is performed after printing. It is understandable that the polarity of the gate line electrodes on the first semiconductor opening area and the second semiconductor opening area is opposite. The gate line electrode can be formed into a silver gate electrode by a screen printing process and low-temperature sintering (temperature <350°C), or it can be formed by electroplating. Optionally, the gate line electrode is formed by electroplating.

[0087] In a third aspect, the present disclosure provides a photovoltaic module comprising the P-type silicon wafer-based combined passivated back contact cell described in the first aspect. The P-type silicon wafer-based combined passivated back contact cell described in the present disclosure can be configured in any photovoltaic application field of the prior art.

[0088] The embodiments of the present disclosure are described in detail below, which are exemplary and are only configured to explain the present disclosure but are not to be construed as limiting the present disclosure.

[0089] Example 1

[0090] A combined passivated back contact cell based on a P-type silicon wafer, as shown in FIG7 , is prepared by the following process:

[0091] S1 includes:

[0092] S101. As shown in FIG1 , a P-type single crystal silicon wafer 1 is double-sided polished. Specifically, an alkaline solution is used to remove the wire-cut damage layer on the surface of the silicon wafer 1. The alkaline solution is a potassium hydroxide aqueous solution (with a concentration of 5 wt%). The reaction temperature of the alkaline solution is 70° C., the reaction time is 10 min, and the thickness removed on one side is controlled to be 1-20 μm. Then, RCA standard cleaning is performed to remove the alkaline solution remaining on the surface of the silicon wafer 1.

[0093] S102, then a first semiconductor layer is formed on the back side of the silicon wafer 1, wherein the first semiconductor layer includes a tunneling oxide layer 2 with a thickness of 1.5 nm and a first phosphorus-doped doped polysilicon layer 3 (with a thickness of 120 nm and an effective doping concentration of 2e20 cm －3 The first semiconductor layer can be formed by LPCVD to form a tunnel oxide layer 2 and an intrinsic polysilicon layer, followed by phosphorus diffusion. Specifically, the process includes thermal oxidation at 600°C for 30 minutes to form a tunnel oxide layer 2 with a thickness of 1.5 nm. An intrinsic polysilicon layer is then grown on the tunnel oxide layer 2; and then the intrinsic polysilicon layer is subjected to high-temperature phosphorus diffusion. The conditions for growing the intrinsic polysilicon layer include a temperature of 600°C, a gas pressure controlled at 100 Pa, a silane flow rate of 100 sccm, and a reaction time of 1000 seconds. The high-temperature phosphorus diffusion adopts the phosphorus oxychloride diffusion method, which includes a first-stage diffusion and a second-stage high-temperature advancement process. During the first-stage diffusion process, POCl3, O2, and N2 are introduced, the POCl3 gas flow rate is 100sccm, the O2 gas flow rate is 100sccm, the N2 gas flow rate is 200sccm, the diffusion temperature is 750°C, the diffusion time is controlled at 10min, and the furnace tube pressure is 100mbar; during the high-temperature advancement process, O2 and N2 are introduced, the O2 gas flow rate is 1000sccm, the N2 gas flow rate is 2000sccm; the high-temperature advancement temperature is 900°C, the furnace tube pressure is 200mbar, and the high-temperature advancement time is controlled at 40min.

[0094] After that, re-cleaning is performed. In this embodiment, there is phosphosilicate glass formed by phosphorus diffusion reaction on the surface of the first semiconductor layer. The solution used for the re-cleaning is HF acid aqueous solution with a HF acid mass concentration of 5% and deionized water as the balance. The treatment time of silicon wafer 1 in the HF acid aqueous solution is 5 minutes and the treatment temperature is 20°C.

[0095] S2. A mask layer 4 is grown on the surface of the cleaned first semiconductor layer. As shown in FIG2 , the mask layer 4 is silicon nitride. Silicon nitride is deposited as the mask layer 4 using tubular PECVD with a thickness of 80 nm. Hydrofluoric acid is used to remove the silicon nitride deposited on the front side.

[0096] Then, a portion of the first semiconductor layer and a portion of the mask layer thereon are removed by laser ablation to form a second semiconductor opening region 102. The laser is a pulsed laser with a pulse width of 10 picoseconds and a low energy density green light with a wavelength of about 560 nm.

[0097] Then, the area after the laser opening is subjected to texturing and cleaning (i.e., texturing first and then cleaning), and all mask layers are removed during the cleaning process (i.e., hydrofluoric acid is used to clean and remove silicon nitride after texturing), as shown in Figure 3. During the texturing and cleaning process, on the one hand, a silicon wafer 1 with a textured front and partially polished back structure is formed to reduce the reflectivity. On the other hand, in order to ensure that the opening area of ​​the second semiconductor region can be fully opened and no film layer remains, the texturing time is 20 minutes and the texturing temperature is 75°C. The texturing solution is an alkaline mixed solution, which is a mixture of potassium hydroxide, a texturing additive and water, wherein the mass percentage of potassium hydroxide is 2% and the mass percentage of the texturing additive is 0.5%.

[0098] S3. Boron is doped on the front side of the silicon wafer 1 by ion implantation to form a boron-doped region 5 with a thickness of 100 nm. The boron implantation dose is 4e17 ions / cm 2 , the effective boron doping concentration is 1e19cm －3 .

[0099] S4. A front passivation layer 6 and an anti-reflection layer are sequentially formed on the front side of the silicon wafer 1. The front passivation layer 6 is aluminum oxide and has a thickness of 50 nm. The anti-reflection layer is composed of silicon nitride 7 and silicon dioxide 8 formed in that order, as shown in FIG4 . The aluminum oxide is deposited using ALD at a process temperature of 150° C. The silicon wafer is first preheated at a constant temperature for 350 seconds, and then a process gas is introduced for reaction. The process gas contains trimethylaluminum (TMA) at a flow rate of 3000 sccm and ozone at a flow rate of 8000 sccm. The reaction time is 100 minutes. The silicon nitride 7 has a thickness of 60 nm, and the silicon dioxide 8 has a thickness of 10 nm.

[0100] S5: After texturing and cleaning, a second semiconductor layer is deposited on the back of the silicon wafer 1. The second semiconductor layer is an intrinsic microcrystalline silicon layer 9 (with a thickness of 6 nm) and a P-type second doped microcrystalline silicon layer 10 (with a thickness of 10 nm and an effective doping concentration of 1e19 cm －3 ), the intrinsic microcrystalline silicon layer 9 is formed by depositing by a PECVD method. During the deposition process, the silane concentration is low, and the flow ratio of silane: hydrogen is 1:400. The second doped microcrystalline silicon layer 10 is doped with a boron-containing dopant during the deposition of microcrystalline silicon and is deposited by a PECVD method. During the deposition process, the silane concentration is low, and the flow ratio of silane: borane: hydrogen is 1:3:400. The crystallization rates of the intrinsic microcrystalline silicon layer 9 and the P-type second doped microcrystalline silicon layer 10 are both above 30%.

[0101] S6. Laser ablation is used to remove the second doped microcrystalline silicon layer on the back side, exposing a portion of the first semiconductor layer, forming first semiconductor opening regions 101 that alternate with second semiconductor opening regions 102, as shown in FIG5 . Second semiconductor opening regions 102 are 500 μm wide, and first semiconductor opening regions 101 are 100 μm wide. HF acid cleaning is then used to remove the oxide layer formed within first semiconductor opening regions 101 due to the high temperature of the laser.

[0102] S7. Then, a transparent conductive film layer 11 is deposited on the back of the silicon wafer 1, as shown in FIG6 . The thickness of the conductive film layer 11 is 100 nm. The conductive film layer 11 is deposited by magnetron sputtering PVD. The conductive film layer 11 is tin-doped indium oxide (ITO), and the sputtering target voltage range is 220 V.

[0103] S8 . Form an isolation trench 103 between the first semiconductor opening region 101 and the second semiconductor opening region 102 by laser. The width of the isolation trench 103 is 50 μm.

[0104] S9, forming a first gate line electrode on the conductive film layer in the first semiconductor opening area, and correspondingly forming a second gate line electrode on the conductive film layer in the second semiconductor opening area, and forming the gate line electrode 12 by electroplating, as shown in FIG7.

[0105] Example 2

[0106] The method of Example 1 is referred to, except that the anti-reflection layer in S4 is silicon nitride and has a thickness of 60 nm.

[0107] Example 3

[0108] The method of Example 1 is followed, except that in S3, the thickness of the boron-doped region is adjusted to 50 nm. The ratio of the surface doping index of the boron-doped region to the first doped polysilicon layer is calculated to be 0.12:1. The doping concentration of the boron-doped region remains unchanged. To meet this condition, the boron implantation dose needs to be adjusted to 3e16 ions / cm 2 According to calculations in this embodiment, the ratio of the thickness of the boron-doped region to the tunnel oxide layer is 33:1, and the ratio of the thickness of the boron-doped region to the front passivation layer is 1:1.

[0109] Example 4

[0110] The method of Example 1 is followed, except that the doping concentration of the boron-doped region is adjusted to 5e18 cm －3 , the ratio of the surface doping index of the boron-doped region to the first doped polysilicon layer is calculated to be 0.03:1, and the thickness of the boron-doped region remains unchanged. To meet this condition, the boron implantation dose needs to be adjusted to 7e16ions / cm 2 .

[0111] Example 5

[0112] The method of Example 1 is referred to, except that the thickness of the tunnel oxide layer is adjusted to 2.5 nm in S102. The ratio of the thickness of the boron-doped region to the thickness of the tunnel oxide layer is calculated to be 40:1. To meet this condition, it is necessary to increase the oxidation temperature of S102 to 605°C.

[0113] Example 6

[0114] The method of Example 1 is referred to, except that the thickness of aluminum oxide is adjusted to 60 nm in S4. The ratio of the thickness of the boron-doped region to the thickness of the front passivation layer is calculated to be 5:3. To meet this condition, it is necessary to adjust the process time for forming aluminum oxide in S4 to be extended to 120 min.

[0115] Example 7

[0116] The method of Example 1 is followed, except that in S5 the effective doping concentration of the second doped microcrystalline silicon layer is adjusted to 2e18 cm －3 , it is calculated that the ratio of the surface doping index of the second doped microcrystalline silicon layer and the first doped polycrystalline silicon layer is 0.12:1, and the thickness of the second doped microcrystalline silicon layer remains unchanged. To meet this condition, it is necessary to adjust: during the deposition of the second doped microcrystalline silicon layer, adjust the flow ratio of silane: borane: hydrogen to 1:2:400.

[0117] Comparative Example 1

[0118] The method of Example 1 is referred to, except that the silicon wafer is N-type and the front structure of the silicon wafer adopts conventional amorphous silicon passivation. The specific structure of the front side of the silicon wafer is as follows: no boron-doped region is set, and intrinsic amorphous silicon (with a thickness of 6nm), an N-type amorphous film layer (with a thickness of 15nm), and an anti-reflection layer are directly set in sequence on the front side of the N-type single crystal silicon wafer. The structure of the anti-reflection layer is the same as that in Example 1.

[0119] Comparative Example 2

[0120] The method of Example 1 is referred to, except that the front structure of the P-type silicon wafer adopts conventional amorphous silicon passivation. The specific structure of the front side of the silicon wafer is as follows: no boron-doped region is set, and instead, intrinsic amorphous silicon (with a thickness of 6nm), a P-type amorphous film layer (with a thickness of 13nm), and an anti-reflection layer are directly set in sequence on the front side of the P-type single crystal silicon wafer. The structure of the anti-reflection layer is the same as that in Example 1.

[0121] Comparative Example 3

[0122] The method of Example 1 is referred to, except that a conventional TOPCON passivated back contact cell based on a P-type silicon wafer is used, and the intrinsic microcrystalline silicon layer in S5 is specifically adjusted to a tunneling oxide layer with a thickness of 1.5 nm.

[0123] Comparative Example 4

[0124] The method of Example 1 is referred to, except that a conventional P-type silicon wafer-based heterojunction passivated back contact cell is used, and the tunneling oxide layer in S102 is specifically adjusted to an intrinsic amorphous film layer with a thickness of 6 nm.

[0125] Comparative Example 5

[0126] The method of Example 1 is referred to, except that in S4, the thickness of aluminum oxide is adjusted to a conventional thin thickness of 20 nm. At this time, the ratio of the thickness of the boron-doped region to the front passivation layer is 5:1. To meet this condition, it is necessary to adjust: the ALD process time is shortened to 40 minutes.

[0127] Comparative Example 6

[0128] The method of Example 1 is followed, except that the doping concentration of the boron-doped region is adjusted to 1e17 cm in S3. －3 , the ratio of the surface doping index of the boron-doped region to the first doped polysilicon layer is calculated to be 0.0006:1, and the thickness of the boron-doped region remains unchanged. To meet this condition, the boron implantation dose needs to be adjusted to 4e16ions / cm 2 .

[0129] Comparative Example 7

[0130] The method of Example 1 is followed, except that the thickness of the boron-doped region is adjusted to 300 nm in S3. The ratio of the surface doping index of the boron-doped region to the first doped polysilicon layer is calculated to be 0.02:1. The doping concentration of the boron-doped region remains unchanged. To meet this condition, the boron implantation dose needs to be adjusted to 6e18 ions / cm 2 In this comparative example, it is calculated that the thickness ratio of the boron-doped region to the tunnel oxide layer is 200:1, and the thickness ratio of the boron-doped region to the front passivation layer is 6:1.

[0131] Test Case

[0132] The combined passivated back contact cells obtained in the above examples and comparative examples were subjected to performance tests, and the results are shown in Table 1.

[0133] Table 1

[0134] The above results show that, compared to the comparative example, the embodiment of the present disclosure can minimize the optical loss of the front film layer, thereby improving the short-circuit current of the battery while also improving the open-circuit voltage and battery conversion efficiency. However, the comparative example cannot achieve excellent short-circuit current, open-circuit voltage, and battery conversion efficiency at the same time.

[0135] Optionally, according to Example 1 and Examples 2-7, it can be seen that by adopting the optional solution of the present disclosure, the short-circuit current can be increased while maintaining the open-circuit voltage at a high level, which is more conducive to improving the battery conversion efficiency.

[0136] The above describes in detail the optional embodiments of the present disclosure, but the present disclosure is not limited thereto. Within the technical concept of the present disclosure, various simple variations of the technical solution of the present disclosure can be made, including combining the various technical features in any other appropriate manner. These simple variations and combinations should also be regarded as the contents disclosed by the present disclosure and fall within the scope of protection of the present disclosure. Industrial Applicability

[0137] The present invention adopts a P-type silicon wafer and ensures a high level of passivation by setting a boron-doped area with a specific thickness ratio and surface doping index on the front side of the silicon wafer. There is no need for electron transmission, and the open circuit voltage is increased by field passivation. The use of aluminum oxide thickened to an appropriate range as a front passivation layer can improve the passivation level. The combined passivation structure set on the back side can ensure that the optical loss of the front film layer is minimized under high level passivation. Therefore, compared with the back contact battery using an N-type silicon wafer and an amorphous passivation layer structure used on the front side in the prior art, the short-circuit current of the combined passivation back contact battery based on the P-type silicon wafer of the present invention is significantly improved, while taking into account the improvement of the battery conversion efficiency.

Claims

1. A combined passivated back contact cell based on a P-type silicon wafer, comprising a silicon wafer, a first semiconductor layer and a second semiconductor layer provided on the back surface of the silicon wafer, and a front passivation layer and an antireflection layer provided on the front surface of the silicon wafer. The first semiconductor layer includes a tunneling oxide layer and a first doped polysilicon layer, and the second semiconductor layer includes an intrinsic silicon crystal layer and a second doped microcrystalline silicon layer. It is characterized in that, The silicon wafer is of P type, and a boron-doped region is provided on the front side of the silicon wafer. The front passivation layer and the antireflection layer are sequentially provided on the surface of the boron-doped region. The thickness ratio of the boron-doped region to the tunneling oxide layer is (30 - 150):1, and the ratio of the surface doping index of the boron-doped region to that of the first doped polysilicon layer is (0.03 - 0.3):1, where the surface doping index is the ratio of the effective doping concentration of the corresponding doped layer to the thickness of the doped layer. The front passivation layer is aluminum oxide with a thickness of 50 - 60 nm, and the thickness ratio of the boron-doped region to the front passivation layer is (1 - 4):

1.

2. The passivated back contact cell based on a P-type silicon wafer according to claim 1, wherein The antireflection layer is at least one of silicon nitride, silicon dioxide, and silicon oxynitride.

3. The passivated back contact cell based on a P-type silicon wafer according to claim 1 or 2, characterized in that, The antireflection layer is composed of two stacked layers of silicon nitride and silicon dioxide. The silicon nitride is located between the silicon dioxide and the aluminum oxide. The thickness of the silicon nitride is 50 - 100 nm, and the thickness of the silicon dioxide is 5 - 20 nm. Alternatively, the antireflection layer is silicon nitride with a thickness of 50 - 100 nm.

4. The passivated back contact cell based on a P-type silicon wafer according to any one of claims 1 to 3, characterized in that, The ratio of the surface doping index of the boron-doped region to that of the second doped microcrystalline silicon layer and the first doped polysilicon layer is (0.03 - 0.3):(0.1 - 0.6):

1.

5. The passivated back contact cell based on a P-type silicon wafer according to any one of claims 1 to 4, characterized in that, The thickness of the boron-doped region is 50 - 200 nm and the effective doping concentration is 1e18 cm －3 -1e19 cm －3 ; The thickness of the tunneling oxide layer is 1.2 - 2.5 nm, the thickness of the first doped polysilicon layer is 80 - 200 nm and the effective doping concentration is 1e20 cm －3 -5e21 cm －3 ; And / or The thickness of the intrinsic silicon crystal layer is 3 - 8 nm, and the thickness of the second doped microcrystalline silicon layer is 10 - 20 nm and has The effective doping concentration is 1e18 cm －3 -1e20 cm －3 , and the crystallization rate of the second doped microcrystalline silicon layer is 30% or more.

6. The passivated back contact cell based on a P-type silicon wafer according to any one of claims 1-5, characterized in that, The first semiconductor layer is arranged at intervals along the back parallel direction of the silicon wafer, and the interval is the second semiconductor opening region. The second semiconductor layer is provided on the surface of the first semiconductor layer and extends to cover the surface of the second semiconductor opening region. A first semiconductor opening region exposing the first semiconductor layer is formed on a part of the second semiconductor layer between adjacent second semiconductor opening regions. The front side of the silicon wafer is a textured surface, and a part of the back side of the silicon wafer located at the second semiconductor opening region is a textured surface, and the rest is a polished surface. And the combined passivation back contact battery based on the P-type silicon wafer further includes: A conductive film layer, which is provided on the surface of the second semiconductor layer and on the surface of the first semiconductor layer exposed at the first semiconductor opening region, and an isolation groove exposing the second semiconductor layer is formed on the conductive film layer between the first semiconductor opening region and the second semiconductor opening region. Grid line electrodes, which are respectively provided on the surfaces of the first semiconductor opening region and the second semiconductor opening region.

7. A preparation method of a jointly passivated back-contact battery based on a P-type silicon wafer, characterized in that, It is configured to prepare the combined passivation back contact battery based on the P-type silicon wafer as described in any one of claims 1 - 6, and the preparation method of the combined passivation back contact battery based on the P-type silicon wafer includes the following steps: S1. First, form a first semiconductor layer on the back side of the double-sided polished P-type silicon wafer. S3. Then, form a boron-doped region on the front side of the silicon wafer. S4. Next, sequentially form a front passivation layer and an antireflection layer on the surface of the boron-doped region. S5. Then, deposit a second semiconductor layer on the back side.

8. The manufacturing method of the combined passivated back contact cell based on a P-type silicon wafer according to claim 7, wherein In S3, the formation of the boron-doped region uses the boron diffusion method or the ion implantation method. When using the ion implantation method, the boron implantation dose is 1e16 ions / cm 2 -4e17 ions / cm 2 ; And / or In S4, the atomic layer deposition process is used to form the front passivation layer in the antireflection layer, and the atomic layer deposition process The conditions of the process include: controlling the process temperature at 150 - 180 °C, preheating the silicon wafer at a constant temperature first, with the constant temperature preheating time being 300 - 450 s, and then introducing process gases for reaction. The flow rate of trimethylaluminum introduced into the process gases is 2000 - 4000 sccm, the ozone flow rate is 6000 - 9000 sccm, and the reaction time is 70 - 150 min.

9. The manufacturing method of the combined passivation back contact battery based on a P-type silicon wafer according to claim 7, characterized in that, The method for preparing the combined passivation back contact cell based on a P-type silicon wafer further includes: S2. Growing a mask layer on the surface of the first semiconductor layer; removing a part of the first semiconductor layer and a part of the mask layer thereon in a preset area on the back surface to form a second semiconductor opening area; then performing texturing and cleaning, during which all the mask layers are removed while cleaning; and then proceeding to S3; S6. After depositing the second semiconductor layer, removing the second semiconductor layer in the preset area on the back surface to form a first semiconductor opening area exposing the first semiconductor layer between adjacent second semiconductor opening areas; S7. Then depositing a conductive film layer on the back surface of the obtained silicon wafer; S8. Opening isolation grooves in the conductive film layer between the first semiconductor opening area and the second semiconductor opening area; S9. Using a screen printing process or electroplating method to form grid line electrodes at the first semiconductor opening area and the second semiconductor opening area respectively. When using the screen printing process, a low-temperature sintering at no more than 350 °C is also performed after printing.

10. A photovoltaic module, characterized in that, It includes the combined passivation back contact cell based on a P-type silicon wafer according to any one of claims 1 - 6.

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