Display panel and driving method therefor and display device

Abstract

Provided are a display panel and a driving method therefor, and a display device, relating to the technical field of display. The display panel comprises: a substrate having a display area and peripheral areas; a plurality of display pixels located in the display area; and light-emitting control circuits located in the peripheral areas. The display pixels can emit light under the driving of signals provided by signal lines, and each signal line comprises a pull-up power line and a pull-down power line. The light-emitting control circuits can control on / off of the pull-up power lines or the pull-down power lines and the display pixels in response to light-emitting control signals provided by light-emitting control lines. In this way, the light-emitting control signals can be flexibly set, so that the light-emitting control circuits can flexibly control the conduction duration of the pull-up power lines or the pull-down power lines and the display pixels, and then the light-emitting duration of the display pixels is flexibly controlled. Therefore, the display panel has relatively good flexibility in driving the display pixels.

Description

Display panel, driving method thereof, and display device

[0001] This disclosure claims priority to Chinese patent application No. 202410063895.7 filed on January 16, 2024, entitled “Display panel, driving method thereof, and display device,” the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a display panel, a driving method thereof, and a display device. Background Art

[0003] A display panel generally includes a plurality of pixels, each pixel including a pixel circuit and a light-emitting unit connected to each other. The pixel circuit can drive the light-emitting unit to emit light, thereby enabling the display panel to display an image.

[0004] In the related art, a pixel circuit typically includes a data write circuit and a light-emitting driver circuit. The data write circuit is connected to a gate line, a data line, and the light-emitting driver circuit, respectively, and is used to control the data line to transmit a data signal to the light-emitting driver circuit in response to a gate drive signal provided by the gate line. The light-emitting driver circuit is also connected to a pull-up power line and a light-emitting unit, respectively, and is used to transmit a light-emitting drive signal to the light-emitting unit based on the data signal and the pull-up power signal provided by the pull-up power line. The light-emitting unit is also connected to a pull-down power line, and the light-emitting unit can emit light under the drive of the light-emitting drive signal and the pull-down power signal provided by the pull-down power line.

[0005] Summary of the Invention

[0006] Provided are a display panel, a driving method thereof, and a display device. The technical solution is as follows:

[0007] In one aspect, a display panel is provided, comprising:

[0008] a substrate having a display area and a peripheral area at least partially surrounding the display area;

[0009] A plurality of display pixels arranged in an array are located in the display area, each of the display pixels comprising: a data writing circuit, a light-emitting driving circuit, an external compensation circuit, and a light-emitting unit, wherein the data writing circuit is respectively connected to a gate line, a data line, and an input node; the external compensation circuit is respectively connected to a compensation line, a sensing line, and an output node; the light-emitting driving circuit is respectively connected to the input node, the output node, and a pull-up power line; and the light-emitting unit is respectively connected to the output node and the pull-down power line;

[0010] a plurality of groups of light-emitting control circuits located in the peripheral area, each group of the light-emitting control circuits corresponding to at least one row of display pixels among the plurality of rows of display pixels, and each group of the light-emitting control circuits corresponding to a different row of display pixels, each group of the light-emitting control circuits comprising: a light-emitting control circuit located on at least one side of the at least one row of display pixels in a row direction, each light-emitting control circuit being connected between a target power line and the at least one row of display pixels and further connected to a light-emitting control line, and being configured to control the on / off connection between the target power line and the at least one row of display pixels in response to a light-emitting control signal provided by the light-emitting control line;

[0011] Wherein, the target power line is the pull-down power line or the pull-up power line.

[0012] Optionally, each group of the light emitting control circuits corresponds to every two adjacent rows of display pixels.

[0013] Optionally, each of the light emitting control circuits includes: an active layer, a gate metal layer, and a source / drain metal layer, which are located on one side of the substrate and stacked in sequence;

[0014] Each of the light-emitting control circuits is connected to the at least one row of display pixels through the source-drain metal layer via a switching via hole; and each of the light-emitting control circuits is connected to two display pixels in the same column of the two adjacent rows of display pixels via the same switching via hole.

[0015] Optionally, the thickness and width of the source / drain metal layer satisfy: I_t / (t*b)≤a;

[0016] Among them, I_t refers to the sum of the pixel currents of the multiple display pixels connected to each of the light-emitting control circuits; t refers to the thickness of the source-drain metal layer; b refers to the width of the source-drain metal layer; a refers to the maximum current density of the portion of the source-drain metal layer located in the transfer via.

[0017] Optionally, each group of the light emitting control circuits includes: one light emitting control circuit located on each side of the at least one row of display pixels in the row direction.

[0018] Optionally, a light emitting control circuit located on one of the two sides is connected to a portion of display pixels in the at least one row of display pixels, and another light emitting control circuit located on the other side of the two sides is connected to another portion of display pixels in the at least one row of display pixels except the portion of display pixels.

[0019] Optionally, the light emitting control circuit includes: a light emitting control transistor;

[0020] A gate of the light emitting control transistor is connected to the light emitting control line, a first electrode of the light emitting control transistor is connected to the target power line, and a second electrode of the light emitting control transistor is connected to the at least one row of display pixels.

[0021] Optionally, the light emitting control transistor is an N-type transistor.

[0022] Optionally, the light emitting control transistor is a dual-gate transistor.

[0023] Optionally, the data writing circuit includes: a data writing transistor;

[0024] The gate of the data writing transistor is connected to the gate line, the first electrode of the data writing transistor is connected to the data line, and the second electrode of the data writing transistor is connected to the input node.

[0025] Optionally, the external compensation circuit includes: a compensation transistor;

[0026] A gate of the compensation transistor is connected to the compensation line, a first electrode of the compensation transistor is connected to the sensing line, and a second electrode of the compensation transistor is connected to the output node.

[0027] Optionally, the light emitting driving circuit includes: a driving transistor;

[0028] When the target power line is the pull-up power line, the gate of the driving transistor is connected to the input node, the first electrode of the driving transistor is connected to the transfer node, the second electrode of the driving transistor is connected to the first electrode of the light-emitting unit, and the second electrode of the light-emitting unit is connected to the pull-down power line;

[0029] When the target power line is the pull-down power line, the gate of the driving transistor is connected to the input node, the first electrode of the driving transistor is connected to the pull-up power line, the second electrode of the driving transistor is connected to the first electrode of the light-emitting unit, and the second electrode of the light-emitting unit is connected to the transfer node;

[0030] The light emitting control circuit is connected to the transfer node.

[0031] Optionally, any one of the data writing transistor included in the data writing circuit, the compensation transistor included in the external compensation circuit, and the driving transistor included in the light emitting driving circuit is an N-type transistor or a P-type transistor.

[0032] Optionally, each of the display pixels further includes: a storage capacitor;

[0033] When the driving transistor is a P-type transistor, the target power line is the pull-down power line, and the storage capacitor is connected in series between the input node and the pull-up power line;

[0034] When the driving transistor is an N-type transistor, the target power line is the pull-up power line, and the storage capacitor is connected in series between the input node and the output node.

[0035] Optionally, the display panel further includes:

[0036] A plurality of dummy pixels are located in the display area and between the plurality of rows of display pixels and the plurality of groups of light emitting control circuits.

[0037] Optionally, the material of the N-type transistor in the display panel includes an oxide material; the material of the P-type transistor in the display panel includes a low-temperature polysilicon material.

[0038] In another aspect, a method for driving a display panel is provided, for driving the display panel according to the above aspect; the method comprising:

[0039] In the writing phase, the potential of the light-emitting control signal provided by the light-emitting control line is a first potential, and the light-emitting control circuit controls the target power line to be disconnected from the display pixel in response to the light-emitting control signal of the first potential;

[0040] In the light emitting stage, the potential of the light emitting control signal provided by the light emitting control line is a second potential, and the light emitting control circuit controls the target power line to be connected to the display pixel in response to the light emitting control signal of the second potential;

[0041] The target power line is a pull-up power line connected to a light-emitting driving circuit in the display pixel, or the target power line is a pull-down power line connected to a light-emitting unit in the display pixel.

[0042] In another aspect, a display device is provided, comprising: a light emitting control driving circuit, and the display panel according to the above aspect;

[0043] The light emitting control driving circuit is connected to a plurality of light emitting control lines connected to a plurality of light emitting control circuits in the display panel, and is used to transmit light emitting control signals to the plurality of light emitting control lines.

[0044] Optionally, the light-emitting control driving circuit is located in the peripheral area of ​​the substrate in the display panel, and the light-emitting control driving circuit includes a plurality of cascaded light-emitting control driving units, the plurality of light-emitting control driving units are connected one-to-one with the plurality of light-emitting control lines, and are used to transmit light-emitting control signals to the plurality of light-emitting control lines in sequence.

[0045] Optionally, the light emitting control driving circuit is independent of the display panel, and the light emitting control driving circuit is used to transmit light emitting control signals to the multiple light emitting control lines simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0047] FIG1 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure;

[0048] FIG2 is a schematic structural diagram of a display pixel and a light emitting control circuit provided by an embodiment of the present disclosure;

[0049] FIG3 is a schematic structural diagram of another display pixel and light-emitting control circuit provided by an embodiment of the present disclosure;

[0050] FIG4 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure;

[0051] FIG5 is a schematic diagram of a circuit structure in a display panel provided by an embodiment of the present disclosure;

[0052] FIG6 is a schematic diagram of a circuit structure of another display panel provided by an embodiment of the present disclosure;

[0053] FIG7 is a schematic diagram of a circuit structure in another display panel provided by an embodiment of the present disclosure;

[0054] FIG8 is a schematic diagram of a circuit structure in yet another display panel provided by an embodiment of the present disclosure;

[0055] FIG9 is a schematic structural diagram of a display panel provided in an embodiment of the present disclosure;

[0056] FIG10 is a schematic structural diagram of another display panel provided in an embodiment of the present disclosure;

[0057] FIG11 is a schematic diagram of a characteristic curve of a light emitting control circuit provided in an embodiment of the present disclosure;

[0058] FIG12 is a schematic flow chart of a method for driving a display panel according to an embodiment of the present disclosure;

[0059] FIG13 is a schematic diagram of a signal timing sequence in a display panel provided by an embodiment of the present disclosure;

[0060] FIG14 is a schematic diagram of a signal timing sequence in another display panel provided by an embodiment of the present disclosure;

[0061] FIG15 is a schematic diagram of signal timing in another display panel provided by an embodiment of the present disclosure;

[0062] FIG16 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure;

[0063] FIG17 is a schematic structural diagram of another display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0064] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0065] It should be noted that the transistors used in all embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used here are symmetrical, their source and drain are interchangeable, and the source is referred to as the first electrode and the drain is referred to as the second electrode, or the drain is referred to as the first electrode and the source is referred to as the second electrode. According to the form in the accompanying drawings, the middle end of the transistor is defined as the gate, the signal input end is the source, and the signal output end is the drain. In addition, the transistors used in the embodiments of the present disclosure may include any one of a P-type transistor and an N-type transistor or a combination thereof. Among them, the P-type transistor is turned on when the gate is at a low voltage and is turned off when the gate is at a high voltage, and the N-type transistor is turned on when the gate is at a high voltage and is turned off when the gate is at a low voltage. In addition, the multiple signals in each embodiment correspond to a first potential and a second potential. The first potential and the second potential only represent that the potential of the signal has two different state quantities, and do not mean that the first potential or the second potential has a specific value.

[0066] Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure. As shown in Figure 1 , the display panel includes: a substrate 01 having a display area AA and a peripheral area BB at least partially surrounding the display area AA.

[0067] For example, FIG1 shows a rectangular display area AA, with the peripheral area BB located on the left and right sides of the display area AA, partially surrounding the display area AA. Of course, in other embodiments, the display area AA may also have other shapes, such as a circle; and the peripheral area BB may be located on each side of the display area AA, i.e., surrounding the display area AA.

[0068] It is understood that the display area AA can display images, while the peripheral area BB cannot. The peripheral area BB can also be called a non-display area. In addition, the area of ​​the display area AA is generally much larger than the area of ​​the non-display area BB. The figures are only for schematic illustration.

[0069] 1 , the display panel further includes: a plurality of display pixels 02 arranged in an array, the plurality of display pixels 02 being located in the display area AA. The array arrangement may refer to an arrangement in rows and columns, that is, the display panel includes display pixels 02 in multiple rows and columns.

[0070] Based on FIG1 and referring to FIG2 , it can be seen that each display pixel 02 includes: a data writing circuit 021, a light-emitting driving circuit 022, an external compensation circuit 023, and a light-emitting unit 024. The data writing circuit 021, the light-emitting driving circuit 022, and the external compensation circuit 023 can be collectively referred to as a pixel circuit.

[0071] Among them, the data writing circuit 021 is respectively connected to the gate line Gate_A, the data line Data and the input node N1, the external compensation circuit 023 is respectively connected to the compensation line Gate_B, the sensing line SENS and the output node N2, the light-emitting driving circuit 022 is respectively connected to the input node N1, the output node N2 and the pull-up power line VDD, and the light-emitting unit 024 is respectively connected to the output node N2 and the pull-down power line VSS.

[0072] Alternatively, the light-emitting unit 024 may be an organic light-emitting diode (OLED). Furthermore, referring to FIG. 2 , a first electrode (e.g., an anode) of the light-emitting unit 024 may be connected to the output node N2, and a second electrode (e.g., a cathode) of the light-emitting unit 024 may be connected to the pull-down power line VSS.

[0073] The data write circuit 021 can control the connection between the data line Data and the input node N1 in response to the gate drive signal provided by the gate line Gate_A. For example, the data write circuit 021 can control the data line Data to be disconnected from the input node N1 when the potential of the gate drive signal is a first potential; and can control the data line Data to be connected to the input node N1 when the potential of the gate drive signal is a second potential, so that the data signal provided by the data line Data can be transmitted to the input node N1.

[0074] The light-emitting driving circuit 022 can transmit a light-emitting driving signal (e.g., pixel current) to the output node N2 based on the potential of the input node N1 and the pull-up power signal provided by the pull-up power line VDD, so that the light-emitting unit 024 can emit light based on the light-emitting driving signal and the pull-down power signal provided by the pull-down power line VSS.

[0075] The external compensation circuit 023 can control the connection between the sensing line SENS and the output node N2 in response to a compensation signal provided by the compensation line Gate_B. Furthermore, as can be seen in FIG. 2 , the sensing line SENS can be connected to the external compensation device 10. For example, when the compensation signal has a first potential, the external compensation circuit 023 can disconnect the sensing line SENS from the output node N2. Alternatively, when the compensation signal has a second potential, the external compensation circuit 023 can connect the sensing line SENS to the output node N2, causing the sensing line SENS to transmit a reference signal provided by the external compensation device 10 to the output node N2 to reset the output node N2. Alternatively, the external compensation device 10 can collect the potential of the output node N2 and transmit it to the external compensation device 10, allowing the external compensation device 10 to extract sensing signals such as the threshold voltage Vth of the driving transistor in the light-emitting driver circuit 022 and the pixel current transmitted from the light-emitting driver circuit 022 to the light-emitting unit 024. Based on the extracted sensing signals, the external compensation device 10 can perform external compensation on the data signal provided by the data line Data, ensuring that the light-emitting unit 024 can reliably emit light.

[0076] Continuing with FIG. 1 , the display panel further includes: multiple groups of light-emitting control circuits 03Z, located in the peripheral area BB. Each group of light-emitting control circuits 03Z corresponds to at least one row of display pixels 02, and each group of light-emitting control circuits 03Z corresponds to a different row of display pixels 02. Furthermore, each group of light-emitting control circuits 03Z includes a light-emitting control circuit 03 located on at least one side of the corresponding row of display pixels 02 in the row direction X. Each light-emitting control circuit 03 is connected between a target power line and at least one row of display pixels 02, and is also connected to a light-emitting control line EM. The circuit is configured to control the connection between the target power line and at least one row of display pixels 02 in response to a light-emitting control signal provided by the light-emitting control line EM.

[0077] For example, each light-emission control circuit 03 can disconnect the target power line from at least one row of display pixels 02 when the potential of the light-emission control signal provided by the light-emission control line EM is a first potential; and can connect the target power line to at least one row of display pixels 02 when the potential of the light-emission control signal is a second potential, so that the power signal provided by the target power line can be transmitted to the display pixels 02, thereby driving the display pixels 02 to reliably emit light. The target power line can be a pull-down power line VSS or a pull-up power line VDD. The target power line shown in FIG1 is a pull-up power line VDD.

[0078] Specifically, referring to FIG2 , in one implementation, the target power line is the pull-up power line VDD. This means that the light-emitting driver circuit 022 in the display pixel 02 can be indirectly connected to the pull-up power line VDD via the light-emitting control circuit 03. This connection point is also referred to as a transfer node N3. The light-emitting control circuit 03 can control the connection between the pull-up power line VDD and the light-emitting driver circuit 022 under the control of a light-emitting control signal provided by the light-emitting control line EM. In conjunction with the foregoing, when the light-emitting control circuit 03 controls the connection between the pull-up power line VDD and the light-emitting driver circuit 022, the light-emitting driver circuit 022 can transmit a light-emitting drive signal to the first electrode of the light-emitting unit 024 based on the potential of the input node N1 and the pull-up power signal provided by the pull-up power line VDD, thereby driving the light-emitting unit 024 to emit light.

[0079] Alternatively, in conjunction with FIG3 , in another implementation, the target power line can be a pull-down power line VSS. Specifically, the second electrode of the light-emitting unit 024 in the display pixel 02 can be indirectly connected to the pull-down power line VSS via the light-emitting control circuit 03. The connection point is also referred to as a transfer node N3. The light-emitting control circuit 03 can control the connection between the pull-down power line VSS and the second electrode of the light-emitting unit 024 under the control of a light-emitting control signal provided by the light-emitting control line EM. In conjunction with the foregoing, when the light-emitting control circuit 03 controls the connection between the pull-down power line VSS and the second electrode of the light-emitting unit 024, the light-emitting unit 024 can emit light based on the light-emitting drive signal transmitted by the light-emitting drive circuit 022 and the pull-down power signal provided by the pull-down power line VSS.

[0080] Thus, by flexibly setting the light-emission control signal, the light-emission control circuit 03 can flexibly control the duration of the pull-up power line VDD or the pull-down power line VSS to transmit the power signal to the display pixel 02, thereby flexibly controlling the light-emission duty of the light-emitting unit 024. This effectively improves display anomalies such as smearing, ensuring a better display quality for the display panel.

[0081] In addition, because in the embodiment of the present disclosure, for the display pixel 02 with an external compensation function, the light-emitting control circuit 03 is located in the peripheral area BB rather than the display area AA, that is, the light-emitting control circuit 03 is an external circuit relative to the pixel circuit included in the display pixel 02. Therefore, compared with the embodiment in which the display pixel 02 is provided with a light-emitting control circuit located in the display area AA, the solution provided by the embodiment of the present disclosure does not increase the size of the display pixel 02 (that is, the pixel pitch), and thus does not cause the PPI of the display area AA to decrease. In other words, it can also facilitate the design of a high PPI display panel. Among them, PPI (pixels per inch) refers to the number of pixels that can be set in 1 inch of the display panel and is used to represent the resolution.

[0082] Optionally, the first potential may refer to an invalid potential, the second potential may refer to an effective potential, and for the N-type transistors included in each circuit, the invalid potential may be a low potential relative to the effective potential; for the P-type transistors included in each circuit, the invalid potential may be a high potential relative to the effective potential.

[0083] In summary, an embodiment of the present disclosure provides a display panel. The display panel includes: a substrate having a display area and a peripheral area, a plurality of display pixels located in the display area, and a light-emitting control circuit located in the peripheral area. The display pixels can emit light under the drive of signals provided by various signal lines, and the various signal lines include pull-up power lines and pull-down power lines. The light-emitting control circuit can control the on-off of the pull-up power line or the pull-down power line and the display pixels in response to the light-emitting control signal provided by the light-emitting control line. In this way, by flexibly setting the light-emitting control signal, the light-emitting control circuit can flexibly control the duration of the conduction between the pull-up power line or the pull-down power line and the display pixels, thereby flexibly controlling the light-emitting duration of the display pixels. It can be seen from this that the display panel has good driving flexibility for the display pixels.

[0084] Alternatively, Figure 4 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure. As shown in Figure 4 , each group of light emitting control circuits 03Z may correspond to every two adjacent rows of display pixels 02 .

[0085] For example, referring to FIG4 , from top to bottom, adjacent display pixels 02 in the first and second rows can be connected to each light control circuit 03 included in the same group of light control circuits 03Z. Adjacent display pixels 02 in the third and fourth rows can be connected to each light control circuit 03 included in the same group of light control circuits 03Z. And so on. This not only simplifies wiring but also requires fewer light control circuits 03, thereby facilitating a narrow-frame design for the display panel.

[0086] Optionally, referring to FIG. 1 and FIG. 4 , it can be seen that in the embodiment of the present disclosure, each group of light-emitting control circuits 03Z may include: one light-emitting control circuit 03 located on each side of at least one row of display pixels 02 in the row direction X. That is, each group of light-emitting control circuits 03Z may include: one light-emitting control circuit 03 located on the left side of the display area AA as shown in the figure, and another light-emitting control circuit 03 located on the right side of the display area AA as shown in the figure, for a total of two light-emitting control circuits 03.

[0087] Furthermore, one light-emitting control circuit 03 located on one of the two sides can be connected to a portion of the display pixels 02 in at least one row of display pixels 02, and another light-emitting control circuit 03 located on the other side of the two sides can be connected to another portion of the display pixels 02 in at least one row of display pixels 02 except for a portion of the display pixels 02.

[0088] In this way, in the row direction X, for display pixels 02 located near the left side of display area AA and near the right side of display area AA, the light-emitting control circuit 03 can promptly control the connection and disconnection between the target power line, such as the pull-up power line VDD or the pull-down power line VSS, and the display pixel 02. Furthermore, since the longer the trace connecting the light-emitting control circuit 03 to the display pixel 02, the greater the impedance on the trace, which can easily lead to poor reliability of the power signal transmitted from the target power line to the display pixel 02, by providing a light-emitting control circuit 03 on each of the left and right sides in the row direction X, the length of the trace connected to each light-emitting control circuit 03 can be reduced, thereby reducing the impedance on the trace and ensuring that the power signal provided by the target power line is reliably transmitted to the display pixel 02. In some embodiments, for scenarios with high impedance, it is also considered to reduce impedance by increasing the trace width. However, using the solution of the embodiments of the present disclosure, there is no need to increase the trace width, which is conducive to the high PPI design of the display panel.

[0089] Optionally, in conjunction with Figure 2 , Figure 5 shows a schematic diagram of a circuit structure in a display panel. Figure 6 shows a schematic diagram of a circuit structure in another display panel. In conjunction with Figure 3 , Figure 7 shows a schematic diagram of a circuit structure in yet another display panel. Figure 8 shows a schematic diagram of a circuit structure in yet another display panel. As can be seen from Figures 5 to 8 , the light emission control circuit 03 may include: a light emission control transistor M0.

[0090] The gate of the emission control transistor M0 can be connected to the emission control line EM, the first electrode of the emission control transistor M0 can be connected to the target power line, and the second electrode of the emission control transistor M0 can be connected to at least one row of display pixels O2, that is, connected to the transfer node N3. For example, the target power line shown in Figures 5 and 6 is the pull-up power line VDD; the target power line shown in Figures 7 and 8 is the pull-down power line VSS.

[0091] Optionally, as shown in Figure 5 , the light emission control transistor M0 may be an N-type transistor. Of course, in other embodiments, as shown in Figures 6 to 8 , the light emission control transistor M0 may be a P-type transistor.

[0092] Optionally, in the embodiment of the present disclosure, the light emission control transistor M0 may also be a dual-gate transistor, that is, the light emission control transistor M0 may have two gates.

[0093] Since P-type transistors generally have a large leakage current, configuring the emission control transistor M0 as an N-type transistor can reduce the leakage current of the emission control transistor M0, thereby ensuring reliable transmission of the power signal to the display pixel 02. Furthermore, configuring the emission control transistor M0 as a dual-gate transistor can stabilize the threshold voltage Vth of the emission control transistor M0, further ensuring reliable transmission of the power signal to the display pixel 02.

[0094] Alternatively, referring to FIG. 5 to FIG. 8 , it can be seen that the data writing circuit 021 may include a data writing transistor M1 , the external compensation circuit 023 may include a compensation transistor M2 , and the light emitting driving circuit 022 may include a driving transistor M3 .

[0095] A gate of the data write transistor M1 may be connected to the gate line Gate_A, a first electrode of the data write transistor M1 may be connected to the data line Data, and a second electrode of the data write transistor M1 may be connected to the input node N1.

[0096] A gate of the compensation transistor M2 may be connected to the compensation line Gate_B, a first electrode of the compensation transistor M2 may be connected to the sensing line SENS, and a second electrode of the compensation transistor M2 may be connected to the output node N2.

[0097] When the target power line is the pull-up power line VDD, as shown in Figures 5 and 6, the gate of the driving transistor M3 can be connected to the input node N1, the first electrode of the driving transistor M3 can be connected to the transfer node N3, the second electrode of the driving transistor M3 can be connected to the first electrode of the light-emitting unit 024, and the second electrode of the light-emitting unit 024 can be connected to the pull-down power line VSS.

[0098] When the target power line is the pull-down power line VSS, as shown in Figures 7 and 8, the gate of the driving transistor M3 can be connected to the input node N1, the first electrode of the driving transistor M3 can be connected to the pull-up power line VDD, the second electrode of the driving transistor M3 can be connected to the first electrode of the light-emitting unit 024, and the second electrode of the light-emitting unit 024 can be connected to the transfer node N3.

[0099] The light emitting control circuit 03 may be connected to the switching node N3. That is, in combination with the above description, the second electrode of the light emitting control transistor M0 may be connected to the display pixel 02 by being connected to the switching node N3.

[0100] Optionally, any one of the data writing transistor M1 included in the data writing circuit 021 , the compensation transistor M2 included in the external compensation circuit 023 , and the driving transistor M3 included in the light emitting driving circuit 022 may be an N-type transistor or a P-type transistor.

[0101] For example, referring to FIG5 , the circuit structure shown therein is a data write transistor M1, a compensation transistor M2, and a drive transistor M3, all of which are N-type transistors. Referring to FIG6 , the circuit structure shown therein is a data write transistor M1, a P-type transistor, and a compensation transistor M2 and a drive transistor M3, all of which are N-type transistors. Referring to FIG7 , the circuit structure shown therein is a data write transistor M1, a drive transistor M3, and a P-type transistor, and a compensation transistor M2 and an N-type transistor. Referring to FIG8 , the circuit structure shown therein is a data write transistor M1, a compensation transistor M2, and a drive transistor M3, all of which are P-type transistors.

[0102] Optionally, in an embodiment of the present disclosure, the material of the P-type transistor in the display panel may include: low temperature polysilicon (LTPS) material. The material of the N-type transistor in the display panel may include: oxide material. On this basis, the circuit structure shown in Figure 5 can be referred to as a pixel circuit of an all-N-type oxide architecture. The circuit structures shown in Figures 6 and 7 can be referred to as a pixel circuit of a low temperature polysilicon oxide (LTPO) architecture that includes both P-type transistors and N-type transistors. The circuit structure shown in Figure 8 can be referred to as a pixel circuit of an all-P-type LTPS architecture.

[0103] Among them, the LTPO architecture shown in Figures 6 and 7 simultaneously utilizes the advantages of low leakage current of N-type transistors of oxide and the mobility of P-type transistors of LTPS, and has good working reliability.

[0104] Optionally, each transistor described in the embodiment of the present disclosure may be a metal oxide semiconductor (MOS) field effect transistor.

[0105] Optionally, as can be seen from FIG5 and FIG8 , each display pixel 02 may further include a storage capacitor Cst. The storage capacitor Cst may be used to store signals.

[0106] When the driving transistor M3 is a P-type transistor, as shown in Figures 7 and 8 , the target power line can be the pull-down power line VSS. That is, the first electrode of the emission control transistor M0 can be connected to the pull-down power line VSS, and the second electrode of the emission control transistor M0 can be connected to the second electrode of the light-emitting unit O24 to the transfer node N3. Furthermore, the storage capacitor Cst can be connected in series between the input node N1 and the pull-up power line VDD.

[0107] When the driving transistor M3 is an N-type transistor, as shown in Figures 5 and 6 , the target power line can be the pull-up power line VDD. That is, the first electrode of the emission control transistor M0 can be connected to the pull-up power line VDD, and the second electrode of the emission control transistor M0 can be connected to the first electrode of the driving transistor M3 to the transfer node N3. Furthermore, the storage capacitor Cst can be connected in series between the input node N1 and the output node N2.

[0108] For an embodiment in which the driving transistor M3 is a P-type transistor, by setting the target power line as the pull-down power line VSS, that is, providing a light-emitting control transistor M0 to indirectly connect the pull-down power line VSS to the second electrode of the light-emitting unit 024, while flexibly controlling the light-emitting duration, the current difference caused by the voltage drop (IR drop) at the source of the driving transistor M3 can also be reduced, ensuring that the driving transistor M3 can reliably transmit the light-emitting drive signal to the light-emitting unit 024, thereby driving the light-emitting unit 024 to reliably emit light.

[0109] It is understood that in the circuit structures shown in Figures 5 to 8, the pixel circuit included in the display pixel 02 can be considered as a 3T1C structure circuit including three transistors and one storage capacitor. Of course, in some other embodiments, it can also be a 2T1C structure circuit.

[0110] Optionally, it can be seen from FIG. 5 to FIG. 8 that the external compensation device 10 described above may further include: a switch K1 and a switch K2 .

[0111] The switch K1 can be connected between the reference signal terminal V_REF and the sensing line SENS, and can be connected to the switch control terminal S_REF, and can be used to control the on / off of the reference signal terminal V_REF and the sensing line SENS in response to the switch control signal provided by the switch control terminal S_REF.

[0112] For example, the switch K1 can control the reference signal terminal V_REF and the sensing line SENS to be turned on when the potential of the switch control signal provided by the switch control terminal S_REF is a valid potential, so that the reference signal terminal V_REF transmits the reference signal described above to the output node N2 via the sensing line SENS; and can control the reference signal terminal V_REF and the sensing line SENS to be disconnected when the potential of the switch control signal provided by the switch control terminal S_REF is an invalid potential.

[0113] The switch K2 may be connected between the test terminal VSENS and the sensing line SENS and to the switch control terminal S_SAMP, and may be used to control the on / off of the test terminal VSENS and the sensing line SENS in response to a switch control signal provided by the switch control terminal S_SAMP.

[0114] For example, the switch K2 can control the test terminal VSENS and the sensing line SENS to be turned on when the potential of the switch control signal provided by the switch control terminal S_SAMP is a valid potential, so that the test terminal VSENS collects the sensing signal recorded above through the sensing line SENS; and can control the test terminal VSENS and the sensing line SENS to be disconnected when the potential of the switch control signal provided by the switch control terminal S_SAMP is an invalid potential.

[0115] Optionally, as shown in Figures 5 to 8 , both switch K1 and switch K2 can be single-pole, single-throw switches. Each switch can be closed when the potential of the switch control signal it receives is a valid potential, and can be opened when the potential of the switch control signal it receives is a invalid potential. Of course, in some other embodiments, switch K1 and / or switch K2 can also be transistors as described above.

[0116] Alternatively, in combination with the structure shown in Figure 4 , Figure 9 shows a structural layout of a display panel. Referring to Figure 9 , it can be seen that each light-emitting control circuit 03 (i.e., the light-emitting control transistor M0 externally mounted in the peripheral area BB) can include: an active (ACT) layer ACT1, a gate metal layer GATE1, and a source and drain (SD) metal layer SD1, which are stacked sequentially on one side of the substrate 01.

[0117] Each light-emitting control circuit 03 can be connected to at least one row of display pixels 02 through the source / drain metal layer SD1 via a transfer via K0. Furthermore, each light-emitting control circuit 03 can be connected to two display pixels 02 located in the same column of two adjacent rows of display pixels 02 through the same transfer via K0. This ensures reliable connection between the light-emitting control circuit 03 and the display pixels 02 while simplifying the process and reducing costs.

[0118] For example, in an embodiment where the target power line is the pull-up power line VDD, that is, the light-emission control transistor M0 is connected to the first electrode of the driving transistor M3 in the display pixel 02, as shown in Figure 9, the source-drain metal layer SD1 of the light-emission control transistor M0 can be connected to the active layer ACT1 of the driving transistor M3. In other words, the active layer ACT1 of the driving transistor M3 in two adjacent rows of display pixels (up and down) can be connected to the source-drain metal layer SD1 of the light-emission control transistor M0 through the same connection via K0.

[0119] For another example, in an embodiment where the target power line is the pull-down power line VSS, that is, the light-emission control transistor M0 is connected to the second electrode of the light-emitting unit 024 in the display pixel 02, assuming that the second electrode of the light-emitting unit 024 is a cathode, it can be considered that the source-drain metal layer SD1 of the light-emission control transistor M0 is connected to the cathode of the light-emitting unit 024. In other words, the cathodes of the light-emitting units 024 in two adjacent rows of display pixels can be connected to the source-drain metal layer SD1 of the light-emission control transistor M0 through the same connection via K0.

[0120] In addition, referring to FIG. 9 , it can be seen that the light emission control transistor M0 shown therein has two gates, and is a dual-gate transistor.

[0121] Optionally, as can be seen in FIG9 , the display panel may further include: a plurality of dummy pixels 04, which may be located in the display area AA and between the multiple rows of display pixels 02 and the multiple groups of light-emitting control circuits 03Z (i.e., external light-emitting control transistors M0). In this way, better etching uniformity can be ensured when preparing the display panel. Optionally, based on the layout shown in FIG9 , FIG10 also schematically shows a structural layout including multiple rows of display pixels 02.

[0122] It's understandable that because the pull-up power line VDD or the pull-down power line VSS is connected to multiple display pixels 02 via a single emission control transistor M0, transmitting power signals to the multiple display pixels 02, the on-state current of the emission control transistor M0 must be relatively high. Furthermore, the width and thickness of the metal trace at the transfer node N3 (i.e., the trace formed by the source and drain metal layer SD1 of the emission control transistor M0) must meet the maximum current density required for high currents to minimize heating.

[0123] Thus, in the embodiment of the present disclosure, the thickness and width of the source-drain metal layer SD1 of the light emitting control transistor M0 may satisfy: I_t / (t*b)≤a.

[0124] Wherein, I_t may refer to the total pixel current of the multiple display pixels 02 connected to each light-emitting control circuit 03. t may refer to the thickness of the source / drain metal layer SD1. b may refer to the width of the source / drain metal layer SD1. a may refer to the maximum current density of the portion of the source / drain metal layer SD1 located at the transfer via K0 (i.e., the transfer node N3).

[0125] Assume that the unit of I_t is microampere (μA) and the unit of a is milliampere / square micrometer (mA / μm 2), the unit of b is μm, and the unit of t is μm. After converting the units, it can be deduced that the line width b formed by the source / drain metal layer SD1 can satisfy: b≥I_t / 1000 / (t*a).

[0126] Furthermore, it is understood that the on-state current of the emission control transistor M0 must also be greater than or equal to I_t, that is, the sum of the maximum currents of all display pixels under control. In some embodiments, the on-state current of the emission control transistor M0 can be increased by increasing the width-to-length ratio W / L of the emission control transistor M0 or the source-to-drain current Vds of the emission control transistor M0.

[0127] For example, assuming that the pixel current of each display pixel is Id (μA), each light-emitting control transistor M0 is connected to n rows of display pixels 02 to control the target power line to transmit the power signal to the n rows of display pixels 02, and each row of display pixels 02 includes m display pixels, then I_t can satisfy: I_t=Id*n*m.

[0128] Here, n is an integer greater than or equal to 1 and less than the number of rows of display pixels 02 , and m is an integer greater than 1 and less than the number of columns of display pixels 02 .

[0129] Taking an OLED display product as an example, assuming its horizontal resolution H = 2000, that is, the display panel includes 2000 columns of display pixels 02, Id = 150 nanoamperes (nA), and a set of light-emission control circuits 03Z includes a light-emission control circuit 03 located on each left and right side, with each light-emission control circuit 03 connected to a row of display pixels 02. (i.e., n = 1, n = H / 2 = 500), then we can calculate: I_t = 150μA. In other words, the on-state current of the light-emission control transistor M0 in each light-emission control circuit 03 must be at least 150μA.

[0130] Alternatively, Figure 11 schematically shows characteristic curves of the light emitting control transistor M0 at different on-state currents (eg, 1, 2.1, 4.1, etc.), wherein the abscissa represents current and the ordinate represents voltage.

[0131] It is understood that the emission control transistor M0 described in the embodiments of the present disclosure is applicable not only to OLED display products in which the light-emitting unit 024 is an OLED, but also to MLED display products in which the light-emitting unit 024 is a micro light-emitting diode (MLED). Since the pixel current required by an MLED is in the μA range, approximately 100 times greater than that required by an OLED, it can be seen that the width-to-length ratio (W / L) of the emission control transistor M0 in an MLED display product can be much greater than that in an OLED display product, requiring it to provide a greater current.

[0132] In summary, an embodiment of the present disclosure provides a display panel. The display panel includes: a substrate having a display area and a peripheral area, a plurality of display pixels located in the display area, and a light-emitting control circuit located in the peripheral area. The display pixels can emit light under the drive of signals provided by various signal lines, and the various signal lines include pull-up power lines and pull-down power lines. The light-emitting control circuit can control the on-off of the pull-up power line or the pull-down power line and the display pixels in response to the light-emitting control signal provided by the light-emitting control line. In this way, by flexibly setting the light-emitting control signal, the light-emitting control circuit can flexibly control the duration of the conduction between the pull-up power line or the pull-down power line and the display pixels, thereby flexibly controlling the light-emitting duration of the display pixels. It can be seen from this that the display panel has good driving flexibility for the display pixels.

[0133] FIG12 is a flow chart of a method for driving a display panel according to an embodiment of the present disclosure, the method being used to drive the display panel as described above. As shown in FIG12 , the method includes:

[0134] Step 1201, writing stage, the potential of the light emitting control signal provided by the light emitting control line is a first potential, and the light emitting control circuit controls the target power line to be disconnected from the display pixel in response to the light emitting control signal of the first potential.

[0135] Step 1202 , in the light emitting stage, the potential of the light emitting control signal provided by the light emitting control line is a second potential, and the light emitting control circuit controls the target power line and the display pixel to be turned on in response to the light emitting control signal of the second potential.

[0136] The target power line is a pull-up power line connected to a light-emitting driving circuit in a display pixel, or the target power line is a pull-down power line connected to a light-emitting unit in a display pixel.

[0137] Optionally, for multiple light-emitting control lines connected to multiple light-emitting control circuits, in one implementation, the required light-emitting control signals can be provided to the multiple light-emitting control lines one by one, or, in another implementation, the required light-emitting control signals can be provided to the multiple light-emitting control lines uniformly. In these two implementations, with the structure shown in Figure 5, Figures 13 and 14 respectively show a signal sequence diagram in a display panel. Referring to the timing diagram, it can be seen that a frame period can include a display phase T1 and a sensing phase T2 that are executed in sequence. The display phase T1 can include a write phase T11 and a light-emitting phase T12 that are executed in sequence. The sensing phase T2 can include a reset phase T21, a compensation phase T22, and an extraction phase T23 that are executed in sequence.

[0138] In which, in the write phase T11, the gate line Gate_A can provide a high-potential gate drive signal, the compensation line Gate_B can provide a high-potential compensation signal, and the light-emitting control line EM can provide a low-potential light-emitting control signal. Under the structure shown in Figure 5, the high potential is the effective potential, and the low potential is the invalid potential. Accordingly, the data write transistor M1 and the compensation transistor M2 can both be turned on, and the light-emitting control transistor M0 can be turned off. Furthermore, the data line Data can transmit a data signal to the input node N1 through the turned-on data write transistor M1 to charge the input node N1; and the sensing line SENS can transmit a reference signal to the output node N2 through the turned-on compensation transistor M2 to reset the output node N2. The storage capacitor Cst can store the data signal transmitted to the input node N1.

[0139] During the light-emitting phase T12, gate line Gate_A can provide a low-potential gate drive signal, compensation line Gate_B can provide a low-potential compensation signal, and emission control line EM can provide a high-potential emission control signal. Accordingly, data write transistor M1 and compensation transistor M2 can both be turned off, and emission control transistor M0 can be turned on. Furthermore, pull-up power line VDD can transmit a pull-up power signal to transfer node N3 via the turned-on emission control transistor M0, enabling emission drive transistor M3 to transmit a light-emitting drive signal to the anode of light-emitting unit 024 based on the pull-up power signal and the data signal from input node N1, thereby enabling light-emitting unit 024 to emit light based on the light-emitting drive signal and the pull-down power signal provided by pull-down power line VSS connected to the cathode. The light-emitting duration is positively correlated with the duration of the high-potential emission control signal. That is, the longer the high-potential emission control signal lasts, the longer the light-emitting duration of light-emitting unit 024. This allows for flexible control of the light-emitting duration of display pixel 02.

[0140] During the reset phase T21 to the extraction phase T23, the gate line Gate_A can provide a high-potential gate drive signal, the compensation line Gate_B can provide a high-potential compensation signal, and the emission control line EM can provide a high-potential emission control signal. Accordingly, the data writing transistor M1, the compensation transistor M2, and the emission control transistor M0 can all be turned on.

[0141] Furthermore, in the reset phase T21, in the external compensation device 10, the switch control terminal S_REF connected to the switch K1 can provide a switch control signal with an active potential (e.g., a low potential), and the switch control terminal S_SAMP connected to the switch K2 can provide a switch control signal with an inactive potential (e.g., a high potential), thereby turning on the switch K1 and turning off the switch K2. Consequently, the reference signal terminal V_REF and the sensing line SENS can be electrically connected, and the reference signal is transmitted to the output node N2 via the sensing line SENS and the turned-on compensation transistor M2, thereby resetting the output node N2, i.e., the anode of the light-emitting unit O24.

[0142] In the compensation stage T22 , in the external compensation device 10 , the switch control terminal S_REF connected to the switch K1 can provide a switch control signal with an invalid potential, and the switch control terminal S_SAMP connected to the switch K2 can also provide a switch control signal with an invalid potential, so that both the switch K1 and the switch K2 are closed.

[0143] During extraction phase T23, in the external compensation device 10, the switch control terminal S_REF connected to the switch K1 can provide a switch control signal at an inactive potential, and the switch control terminal S_SAMP connected to the switch K2 can provide a switch control signal at an active potential, thereby closing the switch K1 and opening the switch K2. This allows electrical conduction between the test terminal VSENS and the sensing line SENS. The sensing line SENS can extract the signal at the output node N2 and transmit it to the test terminal VSENS as a sensing signal, allowing the external compensation device 10 to perform external compensation on the data signal based on the sensing signal.

[0144] It is understood that, with reference to FIG14 , the multiple gate lines Gate_A connected to the multiple rows of display pixels 02 can provide gate drive signals with effective potentials to the multiple rows of display pixels 02 row by row. In the timing sequence shown in FIG13 , the multiple switch control lines EM can be switch control signals that provide effective potentials row by row, i.e., the emission control transistors M0 connected to each row of display pixels 02 can be turned on row by row. In the timing sequence shown in FIG14 , the multiple switch control lines EM can be gate drive signals that provide effective potentials to all rows of display pixels 02 after the multiple gate lines Gate_A provide gate drive signals with effective potentials, so that the emission control transistors M0 connected to each row of display pixels 02 can be turned on simultaneously after the data signals provided by the data lines Data are written to all rows of display pixels 02. In addition, similar to the multiple gate lines Gate_A, as shown in FIG14 , the multiple compensation lines Gate_B connected to the multiple rows of display pixels 02 can also provide compensation signals with effective potentials to the multiple rows of display pixels 02 row by row. The figure illustrates a display panel including n rows of display pixels 02 as an example.

[0145] Optionally, Figure 15 also illustrates a signal sequence diagram in a display panel, using the structure shown in Figure 8 as an example. Comparing Figures 13 and 14 , it can be seen that, unlike the structure shown in Figure 5 , because the data writing transistor M1, the compensation transistor M2, and the emission control transistor M0 are all P-type transistors, the effective potentials of the gate drive signal, the compensation signal, and the emission control signal all become low, while the ineffective potentials all become high.

[0146] It is understandable that since the driving method has substantially the same technical effects as those of the aforementioned display panel embodiment, the technical effects of the driving method will not be repeatedly described herein for the purpose of brevity.

[0147] Fig. 16 is a schematic diagram of the structure of a display device provided by an embodiment of the present disclosure. As shown in Fig. 16, the display device includes: a light emitting control driving circuit 20, and the display panel as described above.

[0148] 1 , the light emitting control driving circuit 20 is connected to a plurality of light emitting control lines EM connected to a plurality of light emitting control circuits 03 in the display panel, and is used to transmit light emitting control signals to the plurality of light emitting control lines EM.

[0149] Alternatively, as an alternative implementation, as shown in FIG16 , the light-emission control driving circuit 20 and the display panel can be independent of each other, and the light-emission control driving circuit 20 can be configured to simultaneously transmit light-emission control signals to multiple light-emission control lines EM. Specifically, the light-emission control signals are transmitted in a timing sequence as shown in FIG14 .

[0150] For example, the light emitting control driving circuit 20 may be an external integrated circuit (IC).

[0151] It can be understood that FIG16 schematically shows the display area AA and the 3T1C pixel circuit + light-emitting unit located in the display area AA, the peripheral area BB and the light-emitting control circuit located in the peripheral area BB in the display panel.

[0152] Alternatively, as another optional implementation, as shown in FIG17 , the light emission control driving circuit 20 can be located in the peripheral area BB of the substrate 01 of the display panel. For example, the light emission control driving circuit 20 can be provided on the substrate 01 using gate driver on array (GOA) technology. Accordingly, the light emission control driving circuit 20 can also be referred to as an EM GOA circuit. Furthermore, the light emission control driving circuit 20 can include multiple cascaded light emission control driving units EM GOA. Each of the multiple light emission control driving units EM GOA can be connected to multiple light emission control lines EM in a one-to-one correspondence and configured to sequentially transmit light emission control signals to the multiple light emission control lines EM. In other words, the light emission control signals are transmitted in a manner that satisfies the timing sequence shown in FIG13 .

[0153] It will be appreciated that FIG17 also schematically illustrates a plurality of rows of display pixels 02 located in the display area AA, and each light-emitting control circuit 03 can be connected to a row of display pixels 02. In addition, a power supply (Power) 30 is also shown, which is connected to the light-emitting control circuit 03 and the display pixels 02, respectively, and is used to supply power to the light-emitting control circuit 03 and the display pixels 02. In addition, the display device may further include: a gate drive circuit located in the peripheral area BB, i.e., a Gate GOA circuit, for transmitting a gate drive signal to the gate line Gate_A. The provision of the compensation signal is similar and will not be described in detail here.

[0154] Optionally, the display device can be any type of display device such as an OLED display device and an MLED display device. Furthermore, the display device includes any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, and a virtual reality (VR). Since a VR display device produces a tail-like effect when moving at a fast speed or changing viewing angles quickly, when two images are reflected in the human brain at the same time, a smearing anomaly will occur, affecting the viewing effect. In the embodiment of the present disclosure, by flexibly controlling the light emission duration, the disadvantage of the smearing anomaly can be effectively improved.

[0155] It should be understood that the terms used in the embodiments of the present disclosure are used to explain the embodiments of the present disclosure and are not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the common meanings understood by people with ordinary skills in the field to which the present disclosure belongs.

[0156] For example, in the embodiments of the present disclosure, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance. The term "connection" may refer to an electrical connection. The term "plurality" refers to two or more, unless otherwise expressly defined. Similarly, "one" or "an" and other similar words do not indicate a quantity limitation, but rather indicate the presence of at least one. "Include" or "comprising" and other similar words mean that the elements or objects appearing before "include" or "comprising" cover the elements or objects listed after "include" or "comprising" and their equivalents, and do not exclude other elements or objects. "Up", "down", "left" or "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0157] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A display panel, comprising: A substrate having a display area and a peripheral area at least partially surrounding the display area; A plurality of display pixels arranged in an array are located in the display area, each of the display pixels comprises: a data writing circuit, a light emitting driving circuit, an external compensation circuit and a light emitting unit, the data writing circuit is respectively connected to a gate line, a data line and an input node, the external compensation circuit is respectively connected to a compensation line, a sensing line and an output node, the light emitting driving circuit is respectively connected to the input node, the output node and a pull-up power line, and the light emitting unit is respectively connected to the output node and the pull-down power line; A plurality of groups of light-emitting control circuits are located in the peripheral area, each group of the light-emitting control circuits corresponds to at least one row of display pixels among the plurality of rows of display pixels, and each group of the light-emitting control circuits corresponds to a different row of display pixels, and each group of the light-emitting control circuits includes: a light-emitting control circuit located on at least one side of the at least one row of display pixels in the row direction, each of the light-emitting control circuits is connected between a target power line and the at least one row of display pixels, and is also connected to a light-emitting control line, and is used to control the on-off of the target power line and the at least one row of display pixels in response to a light-emitting control signal provided by the light-emitting control line; Wherein, the target power line is the pull-down power line or the pull-up power line.

2. The display panel according to claim 1, wherein, Each group of the light emitting control circuits corresponds to every two adjacent rows of display pixels.

3. The display panel according to claim 2, wherein, Each of the light emitting control circuits comprises: an active layer, a gate metal layer and a source-drain metal layer which are located on one side of the substrate and are stacked in sequence; Each of the light emitting control circuits is switched with the at least one row of display pixels through the source-drain metal layer via a switching via hole; and each of the light emitting control circuits is switched with two display pixels in the same column of the two adjacent rows of display pixels through the same switching via hole.

4. The display panel according to claim 3, wherein, The thickness and width of the source and drain metal layers satisfy: I_t / (t*b)≤a; Wherein, I_t refers to the sum of pixel currents of multiple display pixels connected to each of the light emitting control circuits; t refers to the thickness of the source-drain metal layer; b refers to the width of the source-drain metal layer; a refers to the width of the source-drain metal layer at the The maximum current density that can be withstand of the portion of the transfer via.

5. The display panel according to any one of claims 1 to 4, wherein, Each group of the light emitting control circuits includes: one light emitting control circuit each located on both sides of the at least one row of display pixels in the row direction.

6. The display panel according to claim 5, wherein, A light emitting control circuit located on one of the two sides is connected to a portion of display pixels in the at least one row of display pixels, and another light emitting control circuit located on the other side of the two sides is connected to another portion of display pixels in the at least one row of display pixels except the portion of display pixels.

7. The display panel according to any one of claims 1 to 6, wherein, The light emitting control circuit comprises: a light emitting control transistor; A gate of the light emission control transistor is connected to the light emission control line, a first electrode of the light emission control transistor is connected to the target power supply line, and a second electrode of the light emission control transistor is connected to the at least one row of display pixels.

8. The display panel according to claim 7, wherein, The light emission control transistor is an N-type transistor.

9. The display panel according to claim 7 or 8, wherein The light emission control transistor is a dual-gate transistor.

10. The display panel according to any one of claims 1 to 9, wherein, The data writing circuit comprises: a data writing transistor; The gate of the data writing transistor is connected to the gate line, the first pole of the data writing transistor is connected to the data line, and the second pole of the data writing transistor is connected to the input node.

11. The display panel according to any one of claims 1 to 10, wherein, The external compensation circuit includes: a compensation transistor; The gate of the compensation transistor is connected to the compensation line, and the first pole of the compensation transistor is connected to the sensing line, and the second pole of the compensation transistor is connected to the output node.

12. The display panel according to any one of claims 1 to 11, wherein, The light emitting driving circuit includes: a driving transistor; When the target power supply line is the pull-up power supply line, the gate of the driving transistor is connected to the input node, the first pole of the driving transistor is connected to the transfer node, the second pole of the driving transistor is connected to the first pole of the light emitting unit, and the second pole of the light emitting unit is connected to the pull-down power supply line; When the target power supply line is the pull-down power supply line, the gate of the driving transistor is connected to the input node, the first pole of the driving transistor is connected to the pull-up power supply line, the second pole of the driving transistor is connected to the first pole of the light emitting unit, and the second pole of the light emitting unit is connected to the transfer node; The light emitting control circuit is connected to the transfer node.

13. The display panel according to any one of claims 10 to 12, wherein, Any one of the data writing transistor included in the data writing circuit, the compensation transistor included in the external compensation circuit, and the driving transistor included in the light emitting driving circuit is an N-type transistor or a P-type transistor.

14. The display panel according to claim 13, wherein, Each of the display pixels further includes: a storage capacitor; When the driving transistor is a P-type transistor, the target power supply line is the pull-down power supply line, and the storage capacitor is connected in series between the input node and the pull-up power supply line; When the driving transistor is an N-type transistor, the target power supply line is the pull-up power supply line, and the storage capacitor is connected in series between the input node and the output node.

15. The display panel according to any one of claims 1 to 14, wherein, The display panel further includes: A plurality of dummy pixels, located in the display area and between the multi-row display pixels and the multi-group light emitting control circuits.

16. The display panel according to any one of claims 1 to 15, wherein, The material of the N-type transistor in the display panel includes: an oxide material; the material of the P-type transistor in the display panel includes: a low-temperature polycrystalline silicon material.

17. A driving method for a display panel, for driving the display panel according to any one of claims 1 to 16; the method includes: Writing stage, the potential of the light emitting control signal provided by the light emitting control line is a first potential, and the light emitting control circuit responds to the light emitting control signal of the first potential to control the target power supply line to be disconnected from the display pixel; Light emitting stage, the potential of the light emitting control signal provided by the light emitting control line is a second potential, and the light emitting control circuit responds to the light emitting control signal of the second potential to control the target power supply line to be turned on with the display pixel; Wherein, the target power supply line is the pull-up power supply line connected to the light emitting driving circuit in the display pixel, or, the target power supply line is the pull-down power supply line connected to the light emitting unit in the display pixel.

18. A display device, the display device comprising: A light emitting control driving circuit, and a display panel according to any one of claims 1 to 16; Among them, the light-emitting control driving circuit is connected to a plurality of light-emitting control lines connected to a plurality of light-emitting control circuits in the display panel, and is configured to transmit light-emitting control signals to the plurality of light-emitting control lines.

19. The display device according to claim 18, wherein, The light-emitting control driving circuit is located in the peripheral area of the substrate in the display panel, and the light-emitting control driving circuit includes a plurality of cascaded light-emitting control driving units. The plurality of light-emitting control driving units are connected to the plurality of light-emitting control lines in one-to-one correspondence, and are configured to sequentially transmit light-emitting control signals to the plurality of light-emitting control lines.

20. The display device according to claim 18, wherein, The light-emitting control driving circuit is independent of the display panel, and the light-emitting control driving circuit is configured to simultaneously transmit light-emitting control signals to the plurality of light-emitting control lines.

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