PCIE device detection system, method and apparatus, and product

Abstract

The present application relates to the technical field of PCIE devices. Disclosed are a PCIE device detection system, method and apparatus, and a product. The PCIE device detection system at least comprises a CPLD. The CPLD comprises: a control unit, which is used for acquiring in-place information sent by a PCIE device within a detection period, wherein the in-place information comprises in-place signals of all in-place detection pins on the PCIE device; a parsing unit, which is used for acquiring all in-place signals from the in-place information, and determining an actual bandwidth of the PCIE device on the basis of the in-place signals; and a determination unit, which is used for determining, on the basis of a preset bandwidth and the actual bandwidth, whether the PCIE device is tilted. By using this system, when the problem of bandwidth reduction occurs in a device, whether the device is tilted can be quickly and accurately determined without detaching a server case cover to insert and remove the PCIE device again, thereby greatly improving the troubleshooting efficiency, saving on the repair time and reducing the maintenance cost of the device.

Description

A PCIE device detection system, method, device and product

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on January 16, 2024, with application number 202410063487.1, and application name “A PCIE device detection system, method, device and product”, all contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of PCIE device technology, and in particular to a PCIE device detection system, method, device and product. Background Art

[0004] PCIE (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard. As essential peripherals for connecting to the internet, PCIE devices are widely used in servers. For example, PCIE network cards connect to the motherboard via a slot, enabling high-speed data transmission and network connectivity. This meets the demands of large-scale data processing and distributed computing, improving server data transmission efficiency. Detecting bandwidth degradation is crucial in server applications. In environments with numerous servers, such as computer rooms and clusters, PCIE device assembly and replacement, daily customer maintenance, and transportation and handling can cause increasing interference, such as vibration and tilt. This is especially true for edge servers exposed to harsh environments. Force majeure can inevitably cause disturbances to the devices, leading to bandwidth degradation, decreased data rates, increased transmission errors, and impacts on interoperability of network devices.

[0005] Currently, device bandwidth reduction detection is performed through the BIOS (Basic Input / Output System). When the server is turned on, the BIOS will perform a power-on self-test on the device. If the device has an abnormal bandwidth reduction problem, it is necessary to determine the cause of the bandwidth reduction. PCIE device tilt (poor contact) is one of the causes of bandwidth reduction. In the PCIE bus, the presence detection signal line is connected to the presence detection pin of the PCIE device. When the pin is inserted into the slot and working normally, the pin level is pulled low. The presence signal is low, indicating that the device is in place (installed correctly); if the pin is not inserted normally or a fault occurs during operation, the pin level is pulled high. The presence signal is high, indicating that the device is not in place. When detecting whether the device is tilted, the BIOS collects the device's presence signal and transmits it to the BMC (Baseboard Manager Controller) after "wire-AND" on the motherboard side. The BMC determines whether the device is in place. However, when a PCIE device is tilted, some of the in-position signals are low and some are high. In this case, the line-AND result is still low. The BMC determines that the device is installed correctly and does not generate an alarm prompt, so it cannot determine that the device is tilted. In this case, it is necessary to stop business operations, open the server chassis, and re-plug the PCIE device for inspection. The server is in closed mode during operation, the chassis cover is not easy to open, and the PCIE device is not easy to plug in and out. This operation method is cumbersome and inefficient. It is even more difficult for edge servers to operate, consuming a lot of time and cost, and seriously affecting the normal operation of the business.

[0006] Summary of the Invention

[0007] In view of this, the present application aims to propose a PCIE device detection system, method, apparatus and product to achieve rapid detection of whether a PCIE device is tilted.

[0008] To achieve the above objectives, the technical solutions of this application are as follows:

[0009] A first aspect of an embodiment of the present application provides a high-speed serial computer expansion bus device detection system, the system including at least a complex programmable logic device, the complex programmable logic device including:

[0010] A control unit is used to obtain the presence information sent by the high-speed serial computer expansion bus device during a detection cycle; the presence information includes presence signals of all presence detection pins on the high-speed serial computer expansion bus device;

[0011] a parsing unit, configured to obtain all presence signals from the presence information, and determine an actual bandwidth of the high-speed serial computer expansion bus device based on the presence signals;

[0012] The judging unit is used to judge whether the high-speed serial computer expansion bus device is tilted according to the preset bandwidth and the actual bandwidth.

[0013] In some embodiments, the complex programmable logic device further includes a register for storing bit information and a preset bandwidth;

[0014] The parsing unit is further used to determine the specifications of the high-speed serial computer expansion bus device according to the total number of in-position signals of the high-speed serial computer expansion bus device; and store the factory bandwidth corresponding to the specifications of the high-speed serial computer expansion bus device as the preset bandwidth in the register.

[0015] In some embodiments, the parsing unit is specifically configured to perform the following steps:

[0016] Get the number of low-level in-position signals among all in-position signals;

[0017] Calculate the actual bandwidth of a high-speed serial computer expansion bus device based on the number of low-level in-position signals, the total number of in-position signals, and the preset bandwidth.

[0018] In some embodiments, the judgment unit is specifically configured to perform the following steps:

[0019] Compare the actual bandwidth with the preset bandwidth; if the actual bandwidth is less than the preset bandwidth, determine that the high-speed serial computer expansion bus device is in a reduced bandwidth state; when the high-speed serial computer expansion bus device is in the reduced bandwidth state, if the in-position signal has a high level, determine that the high-speed serial computer expansion bus device is tilted.

[0020] In some embodiments, the control unit is configured to receive presence information sent by a high-speed serial computer expansion bus device during a plurality of consecutive detection cycles;

[0021] a parsing unit for determining the actual bandwidth of a high-speed serial computer expansion bus device during each detection cycle;

[0022] The judgment unit is configured to compare the actual bandwidth of the high-speed serial computer expansion bus device with the preset bandwidth in each detection cycle; if the actual bandwidth is less than the preset bandwidth, determine that the high-speed serial computer expansion bus device is in a reduced bandwidth state; and when the duration of the high-speed serial computer expansion bus device in the reduced bandwidth state reaches a first threshold, if the in-position signal is at a high level, determine that the high-speed serial computer expansion bus device is tilted.

[0023] In some embodiments, the control unit is further configured to generate a bandwidth alarm signal when the high-speed serial computer expansion bus device is in a reduced bandwidth state; and to generate a tilt release request signal when the high-speed serial computer expansion bus device is tilted.

[0024] In some embodiments, the complex programmable logic device further includes a fault lighting unit;

[0025] The control unit is further configured to generate a fault lighting signal and send it to the fault lighting unit when the high-speed serial computer expansion bus device is in a reduced bandwidth state;

[0026] The fault lighting unit is used to light an alarm at the corresponding position according to the fault lighting signal.

[0027] In some embodiments, the control unit is further configured to perform the following steps:

[0028] Configure data acquisition instructions, which include: data loading enable signal and clock signal; data acquisition instructions are used to collect in-place information of high-speed serial computer expansion bus devices;

[0029] In one detection cycle, a data acquisition instruction is sent to the high-speed serial computer expansion bus device, and in-position information sent by the high-speed serial computer expansion bus device is received.

[0030] In some embodiments, the high-speed serial computer expansion bus device detection system further includes a baseboard management controller;

[0031] The control unit is further configured to store the bandwidth warning signal and the tilt release request signal in a register;

[0032] The baseboard management controller is used to read the bandwidth alarm signal and the tilt release request signal from the register and generate an alarm prompt.

[0033] In some embodiments, the baseboard management controller is further configured to read the bandwidth alarm signal, the tilt release request signal, and all in-place signals corresponding to the current detection cycle from the register, and record a high-speed serial computer expansion bus fault log.

[0034] According to a second aspect of an embodiment of the present application, a high-speed serial computer expansion bus device detection method is provided. The method is applied to the high-speed serial computer expansion bus device detection system provided in the first aspect of the embodiment of the present application. The method includes:

[0035] Collecting the presence information of the high-speed serial computer expansion bus device; the presence information includes the presence signals of all the presence detection pins of the high-speed serial computer expansion bus device;

[0036] Obtaining all in-position signals from the in-position information, and determining an actual bandwidth of the high-speed serial computer expansion bus device based on the in-position signals;

[0037] Determine whether a high-speed serial computer expansion bus device is tilted based on the preset bandwidth and the actual bandwidth.

[0038] In some embodiments, the high-speed serial computer expansion bus device detection method further includes:

[0039] Determine the specifications of the high-speed serial computer expansion bus device according to the total number of in-position signals of the high-speed serial computer expansion bus device;

[0040] Obtain the corresponding factory bandwidth according to the specifications of the high-speed serial computer expansion bus device, and use the factory bandwidth as the preset bandwidth.

[0041] In some embodiments, determining an actual bandwidth of a high-speed serial computer expansion bus device based on a presence signal includes:

[0042] Get the number of low-level in-position signals among all in-position signals;

[0043] Calculate the actual bandwidth of a high-speed serial computer expansion bus device based on the number of low-level in-position signals, the total number of in-position signals, and the preset bandwidth.

[0044] In some embodiments, determining whether a high-speed serial computer expansion bus device is tilted based on a preset bandwidth and an actual bandwidth includes:

[0045] Compare the actual bandwidth with the preset bandwidth;

[0046] If the actual bandwidth is less than the preset bandwidth, it is determined that the high-speed serial computer expansion bus device is in a reduced bandwidth state;

[0047] When the high-speed serial computer expansion bus device is in a bandwidth reduction state, if the presence signal has a high level, it is determined that the high-speed serial computer expansion bus device is tilted.

[0048] In some embodiments, determining whether a high-speed serial computer expansion bus device is tilted based on a preset bandwidth and an actual bandwidth includes:

[0049] Obtaining the actual bandwidth of a high-speed serial computer expansion bus device over multiple consecutive detection cycles;

[0050] Compare the actual bandwidth with the preset bandwidth in each detection cycle;

[0051] If the actual bandwidth is less than the preset bandwidth, the high-speed serial computer expansion bus device is determined to be in a reduced bandwidth state:

[0052] When the duration of the high-speed serial computer expansion bus device being in the bandwidth reduction state reaches a first threshold, if the presence signal is at a high level, it is determined that the high-speed serial computer expansion bus device is tilted.

[0053] In some embodiments, the high-speed serial computer expansion bus device detection method further includes:

[0054] When it is determined that the high-speed serial computer expansion bus device is in a reduced bandwidth state, a bandwidth alarm signal is generated;

[0055] When the high-speed serial computer expansion bus device is tilted, a de-tilt request signal is generated;

[0056] An alarm prompt is generated based on the bandwidth alarm signal and the tilt release request signal.

[0057] In some embodiments, the high-speed serial computer expansion bus device detection method further includes:

[0058] When it is determined that the high-speed serial computer expansion bus device is in a reduced bandwidth state, a fault lighting signal is generated;

[0059] According to the fault lighting signal, the corresponding position lights up and gives an alarm.

[0060] In some embodiments, obtaining the total number of presence signals of a high-speed serial computer expansion bus device includes:

[0061] Configure data acquisition instructions, which include: data loading enable signal and clock signal; data acquisition instructions are used to collect in-place information of high-speed serial computer expansion bus devices;

[0062] In a detection cycle, a data acquisition instruction is sent to the high-speed serial computer expansion bus device, and in-position information sent by the high-speed serial computer expansion bus device in the detection cycle is received; the in-position information includes in-position signals of all in-position detection pins on the high-speed serial computer expansion bus device;

[0063] Determine the total number of presence signals of high-speed serial computer expansion bus devices based on the presence information.

[0064] In some embodiments, the high-speed serial computer expansion bus device detection method further includes:

[0065] Record the high-speed serial computer expansion bus fault log according to the bandwidth alarm signal, tilt release request signal and all in-place signals corresponding to the current detection cycle.

[0066] According to a third aspect of an embodiment of the present application, a high-speed serial computer expansion bus device detection device is provided, which is used to implement the high-speed serial computer expansion bus device detection method provided in the second aspect of the embodiment of the present application, and the device includes:

[0067] The signal acquisition module is configured to acquire in-position information of a high-speed serial computer expansion bus device; the in-position information includes in-position signals of all in-position detection pins of the high-speed serial computer expansion bus device;

[0068] a bandwidth acquisition module configured to acquire all presence signals from the presence information and determine an actual bandwidth of the high-speed serial computer expansion bus device based on the presence signals;

[0069] The judgment module is configured to judge whether the high-speed serial computer expansion bus device is tilted according to the preset bandwidth and the actual bandwidth.

[0070] According to a fourth aspect of an embodiment of the present application, a computer non-volatile readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the high-speed serial computer expansion bus device detection method of the second aspect of the embodiment of the present application are implemented.

[0071] According to a fifth aspect of an embodiment of the present application, an electronic device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps in the high-speed serial computer expansion bus device detection method according to the second aspect of an embodiment of the present application are implemented.

[0072] The high-speed serial computer expansion bus device detection system provided by the present application actively collects the in-place information of the PCIE device through the CPLD (Complex Programmable Logic Device), determines the current actual bandwidth of the PCIE device based on all in-place signals, and compares the preset bandwidth of the PCIE device with the actual bandwidth to determine whether the device has a bandwidth reduction problem and whether the PCIE device is tilted. Compared with the traditional bandwidth reduction fault detection method, the present application can quickly and accurately determine whether the device is tilted when the device has a bandwidth reduction problem without removing the server box cover and re-inserting the PCIE device, greatly improving the troubleshooting efficiency, saving repair time, and reducing the maintenance cost of the equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0074] FIG1 is a schematic diagram of a high-speed serial computer expansion bus (PCIE) device detection system proposed in one embodiment of the present application;

[0075] FIG2 is a schematic diagram of the hardware architecture of a PCIE device detection system proposed in one embodiment of the present application;

[0076] FIG3 is a flow chart of a PCIE device detection method proposed in one embodiment of the present application;

[0077] FIG4 is a flow chart of detecting whether a PCIE device is tilted in one embodiment of the present application;

[0078] FIG5 is a schematic diagram of a PCIE device detection apparatus proposed in an embodiment of the present application;

[0079] FIG6 is a schematic structural diagram of an electronic device proposed in an embodiment of the present application. DETAILED DESCRIPTION

[0080] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0081] It should be understood that references throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic associated with the embodiment is included in at least one embodiment of the present application. Therefore, the appearances of "in one embodiment" or "in an embodiment" throughout this specification do not necessarily refer to the same embodiment. Furthermore, these particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0082] In the various embodiments of the present application, it should be understood that the size of the serial numbers of the following processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0083] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0084] It should be noted that, unless there is any conflict, the embodiments and features in the embodiments of this application can be combined with each other.

[0085] In the traditional BIOS bandwidth reduction detection method, the motherboard BIOS polls the PCIE device via the I2C bus master arbiter of the two-channel PCA9641. During the connection between the CPU and the PCIE device, it obtains the actual available bandwidth of the PCIE device. The operator then queries the PCIE device's factory theoretical bandwidth based on the model and specifications. This theoretical bandwidth is then compared with the actual bandwidth read by the BIOS. If the two do not match, the device is considered to have bandwidth reduction. However, bandwidth reduction can occur for a variety of reasons, with poor device contact being a common cause. This can manifest as device tilt or foreign objects in the slot. Device tilt causes one end of the presence signal to contact the pin, pulling it low. The other end, due to tilt, does not contact the slot pin, pulling the signal high. Ultimately, the line AND result of the presence signal is low. The BMC reads the line AND result of all the presence signals. In other words, if the device is tilted, the BMC will determine that the device is properly seated. Therefore, with traditional detection methods, eliminating device tilt requires reseating and unplugging the device, resulting in a massive troubleshooting effort and a waste of time.

[0086] The PCIE device detection system disclosed in the present application directly reads the PCIE presence signal through the register of the CPLD and uses a self-judgment mechanism to determine whether the device is tilted. There is no need to detect through the BIOS, and the BMC does not need to obtain the line and resources of the presence signal. This saves the link resources for the interaction between the BIOS and BMC and the slot, while reducing the number of traces on the PCB and the use of logic and gate chips, thereby reducing hardware costs.

[0087] The present application will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0088] FIG1 is a schematic diagram of a high-speed serial computer expansion bus (PCIE) device detection system 100 proposed in an embodiment of the present application. As shown in FIG1 , the system 100 includes at least a CPLD; the CPLD includes:

[0089] The control unit 101 is configured to obtain the presence information sent by the PCIE device during a detection period; the presence information includes presence signals of all presence detection pins on the PCIE device;

[0090] The parsing unit 102 is configured to obtain all presence signals from the presence information and determine the actual bandwidth of the PCIE device based on the presence signals;

[0091] The judging unit 103 is configured to judge whether the PCIE device is tilted according to the preset bandwidth and the actual bandwidth.

[0092] In this embodiment, the PCIE device detection system actively obtains the PCIE device's internal presence signal data through the CPLD. Based on the presence signal, it determines the PCIE device's current actual bandwidth. Then, based on the actual bandwidth data and the preset bandwidth, it determines whether the PCIE device is tilted. Leveraging the CPLD's parallel data processing capabilities, the system integrates the PCIE device's actual bandwidth and preset bandwidth data for comparison, then uses a self-determination mechanism to determine whether the device is tilted. Compared to traditional BIOS power-on self-test detection methods, this system can more quickly and accurately determine whether a PCIE device is tilted.

[0093] As an implementation method of the present application, the CPLD further includes a register for storing in-place information and a preset bandwidth;

[0094] The parsing unit is further configured to determine the specifications of the PCIE device according to the total number of in-place signals of the PCIE device; and store the factory bandwidth corresponding to the specifications of the PCIE device as the preset bandwidth in the register.

[0095] In one embodiment, the parsing unit obtains a presence signal from the presence information and determines the specifications of the PCIE device based on the number of presence signals. Due to the diversification of server products, more and more PCIE types are supported. Taking PCIE network cards as an example, they include NIC, HCA, HBA, CAN and other types. Common PCIE network cards mainly have specifications such as PCIE X1, PCIE X2, PCIE X4, PCIE X8, and PCIE X16. The specifications of different PCIE network cards correspond to different numbers of channels and bandwidth support. For example, an X8-specification PCIE network card has 4 presence signals, and the bandwidth corresponding to the X8-specification PCIE network card is 3814.72MB / s. In this embodiment, the parsing unit can determine the specifications of the PCIE device (for example, X8) based on the total number of presence signals (for example, a total of 4), and then obtain the factory bandwidth of the device, and store the factory bandwidth as the preset bandwidth in the register.

[0096] In some embodiments, in one embodiment, in order to improve detection efficiency, the total number of in-place signals and the corresponding factory bandwidth data can be pre-determined and a bandwidth query table can be constructed based on the model of the PCIE device used in the server. The parsing unit obtains the total number of in-place signals from the in-place information, searches for the corresponding bandwidth data in the bandwidth query table based on the total number of in-place signals, and stores it in the register as preset bandwidth data.

[0097] As an implementation manner of the present application, the parsing unit is specifically configured to perform the following steps:

[0098] Get the number of low-level in-position signals among all in-position signals;

[0099] The actual bandwidth of the PCIE device is calculated based on the number of low-level in-position signals, the total number of in-position signals, and the preset bandwidth.

[0100] In this embodiment, the CPLD obtains the level information of the in-place signal of the PCIE device through polling, and calculates the actual bandwidth based on the high and low levels. A low level of the in-place signal indicates that the in-place detection pin corresponding to the in-place signal can operate normally, and a high level of the in-place signal indicates that the in-place detection pin corresponding to the in-place signal has a fault and is not operating normally. In the in-place signal of the PCIE device, the number of low-level in-place signals has a certain proportional relationship with the actual bandwidth of the PCIE device, and the number of high-level in-place signals has a proportional relationship with the size of the lost bandwidth. Therefore, by determining the number of low-level in-place signals in the current in-place signal of the PCIE device, combined with the total number of in-place signals and the preset bandwidth of the device, the current actual bandwidth of the PCIE device can be calculated.

[0101] Specifically, the actual bandwidth of a PCIE device can be calculated using the following expression:

[0102] Actual bandwidth = number of low-level active signals ÷ total number of active signals × theoretical bandwidth.

[0103] For example, when testing an X8 PCIE device, a total of four in-place signals are obtained, of which three are low-level and one is high-level. At this time, based on the factory bandwidth value of 3814.72 MB / s of the X8 device, the actual bandwidth of the current device can be calculated as: 3 ÷ 4 × 3814.72 = 2861.04 MB / s.

[0104] In this embodiment, after calculating the current actual bandwidth of the device, the parsing unit stores the actual bandwidth data in a register for easy reading.

[0105] As an implementation manner of the present application, the judgment unit is specifically configured to perform the following steps:

[0106] Compare the actual bandwidth with the preset bandwidth; if the actual bandwidth is less than the preset bandwidth, determine that the PCIE device is in a reduced bandwidth state; when the PCIE device is in the reduced bandwidth state, if the in-position signal has a high level, determine that the PCIE device is tilted.

[0107] In this embodiment, the CPLD's characteristic of parallel data processing is utilized, and a judgment unit reads the preset bandwidth data and the current actual bandwidth data of the PCIE device from a register. The two bandwidth data are then compared to determine whether the PCIE device has a bandwidth reduction problem. If the current actual bandwidth is less than the preset bandwidth, the device is determined to be in a bandwidth reduction state. At this time, if there is a high level in the in-bit signal, it can be determined that the bandwidth reduction problem is caused by device tilt. In this embodiment, the advantages of parallel processing of the internal modules of the CPLD are utilized to achieve a rapid comparison of the preset bandwidth and the actual bandwidth and the determination of device tilt.

[0108] As an implementation manner of the present application, the control unit is configured to receive presence information sent by the PCIE device within a plurality of consecutive detection cycles;

[0109] A parsing unit, used to determine the actual bandwidth of the PCIE device in each detection cycle;

[0110] The judgment unit is used to compare the actual bandwidth of the PCIE device with the preset bandwidth in each detection cycle; if the actual bandwidth is less than the preset bandwidth, it is determined that the PCIE device is in a reduced bandwidth state; when the length of time the PCIE device is in the reduced bandwidth state reaches a first threshold, if the in-place signal is at a high level, it is determined that the PCIE device is tilted.

[0111] In one embodiment, a PCIE device is subjected to multiple rounds of continuous testing. During each testing cycle, a device presence signal is obtained from the presence information. The actual bandwidth within the testing cycle is calculated based on the high and low levels of the presence signal, the total number of presence signals, and the preset bandwidth. The actual bandwidth obtained from these multiple rounds of testing is compared with the preset bandwidth. If the duration or number of cycles during which the PCIE device is in a reduced bandwidth state reaches a certain threshold, the device is determined to have a reduced bandwidth problem. In this case, the presence signal level is combined with the judgment. If the presence signal is high, it can be determined that the bandwidth reduction problem is caused by device tilt.

[0112] In some embodiments, in this embodiment, the first threshold value may be set accordingly according to actual application conditions, for example, it may be set according to the number of cycles or according to seconds.

[0113] In this embodiment, whether the device has reduced bandwidth is determined within multiple consecutive detection cycles, thereby further determining whether the device has tilted. The determination is made after the device maintains the reduced bandwidth state for a certain period of time, ensuring that misjudgments and frequent alarms are not caused by bandwidth fluctuations in a very short period of time.

[0114] As an implementation manner of the present application, the control unit is further configured to generate a bandwidth alarm signal when the PCIE device is in a bandwidth reduction state; and generate a tilt release request signal when the PCIE device is tilted.

[0115] In one embodiment, when it is determined that the PCIE device is in a reduced bandwidth state, the control unit generates a bandwidth alarm signal, and when it is determined that the device is in a tilted state, a tilt release request signal is generated. The generated bandwidth reduction alarm signal and tilt release request signal are stored in a register for reading. The contents contained in the bandwidth alarm signal and the tilt release request signal can be set according to actual needs. For example, the bandwidth alarm signal may include the server ID of the device where the bandwidth reduction problem occurs, the location of the slot where the device is located, etc.; the tilt release request may include the device ID where the tilt occurs, the device model, the device specifications, the in-place detection pin where the tilt occurs, and the location of the slot where the device is located. By generating the bandwidth alarm signal and the tilt release request signal, the management personnel can be notified in time to handle the fault.

[0116] As an implementation method of the present application, the CPLD further includes a fault lighting unit;

[0117] The control unit is further configured to generate a fault lighting signal and send it to the fault lighting unit when the PCIE device is in a reduced bandwidth state;

[0118] The fault lighting unit is used to light an alarm at the corresponding position according to the fault lighting signal.

[0119] In one embodiment, to more intuitively warn of device tilt, the system also includes a fault lighting unit. Based on the bandwidth alarm signal, the fault lighting unit issues an alarm to the presence detection pin corresponding to the high-level presence signal experiencing poor contact. In some embodiments, a warning light can be provided on the server to illuminate a bandwidth reduction warning.

[0120] In one embodiment, multiple warning lights can be provided, one for each of warning of bandwidth reduction and prompting a request to release the tilt. In this embodiment, the fault lighting unit illuminates the device experiencing bandwidth reduction to provide a warning, thereby more intuitively indicating the fault type and location, making it easier for management personnel to perform equipment maintenance and troubleshooting, and improving processing efficiency.

[0121] As an embodiment of the present application, the control unit is further configured to perform the following steps:

[0122] Configure data acquisition instructions, which include: data loading enable signal and clock signal; data acquisition instructions are used to collect the in-place information of PCIE devices;

[0123] In a detection cycle, a data collection instruction is sent to the PCIE device, and presence information sent by the PCIE device is received.

[0124] In this embodiment, a custom data acquisition instruction is used to enable the CPLD to act as a master driver to collect presence information from the PCIE device. The data acquisition instruction includes a data loading enable signal and a clock signal. The data loading enable signal controls the PCIE device to start sending presence information during the detection cycle, and the clock signal controls the frequency at which the PCIE device sends data.

[0125] In this embodiment, a data transmission signal is further defined during the data acquisition process. The PCIE device returns in-place signal data to the CPLD based on the data transmission signal. The in-place signal is represented by high and low levels, and one in-place signal occupies 1 bit.

[0126] In one embodiment, the present application also defines a fault lighting control signal, including an alarm control signal and a positioning signal. The location of the alarm light that needs to be turned on or off is determined by the positioning signal, and the lighting and extinguishing of the alarm light are controlled by the alarm control signal, thereby realizing flexible control of the alarm of the PCIE device.

[0127] As an embodiment of the present application, the PCIE device detection system further includes a baseboard management controller;

[0128] The control unit is further configured to store the bandwidth warning signal and the tilt release request signal in a register;

[0129] The baseboard management controller is used to read the bandwidth alarm signal and the tilt release request signal from the register and generate an alarm prompt.

[0130] In one embodiment, the PCIE device detection system also includes a BMC (Baseboard Manager Controller), which implements remote monitoring and alarm prompts for PCIE device detection. In this embodiment, the CPLD stores bandwidth alarm signals and de-tilt request signals in registers. The BMC periodically reads the CPLD registers. When the bandwidth alarm signal or de-tilt request signal is read, a corresponding alarm prompt is generated and displayed in the management interface, making it easier for management personnel to quickly locate the problem and perform troubleshooting in a timely manner, saving troubleshooting time and costs, thereby improving troubleshooting efficiency.

[0131] Based on the alarm prompts, managers can easily monitor equipment failures remotely. When bandwidth reduction problems occur, alarm prompts can quickly obtain relevant information about the faulty equipment, improving the efficiency of troubleshooting.

[0132] Figure 2 is a schematic diagram of the hardware architecture of a PCIE device detection system proposed in one embodiment of the present application. As shown in Figure 2, the PCIE device detection system includes a CPLD and a BMC. The CPLD controls data acquisition via a data loading enable signal LD_N and a clock signal CLK. The PCIE network card sends presence information to the CPLD via a data transmission signal DATA_IN. The CPLD uses an internal module to retrieve all presence signals in the presence information and, based on these signals, determines the device's preset bandwidth and current actual bandwidth, thereby determining whether the device has experienced bandwidth reduction. When bandwidth reduction occurs, the generated bandwidth alarm signal and de-tilt request signal are stored in a register. The BMC reads and interprets these signals from the register via the I2C bus, generating an alarm prompt to promptly alert management personnel to de-tilt the PCIE device and restore normal operation. When bandwidth reduction occurs, the alarm light is illuminated via a fault lighting control signal. Specifically, the fault is located via the SCL / SDA signals, and then the ALERT signal is used to control the alarm light. The SCL / SDA location signal can be configured according to actual needs. For example, the SCL signal can be configured as a positioning signal when the warning light is on, and the SDA signal can be configured as a positioning signal when the warning light is off.

[0133] In this application, the CPLD actively collects the internal in-place signal data of the PCIE device through a custom data acquisition signal and a data transmission signal, generates register data of the preset bandwidth and real-time bandwidth of the device during the detection period for the BMC to read through the I2C bus and record the fault log. When determining whether bandwidth reduction occurs and whether device tilt occurs, the advantage of the CPLD's ability to process data in parallel is utilized to integrate two sets of bandwidth data (preset bandwidth data and actual bandwidth data) for comparison. The judgment result is obtained based on the CPLD's self-judgment mechanism, and a bandwidth alarm signal, a tilt release request signal, and a fault light signal are generated to trigger the alarm light at the corresponding position of the in-place signal, more intuitively displaying the position of the high-level in-place signal where the fault occurs.

[0134] Since information is directly exchanged between the BMC and the CPLD in this embodiment, there is no need to transmit the line-AND result of the in-position signal to the BMC for judgment through the BIOS, which reduces the number of PCB traces and the use of logic AND gate chips in the traditional method, thereby reducing hardware costs.

[0135] As an implementation mode of the present application, the baseboard management controller is further configured to read the bandwidth alarm signal, the tilt release request signal and all in-place signals corresponding to the currently detected cycle from the register, and record the PCIE fault log.

[0136] In one embodiment, the parsing unit is further used to store the in-place signal in the register of the CPLD, and the BMC obtains the in-place signal of each in-place detection pin in the PCIE device by reading the register, thereby knowing the working status of each in-place detection pin, and obtaining the in-place signal (high and low levels) of each pin, thereby accurately knowing the working condition of each in-place detection pin. When the in-place signal is high, it indicates that the in-place detection pin corresponding to the in-place signal has poor contact. The BMC records the PCIE fault log according to the working condition of the in-place detection pin corresponding to each in-place signal. As shown in Figure 2, PCIE_PSNT_N is an example of the in-place signal of the PCIE device. In this application, the parsing unit stores all in-place signals in the register during the detection cycle, and the BMC reads the in-place signal in the register through the I2C bus to obtain the working status of each in-place detection pin.

[0137] In this embodiment, the BMC reads the in-place signal, bandwidth alarm signal, and tilt release request signal, and records the tilt log of the PCIE device based on the read signals, thereby realizing remote fault monitoring and historical fault recording of the PCIE device. The management personnel can check through the log whether the bandwidth reduction problem is caused by device tilt. By checking the historical log, the management personnel can conveniently evaluate the operation status of the PCIE device.

[0138] Compared with the traditional line and method, the in-situ signal data that can be read in this application can obtain more accurate and specific in-situ information. Management personnel can directly determine the equipment tilt fault remotely through the BMC interface, and can also intuitively locate the specific fault location through the fault alarm light at a specific point, which increases the flexibility and practicality of PCIE device management and improves the efficiency of handling equipment bandwidth reduction problems.

[0139] Based on the same inventive concept, an embodiment of the present application provides a PCIE device detection method. Referring to FIG3 , FIG3 is a flow chart of the PCIE device detection method proposed in an embodiment of the present application. As shown in FIG3 , the method includes:

[0140] S21: collecting presence information of a high-speed serial computer expansion bus (PCIE) device; the presence information includes presence signals of all presence detection pins of the high-speed serial computer expansion bus device;

[0141] S22: Obtain all in-position signals from the in-position information, and determine an actual bandwidth of the high-speed serial computer expansion bus device based on the in-position signals;

[0142] S23: Determine whether the high-speed serial computer expansion bus device is tilted according to the preset bandwidth and the actual bandwidth.

[0143] As an embodiment of the present application, the PCIE device detection method further includes:

[0144] Determine the specifications of the PCIE device based on the total number of in-position signals of the PCIE device;

[0145] Obtain the corresponding factory bandwidth according to the specifications of the PCIE device and use the factory bandwidth as the preset bandwidth.

[0146] As an embodiment of the present application, determining the actual bandwidth of the PCIE device based on the presence signal includes:

[0147] Get the number of low-level in-position signals among all in-position signals;

[0148] The actual bandwidth of the PCIE device is calculated based on the number of low-level in-position signals, the total number of in-position signals, and the preset bandwidth.

[0149] As an implementation manner of the present application, judging whether a PCIE device is tilted according to a preset bandwidth and an actual bandwidth includes:

[0150] Compare the actual bandwidth with the preset bandwidth;

[0151] If the actual bandwidth is less than the preset bandwidth, the PCIE device is determined to be in a reduced bandwidth state;

[0152] When the PCIE device is in a bandwidth reduction state, if the in-position signal is at a high level, it is determined that the PCIE device is tilted.

[0153] As an implementation manner of the present application, judging whether a PCIE device is tilted according to a preset bandwidth and an actual bandwidth includes:

[0154] Obtain the actual bandwidth of the PCIE device in multiple consecutive detection cycles;

[0155] Compare the actual bandwidth with the preset bandwidth in each detection cycle;

[0156] If the actual bandwidth is less than the preset bandwidth, the PCIE device is determined to be in a reduced bandwidth state:

[0157] When the duration of the PCIE device being in the bandwidth reduction state reaches a first threshold, if the presence signal is at a high level, it is determined that the PCIE device is tilted.

[0158] As an embodiment of the present application, the PCIE device detection method further includes:

[0159] When it is determined that the PCIE device is in a bandwidth reduction state, a bandwidth alarm signal is generated;

[0160] When the PCIE device is tilted, a tilt release request signal is generated;

[0161] An alarm prompt is generated based on the bandwidth alarm signal and the tilt release request signal.

[0162] As an embodiment of the present application, the PCIE device detection method further includes:

[0163] When it is determined that the PCIE device is in a reduced bandwidth state, a fault light signal is generated;

[0164] According to the fault lighting signal, the corresponding position lights up and gives an alarm.

[0165] As an implementation manner of the present application, obtaining the total number of in-position signals of a PCIE device includes:

[0166] Configure data acquisition instructions, which include: data loading enable signal and clock signal; data acquisition instructions are used to collect the in-place information of PCIE devices;

[0167] In a detection cycle, a data collection instruction is sent to the PCIE device, and the presence information sent by the PCIE device in the detection cycle is received; the presence information includes the presence signals of all the presence detection pins on the PCIE device;

[0168] Determine the total number of presence signals of the PCIE device based on the presence information.

[0169] As an embodiment of the present application, the PCIE device detection method further includes:

[0170] Record the PCIE fault log according to the bandwidth alarm signal, tilt release request signal and all in-place signals corresponding to the current detection cycle.

[0171] Figure 4 is a flow chart of detecting whether a PCIE device is tilted in one embodiment of the present application. As shown in Figure 4, this embodiment implements tilt detection and remote monitoring of PCIE devices based on CPLD and BMC. The specific steps are as follows:

[0172] (1) In the initial state, the data loading enable signal LD_N is at a high level and the clock signal CLK is at a low level. Set the clock period T.

[0173] (2) The CPLD begins collecting in-place information data by pulling LD_N low, generating a low pulse with a pulse width of T, and then pulling it high, triggering the PCIE device to load the latest in-place status information. While LD_N is pulled low, the CLK signal remains low. Taking an X8 PCIE device as an example, an X8 device has four in-place signals, as shown in Table 1 below. When in-place signals 0, 1, and 2 are all low, in-place signal 3 is high.

[0174] (3) After T / 2, the CPLD pulls up CLK to generate a rising edge. The PCIE device sends the total number of internal in-place signals and the status data of all in-place signals to the DATA_IN signal on the rising edge of CLK. After T / 2, the CPLD pulls down CLK to generate a falling edge. At this time, the data sent by the PCIE device to the DATA_IN signal has stabilized. The CPLD collects the data on the DATA_IN signal line as 1 bit data in a frame. The data collection operation is repeated according to the clock CLK cycle to obtain all the in-place information of the PCIE device. The results are shown in Table 1 below. In Table 1, Bit0 to Bit3 are the four in-place signals collected in one detection cycle, corresponding to the in-place signals PRSNTB0_N to PRSNTB3_N of the PCIE device, respectively. Bit4 is the wake-up signal of the CPLD.

[0175] Table 1

[0176] (4) After the PCIE device sends the in-place signal, the CPLD regenerates the LD_N signal low pulse signal while completing the last 1 bit of data acquisition and starts to enter the next detection cycle to collect a new round of in-place information.

[0177] (5) The CPLD compares the total number of in-place signals with the internal register logic and determines the specifications of the PCIE device based on the mapping relationship. Specifically, when the number of in-place signals is 1, the PCIE device bandwidth is mapped to X1; when the number of in-place signals is 2, the PCIE device bandwidth is mapped to X4; when the number of in-place signals is 4, the PCIE device bandwidth is mapped to X8; and when the number of in-place signals is 8, the PCIE device bandwidth is mapped to X16. In actual applications, the device specification information used can be pre-stored in the register, and this application does not impose any restrictions on this. Taking the X8 device as an example, based on the total number of in-place signals collected being 4, it is determined that the bandwidth of this device is X8, that is, 3814.72MB / s. Further, based on the high and low levels of each in-place signal collected by the CPLD, the actual bandwidth is calculated to be 2861.04MB / s. By comparison, this actual bandwidth is less than the factory bandwidth of the X8 device, 3814.72MB / s, and it is determined that the PCIE device has reduced bandwidth.

[0178] (6) The CPLD generates a bandwidth alarm signal based on the bandwidth reduction judgment result, determines that the in-position signal 3 (PRSNTB2_N) is at a high level, determines that the PCIE device has tilted, and generates a tilt release request signal. Based on the bandwidth alarm signal, the lighting module at the position corresponding to the in-position signal 3 is turned on. The CPLD combines the generated signal with the previously collected in-position signal to form a frame of data. As shown in Table 2, in a frame of data, Bits 5 to 7 are the bandwidth alarm signal, the tilt release request signal, and the fault lighting signal, respectively.

[0179] Table 2

[0180] (7) The CPLD stores the generated alarm signal and the tilt release request signal in a register. The BMC reads the CPLD register through the I2C bus and analyzes the signal, records the fault log, generates an alarm prompt, and displays it through the management interface. Through the BMC management interface, the administrator can quickly obtain the alarm information of the PCIE device and take timely action.

[0181] (8) CPLD outputs all in-position signals according to the following logic control and stores them in registers:

[0182] PCIE_PSNT_N=PRSNTB0_N&&PRSNTB31_N&&PRSNTB2_N&&PRSNTB3_N.

[0183] The BMC reads and parses CPLD registers via the I2C bus. This approach is also compatible with the BMC's existing PCIE device presence detection process. The BMC parses and records device bandwidth logs, which administrators can use to monitor PCIE device connectivity.

[0184] Based on the same inventive concept, an embodiment of the present application provides a PCIE device detection device. Referring to FIG5 , FIG5 is a schematic diagram of a PCIE device detection device 500 proposed in an embodiment of the present application. As shown in FIG5 , the device includes:

[0185] The signal acquisition module 501 is configured to collect the presence information of the PCIE device; the presence information includes the presence signals of all the presence detection pins on the PCIE device;

[0186] The bandwidth acquisition module 502 is configured to acquire all presence signals from the presence information and determine the actual bandwidth of the PCIE device based on the presence signals;

[0187] The judgment module 503 is configured to judge whether the PCIE device is tilted according to the preset bandwidth and the actual bandwidth.

[0188] As an embodiment of the present application, the bandwidth acquisition module 502 is further configured to determine the specifications of the PCIE device according to the total number of in-place signals of the PCIE device; obtain the corresponding factory bandwidth according to the specifications of the PCIE device, and use the factory bandwidth as the preset bandwidth.

[0189] As an implementation manner of the present application, the bandwidth acquisition module 502 is configured to perform the following steps:

[0190] Get the number of low-level in-position signals among all in-position signals;

[0191] The actual bandwidth of the PCIE device is calculated based on the number of low-level in-position signals, the total number of in-position signals, and the preset bandwidth.

[0192] As an implementation manner of the present application, the bandwidth acquisition module 502 is configured to perform the following steps:

[0193] Compare the actual bandwidth with the preset bandwidth;

[0194] If the actual bandwidth is less than the preset bandwidth, the PCIE device is determined to be in a reduced bandwidth state;

[0195] When the PCIE device is in a bandwidth reduction state, if the in-position signal is at a high level, it is determined that the PCIE device is tilted.

[0196] As an implementation manner of the present application, the bandwidth acquisition module 502 is further configured to perform the following steps:

[0197] Obtain the actual bandwidth of the PCIE device in multiple consecutive detection cycles;

[0198] Compare the actual bandwidth with the preset bandwidth in each detection cycle;

[0199] If the actual bandwidth is less than the preset bandwidth, the PCIE device is determined to be in a reduced bandwidth state:

[0200] When the duration of the PCIE device being in the bandwidth reduction state reaches a first threshold, if the presence signal is at a high level, it is determined that the PCIE device is tilted.

[0201] As an embodiment of the present application, the PCIE device detection apparatus 500 further includes an output module configured to perform the following steps:

[0202] When it is determined that the PCIE device is in a bandwidth reduction state, a bandwidth alarm signal is generated;

[0203] When the PCIE device is tilted, a tilt release request signal is generated;

[0204] An alarm prompt is generated based on the bandwidth alarm signal and the tilt release request signal.

[0205] As an implementation manner of the present application, the PCIE device detection apparatus 500 further includes an alarm module;

[0206] The output module is further configured to generate a fault lighting signal when it is determined that the PCIE device is in a reduced bandwidth state;

[0207] The alarm module is configured to light up an alarm at a corresponding location according to the fault lighting signal.

[0208] As an embodiment of the present application, the signal acquisition module 501 is further configured to perform the following steps: configuring a data acquisition instruction, the data acquisition instruction including: a data loading enable signal and a clock signal; the data acquisition instruction is used to collect the presence information of the PCIE device; in a detection cycle, sending the data acquisition instruction to the PCIE device and receiving the presence information sent by the PCIE device in the detection cycle; the presence information includes the presence signals of all the presence detection pins on the PCIE device;

[0209] The bandwidth acquisition module 502 is further configured to determine the total number of presence signals of the PCIE device according to the presence information.

[0210] As an embodiment of the present application, the PCIE device detection apparatus 500 further includes a recording module configured to perform the following steps:

[0211] Record the PCIE fault log according to the bandwidth alarm signal, tilt release request signal and all in-place signals corresponding to the current detection cycle.

[0212] Based on the same inventive concept, an embodiment of the present application provides a non-volatile readable storage medium on which a computer program is stored. When the program is executed by a processor, the steps in the PCIE device detection method of any of the above embodiments of the present application are implemented.

[0213] Based on the same inventive concept, an embodiment of the present application provides an electronic device, see Figure 6, the electronic device includes a memory 601, a processor 602 and a computer program stored in the memory and runnable on the processor, and when executed by the processor, the steps in the PCIE device detection method of any of the above embodiments of the present application are implemented.

[0214] Regarding the apparatus in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0215] The above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

[0216] For the sake of simplicity, the method embodiments are described as a series of action combinations. However, those skilled in the art should be aware that this application is not limited by the order of the actions described, because according to this application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all embodiments of this application, and the actions and components involved are not necessarily required by this application.

[0217] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the embodiments of the present application may take the form of a computer program product implemented on one or more computer non-volatile readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program code.

[0218] The present application embodiment is described with reference to the flow chart and / or block diagram of the method, terminal device (system), and computer program product according to the embodiment of the present application. It should be understood that each process and / or box in the flow chart and / or block diagram and the combination of the process and / or box in the flow chart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device produce a device for realizing the function specified in one process or multiple processes and / or one box or multiple boxes of the flow chart.

[0219] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0220] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce computer-implemented processing, so that the instructions executed on the computer or other programmable terminal device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0221] Although the embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic inventive concepts. Therefore, the appended claims are intended to be interpreted as including the embodiments of the present invention and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0222] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0223] The above is a detailed introduction to the PCIE device detection system, method, apparatus and product provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for those skilled in the art, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A high-speed serial computer expansion bus device detection system, characterized in that At least a complex programmable logic device; The complex programmable logic device comprises: A control unit is configured to obtain in-position information sent by a high-speed serial computer expansion bus device during a detection cycle; the in-position information includes in-position signals of all in-position detection pins on the high-speed serial computer expansion bus device; a parsing unit configured to obtain all presence signals from the presence information and determine an actual bandwidth of the high-speed serial computer expansion bus device based on the presence signals; The judging unit is configured to judge whether the high-speed serial computer expansion bus device is tilted according to a preset bandwidth and the actual bandwidth.

2. The high-speed serial computer expansion bus device detection system according to claim 1, wherein The complex programmable logic device further includes a register configured to store the in-place information and the preset bandwidth; The analysis unit is further configured to determine the specification of the high-speed serial computer expansion bus device according to the total number of in-place signals of the high-speed serial computer expansion bus device; and store the factory bandwidth corresponding to the specification of the high-speed serial computer expansion bus device as the preset bandwidth in the register.

3. The high-speed serial computer expansion bus device detection system according to claim 1, characterized in that The parsing unit is specifically configured to perform the following steps: Get the number of low-level in-place signals among all in-place signals; The actual bandwidth of the high-speed serial computer expansion bus device is calculated according to the number of low-level presence signals, the total number of presence signals and the preset bandwidth.

4. The high-speed serial computer expansion bus device detection system according to claim 2, wherein The determining unit is specifically configured to perform the following steps: The actual bandwidth is compared with the preset bandwidth; if the actual bandwidth is less than the preset bandwidth, it is determined that the high-speed serial computer expansion bus device is in a reduced bandwidth state; when the high-speed serial computer expansion bus device is in the reduced bandwidth state, if the in-position signal has a high level, it is determined that the high-speed serial computer expansion bus device is tilted.

5. The high-speed serial computer expansion bus device detection system according to claim 2, wherein The control unit is configured to receive the presence information sent by the high-speed serial computer expansion bus device in a plurality of consecutive detection cycles; The parsing unit is configured to determine the actual bandwidth of the high-speed serial computer expansion bus device in each detection cycle; The judgment unit is configured to compare the actual bandwidth of the high-speed serial computer expansion bus device with the preset bandwidth in each detection cycle; If the actual bandwidth is less than the preset bandwidth, it is determined that the high-speed serial computer expansion bus device is in a reduced bandwidth state. When the duration of the high-speed serial computer expansion bus device in the reduced bandwidth state reaches a first threshold, if the in-place signal has a high level, it is determined that the high-speed serial computer expansion bus device is tilted.

6. The high-speed serial computer expansion bus device detection system according to claim 4 or 5, characterized in that, The control unit is further configured to generate a bandwidth alarm signal when the high-speed serial computer expansion bus device is in a bandwidth reduction state; and to generate a tilt release request signal when the high-speed serial computer expansion bus device is tilted.

7. The high-speed serial computer expansion bus device detection system according to claim 4 or 5, characterized in that The complex programmable logic device also includes a fault lighting unit; The control unit is further configured to generate a fault lighting signal and send it to the fault lighting unit when the high-speed serial computer expansion bus device is in a reduced bandwidth state; The fault lighting unit is configured to light a lamp and give an alarm at a corresponding position according to the fault lighting signal.

8. The high-speed serial computer expansion bus device detection system according to claim 1, wherein The control unit is further configured to perform the following steps: Configure a data acquisition instruction, the data acquisition instruction includes: a data loading enable signal and a clock signal; the data acquisition instruction is configured to collect the in-place information of the high-speed serial computer expansion bus device; In a detection cycle, the data acquisition instruction is sent to the high-speed serial computer expansion bus device, and the presence information sent by the high-speed serial computer expansion bus device is received.

9. The high-speed serial computer expansion bus device detection system according to claim 6, characterized in that Also included is a baseboard management controller; The control unit is further configured to store the bandwidth warning signal and the tilt release request signal in the register; The baseboard management controller is configured to read the bandwidth alarm signal and the tilt release request signal from the register to generate an alarm prompt.

10. The high-speed serial computer expansion bus device detection system according to claim 9, wherein The baseboard management controller is further configured to read the bandwidth alarm signal, the tilt release request signal and all in-place signals corresponding to the current detection cycle from the register, and record a high-speed serial computer expansion bus fault log.

11. A method for detecting a high-speed serial computer expansion bus device, characterized in that A high-speed serial computer expansion bus device detection system applied to any one of claims 1 to 10, comprising: Collecting the in-place information of the high-speed serial computer expansion bus device; the in-place information includes the in-place signals of all in-place detection pins of the high-speed serial computer expansion bus device; Acquire all presence signals from the presence information, and determine the actual bandwidth of the high-speed serial computer expansion bus device based on the presence signals; According to the preset bandwidth and the actual bandwidth, it is determined whether the high-speed serial computer expansion bus device is tilted.

12. The high-speed serial computer expansion bus device detection method according to claim 11, further comprising: Determining the specification of the high-speed serial computer expansion bus device according to the total number of in-place signals of the high-speed serial computer expansion bus device; The corresponding factory bandwidth is obtained according to the specification of the high-speed serial computer expansion bus device, and the factory bandwidth is used as the preset bandwidth.

13. The method for detecting a high-speed serial computer expansion bus device according to claim 11, wherein Determining an actual bandwidth of the high-speed serial computer expansion bus device based on the presence signal includes: Get the number of low-level in-place signals among all in-place signals; The actual bandwidth of the high-speed serial computer expansion bus device is calculated according to the number of low-level presence signals, the total number of presence signals and the preset bandwidth.

14. The method for detecting a high-speed serial computer expansion bus device according to claim 11, wherein According to the preset bandwidth and the actual bandwidth, determining whether the high-speed serial computer expansion bus device is tilted includes: Comparing the actual bandwidth with the preset bandwidth; If the actual bandwidth is less than the preset bandwidth, determining that the high-speed serial computer expansion bus device is in a reduced bandwidth state; When the high-speed serial computer expansion bus device is in a bandwidth reduction state, if the in-place signal has a high level, it is determined that the high-speed serial computer expansion bus device is tilted.

15. The method for detecting a high-speed serial computer expansion bus device according to claim 11, wherein According to the preset bandwidth and the actual bandwidth, determining whether the high-speed serial computer expansion bus device is tilted includes: obtaining an actual bandwidth of the high-speed serial computer expansion bus device during a plurality of consecutive detection cycles; Comparing the actual bandwidth in each detection cycle with the preset bandwidth; If the actual bandwidth is less than the preset bandwidth, it is determined that the high-speed serial computer expansion bus device is in a reduced bandwidth state: When the duration of the high-speed serial computer expansion bus device being in the bandwidth reduction state reaches a first threshold, if the in-place signal is at a high level, it is determined that the high-speed serial computer expansion bus device is tilted.

16. The method for detecting a high-speed serial computer expansion bus device according to claim 14 or 15, characterized in that, Also includes: When it is determined that the high-speed serial computer expansion bus device is in a reduced bandwidth state, generating a bandwidth alarm signal; When the high-speed serial computer expansion bus device is tilted, a de-tilt request signal is generated; A warning prompt is generated based on the bandwidth warning signal and the tilt release request signal.

17. The method for detecting a high-speed serial computer expansion bus device according to claim 14 or 15, characterized in that, Also includes: When it is determined that the high-speed serial computer expansion bus device is in a reduced bandwidth state, generating a fault lighting signal; According to the fault lighting signal, a lighting alarm is performed at the corresponding position.

18. The method for detecting a high-speed serial computer expansion bus device according to claim 11, wherein, Obtaining the total number of in-position signals of the high-speed serial computer expansion bus device, including: Configure a data acquisition instruction, the data acquisition instruction includes: a data loading enable signal and a clock signal; the data acquisition instruction is configured to collect the in-place information of the high-speed serial computer expansion bus device; In a detection cycle, the data acquisition instruction is sent to the high-speed serial computer expansion bus device, and the in-position information sent by the high-speed serial computer expansion bus device in the detection cycle is received; the in-position information includes the in-position signals of all in-position detection pins on the high-speed serial computer expansion bus device; The total number of presence signals of the high-speed serial computer expansion bus device is determined according to the presence information.

19. The method for detecting a high-speed serial computer expansion bus device according to claim 16, wherein Also includes: According to the bandwidth alarm signal, the de-tilt request signal and all in-place signals corresponding to the current detection cycle, the high-speed serial computer expansion bus fault log is recorded.

20. A detection device for a high-speed serial computer expansion bus device, characterized in that, The method is configured to implement any one of claims 11 to 19, including: A signal acquisition module is configured to acquire in-place information of a high-speed serial computer expansion bus device; the in-place information includes in-place signals of all in-place detection pins of the high-speed serial computer expansion bus device; a bandwidth acquisition module, configured to acquire all presence signals from the presence information, and determine an actual bandwidth of the high-speed serial computer expansion bus device based on the presence signals; The judgment module is configured to judge whether the high-speed serial computer expansion bus device is tilted according to the preset bandwidth and the actual bandwidth.

21. A computer non-volatile readable storage medium, on which a computer program is stored, characterized in that, When the computer program is executed by a processor, the steps in the method according to any one of claims 11 to 19 are implemented.

22. An electronic device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, When the processor executes the computer program, the processor implements the steps in the method according to any one of claims 11 to 19.

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