Light detection device

Abstract

The present disclosure relates to a light detection device whereby both improved quantum efficiency and flare suppression can be achieved. The light detection device comprises a pixel array section in which a plurality of pixels are arranged two-dimensionally on a semiconductor substrate. The pixels comprise a photoelectric conversion part formed on the semiconductor substrate to perform photoelectric conversion in response to incident light, a light condensing part that condenses incident light onto the photoelectric conversion unit, and a light guide part formed inside the photoelectric conversion part. The technology of the present disclosure can be applied to, e.g., a light detection device that receives light in the infrared region and generates a signal.

Description

Photodetector

[0001] The present disclosure relates to a photodetector, and more particularly to a photodetector that can achieve both improved quantum efficiency and flare suppression.

[0002] The present applicant has proposed a pixel structure that achieves both improved quantum efficiency (Qe) and flare suppression in Patent Document 1. Patent Document 1 discloses a structure in which incident light collected by an on-chip lens passes through a pinhole and then extends the optical path length of the incident light using a diffraction / scattering structure, and a structure in which reflected or scattered light is confined within the photoelectric conversion unit by an element isolation unit provided at the pixel boundary and a reflecting unit provided on the surface opposite the light-receiving surface of the photoelectric conversion unit. Patent Documents 2 and 3 disclose techniques for forming element isolation units provided at pixel boundary units using crystal anisotropic etching, which utilizes the property that the etching rate varies depending on the plane orientation.

[0003] International Publication No. 2022 / 153583 Japanese Patent Application Laid-Open No. 2020-77650 International Publication No. 2021 / 111818

[0004] Further improvements in pixel structure are needed to achieve both improved quantum efficiency and flare suppression.

[0005] The present disclosure has been made in consideration of such circumstances, and aims to achieve both improved quantum efficiency and flare suppression by guiding incident light into a photoelectric conversion unit and increasing the optical path length.

[0006] A photodetector according to one aspect of the present disclosure includes a pixel array unit in which a plurality of pixels are two-dimensionally arranged on a semiconductor substrate, and each pixel includes: a photoelectric conversion unit formed on the semiconductor substrate that performs photoelectric conversion in response to incident light; a light collecting unit that collects the incident light into the photoelectric conversion unit; and a light guiding unit formed inside the photoelectric conversion unit.

[0007] In one aspect of the present disclosure, a pixel array section is provided on a semiconductor substrate in which a plurality of pixels are arranged two-dimensionally, and each pixel is provided with a photoelectric conversion section formed on the semiconductor substrate that performs photoelectric conversion in response to incident light, a light-collecting section that collects the incident light into the photoelectric conversion section, and a light-guiding section formed inside the photoelectric conversion section.

[0008] The photodetector device may be a stand-alone device or a module that is incorporated into another device.

[0009] 1 is a block diagram showing an example of a configuration of a photodetector according to a first embodiment to which the technology of the present disclosure is applied; FIG. 2 is a diagram showing an example of a circuit configuration of a pixel; FIG. 3 is a cross-sectional view showing a first example of a pixel configuration; FIG. 4 is a plan view taken along the line X-X' of FIG. 3; FIG. 5 is a perspective view of a diffusion section; FIG. 6 is a cross-sectional view showing a modified example of the diffusion section of the pixel according to the first example of configuration; FIG. 7 is a diagram explaining features of a pixel according to the first example of configuration; FIG. 8 is a diagram explaining a method of manufacturing a photodetector having a pixel according to the first example of configuration; FIG. 9 is a diagram explaining a method of manufacturing a photodetector having a pixel according to the first example of configuration; FIG. 10 is a diagram explaining a method of manufacturing a photodetector having a pixel according to the first example of configuration; FIG. 11 is a diagram explaining a method of manufacturing a photodetector having a pixel according to the first example of configuration; FIG. 12 is a diagram explaining a method of manufacturing a photodetector having a pixel according to the first example of configuration; FIG. 13 is a diagram explaining a method of manufacturing a photodetector having a pixel according to the first example of configuration; FIG. 14 is a cross-sectional view showing a second example of configuration of a pixel; FIG. 15 is a diagram explaining a planar layout of a trench section and a diffusion section of the second example of configuration. 35 is a diagram illustrating a planar layout of a trench portion and a diffusion portion in a second configuration example. 36 is a diagram illustrating a planar layout of a trench portion and a diffusion portion in a second configuration example. 37 is a diagram illustrating a planar layout of a trench portion and a diffusion portion in a second configuration example. 38 is a schematic diagram illustrating backbonds in a crystal plane of a silicon substrate. 39 is a cross-sectional view showing a third configuration example of a pixel. 40 is a plan view showing an example of an arrangement of pillars. 41 is a plan view showing an example of an arrangement of pillars according to pixel position. 42 is a cross-sectional view showing an example of a configuration in which a metasurface element and an on-chip lens are combined. 43 is a cross-sectional view showing an example of a configuration in which a metasurface element and an inner lens are combined. 44 is a plan view showing an example of an arrangement of pillars having both a prism function and a lens function. 45 is a cross-sectional view showing a fourth configuration example of a pixel. 46 is a plan view taken along X-X' in FIG. 30. 47 is a perspective view of a diffusion portion. 48 is a cross-sectional view of first and second modified examples of a pixel according to the fourth configuration example. 49 is a cross-sectional view of third and fourth modified examples of a pixel according to the fourth configuration example. 49 is a cross-sectional view of a fifth modified example of a pixel according to the fourth configuration example. 49 is a plan view taken along X-X' in FIG. 45.10 is a cross-sectional view of a sixth modified example of a pixel according to the fourth configuration example. FIG. 11 is a cross-sectional view of a seventh modified example of a pixel according to the fourth configuration example. FIG. 12 is a cross-sectional view of a twelfth modified example of a pixel according to the fourth configuration example. FIG. 13 is a cross-sectional view of a tenth modified example of a pixel according to the fourth configuration example. FIG. 14 is a cross-sectional view of an eleventh modified example of a pixel according to the fourth configuration example. FIG. 15 is a cross-sectional view of an eleventh modified example of a pixel according to the fourth configuration example. FIG. 16 is a cross-sectional view of a twelfth modified example of a pixel according to the fourth configuration example. FIG. 17 is a diagram showing an example of a pixel array in which visible light pixels and non-visible light pixels are mixed. FIG. 18 is a schematic diagram showing an example of the configuration of an image processing system according to a second embodiment to which the technology of the present disclosure is applied. FIG. 19 is a block diagram showing an example of the configuration of a ranging system according to a third embodiment to which the technology of the present disclosure is applied. FIG. 19 is a block diagram showing an example of the general configuration of a vehicle control system. FIG. 19 is an explanatory diagram showing an example of the installation positions of an outside vehicle information detection unit and an imaging unit.

[0010] Hereinafter, modes for carrying out the technology of the present disclosure (hereinafter referred to as embodiments) will be described with reference to the accompanying drawings. The description will be given in the following order: 1. Configuration example of a photodetector 2. First configuration example of a pixel 3. Method for manufacturing a pixel according to the first configuration example 4. Second configuration example of a pixel 5. Third configuration example of a pixel 6. Fourth configuration example of a pixel 7. Modified example of a pixel according to the fourth configuration example 8. Example of a mixed arrangement of visible light pixels and non-visible light pixels 9. Configuration example of an image processing system 10. Configuration example of a ranging system 11. Example of application to a moving object

[0011] In this specification and drawings, identical or similar parts are denoted by identical or similar reference numerals, and redundant explanations are omitted as appropriate. The drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Furthermore, there may be parts in which the dimensional relationships and ratios differ between the drawings.

[0012] Furthermore, the definitions of directions such as up and down in the following description are merely for the convenience of explanation and do not limit the technical idea of ​​the present disclosure. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read, and if it is rotated 180 degrees and observed, up and down are read inverted.

[0013] The technology disclosed herein can be applied to photodetection devices in general that have a pixel array in which pixels are arranged two-dimensionally in a matrix, each pixel detecting incident light, photoelectrically converting the incident light, and outputting a pixel signal. The light detected by the photodetection device may be light in the visible light range, including wavelengths such as R (Red), G (Green), and B (Blue), or light in the non-visible light range, such as infrared light. Alternatively, the light may be light in both the visible and non-visible light ranges. The photodetection device can be used as a solid-state imaging device that generates and outputs an image signal corresponding to the amount of incident light, or as a light receiving device (ranging sensor) in a ranging system that receives infrared light irradiated as active light and measures the distance to a subject using a direct ToF or indirect ToF method.

[0014] 1. Configuration Example of Photodetector> FIG. 1 is a block diagram showing a configuration example of a photodetector according to a first embodiment to which the technology of the present disclosure is applied.

[0015] The photodetector 1 shown in FIG. 1 includes a pixel array section 10, a vertical drive section 20, a column signal processing section 30, and a control section 40.

[0016] The pixel array unit 10 is configured by arranging a plurality of pixels 50 in a two-dimensional array. Each pixel 50 has a photoelectric conversion unit that generates charges in response to incident light (incident light) and generates a pixel signal in response to the incident light. The light that the pixel 50 receives and photoelectrically converts may be visible light or invisible light such as infrared light. Each pixel 50 also has a pixel circuit that generates a pixel signal based on the charges generated by the photoelectric conversion unit. This pixel circuit is controlled by a control signal generated by the vertical drive unit 20.

[0017] Signal lines 11 and 12 are arranged in a grid pattern in the pixel array section 10. The signal lines 11 are signal lines that transmit control signals for pixel circuits in the pixels 50, are arranged for each row of the pixel array section 10, and are wired commonly to the pixels 50 arranged in each row. The signal lines 12 are signal lines that transmit pixel signals generated by the pixel circuits of the pixels 50, are arranged for each column of the pixel array section 10, and are wired commonly to the pixels 50 arranged in each column.

[0018] The vertical drive unit 20 generates control signals that control the pixel circuits of the pixels 50 and transmits them to the pixels 50 via signal lines 11. The column signal processing unit 30 acquires and processes pixel signals generated by the pixels 50 via signal lines 12. The column signal processing unit 30 has, for example, an A / D conversion circuit for each column of pixels 50, and performs A / D conversion processing to convert analog pixel signals generated by the pixels 50 in each row into digital pixel signals. The pixel signals processed by the column signal processing unit 30 are output as signals for the photodetector 1. The control unit 40 controls the entire photodetector 1. The control unit 40 generates control signals that control the vertical drive unit 20 and the column signal processing unit 30, and outputs them to the vertical drive unit 20 and the column signal processing unit 30, thereby controlling the photodetector 1. The control signals generated by the control unit 40 are supplied to the vertical drive unit 20 and the column signal processing unit 30 via signal lines 41 and 42, respectively.

[0019] The photodetector 1 configured as described above has a configuration known as a column AD system, in which A / D conversion circuits are arranged in columns. The wavelength of light that the photodetector 1 targets for photoelectric conversion (hereinafter referred to as the target wavelength) can be any wavelength, such as in the visible light region, the non-visible light region, or both, but in the following, the target wavelength is set to 780 to 1000 nm, and the photodetector 1 receives light in the infrared region (infrared light), generates a signal, and outputs it to the outside of the device.

[0020] <Circuit Configuration of Pixel> FIG. 2 shows an example of the circuit configuration of the pixel 50. As shown in FIG.

[0021] Each pixel 50 includes a photoelectric conversion unit 71, a charge holding unit 72, and MOS transistors 73 to 76. The photoelectric conversion unit 71 is, for example, a photodiode, and performs photoelectric conversion in response to incident light to generate electric charges. The anode of the photodiode serving as the photoelectric conversion unit 71 is grounded, and the cathode of the photodiode is connected to the source of the MOS transistor 73. The drain of the MOS transistor 73 is connected to the source of the MOS transistor 74, the gate of the MOS transistor 75, and one end of the charge holding unit 72. The other end of the charge holding unit 72 is grounded. The drains of the MOS transistors 74 and 75 are commonly connected to a power supply voltage Vdd, and the source of the MOS transistor 75 is connected to the drain of the MOS transistor 76. The source of the MOS transistor 76 is connected to the output signal line OUT. The gates of the MOS transistors 73, 74, and 76 are connected to a transfer signal line TR, a reset signal line RST, and a selection signal line SEL, respectively. The transfer signal line TR, the reset signal line RST, and the selection signal line SEL constitute the signal line 11. The output signal line OUT constitutes the signal line 12. The charge holding portion 72 and the MOS transistors 73 to 76 constitute the pixel circuit described above.

[0022] The MOS transistor 73 is a transfer transistor that transfers charges generated by photoelectric conversion in the photoelectric conversion unit 71 to the charge holding unit 72. The charge transfer in the MOS transistor 73 is controlled by a signal transmitted through a transfer signal line TR. The charge holding unit 72 is a capacitor that holds the charges transferred by the MOS transistor 73. The MOS transistor 75 is an amplification transistor that amplifies a signal based on the charges held in the charge holding unit 72. The MOS transistor 76 is a selection transistor that outputs a signal generated by the MOS transistor 75 as a pixel signal to an output signal line OUT in response to a signal transmitted through a selection signal line SEL. The MOS transistor 74 is a reset transistor that resets the charge holding unit 72 by discharging the charges held in the charge holding unit 72 to the power supply voltage Vdd. This reset by the MOS transistor 74 is controlled by a signal transmitted through a reset signal line RST and is performed before the charge is transferred by the MOS transistor 73. Note that during this reset, the photoelectric conversion unit 71 can also be reset by turning on the MOS transistor 73. In this way, the pixel circuit converts the charges generated by the photoelectric conversion unit 71 into pixel signals and outputs them to the output signal line OUT. The pixel signals output to the output signal line OUT are input to the column signal processing unit 30, and after A / D conversion processing and the like are performed in the column signal processing unit 30, they are output from the input / output terminals (not shown) of the photodetector 1.

[0023] 3 is a cross-sectional view showing a first configuration example of a pixel 50 that can be arranged in the pixel array section 10 of the photodetector 1. Fig. 4 shows a plan view taken along line X-X' in Fig. 3.

[0024] The pixel 50 has a semiconductor substrate (silicon substrate) 101 using, for example, silicon (Si) as a semiconductor, and a wiring layer 102 formed on a first surface of the semiconductor substrate 101. The first surface of the semiconductor substrate 101 on which the wiring layer 102 is formed, which is the lower side in Fig. 3, is the front surface side of the semiconductor substrate 101, and the second surface of the semiconductor substrate 101, which is the upper side in Fig. 3, is the back surface side of the semiconductor substrate 101, which is the light receiving surface (light incident surface) onto which light is incident. Therefore, the photodetector 1 having the pixel 50 is a back-illuminated photodetector in which light is incident from the back surface side of the semiconductor substrate 101.

[0025] On the light-receiving surface side, which is the back side of the semiconductor substrate 101, a substrate surface film 105, an insulating film 106, a light-shielding film portion 107, an on-chip lens (OCL) 110, an anti-reflection film 111, etc. are formed. The substrate surface film 105 is composed of a laminated film of a fixed charge film 103 and an anti-reflection film 104. The light-shielding film portion 107 is composed of a laminated film of a first metal film 108 and a second metal film 109.

[0026] The structure of the pixel 50 will be described in detail below.

[0027] Photoelectric conversion units 71 are formed in the semiconductor substrate 101, and the photoelectric conversion units 71 are separated into individual pixels 50 by element isolation units 135 formed at pixel boundaries. The photoelectric conversion units 71 are formed across the entire thickness of the semiconductor substrate 101. The photoelectric conversion units 71 are configured as pn junction photodiodes (PDs), for example, by forming an n-type semiconductor region, with n-type as the first conductivity type, inside the substrate and forming p-type semiconductor regions, with second conductivity type, facing both the front and back surfaces of the semiconductor substrate 101. In FIG. 3 , the boundaries between the n-type and p-type semiconductor regions of the pn junction are indicated by dashed lines. The p-type semiconductor regions facing both the front and back surfaces of the semiconductor substrate 101 also serve as hole charge accumulation regions for dark current suppression.

[0028] A light guide portion 133, shown surrounded by a dashed line, is formed inside the photoelectric conversion portion 71. The light guide portion 133 guides light collected by the on-chip lens 110 into the inside of the photoelectric conversion portion 71 while suppressing sensitivity loss due to interface reflection. More specifically, the light guide portion 133 includes a trench portion 131 formed by digging in the depth direction from the light-receiving surface side of the semiconductor substrate 101 toward the inside of the photoelectric conversion portion 71, and a diffusion portion 132 provided at the tip of the trench portion 131 in the depth direction. A fixed charge film 103 is formed on the sidewall of the light guide portion 133, and a lens material 110A, which is the material of the on-chip lens 110, is embedded inside the fixed charge film 103. As shown in the plan view of FIG. 4 , the trench portion 131 of the light guide portion 133 is formed approximately in the center of the photoelectric conversion portion 71 and has a planar shape that is approximately the same in the vertical and horizontal directions, such as a rectangular or hole-shaped shape. The end of light guiding section 133 on the light receiving surface side may be formed to have a larger planar area than the deeper side closer to diffusion section 132, so that it has a forward tapered shape in cross section. Forming it into a forward tapered shape makes it easier to embed lens material 110A and has the effect of making it easier to take the condensed light into the inside of light guiding section 133.

[0029] As shown in the perspective view of FIG. 5 , the diffusion portion 132 has a larger planar area than the trench portion 131 and is formed as a three-dimensional polygonal protrusion composed of multiple different planes. The multiple planes constituting the diffusion portion 132 are formed along the crystal plane orientation of the semiconductor substrate 101. Specifically, plane-orientation selective etching is performed on the semiconductor substrate 101, whose surface is the (100) plane of silicon, to expose the (111) plane, which has a lower etching rate, thereby forming the approximately rhombic shape shown in FIG. 5 . As a result, for example, the (111) plane is formed at an inclination angle of 54.7° with respect to the bottom surface of the (100) plane when the semiconductor substrate 101 is dug vertically to form a trench. In other words, the diffusion portion 132 is formed of planes inclined along the plane orientation of the (111) plane of the silicon crystal constituting the semiconductor substrate 101. The shape of the diffusion portion 132 where planes intersect has the effect of localizing the propagated light, and also has the effect of increasing the diffusivity by spreading the light due to the diffraction phenomenon after localization.

[0030] In order to increase the optical path length of the incident light after passing through the light guiding section 133, it is desirable that the depth of the light guiding section 133 be at least shallower than 3 / 4 of the depth of the photoelectric conversion section 71, and it is even more desirable that it be shallower than 2 / 3.

[0031] As shown in FIG. 3 , a void 134 is formed inside the diffusion section 132. The refractive index of the void 134 is lower than that of the lens material 110A embedded in the light guide section 133. The difference in refractive index between the air (refractive index 1) inside the void 134 and the lens material 110A in the light guide section 133 makes light more likely to be scattered. In this case, it is desirable for the void 134 to have a raindrop shape. By forming the void 134 into a raindrop shape, the light guided into the photoelectric conversion section 71 by the light guide section 133 is separated by the raindrop shape, resulting in so-called divergent propagation of light. This reduces the component propagating upward inside the light guide section 133 toward the on-chip lens 110. In other words, this reduces the reflection loss of light passing from the photoelectric conversion section 71 to the light-receiving surface side, thereby suppressing the reflection component of the photodetector 1 that causes flare.

[0032] The corners of the diffusion portion 132 do not need to be formed at sharp angles. For example, the corners may be rounded as shown in FIG. 6 by isotropic wet etching using an acidic mixture of hydrofluoric acid, nitric acid, and acetic acid. FIG. 6 shows a modified example of the diffusion portion 132 of the pixel 50 according to the first configuration example, in which the shape of the diffusion portion 132 is formed in a rounded, approximately spherical shape. By forming the shape of the diffusion portion 132 in a rounded, approximately spherical shape, it is possible to suppress crystal defects and cracks in the semiconductor substrate 101 caused by stress concentration at the corners. In this way, the diffusion portion 132 can have a shape and width different from those of the trench portion 131.

[0033] As shown in the plan view of FIG. 4 , the element isolation region 135 is formed at the pixel boundary between the photoelectric conversion regions 71 of each pixel 50. As shown in the cross-sectional view of FIG. 3 , the element isolation region 135 has a full trench structure penetrating the semiconductor substrate 101 in the thickness direction. A fixed charge film 103 is formed on the sidewall of the full-trench element isolation region 135, and an insulating film 106 such as SiO2 is embedded inside the fixed charge film 103. By forming the fixed charge film 103 on the sidewall, pinning is strengthened by negative fixed charges against damage caused by trench processing, thereby suppressing deterioration of dark characteristics. The element isolation region 135 can effectively suppress crosstalk from light scattered in various directions by the diffusion region 132. The element isolation region 135 may also have a configuration in which a metal material such as tungsten, aluminum, silver, or copper is embedded inside the insulating film 106. If necessary, a film of a material such as Ti or TiN that improves adhesion may be deposited to a thickness of several nanometers to several tens of nanometers before depositing these metal films. By embedding a metal material in the element isolation region 135, the shielding effect against optical crosstalk can be further enhanced. The element isolation region 135 may also have a void inside the insulating film 106. In this case, optical crosstalk can be suppressed by interfacial reflection due to the difference in refractive index. Alternatively, the element isolation region 135 may be formed, for example, from a p-type semiconductor region and grounded. In this case, crosstalk due to charge rolling can be suppressed. The element isolation region 135 may be formed using a DTI (Deep Trench Isolation) structure, which is a trench structure extending to a predetermined depth in the semiconductor substrate 101, rather than a full trench structure that penetrates the thickness direction of the semiconductor substrate 101.

[0034] The wiring layer 102 formed on the first surface of the semiconductor substrate 101 includes multiple layers of metal wiring 121 and insulating films (interlayer insulating films) 122 formed therebetween. The metal wiring 121 is formed of, for example, a metal film made of a metal material such as Al, Ag, Au, Cu, Pt, Mo, Cr, Ti, Ni, W, or Fe, or an alloy material containing these metals. The metal wiring 121 in each layer is connected to other metal wiring 121 in the upper and lower layers at predetermined locations by via plugs made of, for example, W or Cu. The insulating films 122 are formed of, for example, a SiO2 film, a low-k film (low-dielectric constant insulating film), or a SiOC film. The wiring layer 102 includes, for example, signal lines transmitting signals applied to pixel circuits, specifically, a transfer signal line TR, a reset signal line RST, a selection signal line SEL, and an output signal line OUT.

[0035] The wiring layer 102 is provided with a reflective layer 123. The reflective layer 123 is provided on the surface opposite the light-receiving surface of the semiconductor substrate 101. It reflects light that attempts to exit toward the wiring layer 102 and confines it within the photoelectric conversion unit 71. The reflective layer 123 is formed with openings in some areas where via plugs connecting the metal wiring 121 of the upper and lower layers and via plugs connected to pixel transistors and diffusion layers formed on the surface of the semiconductor substrate 101 are arranged. The reflective layer 123 may be formed of the same wiring material as the metal wiring 121, or may be formed of a metal film different from that of the metal wiring 121. The reflective layer 123 may be formed with a stacked structure of multiple metal films. The reflective layer 123 may be formed with a multilayer film of dielectrics with different refractive indices. For example, the reflective layer 123 can be formed by alternately stacking low-refractive-index films and high-refractive-index films with a thickness set to selectively reflect light of a target wavelength. A silicon oxide film, for example, is suitable for the low-refractive-index film. For the highly refractive film, for example, silicon nitride (SiN), titanium oxide (TiO2), alumina (Al2O3), tantalum oxide (Ta2O5), amorphous silicon (α-Si), etc. can be used.

[0036] Although not shown, pixel transistors such as MOS transistors 73 to 76 of the pixel circuit are formed on the surface side of the semiconductor substrate 101 on which the wiring layer 102 is formed. The pixel transistors are configured by forming n-type source and drain regions in a p-type semiconductor well region formed on the surface side of the semiconductor substrate 101, and forming a gate electrode on the substrate surface between both regions via a gate insulating film.

[0037] A substrate surface film 105 composed of a stacked film of a fixed charge film 103 and an anti-reflection film 104 is formed on the light-receiving surface side, which is the back side of the semiconductor substrate 101. The fixed charge film 103 has negative fixed charges due to oxygen dipoles and serves to strengthen the pinning of the photoelectric conversion unit 71. The fixed charge film 103 and the anti-reflection film 104 can be composed of, for example, an oxide or nitride containing at least one of hafnium, aluminum, zirconium, thallium, and titanium. They can also be composed of an oxide or nitride containing at least one of lanthanum, cerium, neodymium, promethium, samarium, europium, gadolinium, terbium, dysprosium, holmium, thulium, ytterbium, lutetium, and yttrium. The fixed charge film 103 can also be composed of hafnium oxynitride or aluminum oxynitride. The fixed charge film 103 can also be doped with silicon or nitrogen in an amount that does not impair its insulating properties. This can improve heat resistance, etc. It is desirable that the film thickness of the fixed charge film 103 be controlled in consideration of the wavelength and refractive index, or that the film be multi-layered so that it also serves as an anti-reflection film for the semiconductor substrate 101, which has a high refractive index. The film thicknesses of the fixed charge film 103 and the anti-reflection film 104 are designed to increase the transmittance of light of a target wavelength relative to the refractive index and extinction coefficient of the material.

[0038] The insulating film 106 is provided between the substrate surface film 105 and the light-shielding film portion 107, and suppresses deterioration of dark characteristics. From the viewpoint of anti-reflection, it is preferable that the insulating film 106 has a lower refractive index than the film that constitutes the substrate surface film 105, and for example, SiO2 and composite materials (SiON, SiOC, etc.) containing SiO2 as a main component can be used. On the insulating film 106, the fixed charge film 103 and the lens material 110A are formed.

[0039] The light-shielding film 107 is located between the photoelectric conversion unit 71 and the on-chip lens 110 and has an opening 112 that allows incident light focused by the on-chip lens 110 to pass through. The light-shielding film 107 is disposed on the light-receiving surface side of the semiconductor substrate 101 and blocks stray light from leaking into adjacent pixels 50. The light-shielding film 107 is preferably a multi-layer film having two or more layers, with the bottom layer on the photoelectric conversion unit 71 side being a reflective film and the top layer on the light-incident side being an anti-reflective film. By using a reflective film for the bottom layer of the light-shielding film 107, light reflected by the reflective layer 123 of the wiring layer 102 can be returned to the photoelectric conversion unit 71, contributing to improved sensitivity. Furthermore, by using an anti-reflective film for the top layer of the light-shielding film 107, light reflected by the light-shielding film 107 without passing through the opening 112 can be reduced, thereby suppressing flare and ghosting.

[0040] In the first configuration example shown in FIG. 3 , the light-shielding film portion 107 is composed of a two-layer laminate film consisting of a first metal film 108 and a second metal film 109. The upper first metal film 108, which functions as an anti-reflection film, may be made of a metal material with low reflectivity, such as tungsten (W) or titanium (Ti), or an alloy thereof, or a nitride thereof, an oxide thereof, or a carbide thereof. Alternatively, instead of the first metal film 108, a multilayer film (dielectric multilayer film) designed for anti-reflection, having a laminated structure of dielectrics with different refractive indices, may be used. These films can be formed using, for example, CVD, ALD, sputtering, or the like. Alternatively, an organic film containing an absorbing material, such as carbon black, may be formed on the upper first metal film 108 by spin coating. The lower second metal film 109, which functions as a reflective film, is made of a metal material with high reflectivity, such as aluminum (Al), copper (Cu), gold (Au), silver (Ag), or platinum (Pt), or an alloy thereof. Alternatively, a multilayer film (dielectric multilayer film) designed for reflection with a laminated structure of dielectrics having different refractive indices may be used instead of the second metal film 109. These films can be formed by, for example, CVD, ALD, sputtering, or the like.

[0041] The on-chip lens 110 has a curved lens shape and is a light-condensing unit that focuses incident light onto the photoelectric conversion unit 71. The on-chip lens 110 can be formed of a lens material 110A using an organic material such as a styrene-based resin, an acrylic-based resin, a styrene-acrylic copolymer resin, or a silosane-based resin. The lens material 110A can also be formed of an inorganic material such as silicon nitride (SiN) or silicon oxynitride (SiON). Alternatively, the lens material 110A can be formed of a material with a high refractive index, such as silicon. The silicon can be amorphous silicon (hereinafter referred to as α-Si) or polycrystalline silicon. While α-Si has high absorption for light with wavelengths in the visible light range, it is suitable for light with wavelengths in the infrared range, as its extinction coefficient k is approximately 0 and no absorption occurs. Polycrystalline silicon also has a wavelength range in the infrared range where its extinction coefficient k is approximately 0.01, but its absorption is extremely small, and it can also be used as a lens. Silicon has a refractive index n = 3.5 to 3.8 in the near-infrared region at a wavelength of 940 nm, while SiN and oxide (SiO2) have refractive indices n = 1.82 and n = 1.45, respectively, making silicon's refractive index n much higher. Therefore, using silicon, which has a high refractive index n, for the on-chip lens 110 makes it possible to narrow the beam waist for incident light. An anti-reflection coating 111 is formed on the upper surface, which is the incident side of the on-chip lens 110. The anti-reflection coating 111 is formed to a thickness of approximately λ / (4n) or an integer multiple thereof, where n is the refractive index of the material and λ is the target wavelength. For example, when SiN is used as the material for the anti-reflection coating 111, it is desirable for the anti-reflection coating 111 to have a thickness of approximately 130 nm for a wavelength of 940 nm. The anti-reflection coating 111 may be formed by stacking multiple films with different refractive indices.

[0042] A lens material 110A, which is the material of the on-chip lens 110, is embedded in at least a portion of the light-guiding section 133 formed on the semiconductor substrate 101. By using the same material for the on-chip lens 110 and the interior of the light-guiding section 133, loss due to interface reflection at the semiconductor substrate 101 is eliminated, and light can be efficiently guided inside the photoelectric conversion section 71. A fixed charge film 103 is formed on the sidewall of the light-guiding section 133, and a void 134 is formed inside the lens material 110A of the diffusion section 132. The refractive index of the fixed charge film 103 and the void 134 other than the lens material 110A formed inside the light-guiding section 133 is lower than that of the lens material 110A. Therefore, the light-guiding section 133 includes a portion where the lens material 110A is embedded and a portion with a refractive index lower than that of the lens material 110A. As a result, light is more likely to be scattered due to the difference in refractive index between the lens material 110A in the light-guiding section 133 and the lens material 110A.

[0043] A support substrate (not shown) is bonded to a lower side of the wiring layer 102 by plasma bonding or an adhesive material. The support substrate is made of, for example, a silicon substrate, and reinforces and supports the semiconductor substrate 101 and the like during the manufacturing process of the photodetector 1. Alternatively, a logic substrate made of a semiconductor substrate and a wiring layer on which a logic circuit is formed may be bonded to a lower side of the wiring layer 102 by plasma bonding or an adhesive material. By stacking the semiconductor substrate 101 on which the photoelectric conversion unit 71 is formed and the logic substrate to form the photodetector 1, various peripheral circuits can be stacked vertically, making it possible to reduce the chip size.

[0044] The pixel 50 according to the first configuration example is configured as described above.

[0045] The characteristics of the pixel 50 according to the first configuration example will be described with reference to FIG.

[0046] Incident light is focused by the on-chip lens 110, passes through the light-shielding film 107, and is guided to the light-guiding section 133. The light that enters the light-guiding section 133 is diffused by the diffusion section 132. If the light-guiding section 133 were only the trench section 131, light reflected by the flat surface of the bottom surface of the trench section 131 would propagate upward through the light-guiding section 133, and a considerable amount of light would escape to the outside of the semiconductor substrate 101 (toward the on-chip lens). However, by providing the diffusion section 132 in the shape of a three-dimensional polygon at the tip of the trench section 131 to give it a complex shape, it is possible to suppress upward propagation and suppress light returning to the light-receiving surface side. As described above, organic materials and inorganic materials can be used as materials for the on-chip lens 110. In addition, materials with a high refractive index, such as silicon, such as α-Si, can be used. Although silicon has the disadvantage of high light absorption in the visible light region, its extinction coefficient is 0 in the infrared region, meaning no absorption occurs, making it suitable for target wavelengths in the infrared region. Furthermore, silicon has a high refractive index, making it possible to narrow the beam waist at the focal point, as shown in Figure 7.

[0047] The light guiding unit 133 can guide light into the photoelectric conversion unit 71. Because the lens material 110A of the on-chip lens 110 is embedded inside the light guiding unit 133, there is no difference in refractive index, which suppresses interface reflection that occurs when the semiconductor substrate 101 and its upper surface are made of different materials, thereby enabling improvement in quantum efficiency. Furthermore, suppressing interface reflection can suppress the flare ghost phenomenon.

[0048] Furthermore, the diffusion portion 132 provided in the light guide portion 133 can scatter the light that has passed through the trench portion 131 in various directions, thereby extending the optical path length of the incident light. The longer optical path length of the light can contribute to improving quantum efficiency.

[0049] As shown by the arrows inside the photoelectric conversion unit 71 in FIG. 7 , light scattered by the diffusion unit 132 is reflected by the element isolation unit 135 formed at the pixel boundary and returned to the inside of the photoelectric conversion unit 71. Light that attempts to exit toward the wiring layer 102 side is reflected by the reflective layer 123 and returned to the inside of the photoelectric conversion unit 71. A portion of the light that attempts to exit toward the light-receiving surface side of the semiconductor substrate 101 is reflected by the substrate surface film 105 and returned to the inside of the photoelectric conversion unit 71. A portion of the light that passes through the substrate surface film 105 is reflected at the interface of the lens material 110A and returned to the photoelectric conversion unit 71. Light that passes through the interface of the lens material 110A and hits the light-shielding film unit 107 is either absorbed by the light-shielding film 107 or reflected toward the semiconductor substrate 101.

[0050] In the present embodiment, the light that is incident on pixel 50 and undergoes photoelectric conversion may be visible light or non-visible light such as infrared light. However, if the incident light is, for example, infrared light, the silicon substrate used as semiconductor substrate 101 has a smaller light absorption coefficient per unit thickness as the wavelength becomes longer due to the wavelength dependency of the light absorption coefficient of Si, and the extinction coefficient k for light in the infrared region is approximately 0, so no absorption occurs. As a result, many of the photons of infrared light that are incident on the silicon layer of semiconductor substrate 101 end up transmitting through the silicon layer.

[0051] As described above, the pixel 50 according to the first configuration example has a confinement structure that confines light incident via the light-guiding section 133 within the pixel, using the substrate surface film 105, the light-shielding film section 107, the element isolation section 135, the reflective layer 123, etc., and this can suppress crosstalk, which occurs when light scattered by the diffusion section 132 leaks into adjacent pixels, and sensitivity loss, which occurs when light escapes to the light-receiving surface side. In other words, the incident light can be guided into the photoelectric conversion section 71 and the optical path length can be increased, thereby achieving both improved quantum efficiency and reduced flare.

[0052] 3. Method for Manufacturing Pixel According to First Configuration Example Next, a method for manufacturing the photodetector 1 having the pixel 50 according to the first configuration example will be described with reference to FIGS. 8 to 17. FIG.

[0053] First, as shown in A of Figure 8, a process is carried out in which a photoelectric conversion unit 71 is formed on a semiconductor substrate 101 in units of pixels 50, and a wiring layer 102 in which a logic circuit, etc. is formed is formed on the front surface side of the semiconductor substrate 101.

[0054] Specifically, n-type and p-type semiconductor regions are formed in predetermined regions of each pixel 50 on a semiconductor substrate (silicon substrate) 101, which uses silicon (Si) as a semiconductor, by ion implanting desired impurities from the front surface side of the substrate using a resist as a mask. The n-type semiconductor region is formed inside the substrate relative to the vicinity of the interfaces between the front and back surfaces, while the p-type semiconductor region is formed so as to face both the front and back surfaces of the semiconductor substrate 101. A p-type semiconductor well region is formed in a region near the front surface of the semiconductor substrate 101, and multiple pixel transistors, such as MOS transistors 73-76, are formed within the p-type semiconductor well region. The pixel transistors are composed of source and drain regions, a gate insulating film, and a gate electrode. Furthermore, a wiring layer 102 consisting of multiple layers of metal wiring 121 and insulating films 122 formed between them is formed on the front surface side of the semiconductor substrate 101 on which the multiple pixel transistors are formed. The wiring layer 102 is formed by sequentially stacking insulating films 122 such as silicon oxide films and metal wiring 121 made of aluminum, copper, or the like, and electrically connecting the metal wiring 121 of each layer with via plugs (through vias) or the like as needed. When the metal wiring 121 is formed on the upper surface of the insulating film 122, the upper surface of the insulating film 122 is planarized by CMP (chemical mechanical polishing), and then the metal wiring 121 is formed on the upper surface. After the wiring layer 102 made of multilayered metal wiring 121 is formed, a support substrate is bonded to the surface of the wiring layer 102 opposite the surface facing the semiconductor substrate 101 by plasma bonding or the like, and the substrate is inverted so that the semiconductor substrate 101 faces up. Then, the semiconductor substrate 101 is thinned from the upper (rear) surface of the semiconductor substrate 101 to a desired thickness using, for example, wet etching, dry etching, CMP, or the like. The thickness of the semiconductor substrate 101 varies depending on the target wavelength expected for the incident light. For example, if the target wavelength is only in the visible light region, the thickness of the semiconductor substrate 101 is preferably in the range of 2 to 6 μm, for example. Alternatively, if the target wavelength also includes wavelengths in the near-infrared region, the thickness of the semiconductor substrate 101 is preferably in the range of 3 to 15 μm, for example.

[0055] 8A shows a state after a photoelectric conversion unit 71 is formed for each pixel 50 of the semiconductor substrate 101, a wiring layer 102 is formed on the front surface side of the semiconductor substrate 101, and the semiconductor substrate 101 has been thinned. The crystal plane orientation of the front and back surfaces of the semiconductor substrate 101 is the (1 0 0) plane. In addition, a reflective layer 123 is provided for each pixel 50 in part of the wiring layer 102.

[0056] 8B, a resist 201 patterned on the semiconductor substrate 101 using lithography is used as a mask to perform dry etching such as the Bosch process, thereby forming trenches 202 that penetrate the semiconductor substrate 101 at the pixel boundary. After the trenches 202 are formed, the resist 201 and processing residues are removed by ashing, wet cleaning, or the like.

[0057] Next, as shown in FIG. 9A, a fixed charge film 103, which is part of the substrate surface film 105, is formed on the upper surface of the backside of the semiconductor substrate 101 and inside the trench 202. The fixed charge film 103 can be formed by, for example, CVD, sputtering, or atomic layer deposition (ALD). However, it is preferable to use ALD, which provides good coverage at the atomic layer level. This results in the fixed charge film 103 being formed inside the trench 202 formed in the pixel boundary portion. The fixed charge film 103 is composed of, for example, an oxide or nitride containing at least one of hafnium, aluminum, zirconium, thallium, and titanium.

[0058] Next, as shown in FIG. 9B, an anti-reflection film 104, which is part of the substrate surface film 105, is formed on the upper surface of the fixed charge film 103 on the backside of the semiconductor substrate 101. While the method for forming the anti-reflection film 104 is not particularly limited, sputtering can be used because the anti-reflection film 104 does not need to be embedded inside the trench 202 and only needs to be formed on the upper surface of the backside of the semiconductor substrate 101. Sputtering is advantageous because it shortens the film formation time and, by not forming a film on the sidewalls of the trench 202, allows for a narrower trench width, thereby ensuring a larger photoelectric conversion section 71. The anti-reflection film 104 can be designed to be anti-reflective for the target wavelength of incident light. It can be formed using a material with a refractive index different from that of the fixed charge film 103, with a thickness that cancels out reflections due to interference effects.

[0059] Next, as shown in FIG. 10A, an insulating film 106 is formed on the top surface of the anti-reflection coating 104 on the backside of the semiconductor substrate 101 and inside the trench 202 using a method with good coverage, such as CVD or ALD. The trench 202 may not be entirely filled with the insulating film 106, leaving an air gap. In this case, the difference in refractive index between the insulating film 106 and the air gap in the trench 202 enhances the confinement effect. For example, a SiO2 film can be formed using ALD. However, because a thin SiO2 film is prone to film peeling due to blistering, it is preferable to have a thickness of at least 20 nm, preferably 50 nm or more. Furthermore, the thickness of the insulating film 106 on the top surface of the anti-reflection coating 104 is set thick to take into account the film loss that occurs during the etching process in the step shown in FIG. 12A, described below. In addition to the insulating film 106, a metal material may be filled into the trench 202 using CVD or other methods. Filling the trench 202 with a metal material enhances the shading ability against stray light. Examples of the metal material that can be used for filling include tungsten, aluminum, silver, and copper. To improve adhesion, a film of a high-melting-point material, such as Ti or TiN, may be formed first. When filling with a metal material, the metal material formed on the top surface of the insulating film 106 must be removed by full etch-back, CMP, or the like.

[0060] 10B, the insulating film 106 is dry-etched using a resist 211 patterned on the insulating film 106 by lithography as a mask, and then the semiconductor substrate 101 is dry-etched using a Bosch process or similar method, thereby forming a trench 212 in the center of the pixel, the trench being dug halfway through the semiconductor substrate 101. After the trench 212 is formed, the resist 211 and processing residues are removed by ashing, wet cleaning, or the like. Note that the resist 211 can be formed into a forward tapered shape by shifting the focus position during transfer in the lithography process or by adding a thermal reflow process, thereby processing the insulating film 106 into a forward tapered shape, and the corners on the light-receiving surface side of the semiconductor substrate 101 can also be rounded.

[0061] 11A, a hard mask 213 is formed using a method with good coverage, such as CVD or ALD. The hard mask 213 is preferably a film that has a selectivity with respect to silicon of the semiconductor substrate 101, and for example, a SiN film can be used. The hard mask 213 is formed on the insulating film 106 on the back surface of the substrate and inside the trench 212 (sidewalls and bottom surface).

[0062] Next, as shown in FIG. 11B, the hard mask 213 on the bottom of the trench 212 and on the insulating film 106 on the back surface of the substrate is removed by anisotropic dry etching or the like to etch back the entire surface.

[0063] Next, as shown in FIG. 12A, a three-dimensional polygon 221 conforming to the crystal orientation is formed on the bottom surface of the trench 212 using plane-orientation selective etching. For plane-orientation selective etching, wet etching using a predetermined alkaline solution is employed. The alkaline solution may be an inorganic solution such as KOH, NaOH, or CsOH. The alkaline solution may be an organic solution such as EDP (ethylenediaminepyrocatechol aqueous solution), N2H4 (hydrazine), NH4OH (ammonium hydroxide), or TMAH (tetramethylammonium hydroxide). Plane-orientation selective etching is anisotropic etching in which the etching rate varies depending on the plane orientation of the surface of the semiconductor substrate 101. When the surface of the semiconductor substrate 101 is a (100) plane, a three-dimensional polygon 221 is formed in a roughly diamond shape, as shown in FIG. 5. The sidewalls of the trench 212 are protected by a hard mask 213 and are therefore not etched.

[0064] 12B, the hard mask 213 on the sidewall of the trench 212 is removed. If the hard mask 213 is made of, for example, a SiN film, it can be removed by wet etching using hot phosphoric acid. Note that removing the hard mask 213 and then filling the trench 212 with a necessary material has the advantage that the width of the light guide section 133 can be narrowed and the photoelectric conversion section 71 can be formed large. However, the hard mask 213 on the sidewall of the trench 212 may be left in order to reduce the number of processes.

[0065] 13A, the fixed charge film 103 is formed on the upper surface of the insulating film 106 and on the side walls of the trench 212 and the three-dimensional polygon 221 by using CVD, sputtering, ALD, etc. As in the process described in FIG. 9A, the fixed charge film 103 can be formed by using ALD, which can provide good coverage at the atomic layer level, for example.

[0066] Next, as shown in FIG. 13B, the lens material 110A of the on-chip lens 110 is embedded on the upper surface of the fixed charge film 103 on the back surface of the substrate, and inside the trench 212 and the three-dimensional polygon 221. This completes the light guide section 133, which is composed of the trench section 131 and the diffusion section 132. If the lens material 110A is an organic material, the lens material 110A is embedded in the light guide section 133 by, for example, spin coating, and then hardened by heat treatment. If the lens material 110A is an inorganic material, the lens material 110A is embedded in the light guide section 133 by, for example, CVD, ALD, sputtering, or the like. The lens material 110A may be embedded so as to form voids 134 inside the three-dimensional polygon 221. Forming the voids 134 can enhance the light diffusion effect. Furthermore, a film with a refractive index different from that of the fixed charge film 103 and the lens material 110A, such as a SiO2 film, may be formed between the fixed charge film 103 and the lens material 110A. By disposing films with different refractive indices, it is possible to improve the controllability of light at the interface with the refractive index difference, and to localize light at the corners of the three-dimensional polygon 221 while providing the effect of spreading the escaped light by diffraction. The material embedded inside the trench 212 and the three-dimensional polygon 221 is not limited to the lens material 110A of the on-chip lens 110, but may be a different material. In this case, it is preferable to use a material that has a refractive index close to that of the material of the on-chip lens 110 and an extinction coefficient of zero or close to zero.

[0067] Next, the lens material 110A formed on the upper surface of the backside of the substrate is planarized by CMP as necessary, and then, as shown in FIG. 14A, a light-shielding film portion 107 is formed, which is composed of a stack of a first metal film 108 and a second metal film 109. The light-shielding film portion 107 is formed in the order of the second metal film 109 and the first metal film 108. The upper first metal film 108 is formed using a metal material with low reflectivity, such as tungsten (W) or titanium (Ti), and functions as an anti-reflection film. The lower second metal film 109 is formed using a metal material with high reflectivity, such as aluminum (Al), copper (Cu), gold (Au), silver (Ag), or platinum (Pt), and functions as a reflective film.

[0068] Note that processing the metal film in an electrically floating state may cause plasma damage. Therefore, as shown in FIG. 14B, in the region outside the effective pixel region, the substrate surface film 105 and the lens material 110A formed on the semiconductor substrate 101 are removed to form an opening 223 several μm wide by dry etching or wet etching, and the first metal film 108 and the second metal film 109 are formed so as to be connected to the semiconductor substrate 101. The region of the semiconductor substrate 101 to which the first metal film 108 and the second metal film 109 are connected is, for example, a p-type semiconductor region set to ground potential, and the first metal film 108 and the second metal film 109 are formed while being grounded. In addition, the light-shielding film portion 107 formed in the region outside the effective pixel region also serves to shield the pixels that determine the optical black level and also serves to shield the peripheral circuit region from light to prevent noise.

[0069] As described above, the light-shielding film unit 107 may be configured as a laminated film including a first dielectric multilayer film on the on-chip lens 110 side and a second dielectric multilayer film on the photoelectric conversion unit 71 side, instead of being configured as a two-layer laminated film of the first metal film 108 and the second metal film 109. In this case as well, the first dielectric multilayer film is configured as a film having a lower reflectance than the second dielectric multilayer film.

[0070] 15A, a resist 225 patterned on the light-shielding film portion 107 is used as a mask to perform dry etching, thereby removing a portion of the light-shielding film portion 107 and forming an opening 112. The light-shielding film portion 107 is also removed from pad portions and scribe line portions (not shown). After the opening 112 is formed, the resist 225 and processing residues are removed by ashing, wet cleaning, or the like.

[0071] 15B, a lens material 110B of the on-chip lens 110 is formed on the upper surface of the lens material 110A in the opening 112 and on the upper surface of the light-shielding film portion 107. The lens material 110B is made of the same material as the lens material 110A described above, and is formed using the same method. For the lens materials 110A and 110B, for example, organic materials such as styrene-based resin, acrylic-based resin, styrene-acrylic copolymer resin, and silosane-based resin, and inorganic materials such as silicon nitride (SiN), silicon oxynitride (SiON), and silicon can be used.

[0072] Next, as shown in Figure 16A, resist 231 is spin-coated on the upper surface of the lens material 110B, and then patterned using an exposure machine and subjected to thermal reflow, etc., to form the resist 231 into a curved lens shape.

[0073] 16B, the resist 231 having a curved lens shape is transferred to the lens material 110B by dry etching, thereby forming the on-chip lenses 110. The gap between the on-chip lenses 110 may be reduced by setting a de-polishing condition during the transfer.

[0074] 17, an anti-reflection film 111 is formed on the upper surface of the on-chip lens 110 to a thickness according to the λ / (4n) rule. The anti-reflection film 111 can be made of, for example, an SiO2 film, a SiN film, a SiON film, an Al2O3 film, a TiO2 film, a HfO2 film, a Ta2O5 film, or the like. The anti-reflection film 111 may also serve as a passivation film as a reliability measure.

[0075] The photodetector device 1 having the pixels according to the first configuration example can be manufactured in the above manner.

[0076] 4. Second Configuration Example of Pixel> FIG. 18 is a cross-sectional view showing a second configuration example of the pixel 50 that can be arranged in the pixel array section 10 of the photodetector 1. As shown in FIG.

[0077] In Fig. 18, the same reference numerals are used to denote parts corresponding to those in the first configuration example shown in Fig. 3. In the description of the second configuration example in Fig. 18, parts that differ from the first configuration example shown in Fig. 3 will be described.

[0078] The second configuration example shown in FIG. 18 differs from the first configuration example shown in FIG. 3 in the shape of the diffusion portion 132. Furthermore, in the first configuration example, the fixed charge film 103 and the lens material 110A were formed between the light-shielding film portion 107 and the insulating film 106, whereas in the second configuration example, the light-shielding film portion 107 is formed on the insulating film 106. Furthermore, in the first configuration example, the light-receiving surface side of the trench portion 131 of the light-guiding portion 133 was formed vertically. In contrast, the trench portion 131 of the light-guiding portion 133 of the second configuration example is formed in a forward tapered shape that is inclined so that the light-receiving surface side is wider. By having the light-guiding portion 133 have a forward tapered shape on the light-receiving surface side of the trench portion 131, the opening of the light-guiding portion 133 is wider, allowing more light to be taken in by the light-guiding portion 133.

[0079] 3, a silicon substrate having a (1 0 0) crystal plane orientation on the front and back surfaces is used as the semiconductor substrate 101. In contrast, in the second configuration example, a silicon substrate having a (1 1 1) crystal plane orientation on the front and back surfaces is used.

[0080] In a semiconductor substrate 101 whose surface has a (111) crystal plane orientation, the etching rate in the <110> direction is significantly higher than the etching rate in the <111> direction. Therefore, when performing plane-orientation selective etching using, for example, an alkaline aqueous solution, etching of the semiconductor substrate 101 progresses in the X direction, while etching hardly progresses in the Y and Z directions. As a result, the space communicating with the trench portion 131 expands in the X direction inside the semiconductor substrate 101, and the diffusion portion 132 becomes a plate-like three-dimensional polygon expanding in the planar direction of the semiconductor substrate 101, as shown in FIG. 18 . In this case, an etching stopper layer may be formed in the X direction along which etching of the diffusion portion 132 progresses, so that the etching progress can be stopped by the etching stopper layer. The etching stopper layer is formed by forming a trench from the wiring layer 102 side and filling the trench with an etching stopper material. This makes it easy to control the etching progress in the <110> direction.

[0081] In the second configuration example of the pixel 50, as shown by the arrows inside the photoelectric conversion unit 71 in FIG. 18 , light scattered by the diffusion unit 132 is reflected by the element isolation unit 135 formed at the pixel boundary and returned to the inside of the photoelectric conversion unit 71. Furthermore, light attempting to exit toward the wiring layer 102 is reflected by the reflective layer 123 and returned to the inside of the photoelectric conversion unit 71. A portion of light attempting to exit toward the light-receiving surface side of the semiconductor substrate 101 is reflected by the substrate surface film 105 and returned to the inside of the photoelectric conversion unit 71. A portion of light that passes through the substrate surface film 105 and hits the light-shielding film unit 107 is absorbed by the light-shielding film 107 or is reflected toward the semiconductor substrate 101. In the second configuration example of the pixel 50, incident light can be guided into the photoelectric conversion unit 71 and the optical path length can be increased, thereby achieving both improved quantum efficiency and reduced flare.

[0082] <Plane Layout of Trench and Diffusion Portion> The plane layout of the trench portion 131 and the diffusion portion 132 in the second configuration example will be described with reference to FIGS. 19 to 22. FIG.

[0083] 19A to 19D show examples of the planar layout of the diffusion portion 132 when the planar shape of the trench portion 131 is formed linearly.

[0084] FIG. 19A shows an example in which the planar shape of the trench portion 131 is formed linearly, and the planar shape of the diffusion portion 132 is formed rhombic (quadrilateral).

[0085] The planar shape of A in FIG. 19 is formed as follows. First, a resist pattern is formed so that the trench portion 131 is linear, and then dry etching is performed to vertically process the semiconductor substrate 101 in the substrate depth direction. Then, as described in the first configuration example, a hard mask such as a SiN film is formed using a method with good coverage, such as CVD or ALD, and the entire surface is etched back, so that the hard mask remains only on the sidewalls of the trench portion 131, as shown in B in FIG. 11 . Then, using a predetermined alkaline aqueous solution, plane orientation selective etching is performed until the third crystal plane with plane index (1 1 1) appears, thereby forming the diffusion portion 132 into a rhombic planar shape. Note that further etching may result in over-etching, resulting in a shape other than a rhombic shape.

[0086] 19B and 19D show an example in which the planar shape of the trench portion 131 is formed linearly, and the planar shape of the diffusion portion 132 is formed hexagonally.

[0087] When performing plane orientation selective etching after forming trench portion 131, if the etching is forcibly stopped before the third crystal plane with plane index (1 1 1) appears, the planar shape of diffusion portion 132 will be the etched shape at that time, which may be a hexagonal shape with two opposing vertices of a rhombus rounded off, as shown in B or D of Figure 19. Depending on the length of the etching time, the planar shape may differ from B or D of Figure 19.

[0088] FIG. 19C shows an example in which the planar shape of the trench portion 131 is formed linearly, and the planar shape of the diffusion portion 132 is formed circular or elliptical.

[0089] In the surface orientation selective etching (wet etching), when an acidic mixed solution of hydrofluoric acid, nitric acid, and acetic acid is used instead of an alkaline aqueous solution, etching proceeds isotropically, and the planar shape of the diffusion portion 132 can be circular or elliptical as shown in C in FIG. 19 .

[0090] FIG. 20 shows an example of a planar layout of the diffusion portion 132 when the planar shape of the trench portion 131 is formed in an I-shape.

[0091] If the planar shape of the trench portion 131 is an I-shape as shown in Fig. 20, by performing plane orientation selective etching until a third crystal plane with a plane index of (1 1 1) appears, the planar shape of the diffusion portion 132 can become a hexagonal shape in which the corners of two opposing vertices of a rhombus are rounded. Depending on the length of the etching time, a planar shape different from that shown in Fig. 20 can also be obtained.

[0092] FIG. 21 shows an example of a planar layout of the diffusion portion 132 when the planar shape of the trench portion 131 is formed in a T-shape.

[0093] 21A, the planar shape of the trench portion 131 may be a diamond shape with corners at the ends of the T-shaped trench portion 131 due to subsequent surface orientation selective etching. However, if the etching is forcibly stopped midway, the shape may become like B in FIG. 21B, or some other planar shape may also be obtained.

[0094] FIG. 22 shows an example of a planar layout of the diffusion portion 132 when the planar shape of the trench portion 131 is formed in an H-shape.

[0095] 22A, the planar shape of the trench portion 131 may be an H-shape as shown in A of Fig. 22A, and the subsequent surface orientation selective etching may result in the planar shape of the diffusion portion 132 becoming a hexagon with corners at the ends of the H-shape trench portion 131. However, if the etching is forcibly stopped midway or if over-etching is performed, the shape may become as shown in B of Fig. 22A, or other planar shapes may also be obtained.

[0096] As described above, the diffusion region 132 is formed by crystal anisotropic etching, which utilizes the property that the etching rate varies depending on the plane orientation of the Si{111} substrate. Here, the Si{111} substrate in this disclosure refers to a substrate or wafer made of silicon single crystal and having a crystal plane represented by {111} in Miller indices. The Si{111} substrate in this disclosure also includes substrates or wafers whose crystal orientation is shifted by several degrees, for example, a few degrees from the {111} plane toward the nearest

[110] direction. Furthermore, it also includes substrates or wafers in which silicon single crystal is grown on a portion or the entire surface of such substrates or wafers by epitaxial methods or the like.

[0097] In addition, in the notation of the present disclosure, the {111} plane is a collective term for the (111) plane, (-111) plane, (1 -11) plane, (11-1) plane, (-1 -11) plane, (-11-1) plane, (1 -1-1) plane, and (-1 -1-1) plane, which are crystal planes equivalent to each other in terms of symmetry. Therefore, the description of a Si{111} substrate in the specification of the present disclosure may be read as, for example, a Si(111) substrate. Here, the bar symbol used to indicate a negative Miller index is substituted with a minus sign. Furthermore, the <1 1 0> direction in the description of the present disclosure is a general term for the

[110] direction,

[101] direction,

[011] direction, [-110] direction, [1-10] direction, [-101] direction, [10-1] direction, [0-11] direction, [01-1] direction, [-1-10] direction, [-10-1] direction, and [0-1-1] direction, which are crystal plane directions equivalent to each other in terms of symmetry, and may be interpreted as any one of them.

[0098] When performing anisotropic etching on a Si substrate (silicon substrate) using an etching solution, for example, an alkaline solution, the Si etching reaction with the alkaline solution proceeds through the reaction between Si bonds and OH ions. It is known that the more dangling bonds exposed on the surface side, the easier the etching proceeds, and the more backbonds extending toward the bulk side, the more difficult the etching proceeds. Backbonds refer to bonds extending in the negative direction on the opposite side of the normal to the Si {111} plane, with the dangling Si bond side being the positive direction. The schematic diagram shown in Figure 23 shows an example of three backbonds at angles between -19.47° and +19.47° relative to the {111} plane. While there are fewer than three Si backbonds in the direction approximately horizontal to the substrate surface, there are three Si backbonds in the direction approximately perpendicular to the substrate surface. Therefore, when surface orientation selective etching is performed using, for example, an alkaline aqueous solution, etching of the semiconductor substrate 101 progresses in the X direction, but etching hardly progresses in the Y and Z directions, and the diffusion portion 132 can be formed into the planar shape shown in FIGS. 19 to 22.

[0099] 5. Third Configuration Example of Pixel> FIG. 24 is a cross-sectional view showing a third configuration example of the pixel 50 that can be arranged in the pixel array section 10 of the photodetector 1. As shown in FIG.

[0100] In Fig. 24, the same reference numerals are used to denote parts corresponding to those in the second configuration example shown in Fig. 18. In the explanation of the third configuration example in Fig. 24, parts that differ from the second configuration example shown in Fig. 18 will be explained.

[0101] The pixel 50 according to the third configuration example shown in Figure 24 differs from the second configuration example shown in Figure 18 in that the focusing unit that focuses incident light on the photoelectric conversion unit 71 has been changed from an on-chip lens 110 to a metasurface element 261.

[0102] In the pixel 50 of Figure 24, the internal configuration of the semiconductor substrate 101 and the configuration of the light-shielding film portion 107 formed on the semiconductor substrate 101 are the same as those in the second configuration example shown in Figure 18. The lens material 110A is formed on the upper surface of the light-shielding film portion 107 and in the opening 112, and is also embedded inside the light-guiding portion 133. The pixel 50 of the third configuration example has, above the lens material 110A, an anti-reflection film 251, a pillar 252, an anti-reflection film 253, a filler material 254, and a protective film 255, in that order from bottom to top. The metasurface element 261 is composed of the pillar 252, the anti-reflection film 253, and the filler material 254.

[0103] To suppress reflection at the refractive index interface with the bottom surface of the pillar 252, the anti-reflection coating 251 is formed to a thickness of approximately λ / (4n) or an integer multiple thereof, where n is the effective refractive index of the material and λ is the target wavelength. For example, if SiN is used as the material for the anti-reflection coating 251, the anti-reflection coating 251 should preferably have a thickness of approximately 130 nm for a wavelength of 940 nm. The anti-reflection coating 251 may be formed by stacking multiple films with different refractive indices. In addition to anti-reflection, the anti-reflection coating 251 can also function as an etching stopper layer during dry etching by selecting a material with a high etching selectivity relative to the pillar 252. For example, if the pillar 252 is made of amorphous silicon, forming the anti-reflection coating 251 from a 125 nm SiN film can simultaneously provide anti-reflection and etching stopper functions.

[0104] The metasurface element 261 is configured by arranging a plurality of pillars 252 processed into a columnar shape within a pixel region. The diameter (thickness), pitch, and shape of the plurality of arranged pillars 252 vary depending on the pixel position within the pixel array unit 10, more specifically, the image height position. For example, the metasurface element 261 shown in FIG. 25 is configured by arranging pillars 252 with different diameters or pitches within a pixel region. By varying at least one of the diameter, pitch, and shape of the pillars 252, the phase difference of light changes locally, making it possible to control the direction of light according to the layout of the pillars 252.

[0105] The metasurface elements 261 may be designed to have a phase difference design that provides a lens function so that light is focused on the light-guiding unit 133 of each pixel. This configuration can improve quantum efficiency. Alternatively, the metasurface elements 261 at each image height may be designed to have a prism function so that the principal ray of obliquely incident light from the module lens is incident on the light-guiding unit 133 at each pixel approximately perpendicularly. This configuration can suppress image-height-dependent sensitivity variations due to differences in the angle of incidence of light on the light-guiding unit 133. Alternatively, a phase difference design may be used that combines a prism phase design that causes the principal ray of obliquely incident light from the module lens to be incident approximately perpendicularly for each image height and a lens phase design that focuses the light to a single point, thereby focusing the light approximately perpendicularly on the light-guiding unit 133 at each pixel. This configuration can improve quantum efficiency and suppress image-height-dependent sensitivity variations.

[0106] The anti-reflection film 253 is a film that suppresses reflection at the refractive index interface with the upper surface of the pillar 252. The film thickness and material of the anti-reflection film 253 can be configured similarly to the anti-reflection film 251. The anti-reflection film 253 may be formed only on the pillar 252 having a high refractive index by forming the film before processing the pillar 252.

[0107] The filler 254 fills the gaps between the pillars 252, preventing the pillars 252 from collapsing and preventing tape from remaining during the assembly process. The filler 254 is not limited to the gaps between the pillars 252, but is formed to cover the pillars 252 on the light incident surface side of the pillars 252. The filler 254 can be made of either an organic or inorganic material. Examples of organic materials include siloxane-based resins, styrene-based resins, acrylic resins, styrene-acrylic copolymer resins, F-containing materials of any of these resins, and materials in which beads with a refractive index lower than that of the resin are embedded in any of these resins. Examples of inorganic materials include silicon oxide, niobium oxide, tantalum oxide, aluminum oxide, hafnium oxide, silicon nitride, silicon nitride oxide, silicon carbide, silicon oxide carbide, silicon nitride carbide, zirconium oxide, and stacked structures thereof.

[0108] The protective film 255 is provided to prevent damage to the filler 254 during a resist removal process during manufacturing. The film thickness of the filler 254 from the top surface of the pillar 252 and the film thickness of the protective film 255 can be determined by taking into account the target wavelength and refractive index, and using, for example, the Fresnel coefficient method, so that reflected waves cancel each other out across the entire multilayer film.

[0109] FIG. 26 is a plan view showing an example of the arrangement of the pillars 252 of a predetermined pixel 50 in the pixel array section 10. In FIG.

[0110] The pillars 252 of the metasurface element 261 are designed according to the image height with a deflection design that matches the prism angle required for each image height in order to make effective use of the incident light.

[0111] 26A shows an example of the pillar arrangement of a pixel 50-1 located at the center of the pixel array section 10, among the pixels 50 arranged in the pixel array section 10. In FIG.

[0112] In pixel 50-1, for example, 100 pillars 252-1 of the same diameter are arranged in a 10 x 10 array as shown in A of Fig. 26. By arranging them in this manner, no phase difference change occurs within pixel 50, and light that is perpendicularly incident on metasurface element 261 is transmitted perpendicularly to the photoelectric conversion unit 71 side.

[0113] FIG. 26B shows an example of a pillar arrangement for pixel 50-2, which is shifted in the X direction in the pixel array unit 10 from pixel 50-1 and into which the chief ray is incident at an angle of 10 degrees in the horizontal direction.

[0114] 26B, in pixel 50-2, for example, pillars 252-1 are arranged in the first and second columns in accordance with the prism angle required for the image height (10 degrees horizontally), pillars 252-2 with a smaller diameter than pillars 252-1 are arranged in the third and fourth columns, no pillars 252 are arranged in the fifth column, and pillars 252-3 with a larger diameter than pillars 252-1 are arranged in the sixth to tenth columns. By arranging pillars 252 in this manner, a continuous gradient of phase difference is generated in pillars 252, and light incident on metasurface element 261 at 10 degrees is transmitted perpendicularly to the photoelectric conversion unit 71 side.

[0115] FIG. 26C shows an example of the pillar arrangement of pixel 50-3, which is shifted in the X direction from pixel 50-2 and into which the chief ray is incident at an angle of 20 degrees to the horizontal direction.

[0116] In pixel 50-3, for example, as shown in FIG. 26C, pillars 252-1 are arranged in the first to fourth columns, pillars 252-2 are arranged in the fifth column, pillars 252-3 are arranged in the sixth to eighth columns, and pillars 252-4, which have a smaller diameter than pillars 252-3 but a larger diameter than pillars 252-1, are arranged in the ninth and tenth columns in accordance with the prism angle required for the image height (20 degrees horizontally). The linear slope of the phase difference at this time is set to be approximately twice the slope at 10 degrees. By arranging the pillars 252 in this manner, a continuous gradient of the phase difference is generated in the pillars 252, and light incident on the metasurface element 261 at 20 degrees is transmitted perpendicularly to the photoelectric conversion unit 71.

[0117] FIG. 26D shows an example of the pillar arrangement of pixel 50-4, which is shifted in the X direction from pixel 50-3 and into which the chief ray is incident at an angle of 30 degrees to the horizontal direction.

[0118] In pixel 50-4, for example, as shown in D of Figure 26, the pillars 252 are arranged to match the prism angle required for the image height (30 degrees horizontally). The linear slope of the phase difference at this time is set to be approximately three times the slope at 10 degrees. By arranging the pillars 252 in this way, a continuous gradient of the phase difference is generated in the pillars 252, and light incident on the metasurface element 261 at 30 degrees is transmitted perpendicularly to the photoelectric conversion unit 71 side.

[0119] 26A to 26D are merely examples, and different layouts are possible by 2π folding or offset processing of the phase difference. What is important is the relative phase difference between the pillars 252.

[0120] In the third configuration example, a design example of the prism function of the metasurface element 261 is shown, but in this configuration, an on-chip lens may be combined with the light incident surface side of the metasurface element 261. Alternatively, an inner lens may be combined with the semiconductor substrate 101 side of the metasurface element 261. By providing an on-chip lens or an inner lens, light can be efficiently guided to the light guide section 133.

[0121] FIG. 27 is a cross-sectional view showing an example of a configuration in which an on-chip lens is provided on the light incident surface side of a metasurface element 261.

[0122] In the example of FIG. 27 , a metasurface element 261 employed in the third configuration example shown in FIG. 24 is further provided between the on-chip lens 110 and the light-shielding film portion 107 of the first configuration example shown in FIG. 3 . However, in the example of FIG. 27 , the filler 254 of the metasurface element 261 in the third configuration example is changed to a void 256, which is an air layer. The other configurations in FIG. 27 are similar to those in the first configuration example shown in FIG. 3 or the third configuration example shown in FIG. 24 , and are denoted by the same reference numerals, so a description thereof will be omitted. Because the void 256 has a refractive index of 1, the refractive index difference between the pillar 252 and the pillar 252 can be increased compared to when the filler 254 is filled between adjacent pillars 252. In FIG. 27 , the on-chip lens 110 is arranged to perform pupil correction in order to reduce stray light caused by light impinging on the boundary between the pillars 252 and the pixels 50 at the edge of the field of view. Specifically, the planar center of the on-chip lens 110 is disposed so as to be shifted from the center of the photoelectric conversion unit 71 depending on the image height position. Although the anti-reflection film 111 on the surface of the on-chip lens 110 is omitted in Fig. 27, the anti-reflection film 111 may be present.

[0123] Figure 28 is a cross-sectional view showing an example configuration in which an inner lens is provided on the semiconductor substrate 101 side of the metasurface element 261.

[0124] In the example of FIG. 28 , the on-chip lens 110 of the first configuration example shown in FIG. 3 is changed to an inner lens 271, and an inner lens upper layer film 272 is formed on the inner lens 271. The inner lens 271 is formed using the lens material 110A. As a material for the inner lens upper layer film 272, a material with a refractive index different from that of the inner lens 271 is used from among the various materials exemplified as the lens material 110A. Then, a metasurface element 261 and a protective film 255 are formed on the flatly formed inner lens upper layer film 272. As in FIG. 27 , the metasurface element 261 has gaps 256 between the pillars 252 instead of the filler material 254, but of course the filler material 254 may also be used.

[0125] The metasurface element 261 can be given a lens function in addition to a prism function.

[0126] Next, we explain the derivation of a metasurface design that combines prism and lens functions.

[0127] FIG. 29 is a plan view showing an example of the arrangement of the pillars 252 of a predetermined pixel 50 in the pixel array section 10. In FIG.

[0128] A to D in Figure 29 correspond to A to D in Figure 26, where A in Figure 29 shows an example of a pillar arrangement for pixel 50-1 located in the center of the pixel array section 10, B in Figure 29 shows an example of a pillar arrangement for pixel 50-2 into which the chief ray is incident at a tilt of 10 degrees horizontally, C in Figure 29 shows an example of a pillar arrangement for pixel 50-3 into which the chief ray is incident at a tilt of 20 degrees horizontally, and D in Figure 29 shows an example of a pillar arrangement for pixel 50-4 into which the chief ray is incident at a tilt of 30 degrees horizontally.

[0129] In order to effectively utilize light at the edge of the field of view of the pixel array section 10, the metasurface element 261 has pillars 252 designed for each pixel by combining a lens design that focuses light at the center of the pixel according to the image height and a deflection design that matches the prism angle required for each image height.

[0130] The principal ray of light from the module lens is incident perpendicularly on pixel 50-1, which is located at the center of the pixel array unit 10. The metasurface elements 261 of pixel 50-1 are arranged point-symmetrically with respect to the pixel center as shown in A of Figure 29, with the phase becoming earlier as you move outwards, and light that passes through the metasurface elements 261 is focused toward the center of the pixel 50. Because the pillars 252 are arranged point-symmetrically, the direction of the principal ray does not change.

[0131] The metasurface element 261 of pixel 50-2, on which the chief ray is incident at a horizontal tilt of 10°, has the above-mentioned lens design at the center of the image height, as shown in B of Figure 29, in addition to which pillars 252 are arranged with a linear phase difference in the horizontal direction so that the prism angle at which light incident at 10° in the horizontal direction becomes vertical. By arranging it in this way, it is possible to simultaneously combine the lens function of focusing light at the center of the pixel and the prism function of providing a prism angle of 10°.

[0132] As shown in C of Figure 29, the metasurface element 261 of pixel 50-3, on which the chief ray is incident at a horizontal tilt of 20°, has the lens design at the center of the image height described above, and in addition, pillars 252 are arranged with a linear phase difference shifted in the horizontal direction to correspond to the prism angle at which light incident at 20° in the horizontal direction becomes vertical. The linear slope of this phase difference is approximately twice that of the slope at 10°. By arranging it in this way, it is possible to simultaneously combine the lens function of focusing light at the center of the pixel and the prism function of providing a prism angle of 20°.

[0133] The metasurface element 261 of pixel 50-4, on which the chief ray is incident at a horizontal tilt of 20°, has the above-mentioned lens design at the center of the image height, and in addition, pillars 252 are arranged with a linear phase difference in the horizontal direction so that light incident at a horizontal angle of 30° becomes vertical, as shown in D of Figure 29. By arranging it in this way, it is possible to simultaneously combine the lens function of focusing light at the center of the pixel and the prism function of providing a prism angle of 30°.

[0134] 29A to 29D are merely examples, and different layouts are possible by 2π folding or offset processing of the phase difference. What is important is the relative phase difference between the pillars 252.

[0135] The metasurface element 261 at each image height is phase-designed so that it focuses light into the light-guiding section 133 and causes the chief ray to be incident approximately perpendicularly on the light-guiding section 133. This arrangement makes it possible to increase quantum efficiency and suppress sensitivity variations that depend on the image height.

[0136] As described above, the light collecting section can be configured using the metasurface element 261 instead of the on-chip lens 110. Also in the third configuration example of the pixel 50, light is collected by the metasurface element 261, guided to the light guiding section 133, and scattered by the diffusing section 132. The light is reflected by the element isolation section 135 formed at the pixel boundary and returned to the inside of the photoelectric conversion section 71. Furthermore, light that attempts to exit toward the wiring layer 102 side is reflected by the reflective layer 123 and returned to the inside of the photoelectric conversion section 71. A portion of the light that attempts to exit toward the light-receiving surface side of the semiconductor substrate 101 is reflected by the substrate surface film 105 and returned to the inside of the photoelectric conversion section 71. A portion of the light that passes through the substrate surface film 105 and hits the light-shielding film section 107 is absorbed by the light-shielding film 107 or reflected toward the semiconductor substrate 101 side. Therefore, also in the third configuration example of the pixel 50, incident light can be guided into the photoelectric conversion unit 71 and the optical path length can be increased, so that it is possible to achieve both improved quantum efficiency and flare suppression.

[0137] In addition, multiple metasurface elements 261 may be stacked between the anti-reflection film 251 and the protective film 255 to form a multi-stage structure of the metasurface elements 261. By using a multi-stage structure, it is possible to reduce the aspect ratio of the pillars 252 per stage, making it easier to avoid pattern collapse. Furthermore, while a single-layer pillar structure is generally designed on the premise of a single wavelength, by providing multi-stage pillars 252, it is possible to broaden the wavelength band and achieve multi-spectrality by changing and combining the designs of each stage. Furthermore, it is also possible to achieve deflection control.

[0138] In the above example, an example was shown in which the on-chip lens 110 of the pixel 50 according to the second configuration example shown in Figure 18 was replaced with a metasurface element 261, but a configuration in which the on-chip lens 110 of the pixel 50 according to the first configuration example shown in Figure 3 is replaced with a metasurface element 261 is also possible.

[0139] 6. Fourth Configuration Example of Pixel> FIG. 30 is a cross-sectional view showing a fourth configuration example of the pixel 50 that can be arranged in the pixel array section 10 of the photodetector 1. As shown in FIG.

[0140] In Fig. 30, parts corresponding to those in the first configuration example shown in Fig. 3 are given the same reference numerals, and the explanation of the fourth configuration example in Fig. 30 will focus on parts that differ from the first configuration example shown in Fig. 3. Note that in Fig. 30, for ease of explanation, some of the parts that are common to the first configuration example are omitted from the illustration.

[0141] 3 is different from the first configuration example in Fig. 3 in the material filled in the trench portion 131 and the diffusion portion 132 that constitute the light-guiding portion 133. In addition, in the fourth configuration example, a deflection portion 304 formed in an uneven shape is formed on the light-receiving surface of the semiconductor substrate 101, and an inter-pixel light-shielding portion 303 is formed at the pixel boundary portion on the light-receiving surface side. Furthermore, instead of the on-chip lens 110 of the first configuration example, an on-chip lens 310 is formed on the light-receiving surface side of the semiconductor substrate 101 as a light-collecting portion that collects incident light on the photoelectric conversion portion 71.

[0142] In the first configuration example, the trench portion 131 and the diffusion portion 132 are filled with a lens material 110A, and the on-chip lens 110 and the light guide portion 133 are made of the same material. In contrast, in the fourth configuration example, the diffusion portion 132 is filled with an insulating film 301, such as an SiO2 film, SiN film, SiON film, or TiO2 film. In this embodiment, an SiO2 film is used as the insulating film 301. Furthermore, the trench portion 131 is filled with silicon 302, a material with a high refractive index. The silicon 302 may be amorphous silicon (α-Si) or polycrystalline silicon. For example, the refractive indexes n of SiN and oxide film (SiO2) at a wavelength of 940 nm are n = 1.82 and n = 1.45, respectively, whereas the refractive index n of silicon at a wavelength of 940 nm is n = 3.5 to 3.8, making it higher than the refractive index of the insulating film 301. The on-chip lens 310 is made of a material having a refractive index close to that of the insulating film 301 embedded inside the diffusion portion 132, such as a resin material such as a styrene-based resin, an acrylic-based resin, a styrene-acrylic copolymer resin, or a silosane-based resin, or silicon nitride (SiN), silicon oxynitride (SiON), or the like.

[0143] The element isolation portion 135 formed in the pixel boundary portion of the semiconductor substrate 101 can be configured in the same manner as in the first configuration example. Although simplified in FIG. 30 , as shown in FIG. 3 , the element isolation portion 135 can be configured with a fixed charge film 103 formed on the sidewall of the full trench structure and an insulating film 106 embedded inside the fixed charge film 103. The element isolation portion 135 may also be configured by further embedding a metal material such as tungsten or aluminum further inside the insulating film 106. The element isolation portion 135 may also be configured to be formed, for example, from a p-type semiconductor region and grounded.

[0144] Like the light-shielding film portion 107 of the first configuration example, the inter-pixel light-shielding portion 303 is composed of a single layer or multiple layers of metal film. While any light-shielding material may be used for the inter-pixel light-shielding portion 303, it is preferable to form the inter-pixel light-shielding portion 303 from a metal film, such as aluminum (Al), tungsten (W), or copper (Cu), which has strong light-shielding properties and can be precisely processed by microfabrication, e.g., etching. Other materials that can be used include silver (Ag), gold (Au), platinum (Pt), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), iron (Fe), tellurium (Te), and alloys containing these metals. The inter-pixel light-shielding portion 303 can also be formed by stacking multiple of the above-mentioned metal films. The inter-pixel light-shielding portion 303 may have a barrier metal layer formed on the underlayer to improve adhesion to the underlying substrate. Examples of barrier metal materials include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), molybdenum (Mo), or alloys, nitrides, oxides, or carbides thereof. The inter-pixel light-shielding portion 303 may also serve as a light shield for the pixels that determine the optical black level, and may also serve as a light shield to prevent noise from reaching the peripheral circuit area. It is desirable for the inter-pixel light-shielding portion 303 to be grounded to prevent it from being destroyed by plasma damage caused by accumulated charge during processing. The grounding structure may be formed within the pixel array, or it may be provided outside the effective pixel area while electrically connecting all conductors.

[0145] The deflection unit 304 is configured with a moth-eye structure having a concave-convex structure in which upward or downward facing quadrangular pyramids are periodically formed on the light receiving surface of the semiconductor substrate 101. The moth-eye structure of the deflection unit 304 produces an anti-reflection effect by grading the refractive index difference on the light receiving surface of the semiconductor substrate 101. The moth-eye structure of the deflection unit 304 also functions as a light diffraction unit that diffracts light using the concave-convex structure.

[0146] Although not shown in the figure, a wiring layer 102 is formed on the surface opposite to the light-receiving surface of the semiconductor substrate 101, as in the first configuration example. Also in the fourth configuration example, the fixed charge film 103 and the anti-reflection film 104 described in the first configuration example may be formed on the light-receiving surface of the semiconductor substrate 101.

[0147] FIG. 31 is a plan view taken along the line XX′ of the cross-sectional view of FIG. 30, and shows an example of the configuration of the planar shape of the trench portion 131. In FIG.

[0148] The trench portion 131 can be formed in a rectangular or hole-shaped planar shape whose vertical and horizontal directions are substantially the same, as shown in A of Fig. 31. The hole shape includes a circle and an ellipse.

[0149] Alternatively, the trench portion 131 can be formed in a linear shape with one of the vertical and horizontal directions being longer than the other, as shown in FIG. 31B.

[0150] When the planar shape of the trench portion 131 is formed to be rectangular or hole-shaped, the perspective view of the light guide portion 133 is similar to that of FIG.

[0151] On the other hand, when the planar shape of the trench portion 131 is formed in a linear shape, the perspective view of the light guide portion 133 is as shown in FIG.

[0152] As shown in FIG. 10B , the light guide section 133 of the fourth configuration example is formed by using CVD, ALD, or the like to bury an insulating film 301 such as an SiO2 film inside a trench dug to a predetermined depth from the light-receiving surface of the semiconductor substrate 101 using dry etching or the like, and then burying silicon 302 such as α-Si. Then, an inter-pixel light-shielding section 303 and a deflection section 304 with a concave-convex structure are formed on the light-receiving surface of the semiconductor substrate 101, and then an on-chip lens 310 is formed. The concave-convex structure of the deflection section 304 can be formed, for example, as follows: A resist mask is formed on the concave-convex surface of the semiconductor substrate 101 in a lithography process in areas that will become the convex portions of the concave-convex structure. Next, recesses are formed by wet etching using the resist mask. When forming the recesses of the uneven structure, the surface orientation of the light-receiving surface and the opposite surface of the semiconductor substrate 101 is set to the (1 0 0) plane, and the wall surfaces of the recesses are set to the (1 1 1) plane, so that a highly accurate quadrangular pyramidal uneven structure can be formed by crystalline anisotropic etching while suppressing crystal defects. After the recesses are formed, the resist is removed.

[0153] The pixel 50 according to the fourth configuration example is configured as described above. According to the fourth configuration example, incident light is focused by the on-chip lens 310 and guided to the light guide 133 and the deflection unit 304 therearound. The light incident on the light guide 133 is diffused into the photoelectric conversion unit 71 by the diffusion unit 132. The diffusion unit 132 included in the light guide 133 can scatter light that has passed through the trench 131 in various directions, thereby extending the optical path length of the incident light. By providing the deflection unit 304 with a moth-eye structure on the light-receiving surface of the semiconductor substrate 101, zero-order diffracted light incident on the light-receiving surface of the semiconductor substrate 101 can be diffused and made to enter the photoelectric conversion unit 71, thereby extending the optical path length of the incident light. The longer optical path length of the incident light can contribute to improved quantum efficiency. By diffusing the zeroth-order diffracted light incident on the light-receiving surface of the semiconductor substrate 101, it is possible to reduce the amount of light (return light) that passes through to the surface of the semiconductor substrate 101 opposite the light-receiving surface (the surface on the wiring layer 102 side), is reflected by the wiring layer 102, and passes through to the light-receiving surface side.

[0154] 7. Modified Examples of Pixels According to Fourth Configuration Example Next, modified examples of the pixels 50 according to the fourth configuration example will be described.

[0155] FIG. 33A shows a cross-sectional view of a first modified example of the pixel 50 according to the fourth configuration example.

[0156] In the first modified example shown in FIG. 33A, the light guide 133 of the fourth configuration example shown in FIG. 30 is replaced with a light guide 133A. The light guide 133A differs from the light guide 133 of the fourth configuration example in the location of the diffusion portion 132. That is, in the light guide 133 of FIG. 30, the diffusion portion 132 is provided at the tip of the trench portion 131 dug in the depth direction from the light-receiving surface of the semiconductor substrate 101. In contrast, in the light guide 133A of the first modified example shown in FIG. 33A, the diffusion portion 132 is provided between the light-receiving surface of the semiconductor substrate 101 and the tip of the trench portion 131. Such a light guide 133A can be formed by forming the diffusion portion 132 in the same manner as in the first configuration example, then further forming a hard mask, and removing the bottom hard mask of the three-dimensional polygonal shape using an etch bank to proceed with etching in the depth direction of the semiconductor substrate 101. In this way, the diffusion portion 132 does not need to be at the tip of the trench portion 131 , but can be provided at any depth between the light-receiving surface of the semiconductor substrate 101 and the tip of the trench portion 131 .

[0157] FIG. 33B shows a cross-sectional view of a second modified example of the pixel 50 according to the fourth configuration example.

[0158] In the second modified example shown in FIG. 33B, the light guide 133 of the fourth configuration example shown in FIG. 30 is replaced with a light guide 133B. The light guide 133B differs from the light guide 133 of the fourth configuration example in the number of diffusion portions 132. That is, in the light guide 133 of FIG. 30, one diffusion portion 132 is provided in the trench portion 131. In contrast, in the light guide 133B of the second modified example shown in FIG. 33B, two diffusion portions 132 are provided in the trench portion 131. Specifically, the diffusion portions 132 are provided at two locations, at the end and midway of the trench portion 131. Such a light guide 133B can be formed by repeating the same formation method as in the first configuration example in the depth direction. While this example shows two diffusion portions 132, three or more diffusion portions 132 may be provided. In this manner, the light guide portion 133B may be composed of the trench portion 131 and a plurality of diffusion portions 132.

[0159] FIG. 34A shows a cross-sectional view of a third modified example of the pixel 50 according to the fourth configuration example.

[0160] In the third modified example shown in FIG. 34A, the light guide portion 133 of the fourth configuration example shown in FIG. 30 is replaced with a light guide portion 133C. The light guide portion 133C includes a diffusion portion 132A, which is a modification of the diffusion portion 132 of FIG. 30. The diffusion portion 132A of the third modified example is configured as a plate-like three-dimensional polygon extending in the planar direction of the semiconductor substrate 101, similar to the diffusion portion 132 of the second configuration example shown in FIG. 18. The diffusion portion 132A, which is configured as a plate-like three-dimensional polygon, is provided at the tip of the trench portion 131. As in the second configuration example, the light guide portion 133C can be formed by plane-orientation selective etching using an alkaline aqueous solution or the like using a silicon substrate having a (100) crystal plane orientation on both the front and back surfaces of the semiconductor substrate 101. In this way, the diffusion portion 132A can be configured as a plate-like three-dimensional polygon extending in the planar direction of the semiconductor substrate 101.

[0161] FIG. 34B shows a cross-sectional view of a fourth modified example of the pixel 50 according to the fourth configuration example.

[0162] In a fourth modified example shown in B of FIG. 34 , the light guide 133 of the fourth configuration example shown in FIG. 30 is replaced with a light guide 133D. The light guide 133D has two diffusion sections 132A each configured as a plate-like three-dimensional polygon. More specifically, in the light guide 133D of the fourth modified example, the diffusion sections 132A each configured as a plate-like three-dimensional polygon extending in the planar direction of the semiconductor substrate 101 are disposed at two locations: one at the tip of the trench section 131 and the other between the light-receiving surface of the semiconductor substrate 101 and the tip of the trench section 131. In this example, two diffusion sections 132A are disposed between the light-receiving surface of the semiconductor substrate 101 and the tip of the trench section 131, but three or more diffusion sections 132A may be disposed. In this manner, the light guide 133D may be configured with a trench section 131 and multiple diffusion sections 132A.

[0163] FIG. 35 shows a cross-sectional view of a fifth modified example of the pixel 50 according to the fourth configuration example.

[0164] In the fifth modified example shown in Fig. 35, a plurality of light guide sections 133 of the fourth configuration example shown in Fig. 30 are provided within a pixel. The planar shape of the plurality of light guide sections 133 may be a rectangular or hole-shaped planar shape as shown in Fig. 31A, or a linear planar shape as shown in Fig. 31B.

[0165] 36 is a plan view taken along the line XX' of the cross-sectional view of FIG.

[0166] When the planar shape of the trench portion 131 is formed to be rectangular or hole-shaped, the pixel 50 of the fifth modified example has 3×3=9 light guide portions 133, as shown in A of FIG.

[0167] On the other hand, when the trench portion 131 has a linear planar shape, the pixel 50 of the fifth modified example has three light guide portions 133 as shown in FIG. 36B.

[0168] In this way, the pixel 50 of the fifth modified example can be configured to have a configuration in which a plurality of light guide sections 133 are provided within the pixel. Because the plurality of light guide sections 133 can be formed simultaneously, it is possible to increase the number of diffusion sections 132 to be arranged within the pixel without increasing the number of processes, thereby extending the optical path length of incident light and improving sensitivity.

[0169] The first modified example shown in FIG. 33 to the fifth modified example shown in FIGS. 35 and 36 can be combined as appropriate.

[0170] FIG. 37 shows a cross-sectional view of a sixth modified example of the pixel 50 according to the fourth configuration example.

[0171] The sixth modified example shown in Fig. 37 has a configuration in which a plurality of light guide sections 133B having a plurality of diffusion sections 132, which is employed in the second modified example shown in Fig. 33B, is provided within a pixel, as in the fifth modified example shown in Fig. 35. The planar shape of light guide section 133B may be a rectangular or hole-shaped planar shape as shown in Fig. 36A, or a linear planar shape as shown in Fig. 36B.

[0172] FIG. 38 shows a cross-sectional view of a seventh modification of the pixel 50 according to the fourth configuration example.

[0173] The seventh modified example shown in Fig. 38 has a configuration in which light guiding section 133 shown in Fig. 30 and light guiding section 133B of the second modified example shown in Fig. 33B are provided within a pixel. When a plurality of light guiding sections 133 are provided within a pixel in this manner, the type of light guiding section 133 to be formed may be changed depending on, for example, the planar position within the pixel. The planar shape of light guiding section 133 and light guiding section 133B may be a rectangular or hole-shaped planar shape as shown in Fig. 36A, or a linear planar shape as shown in Fig. 36B.

[0174] FIG. 39 shows a cross-sectional view of an eighth modification of the pixel 50 according to the fourth configuration example.

[0175] In the eighth modified example shown in FIG. 39 , 2×2=4 on-chip lenses 310 are arranged in one pixel, and a light guide unit 133 is arranged at the position of the photoelectric conversion unit 71, which corresponds to the planar center of each on-chip lens 310. Therefore, in the eighth modified example, four light guide units 133 are formed in one pixel. The planar shape of the light guide unit 133 may be a rectangular or hole-shaped planar shape as shown in FIG. 31A , or a linear planar shape as shown in FIG. 31B . In this manner, multiple on-chip lenses 310 may be formed in one pixel, and multiple light guide units 133 may be arranged in the pixel corresponding to each on-chip lens 310. For example, the number of on-chip lenses 310 and the number of light guide units 133 arranged in one pixel are not limited to four, and may be, for example, 3×3=9.

[0176] FIG. 40 shows a cross-sectional view of a ninth modification of the pixel 50 according to the fourth configuration example.

[0177] The ninth modified example shown in FIG. 40 differs from the pixel 50 according to the fourth configuration example shown in FIG. 30 in that the light receiving surface of the semiconductor substrate 101 is formed as a flat surface. That is, in the pixel 50 of FIG. 30 , a deflection section 304 formed in an uneven shape is provided on the light receiving surface of the semiconductor substrate 101. In contrast, in the ninth modified example of FIG. 40 , the deflection section 304 is omitted, and the light receiving surface of the semiconductor substrate 101 is formed as a flat surface. In this way, the pixel 50 includes the light guide section 133, but may be configured without the deflection section 304. If the deflection section 304 is not provided, the process of forming the deflection section 304 can be omitted, thereby simplifying the manufacturing process.

[0178] FIG. 41 shows a cross-sectional view of a tenth modification of the pixel 50 according to the fourth configuration example.

[0179] The tenth modified example shown in FIG. 41 differs from the pixel 50 according to the fourth configuration example shown in FIG. 30 in that it further includes a reflective deflector 331 having an uneven shape on the surface of the semiconductor substrate 101 opposite the light-receiving surface. That is, in the pixel 50 of FIG. 30 , the surface of the semiconductor substrate 101 opposite the light-receiving surface is formed as a flat surface. In contrast, in the tenth modified example shown in FIG. 41 , the reflective deflector 331 having an uneven shape is formed on the surface of the semiconductor substrate 101 opposite the light-receiving surface. An insulating film 332 made of, for example, SiO or SiN is embedded in the recesses of the reflective deflector 331. The insulating film 332 can be a multilayer film (dielectric multilayer film) designed for reflection using a layered structure of dielectrics with different refractive indices. This allows light that would otherwise be transmitted toward the wiring layer 102 (not shown) to be returned to the photoelectric conversion unit 71. Furthermore, the light that is about to be transmitted to the wiring layer 102 side (not shown) can be reflected at an angle by the reflective deflection section 331, thereby making it possible to further increase the optical path length.

[0180] FIG. 42 shows a cross-sectional view of an eleventh modification of the pixel 50 according to the fourth configuration example.

[0181] 42 differs from the fourth configuration example shown in Fig. 30 in that the deflection unit 304 is omitted and a color filter layer 351 is formed on the light-receiving surface of the flat semiconductor substrate 101. The color filter layer 351 may be formed between the on-chip lens 310 and the semiconductor substrate 101, and an inter-pixel light-shielding unit 303 or an anti-reflection film may be formed between the light-receiving surface of the semiconductor substrate 101 and the color filter layer 351.

[0182] The color filter layer 351 is formed in a so-called Bayer array in which, for example, 2 × 2 four pixels are used as a repeating unit and G, B, R, and G color filters are arranged in the four pixels that make up the repeating unit. The cross-sectional view of Fig. 42 shows two pixels, a pixel 50 having an R color filter and a pixel 50 having a G color filter, out of the four pixels having G, B, R, and G color filters that make up the repeating unit.

[0183] The color filter array of the color filter layer 351 is not limited to the Bayer array, and may be other arrays. For example, as shown in the example of FIG. 43 , the color filter array may be an RGBW array in which G, B, R, and W color filters are arranged in four 2×2 pixels constituting a repeating unit. The cross-sectional view of FIG. 8 shows two pixels, one having an R color filter and the other having a W color filter, out of the four pixels having G, B, R, and W color filters constituting a repeating unit. The W color filter is a color filter that transmits light of all colors (wavelengths) of R, G, and B, and is sometimes referred to as C (clear). In the example of FIG. 43 , the W color filter is formed of the same material as the on-chip lens 310.

[0184] The color filter array may be a quad Bayer array in which G, B, R, and G color filters are arranged in a Bayer array in 2 x 2 four-pixel units, with each color being arranged in a 2 x 2 four-pixel unit, or a quad RGBW array in which G, B, R, and W color filters are arranged in 2 x 2 four-pixel units. Alternatively, color filters of complementary colors such as yellow (Y), cyan (Cy), and magenta (Mg) may be arranged.

[0185] FIG. 44 shows a cross-sectional view of a twelfth modification of the pixel 50 according to the fourth configuration example.

[0186] In the twelfth modified example shown in Fig. 44 , the deflection unit 304 is omitted, and a color filter layer 351 is formed on the light-receiving surface of a flat semiconductor substrate 101. The color filter layer 351 may be formed between the on-chip lens 310 and the semiconductor substrate 101, and an inter-pixel light-shielding unit 303 or an anti-reflection film may be formed between the light-receiving surface of the semiconductor substrate 101 and the color filter layer 351. The color filter arrangement of the color filter layer 351 may be any arrangement, as in the eleventh modified example described above. Fig. 44 shows an example in which the color filter arrangement is a Bayer arrangement.

[0187] Furthermore, in the twelfth modification, the semiconductor substrate 101 is configured by stacking two layers, a first semiconductor layer 361 and a second semiconductor layer 362, in the substrate depth direction. An insulating layer 363 is formed between the first semiconductor layer 361 and the second semiconductor layer 362. The insulating layer 363 is formed of, for example, an SiO2 film. The insulating layer 363 may be formed of the same material as the insulating film 301 embedded inside the diffusion portion 132, or the same material as the on-chip lens 310.

[0188] Each pixel 50 has two photoelectric conversion sections 71: a photoelectric conversion section 71 formed in the first semiconductor layer 361 (hereinafter referred to as the first photoelectric conversion section 71-1) and a photoelectric conversion section 71 formed in the second semiconductor layer 362 (hereinafter referred to as the second photoelectric conversion section 71-2).

[0189] The first photoelectric conversion unit 71-1 formed on the light-receiving surface side of the semiconductor substrate 101 photoelectrically converts G, B, or R light that has passed through the color filter layer 351. In the example of FIG. 44 , an R color filter is formed in the color filter layer 351 of the left pixel 50, so the first photoelectric conversion unit 71-1 of the left pixel 50 photoelectrically converts the incident R light. A G color filter is formed in the color filter layer 351 of the right pixel 50, so the first photoelectric conversion unit 71-1 of the right pixel 50 photoelectrically converts the incident G light.

[0190] The second photoelectric conversion section 71-2 formed on the wiring layer 102 side of the semiconductor substrate 101 photoelectrically converts infrared light that has passed through the color filter layer 351 and further through the first photoelectric conversion section 71-1. A light guide section 133 consisting of a trench section 131 and a diffusion section 132 is formed inside the second photoelectric conversion section 71-2.

[0191] As described above, the pixel 50 according to the twelfth modification has two photoelectric conversion units 71: a first photoelectric conversion unit 71-1 that photoelectrically converts visible light of a predetermined wavelength, and a second photoelectric conversion unit 71-2 that photoelectrically converts infrared light, and at least one of the two photoelectric conversion units 71 has a light guide unit 133. In the example shown in Fig. 44, by providing the light guide unit 133 in the second photoelectric conversion unit 71-2 that photoelectrically converts infrared light, the optical path length of the infrared light can be extended, and the quantum efficiency of the infrared light can be improved. If the first photoelectric conversion unit 71-1 is also provided with a light guide unit 133, the quantum efficiency of visible light of a predetermined wavelength can be improved.

[0192] 44 shows a configuration example in which the pixel regions that photoelectrically convert G, B, or R light and the pixel regions that photoelectrically convert infrared light are formed in the same unit, but the pixel regions that photoelectrically convert G, B, or R light and the pixel regions that photoelectrically convert infrared light may be formed in different units. For example, in the second semiconductor layer 362 on the wiring layer 102 side of the semiconductor substrate 101, the element isolation portions 135 may be formed in 2 x 2 four-pixel units in the first semiconductor layer 361 on the light-receiving surface side, so that signals photoelectrically converted from infrared light are output in four-pixel units of RGB pixels.

[0193] The first to twelfth modified examples described with reference to Fig. 33 to Fig. 44 are modified examples of the pixel 50 according to the fourth configuration example shown in Fig. 30, but these modified examples can also be similarly applied to the pixel 50 according to the first to third configuration examples described above. Two or more of the first to fourth configuration examples of the pixel 50 described above and their respective modified examples can be combined within a range that does not contradict each other.

[0194] 8. Example of a Mixed Array of Visible Light Pixels and Non-Visible Light Pixels An example of a pixel array in which pixels 50 that perform photoelectric conversion of R, G, or B visible light and pixels 50 that perform photoelectric conversion of non-visible infrared light are mixed and arranged in the pixel array unit 10 of the photodetector 1 will be described.

[0195] FIG. 45A shows a first example of a pixel arrangement in which visible light pixels and non-visible light pixels are mixed.

[0196] The first pixel array example of A in Fig. 45 is configured such that eight pixels 50G, four pixels 50IR, two pixels 50R, and two pixels 50B are arranged in a pixel region of 16 pixels (4 x 4) that serves as a repeating unit. Pixel 50G has a G color filter and is a pixel that receives G light, pixel 50R has an R color filter and is a pixel that receives R light, and pixel 50B has a B color filter and is a pixel that receives B light. Pixel 50IR has an IR color filter and is a pixel that receives IR light (infrared light).

[0197] FIG. 45B shows a second example of a pixel arrangement in which visible light pixels and non-visible light pixels are mixed.

[0198] The second pixel array example in B of Fig. 45 is configured such that four pixels 50G, eight pixels 50IR, two pixels 50R, and two pixels 50B are arranged in a pixel region of 16 pixels, which is a 4 x 4 repeating unit. When the resolution of an object using infrared light is more important and colorization is also required, an array with a higher occupancy rate of the pixels 50IR may be used.

[0199] FIG. 45C shows a third example of a pixel arrangement in which visible light pixels and non-visible light pixels are mixed.

[0200] The third pixel arrangement example shown in C of Figure 45 is configured such that four pixels 50G, four pixels 50IR, four pixels 50W, two pixels 50R, and two pixels 50B are arranged in a pixel region of 16 pixels (4 x 4) that serves as a repeating unit. Pixel 50W is a pixel that receives R, G, and B visible light and IR invisible light. The third pixel arrangement example is suitable for cases where luminance information, color information, and sensing information in a low-illuminance environment are all required from a single photodetector device 1.

[0201] 9. Configuration Example of Image Processing System FIG. 46 is a schematic diagram showing a configuration example of an image processing system according to a second embodiment to which the technology of the present disclosure is applied.

[0202] The image processing system 500 in Figure 46 acquires spectral information of a subject and also acquires sensing information of the subject. The image processing system 500 includes a light source unit 510 that irradiates the subject with infrared light, an optical unit (imaging lens) 520 that forms an image of the light from the subject, and an imaging device 530 that images the subject. The image processing system 500 also includes a signal processing unit 540 that processes signals from the imaging device 530, an authentication processing unit 550 that performs authentication processing based on the infrared light image, and a viewing processing unit 560 that performs viewing processing. The image processing system 500 performs authentication processing and viewing processing based on signals output from the imaging device 530. The operation of the entire image processing system 500 is controlled by a control unit (not shown) and the like.

[0203] In this image processing system 500, a mixed pixel array such as those shown in Figures 45A to 45C can be applied to the pixel array of the imaging device 530. The signal processing unit 540 separates the pixel signals from the imaging device 530 into pixel signals of visible light pixels and pixel signals of infrared light pixels. The separated pixel signals of the visible light pixels are used as a visible light image (RGB image). The separated pixel signals of the infrared light pixels are used as an infrared light image. The signal processing unit 540 detects a phase difference based on the separated pixel signals of the infrared light pixels and generates a distance image.

[0204] The authentication processing unit 550 performs authentication processing using at least one of the visible light image, infrared light image, and distance image supplied from the signal processing unit 540. For example, the authentication processing unit 550 can perform integrated authentication such as 3D (three-dimensional) face recognition and iris recognition based on information from the infrared light image and distance image. The viewing processing unit 560 performs viewing processing based on the visible light image supplied from the signal processing unit 540. In the image processing system 500, by guiding incident light into the photoelectric conversion unit 71 and increasing the optical path length, the image capturing device 530 includes a photodetector 1 having pixels 50 that achieve both improved quantum efficiency and flare suppression, thereby achieving high sensitivity and enabling authentication processing and viewing processing to be performed with higher accuracy.

[0205] 10. Configuration Example of Distance Measuring System FIG. 47 is a block diagram showing a configuration example of a distance measuring system according to a third embodiment to which the technology of the present disclosure is applied.

[0206] 47 includes a distance measuring device 611 and an application unit 612. The distance measuring device 611 has a light source unit 641, a light receiving unit 642, and a distance measurement processing unit 643.

[0207] The light source unit 641 includes, for example, a light-emitting element that emits infrared light and a drive circuit that drives the light-emitting element. The light-emitting element included in the light source unit 641 can be, for example, a light-emitting diode (LED). Alternatively, the light-emitting element included in the light source unit 641 can be a vertical cavity surface-emitting laser (VCSEL) in which a plurality of light-emitting elements are formed in an array. Hereinafter, unless otherwise specified, "the light-emitting element of the light source unit 641 emits light" will be expressed as "the light source unit 641 emits light," etc.

[0208] The light receiving unit 642 includes, for example, a light receiving element capable of detecting infrared light, and a signal processing circuit that outputs a pixel signal corresponding to the light detected by the light receiving element. This light receiving unit 642 is configured with the above-described light detection device 1. Hereinafter, unless otherwise specified, "the light receiving element included in the light receiving unit 642 receives light" will be expressed as "the light receiving unit 642 receives light," etc.

[0209] The ranging processing unit 643 executes ranging processing in the ranging device 611 in response to, for example, a ranging instruction from the application unit 612. For example, the ranging processing unit 643 generates a light source control signal for driving the light source unit 641 and supplies it to the light source unit 641. The ranging processing unit 643 also controls light reception by the light receiving unit 642 in synchronization with the light source control signal supplied to the light source unit 641. For example, the ranging processing unit 643 generates an exposure control signal for controlling an exposure period in the light receiving unit 642 in synchronization with the light source control signal and supplies it to the light receiving unit 642. The light receiving unit 642 outputs a valid pixel signal within the exposure period indicated by the exposure control signal. The ranging processing unit 643 calculates distance information based on the pixel signal output from the light receiving unit 642 in response to light reception and the light source control signal for driving the light source unit 641. The ranging processing unit 643 can also generate predetermined image information based on this pixel signal. The distance measurement processing unit 643 supplies the distance information and image information calculated and generated based on the pixel signals to the application unit 612 .

[0210] In this configuration, for example, the distance measurement processing unit 643 generates a light source control signal for driving the light source unit 641 in accordance with an instruction to perform distance measurement from the application unit 612, and supplies the signal to the light source unit 641. The distance measurement processing unit 643 also generates an exposure control signal synchronized with the light source control signal and supplies the signal to the light receiving unit 642. The light source unit 641 emits light in accordance with the light source control signal generated by the distance measurement processing unit 643. The light emitted by the light source unit 641 is emitted from the light source unit 641 as emitted light 631. This emitted light 631 is reflected by, for example, the object under measurement 621, and received by the light receiving unit 642 as reflected light 632. The light receiving unit 642 generates a pixel signal in accordance with the reception of the reflected light 632, and supplies the pixel signal to the distance measurement processing unit 643.

[0211] The distance measurement processing unit 643 measures the distance D to the object under measurement 621 based on the timing at which the light source unit 641 emits light and the timing at which the reflected light is received by the light receiving unit 642. Known distance measurement methods using reflected light include a direct ToF (Time of Flight) method and an indirect ToF method. The direct ToF method measures the distance D based on the difference (time difference) between the timing at which the light source unit 641 emits light and the timing at which the reflected light is received by the light receiving unit 642. The indirect ToF method measures the distance D based on the phase difference between the phase of the light emitted by the light source unit 641 and the phase of the light received by the light receiving unit 642. The pixel 50 of the photodetector 1 used as the pixel of the light receiving unit 642 can efficiently confine the incident reflected light 632 within the photoelectric conversion unit 71, thereby achieving both improved quantum efficiency and flare suppression.

[0212] The application unit 612 is realized by running a program on a CPU (Central Processing Unit), for example, and requests the distance measuring device 611 to perform distance measurement, and obtains distance information and the like as a result of the distance measurement from the distance measuring device 611.

[0213] In a distance measurement system 600 that uses, for example, infrared light as the emitted light 631 emitted by a light source unit 641 toward an object to be measured 621, by guiding incident light into a photoelectric conversion unit 71 and increasing the optical path length, a photodetector 1 having pixels 50 that achieve both improved quantum efficiency and flare suppression is provided as a light receiving unit 642, thereby achieving high sensitivity and making it possible to measure the distance D with higher accuracy.

[0214] 11. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0215] FIG. 48 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology of the present disclosure can be applied.

[0216] 48 , a vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. The vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 also includes a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0217] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0218] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0219] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0220] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0221] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0222] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0223] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0224] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0225] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 48, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0226] FIG. 49 is a diagram showing an example of the installation position of the imaging unit 12031.

[0227] In FIG. 49, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0228] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0229] 49 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0230] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for detecting a phase difference.

[0231] For example, based on distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the closest three-dimensional object on the path of the vehicle 12100 that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which travels autonomously without relying on driver operation.

[0232] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into categories such as two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into those that are visible to the driver of the vehicle 12100 and those that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drivetrain control unit 12010.

[0233] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching processing on a series of feature points that indicate the outline of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0234] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. Specifically, the light detection device 1 can be used as the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to obtain a more easily visible captured image and acquire distance information while reducing the size of the imaging unit. Furthermore, using the obtained captured image and distance information, it is possible to reduce driver fatigue and increase the safety of the driver and the vehicle.

[0235] In the above example, a solid-state imaging device in which the first conductivity type is p-type and the second conductivity type is n-type and electrons are used as signal charges has been described, but the present disclosure can also be applied to a solid-state imaging device in which holes are used as signal charges. That is, the first conductivity type can be n-type and the second conductivity type can be p-type, and the aforementioned semiconductor regions can be configured with semiconductor regions of opposite conductivity types.

[0236] The embodiments of the present disclosure are not limited to the above-described embodiments, and various modifications are possible within the scope of the gist of the technology of the present disclosure. For example, it is possible to adopt a configuration in which all or part of the above-described multiple configuration examples are appropriately combined.

[0237] The effects described in this specification are merely examples and are not limiting, and there may be effects other than those described in this specification.

[0238] The technology disclosed herein may have the following configurations: (1) A photodetector including a pixel array unit in which a plurality of pixels are two-dimensionally arranged on a semiconductor substrate, each pixel including: a photoelectric conversion unit formed on the semiconductor substrate and performing photoelectric conversion in response to incident light; a light collecting unit that collects the incident light at the photoelectric conversion unit; and a light guiding unit formed inside the photoelectric conversion unit. (2) The photodetector according to (1), wherein the light guiding unit includes: a trench unit formed in a depth direction from a light-receiving surface of the semiconductor substrate; and a diffusion unit formed at a predetermined depth from the light-receiving surface of the semiconductor substrate. (3) The photodetector according to (2), wherein the diffusion unit is formed as a three-dimensional polygon including a face aligned with a crystal plane orientation of the semiconductor substrate. (4) The photodetector according to (2) or (3), wherein the diffusion unit is formed as a protrusion having a plane area larger than that of the trench unit. (5) The photodetector according to any one of (2) to (4), wherein the diffusion unit has a void in at least a portion thereof. (6) The photodetector according to any one of (2) to (5), wherein the diffusion portion is formed in a plate shape extending in a planar direction of the semiconductor substrate. (7) The photodetector according to any one of (2) to (6), wherein the trench portion is formed in a rectangular shape or a hole shape whose vertical and horizontal directions are approximately the same in a plan view. (8) The photodetector according to any one of (2) to (7), wherein the trench portion is formed in a linear shape whose vertical or horizontal direction is longer than the other in a plan view. (9) The photodetector according to any one of (2) to (8), wherein the diffusion portion is provided at the tip of the trench portion. (10) The photodetector according to any one of (2) to (9), wherein the diffusion portion is provided between the light receiving surface of the semiconductor substrate and the tip of the trench portion. (11) The photodetector according to any one of (2) to (10), wherein the light guide portion includes a plurality of the diffusion portions. (12) The photodetector according to any one of (1) to (11), wherein the pixel includes a plurality of the light guide units. (13) The photodetector according to any one of (1) to (12), wherein the pixel further includes an element isolation unit that isolates the photoelectric conversion units of each pixel.(14) The photodetector according to any one of (1) to (13), wherein the light-collecting portion is formed of a material containing silicon. (15) The photodetector according to any one of (1) to (14), wherein the light-collecting portion is formed of an organic or inorganic insulating material. (16) The photodetector according to any one of (1) to (15), wherein the light-collecting portion has a curved lens shape. (17) The photodetector according to any one of (1) to (15), wherein the light-collecting portion is formed of a metasurface element having a plurality of pillars arranged. (18) The photodetector according to any one of (1) to (17), wherein the material of the light-collecting portion is embedded in the light-guiding portion. (19) The photodetector according to any one of (1) to (18), wherein the light-guiding portion includes a portion where the material of the light-collecting portion is embedded and a portion having a refractive index lower than that of the material of the light-collecting portion. (20) The photodetector according to any one of (1) to (19), wherein the light-guiding portion has a fixed charge film on a sidewall. (21) The photodetector according to any one of (1) to (20), wherein the pixel further includes a light-shielding film portion located between the photoelectric conversion portion and the light-collecting portion and having an opening for passing the incident light collected by the light-collecting portion. (22) The photodetector according to (21), wherein the light-shielding film portion is composed of a stacked film including a first metal film on the light-collecting portion side and a second metal film on the photoelectric conversion portion side, and the first metal film is composed of a film having a lower reflectivity than the second metal film. (23) The photodetector according to (21), wherein the light-shielding film portion is composed of a stacked film including a first dielectric multilayer film on the light-collecting portion side and a second dielectric multilayer film on the photoelectric conversion portion side, and the first dielectric multilayer film is composed of a film having a lower reflectivity than the second dielectric multilayer film. (24) The photodetector according to (23), wherein the second dielectric multilayer film is designed to reflect the wavelength of the incident light to be photoelectrically converted. (25) The photodetector according to any one of (1) to (24), wherein the pixel further comprises a deflector having an uneven shape on the light-receiving surface side of the semiconductor substrate. (26) The photodetector according to any one of (1) to (25), wherein the pixel further comprises a reflective layer on the surface of the semiconductor substrate opposite to the light-receiving surface side.(27) The photodetector according to (26), wherein the reflective layer is a laminated film of multiple dielectric layers having different refractive indices. (28) The photodetector according to (26), wherein the reflective layer is a metal film having a portion opened. (29) The photodetector according to (28), wherein the metal film is a wiring material of a wiring layer. (30) The photodetector according to any of (1) to (29), wherein the pixel further includes a reflective deflector having an uneven shape on a surface opposite to the light-receiving surface side of the semiconductor substrate. (31) The photodetector according to any of (1) to (30), wherein the light-guiding section has a tapered shape on the light-receiving surface side of the semiconductor substrate.

[0239] 1 Photodetector, 10 Pixel array section, 30 Column signal processing section, 40 Control section, 50 Pixel, 71 Photoelectric conversion section, 71-1 First photoelectric conversion section, 71-2 Second photoelectric conversion section, 72 Charge storage section, 73 to 76 MOS transistor, 101 Semiconductor substrate, 102 Wiring layer, 103 Fixed charge film, 104 Anti-reflection film, 105 Substrate surface film, 106 Insulating film, 107 Light-shielding film section, 108 First metal film, 109 Second metal film, 110 On-chip lens, 110A Lens material, 110B Lens material, 111 Anti-reflection film, 112 Opening, 121 Metal wiring, 122 Insulating film, 123 Reflecting layer, 131 Trench section, 132 Diffusion portion, 132A Diffusion portion, 133 Light guide portion, 133A Light guide portion, 133B Light guide portion, 133C Light guide portion, 133D Light guide portion, 134 Air gap, 135 Element isolation portion, 201 Resist, 202 Trench, 211 Resist, 212 Trench, 213 Hard mask, 214 Light guide portion, 221 Three-dimensional polygon, 223 Opening, 225 Resist, 231 Resist, 251 Anti-reflection film, 252 Pillar, 253 Anti-reflection film, 254 Filler, 255 Protective film, 256 Air gap, 261 Metasurface element, 271 Inner lens, 272 Inner lens upper layer film, 301 Insulating film, 302 Silicon, 303 inter-pixel light shielding portion, 304 deflection portion, 310 on-chip lens, 331 reflective deflection portion, 332 insulating film, 351 color filter layer, 361 first semiconductor layer, 362 second semiconductor layer, 363 insulating layer, 500 image processing system, 510 light source portion, 530 imaging device, 540 signal processing portion, 550 authentication processing portion, 560 viewing processing portion, 600 ranging system, 611 ranging device, 612 application portion, 621 object to be measured, 631 emitted light, 632 reflected light, 641 light source portion, 642 light receiving portion, 643 ranging processing portion

Claims

1. A photodetector comprising a pixel array portion in which a plurality of pixels are two-dimensionally arranged on a semiconductor substrate, wherein each pixel includes a photoelectric conversion portion formed on the semiconductor substrate for performing photoelectric conversion in response to incident light, a light condensing portion for condensing the incident light onto the photoelectric conversion portion, and a light guiding portion formed inside the photoelectric conversion portion.

2. The photodetector according to claim 1, wherein the light guiding portion includes a trench portion formed in a depth direction from a light receiving surface of the semiconductor substrate, and a diffusion portion formed at a predetermined depth from the light receiving surface of the semiconductor substrate.

3. The photodetector according to claim 2, wherein the diffusion portion is formed in a three-dimensional polygon including a plane along a crystal plane orientation of the semiconductor substrate.

4. The photodetector according to claim 2, wherein the diffusion portion is formed by a protrusion having a larger planar area than the trench portion.

5. The photodetector according to claim 2, wherein the diffusion portion has voids at least in part.

6. The photodetector according to claim 2, wherein the diffusion portion is formed in a plate shape extending in a planar direction of the semiconductor substrate.

7. The photodetector according to claim 2, wherein the trench portion is formed in a rectangular shape or a hole shape in a plan view, with substantially the same vertical and horizontal directions.

8. The photodetector according to claim 2, wherein the trench portion is formed in a linear shape in a plan view, with one of the vertical and horizontal directions being longer than the other.

9. The photodetector according to claim 2, wherein the diffusion portion is provided at a tip of the trench portion.

10. The photodetector according to claim 2, wherein the diffusion portion is provided between a light receiving surface of the semiconductor substrate and a tip of the trench portion.

11. The photodetector according to claim 2, wherein the light guiding portion includes a plurality of the diffusion portions.

12. The photodetector according to claim 1, wherein each pixel includes a plurality of the light guiding portions.

13. The photodetector according to claim 1, wherein each pixel further includes an element isolation portion for separating the photoelectric conversion portions of the respective pixels.

14. The photodetector according to claim 1, wherein the light condensing portion is formed of a material containing silicon.

15. The photodetector according to claim 1, wherein the light condensing portion is formed of an organic or inorganic insulating material.

16. The photodetector according to claim 1, wherein the light condensing portion has a curved lens shape.

17. The light condensing unit is formed of a metasurface element in which a plurality of pillars are arranged. The light detection device according to claim 1.

18. In the light guiding unit, the material of the light condensing unit is embedded. The light detection device according to claim 1.

19. The light guiding unit includes a portion in which the material of the light condensing unit is embedded and a portion having a lower refractive index than the material of the light condensing unit. The light detection device according to claim 1.

20. The light guiding unit has a fixed charge film on its side wall. The light detection device according to claim 1.

21. The pixel further includes a light shielding film portion that is located between the photoelectric conversion unit and the light condensing unit and has an opening that allows the incident light condensed by the light condensing unit to pass through. The light detection device according to claim 1.

22. The light shielding film portion is composed of a laminated film including a first metal film on the light condensing unit side and a second metal film on the photoelectric conversion unit side. The first metal film is composed of a film having a lower reflectance than the second metal film. The light detection device according to claim 21.

23. The light shielding film portion is composed of a laminated film including a first dielectric multilayer film on the light condensing unit side and a second dielectric multilayer film on the photoelectric conversion unit side. The first dielectric multilayer film is composed of a film having a lower reflectance than the second dielectric multilayer film. The light detection device according to claim 21.

24. The second dielectric multilayer film is designed for reflection with respect to the wavelength of the incident light to be photoelectrically converted. The light detection device according to claim 23.

25. The pixel further includes a deflection portion having an uneven shape on the light receiving surface side of the semiconductor substrate. The light detection device according to claim 1.

26. The pixel further includes a reflection layer on the surface of the semiconductor substrate opposite to the light receiving surface side. The light detection device according to claim 1.

27. The reflection layer is a laminated film of a plurality of dielectric layers having different refractive indices. The light detection device according to claim 26.

28. The reflection layer is a metal film with a part opened. The light detection device according to claim 26.

29. The metal film is the wiring material of the wiring layer. The light detection device according to claim 28.

30. The pixel further includes a reflection and deflection portion having an uneven shape on the surface of the semiconductor substrate opposite to the light receiving surface side. The light detection device according to claim 1.

31. The light guiding unit has a tapered shape on the light receiving surface side of the semiconductor substrate. The light detection device according to claim 1.

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