Thick, insulating epitaxial strontium titanate, barium strontium titanate or barium titanate on silicon wafers and fabrication methods therefor

Abstract

A material that may be embodied in a wafer. The wafer may include a silicon (Si) substrate. The wafer may also include a nucleation layer formed on the Si substrate. The nucleation layer may include strontium titanate (STO). The wafer may further include an oxide layer formed on the nucleation layer. The oxide layer may include STO, barium strontium titanate (BST) or barium titanate (BTO). The oxide layer may be at least one of: fully oxygenated, more insulating than Si, or fully stoichiometric.

Description

THICK, INSULATING EPITAXIAL STRONTIUM TITANATE, BARIUM STRONTIUM TITANATE OR BARIUM TITANATE ON SILICON WAFERS AND FABRICATION METHODS THEREFORTECHNICAL FIELD

[0001] Various embodiments of the present technology generally relate to fabrication of single crystal oxide layers on silicon (Si) substrates. More specifically, some embodiments of the present technology relate to insulating epitaxial strontium titanate, barium strontium titanate or barium titanate on Si wafers and methods of fabricating the same.BACKGROUND

[0002] Strontium titanate (SrTiO3, abbreviated STO) is one of a handful of oxide materials that can be grown in single crystal form on silicon (Si) wafers. STO is an important oxide single crystal substrate in itself as it is used by the oxide thin film community to grow a wide variety of perovskite structure oxides, which can exhibit properties like ferromagnetism, metallic conductivity, superconductivity, ferroelectricity, etc. At least some known STO substrate materials are only readily available as 1 inch wafers at a cost of, for example, 270 U.S. dollars each. Reduction of the per area cost of STO substrate materials is thus a commercially relevant pursuit given that Si is readily available as 8 inch or even 12 inch wafers.

[0003] In a known process, STO may be grown epitaxially on Si using molecular beam epitaxy (MBE), which is a very slow process. STO films grown by MBE also suffer from a high degree of oxygen deficiency making as-grown films conductive. Turning them insulating may require a prolonged anneal in flowing oxygen after the growth. Furthermore, at least some known MBE- grown STO will be practically capped at 100 nm thickness. As MBE-grown STO films on Si require post-deposition annealing for several hours in oxygen since the as-grown films are oxygendeficient and quite conductive, opportunities exist in the field to increase the time and costefficiency (e.g., reducing per area cost) of known processes for growing STO directly on Si.

[0004] Accordingly, a need exists for technology that overcomes the problems demonstrated above, as well as one that provides additional benefits. The examples provided herein of some prior or related devices, systems and methods, and their associated limitations, are intended to be illustrative and not exclusive. Other limitations of existing or prior methods and systems will become apparent to those of skill in the art upon reading the following detailed description.SUMMARY

[0005] Embodiments of the present technology may provide a wafer of STO that is insulating as grown, single crystal, and has a thickness exceeding 200 nm. A 2 nm nucleation layer of MBE- grown STO is first deposited and then this thin STO layer is used as a seed for subsequent rapid STO growth using off-axis RF sputtering. The film remains epitaxial and of high crystalline quality even after rapid growth. Due to the high oxygen pressure during sputtering, the as-grown film is already insulating, thereby removing the need for time-consuming and costly post-deposition oxygen annealing needed for MBE-grown STO.

[0006] Additionally, embodiments of the present technology may provide a fabrication process for making a wafer of single crystal oxide on a silicon carrier substrate. The STO layer is highly insulating and can be grown to very large thicknesses with similar quality to MBE-grown STO on Si. This can allow for oxide film growers to have access to a large area STO substrate as Si wafers are available in large sizes (8", 12"), which can allow for either more time and cost-efficient mass production, or to test multiple devices at the same time.

[0007] A first aspect of the disclosure provides a new material. The material may be embodied in a wafer. The wafer may include a silicon (Si) substrate. The wafer may also include a nucleation layer formed on the Si substrate. The nucleation layer may include strontium titanate (STO). The wafer may further include an oxide layer formed on the nucleation layer. The oxide layer may include STO, barium strontium titanate (BST) or barium titanate (BTO). The oxide layer may be fully oxygenated. The oxide layer may be more insulating than Si. The oxide layer may be fully stoichiometric.

[0008] A second aspect of the disclosure provides another new material. The material may be embodied in a wafer. The wafer may include an Si substrate. The wafer may also include a nucleation layer formed on the Si substrate. The nucleation layer may include STO. The wafer may further include a buffer layer formed on the nucleation layer. The buffer layer may include STO, BST or BTO. The wafer may also include an oxide layer formed on the buffer layer. The oxide layer may include STO, BST or BTO. The oxide layer may be fully oxygenated. The oxide layer may be more insulating than Si. The oxide layer may be fully stoichiometric.

[0009] A third aspect of the disclosure provides a method or process for making the new material of the first aspect of the disclosure. The method or process may be a method for fabricating the wafer according to the first aspect. The method may include the step ofdepositing, on an Si substrate, a nucleation layer including STO. The method may also include the step of depositing, using radio frequency (RF) sputtering and on the nucleation layer, an oxide layer including STO, BST or BTO.

[0010] A fourth aspect of the disclosure provides a method or process for making the new material of the second aspect of the disclosure. The method or process may be a method for fabricating the wafer according to the second aspect. The method may include the step of depositing, on an Si substrate, a nucleation layer including STO. The method may also include the step of depositing, on the nucleation layer, a buffer layer including STO, BST, or BTO. The method may further include the step of depositing, using radio frequency (RF) sputtering and on the buffer layer, an oxide layer including STO, BST or BTO.

[0011] The oxide layer so formed using the method according to the third or fourth aspects may be at least one of: fully oxygenated, more insulating than Si, and fully stoichiometric.

[0012] Embodiments of the present technology shown and described herein may enable commercial and practical improvements to oxide (e.g., STO) on silicon wafers and associated fabrication methods to thereby realize increased oxide layer thicknesses above those achievable by MBE-based techniques alone, while simultaneously decreasing per area costs of known processes for growing oxides like STO directly on Si.

[0013] While multiple embodiments are disclosed, still other embodiments of the present invention will become apparent to those skilled in the art from the following detailed description, which shows and describes illustrative embodiments of the invention. As will be realized, the invention is capable of modifications in various aspects, all without departing from the scope of the present invention. Accordingly, the drawings and detailed description are to be regarded as illustrative in nature and not restrictive.BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Embodiments of the present technology will be described and explained through the use of the accompanying drawings.

[0015] FIG. 1 depicts a cross-sectional view of a wafer, according to some embodiments of the present technology.

[0016] FIG. 2 depicts a flowchart of a method for manufacturing a wafer, according to some embodiments of the present technology.

[0017] FIG. 3 depicts a cross section transmission electron microscopy (TEM) image of a wafer as in FIG. 1 and fabricated using the method of FIG. 2, according to some embodiments of the present technology.

[0018] FIG. 4 depicts a plot of high resolution x-ray diffraction (XRD) results for a wafer having the stack layers of FIG. 1 as fabricated using the method of FIG. 2, according to some embodiments of the present technology. The scan highlights the insulating oxide layer in the form of STO.

[0019] FIG. 5 depicts another plot of XRD results for a wafer having the stack layers of FIG. 1 as fabricated using the method of FIG. 2, according to some embodiments of the present technology. This scan shows the single orientation of the oxide layer (STO) on top of the silicon substrate.

[0020] FIG. 6 depicts a cross-sectional view of a wafer, according to other embodiments of the present technology.

[0021] FIG. 7 depicts a flowchart of a method for manufacturing a wafer, according to other embodiments of the present technology.

[0022] FIG. 8 depicts a cross section TEM image of a wafer as in FIG. 6 and fabricated using the method of FIG. 7, according to other embodiments of the present technology.

[0023] FIG. 9 is a photograph of a 2 inch wafer material produced using method of FIG. 2, according to an embodiment of the present technology.

[0024] FIGS. 10A and 10B depict reflection high energy electron diffraction (RHEED) images along the <110> direction and the <100> direction, respectively, of the RF sputtered STO of the oxide layer of the wafer shown in FIG. 9.

[0025] FIG. 11 depicts an X-ray diffraction (XRD) rocking curve around the STO 200 Bragg peak of the RF sputtered STO of the oxide layer of the wafer shown in FIG. 9.

[0026] The drawings have not necessarily been drawn to scale. Similarly, some components and / or operations may be separated into different blocks or combined into a single block for the purposes of discussion of some of the embodiments of the present technology. Moreover, while the technology is amenable to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and are described in detail below. The intention, however, is not to limit the technology to the particular embodimentsdescribed. On the contrary, the technology is intended to cover all modifications, equivalents, and alternatives falling within the scope of the technology as defined by the appended claims. DETAILED DESCRIPTION

[0027] Various embodiments of the present technology generally relate to fabrication of single crystal oxide layers on silicon (Si) substrates. More specifically, some embodiments of the present technology relate to insulating epitaxial strontium titanate on Si wafers and methods of fabricating the same.

[0028] The present technology includes a wafer of STO that is insulating as grown, single crystal, and has thicknesses exceeding 200 nm. A 2 nm nucleation layer of MBE-grown STO may be first deposited, and then this thin STO layer may be used as a seed for subsequent rapid STO growth using off-axis RF sputtering. The film remains epitaxial and of high crystalline quality even after rapid growth. Due to the high oxygen pressure during sputtering, the as-grown film is already insulating, thereby removing the need for time-consuming and costly post-deposition oxygen annealing needed for MBE-grown STO.

[0029] The present technology also includes a way of making a wafer of single crystal oxide on a silicon carrier substrate. The STO layer is highly insulating and can be grown to very large thicknesses with similar quality to MBE-grown STO on Si. This can allow for oxide film growers to have access to a large area STO substrate as Si wafers are available in large sizes (e.g., 8", 12"), which can allow for either more time and cost-efficient mass production, or to test multiple devices at the same time.

[0030] In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the present technology. It will be apparent, however, to one skilled in the art that embodiments of the present technology may be practiced without some of these specific details.

[0031] The phrases "in some embodiments," "according to some embodiments," "in the embodiments shown," "in other embodiments," and the like generally mean the particular feature, structure, or characteristic following the phrase is included in at least one implementation of the present technology and may be included in more than one implementation. In addition, such phrases do not necessarily refer to the same embodiments or different embodiments.

[0032] A commercial-size (e.g., 8" or 12") silicon or silicon-on-insulator wafer may be used as the starting substrate. The native oxide may be removed using an strontium (Sr)-assisted oxide desorption process. After this, a1monolayer of Sr may be chemisorbed on the surface to prevent oxidation of Si. Then STO may be deposited by MBE to a thickness of 1.5-2 nm and crystallized in vacuum by a 5 min anneal at 550 °C. The templated Si is then transferred to an off-axis RF sputtering system. STO may be deposited onto the templated Si at 550 °C in 20 mTorr of an 80:20 Ar:O2gas mixture from a stoichiometric STO sputtering target. The growth rate may be about 5 nm / min. By growing at the right geometry, a high crystalline quality STO layer can be grown as thick as needed. The Applicant envisions that 200 nm - 500 nm may be of interest to some customers. A 500 nm film will take almost 21 hours by MBE, but will take under 2 hours with the process described herein according to the present technology. Most MBE grown STO will be practically capped at 100 nm thickness. Radio frequency (RF) sputtering also has the advantage that composition does not drift during growth, unlike MBE, where one needs to adjust fluxes constantly.

[0033] The sputter-grown films are already insulating as grown and do not require any postdeposition annealing. MBE-grown films will require post-deposition annealing for several hours in oxygen as the as-grown films are oxygen-deficient and quite conductive. Both the growth rate speed up and the exclusion of the annealing requirement greatly save time, energy, and / or material cost for making bulk-like STO wafers on Si or SOI substrates.Thick, Insulating Epitaxial Strontium Titanate on Silicon WafersEXAMPLE 1

[0034] FIG. 1 depicts a cross-sectional view of a wafer 100, according to some embodiments of the present technology. Wafer 100 may include a silicon (Si) substrate 110. Wafer 100 may also include a nucleation layer 120 including strontium titanate (STO) formed on the Si substrate 110. Wafer 100 may further include an oxide layer 130 including STO, barium strontium titanate (BST) or barium titanate (BTO) formed on the nucleation layer 120. The oxide layer 130 may be fully oxygenated. The oxide layer 130 may be more insulating than Si. The oxide layer 130 may be fully stoichiometric. The oxide layer 130 may be non-conductive.

[0035] In the wafer 100 according to the present technology, the nucleation layer 120 may prevent Si from being oxidized in a broad temperature range. Si also has a structure to match anoverall lattice structure of oxide layer 130 and, as such, provides an Si template for wafer 100. Si is a semiconductor and is semi-insulating or can be a poor conductor. The oxide layer 130 of wafer 100 is fully insulating because it is not annealed during its fabrication0that makes it insulating and provides it a bandgap of three times that of Si. This property is believed to be unique among materials and a useful advance over known materials and wafers having oxide layers including STO, BST or BTO. As used herein, the phrase "fully insulating" means the oxide layer according to the present technology (e.g., layer 130 or layer 240, as described below with reference to FIG. 6) is more insulating than Si. More specifically, "fully insulating" may mean that the oxide layer according to the present technology has a sheet resistance of greater than or equal to 1 gigaohm (GQ) per square or greater than or equal to about 1 GQ per square, or has a resistivity of greater than or equal to 1 GQ-cm or greater than or equal to about 1 GQ-cm. The advantageous property of the oxide layer according to the present technology being fully insulating may arise from the removal of oxygen vacancies in the MBE-deposited STO in the nucleation layer (e.g., layer 120 or layer 220, as described below with reference to FIG. 6).

[0036] In some embodiments, the Si substrate 110 of wafer 100 may be an Si wafer. In an example, the Si wafer may have a diameter of from 1 inch to 18 inches. In another example, the Si wafer may have a diameter of from about 1 inch to about 18 inches. In yet another example, the Si wafer may have a diameter of from 8 inches to 12 inches. In still another example, the Si wafer may have a diameter of from about 8 inches to about 12 inches. In another example, the Si wafer may have a diameter of from 4 inches to 8 inches. In yet another example, the Si wafer may have a diameter of from about 4 inches to about 8 inches. In still another example, the Si wafer may have a diameter of from 1 inch to 4 inches. In another example, the Si wafer may have a diameter of from about 1 inch to about 4 inches. In another example, the Si wafer may have a diameter of from 1 inch to 2 inches. In yet another example, the Si wafer may have a diameter of from about 1 inch to about 2 inches.

[0037] As used herein, the term "about" means approximately equal to the stated value, such as within a tolerance (±) range of the stated value that allows for variation in precision and / or accuracy as between two or more instruments of the same, or different, type, operators, or techniques, taking the measurement resulting in the value of the particular parameter (e.g., for comparison to the stated value). Depending on such factors as, for example and without limitation, the size or magnitude of the value, conditions under which the measurement istaken, conversions from standard units to metric or SI units, the nature of the measured physical or chemical property corresponding to the stated value, the availability of art- recognized standard measurements (e.g., as maintained by NIST or another formal or informal standards seting body), among other factors, "about" may take on a more narrow definition. As applied to a value or range of values for wafer diameter as described and / or claimed herein, "about" means that the value or range of values may vary by up to ± 0.3 inches from the stated value(s). As applied to a value or range of values for layer thickness as described and / or claimed herein, "about" means that the value or range of values (e.g., in nanometers (nm)) may vary by up to ± 10% from the stated value(s). As applied to a value or range of values for a fraction of a monolayer (e.g., a quarter, or a half, a monolayer) as described and / or claimed herein, "about" means that the value or range of values may vary by up to ± 20% from the stated value(s). As applied to a value or range of values for annealing temperature as described and / or claimed herein, "about" means that the value or range of values in degrees (e.g., °C) may vary by up to ± 50 °C from the stated value(s). As applied to a value or range of values for sheet resistance as described and / or claimed herein, "about" means that the value or range of values in GQ per square may vary by an extent defined by an accuracy or precision of instrumentation used to measure the sheet resistance. As applied to a value or range of values for pressure (e.g., mTorr) as described and / or claimed herein, and when the stated value or range of pressure values is within, or is, 10 mTorr - 30 mTorr, "about" means that the value or range of values in mTorr may vary by up to ± 5 mTorr from the stated value(s). As applied to a value or range of values for pressure (e.g., mTorr) as described and / or claimed herein, and when the stated value or range of pressure values is within, or is, 2 mTorr - 10 mTorr, "about" means that the value or range of values in mTorr may vary by up to ± 1-2 mTorr from the stated value(s). As applied to a value or range of values for pressure (e.g., mTorr) as described and / or claimed herein, and when the stated value or range of pressure values is within, or is, 0.1 mTorr - 2 mTorr, "about" means that the value or range of values in mTorr may vary by up to ± 0.05 mTorr from the stated value(s). As applied to a value or range of values for a ratio of argon gas to oxygen gas content of a mixture of those gases (e.g., Ar:O2) as described and / or claimed herein, "about" means that the value or range of values of such ratio may vary by up to ± 10% from the stated value(s). As applied to a value or range of values for a growth rate (e.g., nanometers per minute (nm / min)) as described and / or claimed herein, "about" means that the value or range of valuesof such ratio may vary by up to ± 10% from the stated value(s). As applied to a value or range of values for lattice constants as described and / or claimed herein, "about" means that the value or range of values may vary by up to ± 0.02 angstroms (A) from the stated value(s).

[0038] In one embodiment, the Si substrate 110 of wafer 100 may be a silicon-on-insulator (SOI) wafer. In an example, the SOI wafer may have a diameter of from 1 inch to 18 inches. In another example, the SOI wafer may have a diameter of from about 1 inch to about 18 inches. In yet another example, the SOI wafer may have a diameter of from 8 inches to 12 inches. In still another example, the SOI wafer may have a diameter of from about 8 inches to about 12 inches. In another example, the SOI wafer may have a diameter of from 4 inches to 8 inches. In yet another example, the SOI wafer may have a diameter of from about 4 inches to about 8 inches. In still another example, the SOI wafer may have a diameter of from 1 inch to 4 inches. In another example, the SOI wafer may have a diameter of from about 1 inch to about 4 inches. In yet another example, the SOI wafer may have a diameter of from 1 inch to 2 inches. In yet another example, the SOI wafer may have a diameter of from about 1 inch to about 2 inches.

[0039] In some embodiments, the nucleation layer 120 of wafer may include, or comprise, STO. In other embodiments, the nucleation layer 120 of wafer 100 may consist essentially of STO. In another embodiment, nucleation layer 120 of wafer 100 may consist of STO. In an example, an interface between the nucleation layer 120 and the Si substrate 110 may include a quarter (%) to a half (%) of a monolayer 160 of strontium (Sr) formed on a surface 170 of the Si substrate 110 between the Si substrate 110 and the nucleation layer 120. In another example, the interface between the nucleation layer 120 and the Si substrate 110 may include about a quarter (%) to about a half (%) of a monolayer 160 of Sr formed on the surface 170 of the Si substrate 110 between the Si substrate 110 and the nucleation layer 120.

[0040] In one embodiment, the oxide layer 130 may include, or comprise, STO. In another embodiment, the oxide layer 130 may consist essentially of STO. In yet another embodiment, the oxide layer 130 may consist of STO. In the wafer 100 according to the present technology, the STO of the oxide layer 130 may be epitaxial STO and thus also single crystal STO. That is, the epitaxial STO of oxide layer 130 may provide the single crystal STO property of the oxide layer 130 in wafer 100. In an example, the oxide layer 130 may include, or comprise, epitaxial STO. In another example, the oxide layer 130 may consist essentially of epitaxial STO. In yet another example, the oxide layer 130 may consist of epitaxial STO.

[0041] In some embodiments, the oxide layer 130 may include, or comprise, BTO. In another embodiment, the oxide layer 130 may consist essentially of BTO. In yet another embodiment, the oxide layer 130 may consist of BTO. In the wafer 100 according to the present technology, the BTO of the oxide layer 130 may be epitaxial BTO and thus also single crystal BTO. That is, the epitaxial BTO of oxide layer 130 may provide the single crystal BTO property of the oxide layer 130 in wafer 100. In an example, the oxide layer 130 may include, or comprise, epitaxial BTO. In another example, the oxide layer 130 may consist essentially of epitaxial BTO. In yet another example, the oxide layer 130 may consist of epitaxial BTO.

[0042] In some embodiments, the oxide layer 130 may include, or comprise, BST. In another embodiment, the oxide layer 130 may consist essentially of BST. In yet another embodiment, the oxide layer 130 may consist of BST. In the wafer 100 according to the present technology, the BST of the oxide layer 130 may be epitaxial BST and thus also single crystal BST. That is, the epitaxial BST of oxide layer 130 may provide the single crystal BST property of the oxide layer 130 in wafer 100. In an example, the oxide layer 130 may include, or comprise, epitaxial BST. In another example, the oxide layer 130 may consist essentially of epitaxial BST. In yet another example, the oxide layer 130 may consist of epitaxial BST.

[0043] In one embodiment, the oxide layer 130 of wafer 100 may be integrated epitaxially onto the Si substrate 110 via the nucleation layer 120. The nucleation layer 120 and the oxide layer 130 may each be formed to respectively specified thicknesses in wafer 100. In some embodiments, the nucleation layer 120 may have a first thickness and the oxide layer 130 may have a second thickness that is greater than the first thickness. In other embodiments, the second thickness of the oxide layer 130 may be less than the first thickness of the nucleation layer 120. In another embodiment, the aforementioned first and second thicknesses may be equal. In still other embodiments, the aforementioned first and second thicknesses may be about equal.

[0044] In an example, the nucleation layer 120 may have a thickness of from 0.5 nanometer (nm) to 5 nm. In another example, the nucleation layer 120 may have a thickness of from about 0.5 nm to about 5 nm. In yet another example, the nucleation layer 120 may have a thickness of 5 nm. In still another example, the nucleation layer 120 may have a thickness of about 5 nm. In still another example, the nucleation layer 120 may have a thickness of from 0.5 nanometer (nm) to 4 nm. In another example, the nucleation layer 120 may have a thickness of from about0.5 nm to about 4 nm. In yet another example, the nucleation layer 120 may have a thickness of from 1 nm to 3 nm. In still another example, the nucleation layer 120 may have a thickness of from about from 1 nm to about 3 nm. In another example, the nucleation layer 120 may have a thickness of from 1.5 nm to 2 nm. In yet another example, the nucleation layer 120 may have a thickness of from about from 1.5 nm to about 2 nm. In practice, it may be advantageous to have nucleation layer 120 be as thin as possible in wafer 100 so as to minimize the time required to move from deposition of the nucleation layer 120 (e.g., using MBE) to deposition of the oxide layer 130 on top of the nucleation layer 120 (e.g., using the faster technique of RF sputtering).

[0045] In an example, the oxide layer 130 may have a thickness of from 0.4 nm to 2000 nm. In another example, the oxide layer 130 may have a thickness of from about 0.4 nm to about 2000 nm. In yet another example, the oxide layer 130 may have a thickness of from 1.5 nm to 1000 nm. In still another example, the oxide layer 130 may have a thickness of from about from 1.5 nm to about 1000 nm. In another example, the oxide layer 130 may have a thickness of from 2.0 nm to 900 nm. In yet another example, the oxide layer 130 may have a thickness of from about from 2.0 nm to about 900 nm. In still another example, the oxide layer 130 may have a thickness of from 50 nm to 800 nm. In another example, the oxide layer 130 may have a thickness of from about from 50 nm to about 800 nm. In yet another example, the oxide layer 130 may have a thickness of from 100 nm to 700 nm. In still another example, the oxide layer 130 may have a thickness of from about 100 nm to about 700 nm. In another example, the oxide layer 130 may have a thickness of from 150 nm to 600 nm. In yet another example, the oxide layer 130 may have a thickness of from about 150 nm to about 600 nm. In still another example, the oxide layer 130 may have a thickness of from 200 nm to 500 nm. In another example, the oxide layer 130 may have a thickness of from about 200 nm to about 500 nm.

[0046] In some embodiments, the Si substrate 110 of wafer 100 may be, or may include, silicon (001). In an example with wafer 100 having the Si (001) substrate 110, the oxide layer 130 may be, or may include, STO (001). In another example with wafer 100 having the Si (001) substrate 110, the oxide layer 130 may be, or may include, BTO (001). In yet another example with wafer 100 having the Si (001) substrate 110, the oxide layer 130 may be, or may include, BST (001). In other embodiments, the Si substrate 110 of wafer 100 may be, or may include, silicon (111). In an example with wafer 100 having the Si (111) substrate 110, the oxide layer 130 may be, or may include, STO (111). In another example with wafer 100 having the Si (111) substrate 110,the oxide layer 130 may be, or may include, BTO (111). In yet another example with wafer 100 having the Si (111) substrate 110, the oxide layer 130 may be, or may include, BST (111).

[0047] In one embodiment, the wafer 100 may also include a buffer layer 140 formed on the nucleation layer 120 and positioned between the nucleation layer 120 and the oxide layer 130. In an example, the buffer layer 140 may be, or may include, STO. In another example, the buffer layer 140 may be, or may include, BST. In yet another example, the buffer layer 140 may be, or may include, BTO.

[0048] In some embodiments, at least a portion of the oxide layer 130 may be at least one of: etched, polished, and annealed. Such modifications to the oxide layer 130 of wafer 100 may be made to the oxide layer 130 in preparation for additional layer(s) or film(s) that may be formed on the oxide layer 130 for a particular product or other application of the wafer 100 according to the present technology. In one embodiment, wafer 100 may also include at least one device 150 formed in or on the oxide layer 130. The at least one device 150 may include at least one of: a microelectronic device, an optoelectronic device, a micro-electromechanical system (MEMS), an integrated circuit, a transistor, a sensor, a Josephson junction, a capacitor, and a semiconductor device.EXAMPLE 2

[0049] FIG. 6 depicts a cross-sectional view of a wafer 200, according to other embodiments of the present technology. Wafer 200 may include an Si substrate 210. Wafer 200 may also include a nucleation layer 220 including STO formed on the Si substrate 210. Wafer 200 may further include a buffer layer 230 including STO, BST or BTO formed on the nucleation layer 220. Wafer 200 may also include an oxide layer 240 including STO, BST or BTO formed on the nucleation layer 220. The oxide layer 240 may be fully oxygenated. The oxide layer 240 may be more insulating than Si. The oxide layer 240 may be fully stoichiometric. The oxide layer 240 may be non-conductive.

[0050] In some embodiments, the buffer layer 230 of wafer 200 may consist essentially of STO. In other embodiments, buffer layer 230 of wafer 200 may consist of STO. In some embodiments, the buffer layer 230 of wafer 200 may consist essentially of BST. In other embodiments, buffer layer 230 of wafer 200 may consist of BST. In some embodiments, the buffer layer 230 of wafer 200 may consist essentially of BTO. In other embodiments, buffer layer 230 of wafer 200 may consist of BTO.

[0051] The Si substrate 210, the nucleation layer 220 and the oxide layer 240 of the wafer 200 of Example 2 and as shown in FIG. 6 may have any of the features, properties, or additional components as described above with reference to Example 1 and as shown in FIG. 1.Methods for Manufacturing Thick, Insulating Epitaxial Strontium Titanate on Silicon WafersEXAMPLE 3

[0052] FIG. 2 depicts a flowchart of a method 300 for manufacturing wafer 100, according to some embodiments of the present technology. With further reference being made to features of wafer 100 described above and as shown in FIG. 1, method 300 may include the step of depositing 310 nucleation layer 120 including STO on silicon (Si) substrate 110. Method 300 may also include the step of depositing 320, using RF sputtering, oxide layer 130 including STO, BST or BTO on nucleation layer 120. In one embodiment, the method 300 step of depositing 310 the nucleation layer 120 on the Si substrate 110 may include depositing the nucleation layer 120 using a molecular beam epitaxy (MBE) process.

[0053] In some embodiments, method 300 may also include the step of removing, prior to depositing 310 the nucleation layer 310, native oxide from a surface of the Si substrate 110 upon which the nucleation layer 120 is to be formed. In an example, the aforementioned removing step of method 200 may include removing the native oxide using a strontium (Sr)- assisted oxide desorption process. In one embodiment, method 300 may also include chemisorbing Sr onto a surface 170 of the Si substrate 110 prior to forming the nucleation layer 120. Chemisorbing Sr onto surface 170 in method 200 may be performed after removal of the native oxide from Si substrate 110. In an example, the method 300 step of chemisorbing Sr onto surface 170 may include chemisorbing a quarter (%) to a half (1 / 2) of a monolayer 160 of Sr onto the surface 170 of the Si substrate 110. In another example, the method 300 step of chemisorbing Sr onto surface 170 may include chemisorbing about a % to about a1of a monolayer 160 of Sr onto the surface 170 of the Si substrate 110.

[0054] In one embodiment, method 300 may include crystallizing the STO of the nucleation layer 120 in vacuum. Method 300 may include the step of annealing the nucleation layer 120. In an example, annealing nucleation layer 120 in method 300 may include annealing the nucleation layer 120 at 500 -600 °C. In another example, annealing nucleation layer 120 in method 300 may include annealing the nucleation layer 120 at a temperature of from about500 °C to about 600 °C. In yet another example, annealing nucleation layer 120 in method 300 may include annealing the nucleation layer 120 at 550 °C. In still another example, annealing nucleation layer 120 in method 300 may include annealing the nucleation layer 120 at about 550 °C.

[0055] In some embodiments, depositing 310 the nucleation layer 120 in method 300 may include depositing the nucleation layer 120 on an Si wafer. In an example, depositing the nucleation layer 120 on the Si wafer may include depositing the nucleation layer 120 on an Si wafer having a diameter of from 1 inch to 18 inches. In another example, depositing the nucleation layer 120 on the Si wafer may include depositing the nucleation layer 120 on an Si wafer having a diameter of from about 1 inch to about 18 inches. In yet another example, depositing the nucleation layer 120 on the Si wafer may include depositing the nucleation layer 120 on an Si wafer having a diameter of from 8 inches to 12 inches. In still another example, depositing the nucleation layer 120 on the Si wafer may include depositing the nucleation layer 120 on an Si wafer having a diameter of from about 8 inches to about 12 inches. In another example, depositing the nucleation layer 120 on the Si wafer may include depositing the nucleation layer 120 on an Si wafer having a diameter of from 4 inches to 8 inches. In yet another example, depositing the nucleation layer 120 on the Si wafer may include depositing the nucleation layer 120 on an Si wafer having a diameter of from about 4 inches to about 8 inches. In still another example, depositing the nucleation layer 120 on the Si wafer may include depositing the nucleation layer 120 on an Si wafer having a diameter of from 1 inch to 4 inches. In another example, depositing the nucleation layer 120 on the Si wafer may include depositing the nucleation layer 120 on an Si wafer having a diameter of from about 1 inch to about 4 inches. In yet another example, depositing the nucleation layer 120 on the Si wafer may include depositing the nucleation layer 120 on an Si wafer having a diameter of from 1 inch to 2 inches. In still another example, depositing the nucleation layer 120 on the Si wafer may include depositing the nucleation layer 120 on an Si wafer having a diameter of from about 1 inch to about 2 inches.

[0056] In one embodiment, depositing 310 the nucleation layer 120 in method 300 may include depositing the nucleation layer 120 on a silicon-on-insulator (SOI) wafer. In an example, depositing the nucleation layer 120 on the SOI wafer may include depositing the nucleation layer 120 on an SOI wafer having a diameter of from 1 inch to 18 inches. In another example,depositing the nucleation layer 120 on the SOI wafer may include depositing the nucleation layer 120 on an SOI wafer having a diameter of from about 1 inch to about 18 inches. In yet another example, depositing the nucleation layer 120 on the SOI wafer may include depositing the nucleation layer 120 on an SOI wafer having a diameter of from 8 inches to 12 inches. In still another example, depositing the nucleation layer 120 on the SOI wafer may include depositing the nucleation layer 120 on an SOI wafer having a diameter of from about 8 inches to about 12 inches. In another example, depositing the nucleation layer 120 on the SOI wafer may include depositing the nucleation layer 120 on an SOI wafer having a diameter of from 4 inches to 8 inches. In yet another example, depositing the nucleation layer 120 on the SOI wafer may include depositing the nucleation layer 120 on an SOI wafer having a diameter of from about 4 inches to about 8 inches. In still another example, depositing the nucleation layer 120 on the SOI wafer may include depositing the nucleation layer 120 on an SOI wafer having a diameter of from 1 inch to 4 inches. In another example, depositing the nucleation layer 120 on the SOI wafer may include depositing the nucleation layer 120 on an SOI wafer having a diameter of from about 1 inch to about 4 inches. In yet another example, depositing the nucleation layer 120 on the SOI wafer may include depositing the nucleation layer 120 on an SOI wafer having a diameter of from 1 inch to 2 inches. In still another example, depositing the nucleation layer 120 on the SOI wafer may include depositing the nucleation layer 120 on an SOI wafer having a diameter of from about 1 inch to about 2 inches.

[0057] In some embodiments, depositing 310 the nucleation layer 120 in method 300 may include depositing the nucleation layer 120 on an Si (001) substrate 110. In an example, the method 300 step of depositing 320 the oxide layer 130 on the nucleation layer 120 may include depositing the oxide layer 130 of, or including, STO (001) on the Si (001) substrate 110. In yet another example, the method 300 step of depositing 320 the oxide layer 130 on the nucleation layer 120 may include depositing the oxide layer 130 of, or including, BST (001) on the Si (001) substrate 110. In still another example, the method 300 step of depositing 320 the oxide layer 130 on the nucleation layer 120 may include depositing the oxide layer 130 of, or including, BTO (001) on the Si (001) substrate 110.

[0058] In some embodiments, depositing 310 the nucleation layer 120 in method 300 may include depositing the nucleation layer 120 on an Si (111) substrate 110. In an example, the method 300 step of depositing 320 the oxide layer 130 on the nucleation layer 120 may includedepositing the oxide layer 130 of, or including, STO (111) on the Si (111) substrate 110. In yet another example, the method 300 step of depositing 320 the oxide layer 130 on the nucleation layer 120 may include depositing the oxide layer 130 of, or including, BST (111) on the Si (111) substrate 110. In still another example, the method 300 step of depositing 320 the oxide layer 130 on the nucleation layer 120 may include depositing the oxide layer 130 of, or including, BTO (111) on the Si (111) substrate 110.

[0059] In one embodiment, the method 300 step of depositing 310 the nucleation layer 120 may include depositing the nucleation layer 120 having a first thickness on the Si substrate 110. In an example, depositing 320 the oxide layer 130 in method 300 may include depositing the oxide layer 130 on the nucleation layer 120 having a second thickness on the Si substrate 110, where the second thickness is greater than the first thickness. In another embodiment, depositing 320 the oxide layer 130 in method 300 may include depositing the oxide layer 130 on the nucleation layer 120 having a second thickness that is less than the first thickness. In yet another example, depositing 320 the oxide layer 130 in method 300 may include depositing the oxide layer 130 on the nucleation layer 120 having a second thickness that is equal to the first thickness. In yet another example, depositing 320 the oxide layer 130 in method 300 may include depositing the oxide layer 130 on the nucleation layer 120 having a second thickness that is about equal to the first thickness.

[0060] In some embodiments, nucleation layer 120 may be deposited 310 on the Si substrate 110 to a specified thickness. In an example, depositing 310 the nucleation layer 120 in method 300 may include depositing the nucleation layer 120 having a thickness of from 0.5 nanometer (nm) to 5 nm on the Si substrate 110. In another example, depositing 310 the nucleation layer 120 in method 300 may include depositing the nucleation layer 120 having a thickness of from about 0.5 nm to about 5 nm on the Si substrate 110. In yet another example, depositing 310 the nucleation layer 120 in method 300 may include depositing the nucleation layer 120 having a thickness of 5 nm on the Si substrate 110. In still another example, depositing 310 the nucleation layer 120 in method 300 may include depositing the nucleation layer 120 having a thickness of from about 5 nm on the Si substrate 110. In an example, depositing 310 the nucleation layer 120 in method 300 may include depositing the nucleation layer 120 having a thickness of from 0.5 nm to 4.0 nm on the Si substrate 110. In another example, depositing 310 the nucleation layer 120 may include depositing the nucleation layer 120 having a thickness offrom about 0.5 nm to about 4.0 nm on the Si substrate 110. In yet another example, depositing 310 the nucleation layer 120 in method 300 may include depositing the nucleation layer 120 having a thickness of from 1.0 nm to 3.0 nm on the Si substrate 110. In still another example, depositing 310 the nucleation layer 120 may include depositing the nucleation layer 120 having a thickness of from about 1.0 nm to about 3.0 nm on the Si substrate 110. In another example, depositing 310 the nucleation layer 120 in method 300 may include depositing the nucleation layer 120 having a thickness of from 1.5 nm to 2.0 nm on the Si substrate 110. In yet another example, depositing 310 the nucleation layer 120 may include depositing the nucleation layer 120 having a thickness of from about 1.5 nm to about 2.0 nm on the Si substrate 110.

[0061] In some embodiments, oxide layer 130 may be deposited 320 on the nucleation layer 120 to a specified thickness. In an example, depositing 320 the oxide layer 130 in method 300 may include depositing the oxide layer 130 having a thickness of from 0.4 nm to 2000 nm on the nucleation layer 120. In another example, depositing 320 the oxide layer 130 in method 300 may include depositing the oxide layer 130 having a thickness of from about 0.4 nm to about 2000 nm on the nucleation layer 120. In yet another example, depositing 320 the oxide layer 130 in method 300 may include depositing the oxide layer 130 having a thickness of from 1.5 nm to 1000 nm on the nucleation layer 120. In still another example, depositing 320 the oxide layer 130 in method 300 may include depositing the oxide layer 130 having a thickness of from about 1.5 nm to about 1000 nm on the nucleation layer 120. In another example, depositing 320 the oxide layer 130 in method 300 may include depositing the oxide layer 130 having a thickness of from 2.0 nm to 900 nm on the nucleation layer 120. In yet another example, depositing 320 the oxide layer 130 in method 300 may include depositing the oxide layer 130 having a thickness of from about 2.0 nm to about 900 nm on the nucleation layer 120. In still another example, depositing 320 the oxide layer 130 in method 300 may include depositing the oxide layer 130 having a thickness of from 50 nm to 800 nm on the nucleation layer 120. In another example, depositing 320 the oxide layer 130 in method 300 may include depositing the oxide layer 130 having a thickness of from about 50 nm to about 800 nm on the nucleation layer 120. In yet another example, depositing 320 the oxide layer 130 in method 300 may include depositing the oxide layer 130 having a thickness of from 100 nm to 700 nm on the nucleation layer 120. In still another example, depositing 320 the oxide layer 130 in method 300 may include depositing the oxide layer 130 having a thickness of from about 100 nm to about700 nm on the nucleation layer 120. In another example, depositing 320 the oxide layer 130 in method 300 may include depositing the oxide layer 130 having a thickness of from 150 nm to 600 nm on the nucleation layer 120. In yet another example, depositing 320 the oxide layer 130 in method 300 may include depositing the oxide layer 130 having a thickness of from about 150 nm to about 600 nm on the nucleation layer 120. In still another example, depositing 320 the oxide layer 130 in method 300 may include depositing the oxide layer 130 having a thickness of from 200 nm to 500 nm on the nucleation layer 120. In another example, depositing 320 the oxide layer 130 in method 300 may include depositing the oxide layer 130 having a thickness of from about 200 nm to about 500 nm on the nucleation layer 120.

[0062] In one embodiment, depositing 320 the oxide layer 130 in method 300 may include RF sputtering STO, BST or BTO onto the nucleation layer 120. The RF sputtering may be performed in method 300 at a specified temperature. In an example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 at 500 °C - 700 °C. In another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 at a temperature of about 500 °C to about 700 °C. In yet another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 at 550 °C. In still another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 at a temperature of about 550 °C. In another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 at 650 °C. In yet another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 at a temperature of about 650 °C.

[0063] In some embodiments, depositing 320 the oxide layer 130 in method 300 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 at specified pressure and composition of the sputtering gas. In an example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 in 0.1 mTorr to 30 mTorr of an 80:20 argo oxygen (Ar:O2) gas mixture (or of an about 80:20 Ar:O2gas mixture). In another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 in about 0.1 mTorr to about 30 mTorr of an 80:20 Ar:O2gas mixture (or of an about 80:20 Ar:O2gas mixture). In yet another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 in 1 mTorr to 30mTorr of an 80:20 Ar:O2gas mixture (or of an about 80:20 Ar:O2gas mixture). In still another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 in about 1 mTorr to about 30 mTorr of an 80:20 Ar:O2gas mixture (or of an about 80:20 Ar:O2gas mixture). In another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 in 1 mTorr to 25 mTorr of an 80:20 Ar:O2gas mixture (or of an about 80:20 Ar:O2gas mixture). In yet another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 in about 1 mTorr to about 25 mTorr of an 80:20 Ar:O2gas mixture (or of an about 80:20 Ar: O2gas mixture). In still another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 in 1 mTorr to 5 mTorr of an 80:20 Ar:O2gas mixture (or of an about 80:20 Ar:O2gas mixture). In another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 in about 1 mTorr to about 5 mTorr of an 80:20 Ar:O2gas mixture (or of an about 80:20 Ar:O2gas mixture). In yet another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 in 3 mTorr of an 80:20 Ar:O2gas mixture (or of an about 80:20 Ar:O2gas mixture). In still another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 in about 3 mTorr of an 80:20 Ar:O2gas mixture (or of an about 80:20 Ar:O2gas mixture). In another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 in 20 mTorr of an 80:20 argo oxygen (Ar:O2) gas mixture. In yet another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 in about 20 mTorr of an 80:20 Ar:O2gas mixture. In still another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 in 20 mTorr of an about 80:20 Ar:O2gas mixture. In another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 in about 20 mTorr of an about 80:20 Ar:O2gas mixture.

[0064] In an example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 in 0.1 mTorr to 30 mTorr of a 70:30 argomoxygen (Ar:O2) gas mixture (or of an about 70:30 Ar:O2gas mixture). In another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 in about 0.1 mTorr to about 30 mTorr of a 70:30 argomoxygen (Ar:O2) gas mixture (or of an about 70:30Ar:O2gas mixture). In yet another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 in 1 mTorr to 30 mTorr of a 70:30 argo oxygen (Ar:O2) gas mixture (or of an about 70:30 Ar:O2gas mixture). In still another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 in about 1 mTorr to about 30 mTorr of a 70:30 argomoxygen (Ar:O2) gas mixture (or of an about 70:30 Ar:O2gas mixture). In another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 in 1 mTorr to 25 mTorr of a 70:30 argomoxygen (Ar:O2) gas mixture (or of an about 70:30 Ar:O2gas mixture). In yet another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 in about 1 mTorr to about 25 mTorr of a 70:30 argomoxygen (Ar:O2) gas mixture (or of an about 70:30 Ar:O2gas mixture). In still another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 in 1 mTorr to 5 mTorr of a 70:30 argomoxygen (Ar:O2) gas mixture (or of an about 70:30 Ar:O2gas mixture). In another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 in about 1 mTorr to about 5 mTorr of a 70:30 argomoxygen (Ar:O2) gas mixture (or of an about 70:30 Ar:O2gas mixture). In yet another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 in 3 mTorr of a 70:30 argomoxygen (Ar:O2) gas mixture (or of an about 70:30 Ar:O2gas mixture). In still another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 in about 3 mTorr of a 70:30 argomoxygen (Ar:O2) gas mixture (or of an about 70:30 Ar:O2gas mixture). In an example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 in 20 mTorr of a 70:30 Ar:O2gas mixture. In another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 in about 20 mTorr of a 70:30 Ar:O2gas mixture. In yet another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 in 20 mTorr of an about 70:30 Ar:O2gas mixture. In still another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 in about 20 mTorr of an about 70:30 Ar:O2gas mixture.

[0065] In one embodiment, depositing 320 the oxide layer 130 in method 300 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 from a stoichiometric STO, BST or BTOsputtering target. In some embodiments, depositing 320 the oxide layer 130 in method 300 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 using an off-axis RF sputtering system.

[0066] In one embodiment, depositing 320 the oxide layer 130 in method 300 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 at specified growth rate. In an example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 at a growth rate of 1 nm per minute (nm / min) to 7 nm / min. In another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 at a growth rate of about 1 nm / min to about 7 nm / min. In yet another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 at a growth rate of 2 nm / min to 6 nm / min. In still another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 at a growth rate of about 2 nm / min to about 6 nm / min. In another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 at a growth rate of 3 nm / min. In yet another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 at a growth rate of about 3 nm / min. In still another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 at a growth rate of 4 nm / min to 6 nm / min. In another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 at a growth rate of about 4 nm / min to about 6 nm / min. In yet another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 at a growth rate of 5 nm / min. In still another example, depositing 320 the oxide layer 130 may include RF sputtering STO, BST or BTO onto the nucleation layer 120 at a growth rate of about 5 nm / min.

[0067] In some embodiments, depositing 320 the oxide layer 130 on the nucleation layer 120 in method 300 may include epitaxially integrating the STO, BST or BTO onto the Si substrate 110 via the nucleation layer 120. In one embodiment, depositing 320 the oxide layer 130 in method 300 may include depositing the oxide layer 130 in the absence of annealing the oxide layer 130, thereby forming a fully oxygenated oxide layer 130. In some embodiments, depositing 320 the oxide layer 130 in method 300 may include depositing the oxide layer 130 as having a greater insulative property than Si. In one embodiment, depositing 320 the oxide layer 130 in method300 may include depositing the oxide layer 130 as a fully stoichiometric oxide layer 130. In some embodiments, method 300 may also include at least one of: etching, polishing, and annealing, at least a portion of the oxide layer 130. Such modifications to the oxide layer 130 of wafer 100 may be made to the oxide layer 130 in preparation for additional layer(s) or film(s) that may be formed on the oxide layer 130 for a particular product application of the wafer 100 according to the present technology. As such, method 300 may further include depositing at least one layer and / or at least one film on the oxide layer 130.

[0068] In one embodiment, method 300 may include depositing a buffer layer 140 on the nucleation layer 120 and positioned between the nucleation layer 120 and the oxide layer 130. In an example, depositing the buffer layer 140 may include depositing the buffer layer 140 of, or including, STO on the nucleation layer 120. In another example, depositing the buffer layer 140 may include depositing the buffer layer 140 of, or including, BST on the nucleation layer 120. In yet another example, depositing the buffer layer 140 may include depositing the buffer layer 140 of, or including, BTO on the nucleation layer 120. The buffer layer 140 may be deposited on the nucleation layer 120 after the nucleation layer 120 is deposited 310 on the Si substrate 110 and before the oxide layer 130 being deposited in method 300.

[0069] In some embodiments, method 300 may include forming at least one device 150 in or on the oxide layer 130 of wafer 100. In an example, forming the at least one device 150 in method may include forming at least one of: a microelectronic device, an optoelectronic device, a micro-electromechanical system (MEMS), an integrated circuit, a transistor, a sensor, a Josephson junction, a capacitor, and a semiconductor device, in or on the oxide layer 130.

[0070] FIG. 3 depicts a cross section transmission electron microscopy (TEM) image of a wafer (e.g., wafer 100) as in FIG. 1 and fabricated using the method 300 of FIG. 2, according to some embodiments of the present technology. FIG. 3 depicts epitaxial STO formed on an Si (001) substrate (labeled 110) according to the present technology. In the example shown in FIG. 3, nucleation layer 120 and oxide layer 130 are both formed of STO. Notably, FIG. 3 demonstrates that, in some embodiments, the present technology may achieve deposition of epitaxial STO on Si in the absence of formation of an interfacial layer of silicon dioxide (SiO2) formed during method 300 on top surface 170 of the Si substrate 110 between Si substrate 110 and oxide layer 130. A capping layer 550 is also shown in FIG. 3. In some embodiments, a capping layer 550 may be formed atop oxide layer 130 as a way to protect layer 130 for shipment or storage of wafer100. For example, and without limitation, such a capping layer 550 may be deposited as amorphous carbon.

[0071] FIG. 4 depicts a plot of high resolution x-ray diffraction (XRD) results for a wafer (e.g., wafer 100) having the stack layers of FIG. 1 as fabricated using the method 300 of FIG. 2, according to some embodiments of the present technology. The plot of FIG. 4 provides counts per second (cps) data for a 2theta / theta XRD scan. The XRD scan shown in FIG. 4 demonstrates an STO 200 Bragg peak from a wafer 100 having an oxide layer 130 formed of STO and having a thickness of 65 nm. The results shown in FIG. 4 further demonstrate a strong crystallinity of STO in the oxide layer 130 fabricated according to the present technology using method 300. Additionally, the XRD results provided in FIG. 4 demonstrate that the STO in the oxide layer 130 has a latice constant of 3.902 angstroms (A), In other embodiments, the STO in the oxide layer 130 may have a latice constant of about 3.902 A.

[0072] FIG. 5 depicts another plot of XRD results for a wafer (e.g., wafer 100) having the stack layers of FIG. 1 as fabricated using the method 300 of FIG. 2, according to some embodiments of the present technology. The plot of FIG. 5 provides counts per second (cps) data for a 2theta / theta XRD scan for a 65 nm oxide layer 130 formed of STO, as in the example described above with reference to FIG. 4. The XRD scan shown in FIG. 5 shows an oxide layer 130 formed of highly insulating epitaxial STO on Si substrate 110 and with the STO having strong crystallinity and a single orientation.EXAMPLE 4

[0073] FIG. 7 depicts a flowchart of a method 400 for manufacturing wafer 200, according to other embodiments of the present technology. With further reference being made to features of wafer 200 described above and as shown in FIG. 6, method 400 may include the step of depositing 410 the nucleation layer 220 including STO on the Si substrate 210. Method 400 may also include the step of depositing 420 the buffer layer 230 of, or including, STO, BST or BTO on the nucleation layer 220. Method 400 may further include the step of depositing 430, using RF sputering, the oxide layer 240 of, or including, STO, BST or BTO on the buffer layer 230. In one embodiment, depositing 410 the nucleation layer 220 on the Si substrate 210 in method 200 may include depositing the nucleation layer 220 using an MBE process. In some embodiments of method 400, depositing 420 the buffer layer 230 on the nucleation layer 220 may include depositing the nucleation layer 220 using an MBE process.

[0074] In some embodiments, depositing the buffer layer 230 on the nucleation layer 220 in method 400 may include forming the buffer layer 230 of, or including, STO, BST and BTO. In an example, depositing 420 the buffer layer 230 includes depositing the buffer layer 230 of, or including, STO on the nucleation layer 220. In another example, depositing 420 the buffer layer 230 includes depositing the buffer layer 230 of, or including, BST on the nucleation layer 220. In yet another example, depositing 420 the buffer layer 230 includes depositing the buffer layer 230 of, or including, BTO on the nucleation layer 220. The buffer layer 230 may be deposited on the nucleation layer 220 after the nucleation layer 220 is deposited 410 on the Si substrate 210 and before the oxide layer 240 being deposited in method 400.

[0075] In one embodiment, depositing 430 the oxide layer 240 on the buffer layer 230 in method 400 may include depositing the oxide layer 240 in the absence of annealing the oxide layer 240, thereby forming a fully oxygenated oxide layer 240. In some embodiments, depositing 430 the oxide layer 240 on the buffer layer 230 in method 400 may include depositing the oxide layer 240 as having a greater insulative property than Si. In one embodiment, depositing 430 the oxide layer 240 on the buffer layer 230 in method 400 may include depositing the oxide layer 240 as a fully stoichiometric oxide layer 240.

[0076] The method 400 steps of depositing 410 the nucleation layer 220 and depositing 430 the oxide layer 240 of Example 4 and as shown in FIG. 7 may have any of the features, process conditions and / or techniques, or additional steps in the method 300 steps of depositing 310 the nucleation layer 120 and depositing 320 the oxide layer 130 as described above with reference to Example 3 and as shown in FIG. 2.

[0077] FIG. 8 depicts a cross section TEM image of a wafer (e.g., wafer 200) as in FIG. 6 and fabricated using the method 400 of FIG. 7, according to other embodiments of the present technology. In the example shown in FIG. 8, nucleation layer 220 and buffer layer 230 are both formed of STO, while oxide layer 240 is formed of BTO. Also shown in FIG. 8 is an interfacial layer 850 formed of SiO2. Some embodiments of wafer 200 fabricated using method 400 may include interfacial layer 850 as a consequence of oxygen diffusion during deposition of oxide layer 240 (e.g., BTO) upon buffer layer 230 (e.g., STO) due to higher temperature and pressure conditions during, for example, step 430 of method 400.Additional Thick, Insulating Epitaxial Strontium Titanate on Silicon Wafer ExampleEXAMPLE 5

[0078] FIG. 9 is a photograph of a 2 inch wafer 100 material produced using method 300, according to an embodiment of the present technology. To produce the wafer 100 shown in FIG. 9, an STO nucleation layer 120 was deposited 310 according to method 300 on a 2 inch Si (001) substrate 110 using MBE to a thickness of 5 nm. An oxide layer 130 of STO was deposited 320 according to method 300 by RF sputtering on the nucleation layer 120 to a thickness of 500 nm. In producing the wafer 100 shown in FIG. 9, the oxide layer 130 was deposited 320 under the following RF sputtering conditions: 3 mTorr of a 70:30 Ar:O2gas mixture at 650 °C growth temperature and 3 nm / min growth rate.

[0079] FIGS. 10A and 10B depict RHEED images along the <110> direction and the <100> direction, respectively, of the RF sputtered STO of the oxide layer 130 of the wafer 100 shown in FIG. 9. The RHEED images shown in FIGS. 10A and 10B demonstrate and provide a qualitative measurement and indication of the surface crystalline quality of the oxide layer 130 film of the final product of wafer 100 material depicted in FIG. 9. The 2D pattern shown in FIGS. 10A and 10B show a predominantly streaked, as opposed to spotted, pattern, thus demonstrating that the STO oxide layer 130 of the wafer 100 of FIG. 9 has a flat crystalline surface that is singlecrystalline and epitaxial. Based on the RHEED images of FIGS. 10A and 10B, the surface roughness of the STO oxide layer 130 of the wafer 100 of FIG. 9 is estimated to be less than 1.0 nm.

[0080] FIG. 11 depicts an XRD rocking curve around STO 200 Bragg peak of the RF sputtered STO of the oxide layer 130 of the wafer 100 shown in FIG. 9. This provides a measurement of how well-stacked the individual atomic layers and how well aligned the crystallographic planes are in the STO oxide layer 130 film. The width of the peak is 0.27 degrees, which indicates excellent crystal plane alignment for an oxide film grown on silicon.

[0081] Embodiments of the present technology shown and described herein may enable commercial and practical improvements to oxide (e.g., STO) on silicon wafers and associated fabrication methods to thereby realize increased oxide layer thicknesses above those achievable by MBE-based techniques alone, while simultaneously decreased per area costs of known processes for growing oxides like STO directly on Si.

[0082] One field that the present technology may positively impact is general epitaxial oxide thin film deposition. The ability to have larger area substrates for oxide deposition makes scalable manufacturing feasible. The integration with Si can allow devices such as sensors to be easily inserted into a silicon-compatible process flow. STO on Si itself has also been shown to be a viable photocathode material for solar water spliting.Conclusion

[0083] Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise," "comprising," and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense° that is to say, in the sense of "including, but not limited to." As used herein, the terms "connected," "coupled," or any variant thereof means any connection or coupling, either direct or indirect, between two or more elements0the coupling or connection between the elements can be physical, logical, or a combination thereof. Additionally, the words "herein," "above," "below," and words of similar import, when used in this application, refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word "or," in reference to a list of two or more items, covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0084] The above Detailed Description of examples of the technology is not intended to be exhaustive or to limit the technology to the precise form disclosed above. While specific examples of the technology are described above for illustrative purposes, various equivalent modifications are possible within the scope of the technology, as those skilled in the relevant art will recognize. The teachings of the technology provided herein can be applied to other devices, systems and methods, not necessarily the devices, systems and methods described above. The elements and acts of the various examples described above can be combined to provide further implementations of the technology. Some alternative implementations of the technology may include not only additional elements to those implementations noted above, but also may include fewer elements.

[0085] These and other changes can be made to the technology in light of the above Detailed Description. While the above description describes certain examples of the technology, anddescribes the best mode contemplated, no matter how detailed the above appears in text, the technology can be practiced in many ways. Details of the above described embodiments may vary considerably in their specific implementations, while still being encompassed by the technology disclosed herein. As noted above, particular terminology used when describing certain features or aspects of the technology should not be taken to imply that the terminology is being redefined herein to be restricted to any specific characteristics, features, or aspects of the technology with which that terminology is associated. In general, the terms used in the following claims should not be construed to limit the technology to the specific examples disclosed in the specification, unless the above Detailed Description section explicitly defines such terms. Accordingly, the actual scope of the technology encompasses not only the disclosed examples, but also all equivalent ways of practicing or implementing the technology under the claims.

[0086] To reduce the number of claims, certain aspects of the technology are presented below in certain claim forms, but the applicant contemplates the various aspects of the technology in any number of claim forms. For example, while only one aspect of the technology is recited as a device or a system, other aspects may likewise be embodied as a method or a process of manufacturing or operating such device or system. In some cases, aspects of the technology may be embodied in a means-plus-function claim. Any claims intended to be treated under 35 U.S.C. § 112(f) will begin with the words "means for", but use of the term "for" in any other context is not intended to invoke treatment under 35 U.S.C. § 112(f). Accordingly, the applicant reserves the right to pursue additional claims after filing this application to pursue such additional claim forms, in either this application or in a continuing application.

Claims

CLAIMSWhat is claimed is:

1. A wafer comprising: a silicon (Si) substrate° a nucleation layer comprising strontium titanate (STO) formed on the Si substrate° and an oxide layer comprising STO, barium strontium titanate (BST) or barium titanate (BTO) formed on the nucleation layer, wherein the oxide layer is fully oxygenated.

2. A wafer comprising: a silicon (Si) substrate° a nucleation layer comprising strontium titanate (STO) formed on the Si substrate° and an oxide layer comprising STO, barium strontium titanate (BST) or barium titanate (BTO) formed on the nucleation layer, wherein the oxide layer is more insulating than Si.

3. A wafer comprising: a silicon (Si) substrate° a nucleation layer comprising strontium titanate (STO) formed on the Si substrate° and an oxide layer comprising STO, barium strontium titanate (BST) or barium titanate (BTO) formed on the nucleation layer, wherein the oxide layer is fully stoichiometric.

4. The wafer of any one of claims 1, 2 and 3, wherein the Si substrate is an Si wafer.

5. The wafer of claim 4, wherein the Si wafer has a diameter of from about 1 inch to about 18 inches.

6. The wafer of any one of claims 1, 2 and 3, wherein the Si substrate is a silicon-on- insulator (SOI) wafer.

7. The wafer of claim 6, wherein the SOI wafer has a diameter of from about 1 inch to about 18 inches.

8. The wafer of any one of claims 1, 2 and 3, wherein the oxide layer is non-conductive.

9. The wafer of any one of claims 1, 2 and 3, wherein the oxide layer comprises epitaxial STO.

10. The wafer of any one of claims 1, 2 and 3, wherein the oxide layer comprises epitaxial BTO.

11. The wafer of any one of claims 1, 2 and 3, wherein the oxide layer comprises epitaxial BST.

12. The wafer of any one of claims 1, 2 and 3, wherein the oxide layer is integrated epitaxially onto the Si substrate via the nucleation layer.

13. The wafer of any one of claims 1, 2 and 3, wherein the nucleation layer has a first thickness, and wherein the oxide layer has a second thickness that is greater than the first thickness.

14. The wafer of any one of claims 1, 2 and 3, wherein the nucleation layer has a first thickness, and wherein the oxide layer has a second thickness that is less than the first thickness.

15. The wafer of any one of claims 1, 2 and 3, wherein the nucleation layer has a first thickness, and wherein the oxide layer has a second thickness that is about equal to the first thickness.

16. The wafer of any one of claims 1, 2 and 3, wherein the nucleation layer has a thickness of from about 0.5 nanometer (nm) to about 5 nm.

17. The wafer of any one of claims 1, 2 and 3, wherein the oxide layer has a thickness of from about 0.4 nm to about 2000 nm.

18. The wafer of any one of claims 1, 2 or 3, further comprising a buffer layer comprising STO, BST or BTO formed on the nucleation layer and positioned between the nucleation layer and the oxide layer.

19. The wafer of any one of claims 1, 2 or 3, further comprising at least one device formed in or on the oxide layer.

20. The wafer of claim 19, wherein the at least one device includes at least one of: a microelectronic device, an optoelectronic device, a micro-electromechanical system (MEMS), an integrated circuit, a transistor, a sensor, a Josephson junction, a capacitor, and a semiconductor device.

21. The wafer of any one of claims 1, 2 and 3, wherein an interface between the nucleation layer and the Si substrate comprises about a quarter (%) to about a half (1 / 2) of a monolayer of strontium (Sr) formed on a surface of the Si substrate between the Si substrate and the nucleation layer.

22. The wafer of any one of claims 1, 2 and 3, wherein the Si substrate comprises silicon (001).

23. The wafer of claim 22, wherein the oxide layer comprises STO (001).

24. The wafer of claim 22, wherein the oxide layer comprises BTO (001).

25. The wafer of claim 22, wherein the oxide layer comprises BST (001).

26. The wafer of any one of claims 1, 2 and 3, wherein the Si substrate comprises silicon(111).

1. The wafer of claim 26, wherein the oxide layer comprises STO (111).

28. The wafer of claim 26, wherein the oxide layer comprises BTO (111).

29. The wafer of claim 26, wherein the oxide layer comprises BST (111).

30. The wafer of any one of claims 1, 2 and 3, wherein a sheet resistance of the oxide layer is greater than or equal to about 1 gigaohm per square.

31. A method comprising: depositing a nucleation layer comprising strontium titanate (STO) on a silicon (Si) substrate° and depositing, using radio frequency (RF) sputtering, an oxide layer comprising STO, barium strontium titanate (BST) or barium titanate (BTO) on the nucleation layer.

32. The method of claim 31 further comprising removing, prior to depositing the nucleation layer, native oxide from a surface of the Si substrate upon which the nucleation layer is to be formed.

33. The method of claim 32, wherein the removing step comprises removing the native oxide using a strontium (Sr)-assisted oxide desorption process.

34. The method of claim 31 further comprising chemisorbing about a quarter (%) to about a half (1 / 2) of a monolayer of Sr onto a surface of the Si substrate prior to forming the nucleation layer.

35. The method of claim 31 further comprising crystallizing the STO of the nucleation layer in vacuum.

36. The method of claim 35 further comprising annealing the nucleation layer at a temperature of about 500 °C to about 600 °C.

37. The method of claim 31, wherein depositing the oxide layer comprises RF sputtering STO, BST or BTO onto the nucleation layer at a temperature of about 500 °C to about 700 °C.

38. The method of claim 31, wherein depositing the oxide layer comprises RF sputtering STO, BST or BTO onto the nucleation layer in about 1 mTorr to about 25 mTorr of an about 80:20 argo oxygen (Ar:O2) gas mixture.

39. The method of claim 31, wherein depositing the oxide layer comprises RF sputtering STO, BST or BTO onto the nucleation layer in about 1 mTorr to about 25 mTorr of an about 70:30 Ar:O2gas mixture.

40. The method of claim 31, wherein depositing the oxide layer comprises RF sputtering STO, BST or BTO onto the nucleation layer from a stoichiometric STO, BST or BTO sputtering target.

41. The method of claim 31, wherein depositing the oxide layer comprises RF sputtering STO, BST or BTO onto the nucleation layer using an off-axis RF sputtering system.

42. The method of claim 31, wherein depositing the oxide layer comprises RF sputtering STO, BST or BTO onto the nucleation layer at a growth rate of about 1 nanometer per minute (nm / min) to about 7 nm / min.

43. The method of claim 31, wherein depositing the oxide layer comprises epitaxially integrating the STO, BST or BTO onto the Si substrate via the nucleation layer.

44. The method of claim 31, wherein depositing the nucleation layer comprises depositing the nucleation layer on an Si wafer.

45. The method of claim 44, wherein depositing the nucleation layer on the Si wafer comprises depositing the nucleation layer on an Si wafer having a diameter of from about 1 inch to about 18 inches.

46. The method of claim 31, wherein depositing the nucleation layer comprises depositing the nucleation layer on a silicon-on-insulator (SOI) wafer.

47. The method of claim 46, wherein depositing the nucleation layer on the Si wafer comprises depositing the nucleation layer on an SOI wafer having a diameter of from about 1 inch to about 18 inches.

48. The method of claim 31, wherein: depositing the nucleation layer comprises depositing the nucleation layer having a first thickness on the Si substrate° and depositing the oxide layer comprises depositing the oxide layer having a second thickness that is greater than the first thickness on the nucleation layer.

49. The method of claim 31, wherein: depositing the nucleation layer comprises depositing the nucleation layer having a first thickness on the Si substrate° and depositing the oxide layer comprises depositing the oxide layer having a second thickness that is less than the first thickness on the nucleation layer.

50. The method of claim 31, wherein: depositing the nucleation layer comprises depositing the nucleation layer having a first thickness on the Si substrate° and depositing the oxide layer comprises depositing the oxide layer having a second thickness that is equal to the first thickness on the nucleation layer.

51. The method of claim 31, wherein depositing the nucleation layer comprises depositing the nucleation layer having a thickness of from about 0.5 nanometer (nm) to about 5 nm on the Si substrate.

52. The method of claim 31, wherein depositing the oxide layer comprises depositing the oxide layer having a thickness of from about 0.4 nm to about 2000 nm on the nucleation layer.

53. The method of claim 31 further comprising depositing a buffer layer comprising STO, BST or BTO on the nucleation layer and positioned between the nucleation layer and the oxide layer.

54. The method of claim 31 further comprising forming at least one device in or on the oxide layer.

55. The method of claim 54, wherein forming the at least one device comprises forming at least one of: a microelectronic device, an optoelectronic device, a micro-electromechanical system (MEMS), an integrated circuit, a transistor, a sensor, a Josephson junction, a capacitor, and a semiconductor device, in or on the oxide layer.

56. The method of claim 31, wherein depositing the nucleation layer comprises depositing the nucleation layer on silicon (001).

57. The method of claim 56, wherein depositing the oxide layer on the nucleation layer comprises depositing the oxide layer comprising STO (001).

58. The method of claim 56, wherein depositing the oxide layer on the nucleation layer comprises depositing the oxide layer comprising BST (001).

59. The method of claim 56, wherein depositing the oxide layer on the nucleation layer comprises depositing the oxide layer comprising BTO (001).

60. The method of claim 31, wherein depositing the nucleation layer comprises depositing the nucleation layer on silicon (111).

61. The method of claim 60, wherein depositing the oxide layer on the nucleation layer comprises depositing the oxide layer comprising STO (111).

62. The method of claim 60, wherein depositing the oxide layer on the nucleation layer comprises depositing the oxide layer comprising BST (111).

63. The method of claim 60, wherein depositing the oxide layer on the nucleation layer comprises depositing the oxide layer comprising BTO (111).

64. The method of claim 31, wherein depositing the oxide layer on the nucleation layer comprises depositing the oxide layer in the absence of annealing the oxide layer, thereby forming a fully oxygenated oxide layer.

65. The method of claim 31, wherein depositing the oxide layer on the nucleation layer comprises depositing the oxide layer as having a greater insulative property than Si.

66. The method of claim 31, wherein depositing the oxide layer on the nucleation layer comprises depositing the oxide layer as a fully insulating oxide layer.

67. The method of claim 31, wherein depositing the oxide layer on the nucleation layer comprises depositing the oxide layer as a fully stoichiometric oxide layer.

68. The method of claim 31, wherein depositing the nucleation layer on the Si substrate comprises depositing the nucleation layer using a molecular beam epitaxy (MBE) process.

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