Photovoltaic cell and photovoltaic cell manufacturing method

Abstract

A photovoltaic cell and a photovoltaic cell manufacturing method, which are applied in the field of photovoltaic cell manufacturing. A back surface of a substrate in the photovoltaic cell comprises a conductive region functional layer and a non-conductive region functional layer, wherein the conductive region functional layer comprises a first passivation layer arranged on the back surface of the substrate and a back metal gate line arranged on a back side of the substrate; the non-conductive region functional layer comprises a second passivation layer arranged on the back surface of the substrate; the first passivation layer at least comprises, from the back surface of the substrate to the outside, a first tunneling layer and a first polysilicon layer that are sequentially stacked; the total thickness of the polysilicon layer arranged in the first passivation layer is at least a first preset thickness; and a polysilicon layer is correspondingly provided in the second passivation layer, the total thickness of the polysilicon layer correspondingly arranged in the second passivation layer is a second preset thickness, and the second preset thickness is less than the first preset thickness, or no polysilicon layer is provided in the second passivation layer. By reducing the thickness of a polysilicon layer in a non-conductive region, the optical parasitic absorption of the polysilicon layer is reduced.

Description

Photovoltaic cell and method for preparing photovoltaic cell

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on January 22, 2024, with application number 202410087476.7 and invention name “A Photovoltaic Cell and Photovoltaic Cell Preparation Method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of photovoltaic cell preparation, and in particular to a photovoltaic cell and a method for preparing the photovoltaic cell. Background Art

[0003] Taking the TopCon cell (a solar cell with tunneling oxide passivation contact based on the principle of selective carriers) as an example, in the current preparation process of crystalline silicon TopCon cells, the Poly (polycrystalline material) layer on the back of the cell needs to be set to 120 nanometers in thickness to avoid the slurry burning through the contact in the conductive area. However, the Poly layer in the crystalline silicon TopCon cell has light absorption properties, resulting in the absorption of long-wave light on the back by the Poly layer, causing poor long-wave quantum efficiency response on the back and low short-circuit current of the cell, which reduces the performance of the photovoltaic cell.

[0004] Summary of the Invention

[0005] In view of this, the purpose of this application is to provide a photovoltaic cell and a method for preparing a photovoltaic cell, which solves the problem in the prior art that the long-wave light on the back side is absorbed by the Poly layer, resulting in poor long-wave quantum efficiency response on the back side and low short-circuit current of the battery.

[0006] To solve the above technical problems, the present application provides a photovoltaic cell, comprising:

[0007] A substrate, a first functional layer disposed on a front surface of the substrate, and a second functional layer disposed on a back surface of the substrate;

[0008] The second functional layer includes a conductive region functional layer and a non-conductive region functional layer; the conductive region functional layer includes a first passivation layer disposed on the back side of the substrate and a back metal grid line disposed on the back side of the substrate; the non-conductive region functional layer includes a second passivation layer disposed on the back side of the substrate;

[0009] The first passivation layer includes at least a first tunneling layer and a first polysilicon layer stacked in sequence along the back surface of the substrate. The total thickness of the polysilicon layer provided in the first passivation layer is at least a first preset thickness. The polysilicon layer of the first preset thickness prevents the metal gate line paste from burning through the entire polysilicon layer.

[0010] A polysilicon layer is correspondingly provided in the second passivation layer, and the total thickness of the polysilicon layer correspondingly provided in the second passivation layer is a second preset thickness, and the second preset thickness is less than the first preset thickness; or the second passivation layer does not have a polysilicon layer;

[0011] One end of the back metal grid line is disposed in the first polysilicon layer, and the other end of the back metal grid line is exposed on the back side of the photovoltaic cell.

[0012] Optionally, along the back surface of the substrate outward, the first passivation layer includes a first tunneling layer, a first polysilicon layer, a second tunneling layer, and a second polysilicon layer stacked in sequence; the total thickness of the first polysilicon layer and the second polysilicon layer is at least the first preset thickness;

[0013] The second passivation layer correspondingly includes a first tunneling layer and a first polysilicon layer, and the thickness of the first polysilicon layer is the second preset thickness.

[0014] Optionally, along the back surface of the substrate outward, the first passivation layer includes a first tunneling layer, a first polysilicon layer, and a metal oxide passivation layer stacked in sequence; the thickness of the first polysilicon layer is at least the first preset thickness;

[0015] The second passivation layer is correspondingly a metal oxide passivation layer.

[0016] Optionally, a silicon nitride protective layer is provided on the side of the first passivation layer and the side of the second passivation layer facing away from the substrate.

[0017] Optionally, along the front surface of the substrate outward, the first functional layer includes a front passivation layer and a front metal grid line;

[0018] The front passivation layer is correspondingly a metal oxide passivation layer.

[0019] The present application also provides a method for preparing a photovoltaic cell, which is used to prepare the photovoltaic cell as described above, comprising:

[0020] A photovoltaic cell preform is provided, wherein the back side of the substrate of the photovoltaic cell preform is provided with at least a first tunneling layer, a first polysilicon layer, and a mask layer stacked outward in sequence; the total thickness of the polysilicon layer provided on the back side of the photovoltaic cell preform is at least a first preset thickness, and the polysilicon layer of the first preset thickness prevents metal grid line paste from burning through the entire polysilicon layer; the back side of the photovoltaic cell preform is divided into a conductive area and a non-conductive area, and the mask layer in the non-conductive area is etched away to obtain a first patterned photovoltaic cell preform;

[0021] removing at least a portion of the thickness of the polysilicon layer in the non-conductive region;

[0022] A back metal grid line is prepared in the conductive area; one end of the back metal grid line is arranged in the first polysilicon layer, and the other end of the back metal grid line is exposed on the back side of the photovoltaic cell.

[0023] Optionally, the back side of the substrate in the photovoltaic cell preform is provided with at least the first tunneling layer, the first polysilicon layer, the second tunneling layer, the second polysilicon layer, and the mask layer stacked outward in sequence; the total thickness of the first polysilicon layer and the second polysilicon layer is at least the first preset thickness, and the thickness of the first polysilicon layer is the second preset thickness;

[0024] Accordingly, removing at least a portion of the polysilicon layer in the non-conductive region includes:

[0025] At least the second polysilicon layer in the non-conductive region is removed.

[0026] Optionally, the entire first polysilicon layer in the non-conductive region is removed, and a metal oxide passivation layer is formed on the back side of the substrate.

[0027] Optionally, dividing the back surface of the photovoltaic cell preform into a conductive area and a non-conductive area, and removing the mask layer in the non-conductive area by etching to obtain a first patterned photovoltaic cell preform, comprising:

[0028] preparing a barrier slurry on the surface of the mask layer in the conductive area to prevent the mask layer in the conductive area from being corroded;

[0029] The back side of the photovoltaic cell preform is immersed in an etching solution to remove the mask layer in the non-conductive area.

[0030] Optionally, a BSG mask layer is provided on the front side of the substrate, and when the photovoltaic cell preform is immersed in an etching solution, the BSG mask layer protects the front structure of the photovoltaic cell preform from being etched; the BSG mask layer is the BSG mask layer retained after the front side of the substrate is subjected to boron diffusion treatment.

[0031] Optionally, the mask layer is a phosphosilicate glass layer;

[0032] Accordingly, immersing the back surface of the photovoltaic cell preform in an etching solution to remove the mask layer in the non-conductive area includes:

[0033] The back side of the photovoltaic cell preform is immersed in a hydrofluoric acid etching solution to remove the phosphosilicate glass layer in the non-conductive area.

[0034] Optionally, dividing the back surface of the photovoltaic cell preform into a conductive area and a non-conductive area, and removing the mask layer in the non-conductive area by etching to obtain a first patterned photovoltaic cell preform, comprising:

[0035] The back side of the photovoltaic cell preform is divided into the conductive area and the non-conductive area, and an etching slurry is prepared on the surface of the mask layer in the non-conductive area to remove the mask layer in the non-conductive area using the etching slurry to obtain the first patterned photovoltaic cell preform.

[0036] Optionally, removing at least a portion of the polysilicon layer in the non-conductive region includes:

[0037] At least a portion of the polysilicon layer in the non-conductive region is removed by using an alkaline solution and an additive.

[0038] It can be seen that the photovoltaic cell provided by the present application includes a substrate, a first functional layer arranged on the front side of the substrate, and a second functional layer arranged on the back side of the substrate, the second functional layer includes a conductive area functional layer and a non-conductive area functional layer, the conductive area functional layer includes a first passivation layer arranged on the back side of the substrate, and a back metal gate line arranged on the back side of the substrate, the non-conductive area functional layer includes a second passivation layer arranged on the back side of the substrate, along the back side of the substrate outward, the first passivation layer includes at least a first tunneling layer and a first polysilicon layer stacked in sequence, the total thickness of the polysilicon layer arranged in the first passivation layer is at least a first preset thickness, the polysilicon layer of the first preset thickness prevents the metal gate line slurry from burning through the entire polysilicon layer, a polysilicon layer is correspondingly arranged in the second passivation layer, the total thickness of the polysilicon layer correspondingly arranged in the second passivation layer is a second preset thickness, and the second preset thickness is less than the first preset thickness; or the second passivation layer is not provided with a polysilicon layer, one end of the back metal gate line is arranged in the first polysilicon layer, and the back side of the photovoltaic cell exposes the other end of the back metal gate line. The present application reduces the thickness of the polysilicon layer in the non-conductive area to reduce the optical parasitic absorption of the polysilicon layer, thereby improving long-wave reflection, improving long-wave quantum response efficiency, and ultimately increasing the short-circuit current of the photovoltaic cell.

[0039] In addition, the present application also provides a method for preparing a photovoltaic cell, which also has the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0041] FIG1 is a schematic structural diagram of a photovoltaic cell provided in an embodiment of the present application;

[0042] FIG2 is a schematic structural diagram of another photovoltaic cell provided in an embodiment of the present application;

[0043] FIG3 is a flow chart of a method for preparing a photovoltaic cell provided in an embodiment of the present application;

[0044] In Figures 1 and 2, the reference numerals are explained as follows: 100 - substrate; 21 - conductive area functional layer, 22 - non-conductive area functional layer, 201 - first tunneling layer, 202 - first polysilicon layer, 203 - second tunneling layer, 204 - second polysilicon layer, 211 - back metal gate line; 301 - silicon nitride protective layer; 401 - metal oxide passivation layer; 500 - textured surface. DETAILED DESCRIPTION

[0045] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0046] Example 1

[0047] Please refer to Figure 1, which is a schematic diagram of the structure of a photovoltaic cell provided in an embodiment of the present application. The photovoltaic cell may include:

[0048] A substrate 100, a first functional layer disposed on a front surface of the substrate 100, and a second functional layer disposed on a back surface of the substrate 100;

[0049] The second functional layer includes a conductive region functional layer 21 and a non-conductive region functional layer 22; the conductive region functional layer 21 includes a first passivation layer disposed on the back side of the substrate 100 and a back metal gate line 211 disposed on the back side of the substrate 100; the non-conductive region functional layer 22 includes a second passivation layer disposed on the back side of the substrate 100;

[0050] Along the back surface of the substrate 100 outward, the first passivation layer includes at least a first tunneling layer 201 and a first polysilicon layer 202 stacked in sequence; the total thickness of the polysilicon layer provided in the first passivation layer is at least a first predetermined thickness, and the polysilicon layer of the first predetermined thickness prevents the metal gate line paste from burning through the entire polysilicon layer;

[0051] A polysilicon layer is correspondingly provided in the second passivation layer, and the total thickness of the polysilicon layer correspondingly provided in the second passivation layer is a second preset thickness, which is less than the first preset thickness; or the second passivation layer does not have a polysilicon layer;

[0052] One end of the back metal gate line 211 is disposed in the first polysilicon layer 202 , and the other end of the back metal gate line 211 is exposed at the back side of the photovoltaic cell.

[0053] This application mainly improves photovoltaic cells with a Poly finger cell structure. Since the thickness of the polysilicon layer is generally 120 nanometers only to avoid the slurry burn-through contact under the finger, but only a 20-nanometer thick polysilicon layer is required in the non-finger area to meet the passivation requirements, this cell structure with a thick polysilicon layer under the finger and a thin polysilicon layer under the non-finger area is called a Poly finger cell structure.

[0054] In this embodiment, the substrate 100 can be either an N-type substrate or a P-type substrate, and this embodiment does not impose any specific limitations. In this embodiment, the polysilicon layer in the first passivation layer provided in the conductive region is thicker than the thickness of the polysilicon layer in order to prevent the slurry from burning through the polysilicon layer during the preparation of the metal gate lines, which could damage the device. In the second passivation layer, to minimize the thickness of the polysilicon layer and thereby reduce the polysilicon layer's absorption of long-wavelength light, the total thickness of the polysilicon layer is set to a second predetermined thickness, or no polysilicon layer is provided in the second passivation layer. It should be noted that when only the tunneling layer and the polysilicon layer are used to form the back passivation layer in this embodiment, the thickness of the polysilicon layer in the second passivation layer can be the second predetermined thickness. A polysilicon layer of the second predetermined thickness is provided in the second passivation layer to ensure passivation capability in the functional layer in the non-conductive region. When other materials are used to form the passivation layer, the thickness of the polysilicon layer can be reduced or even completely removed. In this embodiment, the first predetermined thickness is greater than the second predetermined thickness. Generally, the first predetermined thickness can be set to 120 nanometers, while the second predetermined thickness only needs to be set to 20 nanometers. The location and method of forming the back metal grid lines 211 in this embodiment can refer to the preparation methods of the prior art. In the prior art, a textured surface 500 is generally formed on the front side of the substrate to improve photoelectric conversion efficiency.

[0055] Furthermore, in a structure in which a polysilicon layer and a tunneling layer are used to form a back passivation layer, the use of polysilicon in the non-conductive region is reduced. From the back side of the substrate 100 outward, the first passivation layer may include a first tunneling layer 201, a first polysilicon layer 202, a second tunneling layer 203, and a second polysilicon layer 204 stacked in sequence. The total thickness of the first polysilicon layer 202 and the second polysilicon layer 204 is at least a first predetermined thickness.

[0056] The second passivation layer correspondingly includes a first tunneling layer 201 and a first polysilicon layer 202 . The thickness of the first polysilicon layer 202 is a second preset thickness.

[0057] In this embodiment, the first passivation layer is set to a stacked structure formed by the first tunneling layer 201, the first polysilicon layer 202, the second tunneling layer 203 and the second polysilicon layer 204, and the second passivation layer is set to a stacked structure formed by the first tunneling layer 201 and the first polysilicon layer 202, and the first polysilicon layer 202 is set to the second preset thickness, and the total thickness of the second polysilicon layer 204 and the first polysilicon layer 202 is set to the first preset thickness. While meeting the functionality of the polysilicon layer, the first tunneling layer 201 and the first polysilicon layer 202 in the conductive area and the non-conductive area can be prepared at the same time, thereby improving the preparation efficiency.

[0058] Furthermore, in order to protect the back side of the device and prevent the first passivation layer and the second passivation layer from being corroded and damaged, a silicon nitride protection layer 301 may be provided on the side of the first passivation layer and the second passivation layer facing away from the substrate 100 .

[0059] In this embodiment, a silicon nitride protection layer 301 is provided on the outer sides of the first passivation layer and the second passivation layer, so as to protect the first passivation layer and the second passivation layer and improve the stability of the device.

[0060] Furthermore, in order to ensure normal operation of the device, the first functional layer may include a front passivation layer and a front metal gate line along the front surface of the substrate 100.

[0061] The front passivation layer corresponds to the metal oxide passivation layer 401 .

[0062] In this embodiment, the front passivation layer is provided as a metal oxide passivation layer 401, and a front metal grid line is formed on the front surface to ensure stable operation of the photovoltaic cell device. It should be further noted that a front velvet surface can also be formed on the front surface of the substrate 100 to improve the photoelectric conversion efficiency. This embodiment does not limit the specific material of the metal oxide passivation layer 401 provided on the front surface; it can be selected based on the process and performance. For example, aluminum oxide can be used as the front passivation layer.

[0063] The photovoltaic cell provided by the embodiment of the present application includes a substrate 100, a first functional layer arranged on the front side of the substrate 100, and a second functional layer arranged on the back side of the substrate 100, the second functional layer includes a conductive region functional layer 21 and a non-conductive region functional layer 22, the conductive region functional layer 21 includes a first passivation layer arranged on the back side of the substrate 100, and a back metal grid line 211 arranged on the back side of the substrate 100, the non-conductive region functional layer 22 includes a second passivation layer arranged on the back side of the substrate 100, and along the back side of the substrate 100 outward, the first passivation layer includes at least a plurality of layers stacked in sequence. A first tunneling layer 201 and a first polysilicon layer 202 are provided. The total thickness of the polysilicon layer provided in the first passivation layer is at least a first predetermined thickness. The polysilicon layer of the first predetermined thickness prevents the metal gate line slurry from burning through the entire polysilicon layer. A corresponding polysilicon layer is provided in the second passivation layer. The total thickness of the polysilicon layer provided in the second passivation layer is a second predetermined thickness. The second predetermined thickness is less than the first predetermined thickness, or the second passivation layer does not include a polysilicon layer. One end of the back metal gate line 211 is provided in the first polysilicon layer 202, and the other end of the back metal gate line 211 is exposed on the back side of the photovoltaic cell. This application reduces the thickness of the polysilicon layer in the non-conductive region to reduce optical parasitic absorption of the polysilicon layer, thereby improving long-wave reflection, improving long-wave quantum response efficiency, and ultimately increasing the short-circuit current of the photovoltaic cell. In addition, the embodiment of the present application improves the preparation efficiency by setting the first passivation layer to a stacked structure formed by the first tunneling layer 201, the first polysilicon layer 202, the second tunneling layer 203 and the second polysilicon layer 204, and setting the second passivation layer to a stacked structure formed by the first tunneling layer 201 and the first polysilicon layer 202, and setting the first polysilicon layer 202 to the second preset thickness, and setting the total thickness of the second polysilicon layer 204 and the first polysilicon layer 202 to the first preset thickness; by setting a silicon nitride protective layer 301 on the outside of the first passivation layer and the second passivation layer, the first passivation layer and the second passivation layer can be protected, thereby improving the stability of the device; setting the front passivation layer to a metal oxide passivation layer 401, and preparing a front metal gate line on the front, can ensure the stable operation of the photovoltaic cell device.

[0064] Example 2

[0065] Please refer to Figure 2 for details, which is a schematic diagram of the structure of another photovoltaic cell provided in an embodiment of the present application. The photovoltaic cell may include:

[0066] A substrate 100, a first functional layer disposed on a front surface of the substrate 100, and a second functional layer disposed on a back surface of the substrate 100;

[0067] The second functional layer includes a conductive region functional layer 21 and a non-conductive region functional layer 22; the conductive region functional layer 21 includes a first passivation layer disposed on the back side of the substrate 100 and a back metal gate line 211 disposed on the back side of the substrate 100; the non-conductive region functional layer 22 includes a second passivation layer disposed on the back side of the substrate 100;

[0068] From the back side of the substrate 100 outward, the first passivation layer includes a first tunneling layer 201, a first polysilicon layer 202, and a metal oxide passivation layer 401 stacked in sequence; the thickness of the first polysilicon layer 202 is at least a first predetermined thickness;

[0069] The second passivation layer corresponds to the metal oxide passivation layer 401;

[0070] One end of the back metal gate line 211 is disposed in the first polysilicon layer 202 , and the other end of the back metal gate line 211 is exposed at the back side of the photovoltaic cell.

[0071] It should be noted that in this embodiment, by setting the second passivation layer as a metal oxide passivation layer 401, it is possible to avoid the preparation of polysilicon in the non-conductive area, thereby minimizing the absorption of long-wave light in the non-conductive area and improving the photoelectric conversion efficiency. It should be noted that the total thickness of the polysilicon layer prepared in the conductive area should be a first preset thickness to avoid the back metal gate line 211 from burning through the polysilicon layer during preparation. This embodiment does not limit the specific material of the prepared metal oxide passivation layer 401, as long as it can meet the passivation effect on the back of the substrate 100. For example, the metal oxide passivation layer 401 can be prepared using an aluminum oxide material. The specific thickness of the aluminum oxide passivation layer prepared in this embodiment can be set according to the device parameters.

[0072] A photovoltaic cell provided by an embodiment of the present application includes a substrate 100, a first functional layer disposed on the front surface of the substrate 100, and a second functional layer disposed on the back surface of the substrate 100. The second functional layer includes a conductive region functional layer 21 and a non-conductive region functional layer 22. The conductive region functional layer 21 includes a first passivation layer disposed on the back surface of the substrate 100 and a back metal gate line 211 disposed on the back side of the substrate 100. The non-conductive region functional layer 22 includes a second passivation layer disposed on the back surface of the substrate 100. From the back surface of the substrate 100 outward, the first passivation layer includes a first tunneling layer 201, a first polysilicon layer 202, and a metal oxide passivation layer 401 stacked in sequence. The thickness of the first polysilicon layer 202 is at least a first predetermined thickness. The second passivation layer corresponds to the metal oxide passivation layer 401. One end of the back metal gate line 211 is disposed in the first polysilicon layer 202, and the other end of the back metal gate line 211 is exposed on the back side of the photovoltaic cell. The present application reduces the thickness of the polysilicon layer in the non-conductive area to reduce the optical parasitic absorption of the polysilicon layer, thereby improving long-wave reflection, improving the long-wave quantum response efficiency, and ultimately improving the short-circuit current of the photovoltaic cell. By setting the second passivation layer to a metal oxide passivation layer 401, it is possible to avoid preparing polysilicon in the non-conductive area, thereby minimizing the absorption of long-wave light in the non-conductive area and further improving the photoelectric conversion efficiency.

[0073] The non-conductive region in the embodiment of the present application can be a non-metallic gate line region in an actual solution; further, since the polysilicon layer of the present application is doped, if part of the doped polysilicon layer remains in the non-conductive region, the non-conductive region has at least partial conductive function.

[0074] The following is an introduction to the photovoltaic cell preparation method provided in the embodiments of the present application. The photovoltaic cell preparation method described below and the photovoltaic cell described above can be referenced to each other.

[0075] Please refer to FIG3 for details. FIG3 is a flow chart of a method for preparing a photovoltaic cell provided in an embodiment of the present application. The method may include:

[0076] S101: A photovoltaic cell preform is provided, wherein the back side of the substrate in the photovoltaic cell preform is provided with at least a first tunneling layer, a first polysilicon layer and a mask layer stacked outward in sequence; the total thickness of the polysilicon layer provided on the back side of the photovoltaic cell preform is at least a first preset thickness, and the polysilicon layer with the first preset thickness prevents the metal grid line paste from burning through the entire polysilicon layer; the back side of the photovoltaic cell preform is divided into a conductive area and a non-conductive area, and the mask layer in the non-conductive area is etched away to obtain a first patterned photovoltaic cell preform.

[0077] In this embodiment, the executor is a photovoltaic cell manufacturing device. A photovoltaic cell preform is provided. The preform comprises a first patterned photovoltaic cell preform having at least a first tunneling layer and a first polysilicon layer stacked along the back surface of a substrate, forming a back passivation layer. The back passivation layer, facing away from the substrate, is divided into a conductive region and a non-conductive region. A mask layer is retained in the conductive region to form a first patterned photovoltaic cell preform.

[0078] S102: removing at least a portion of the polysilicon layer in the non-conductive region.

[0079] This embodiment can directly etch and remove the structure in the non-conductive area by blocking the conductive area from being etched through the mask layer after obtaining the above-mentioned first patterned photovoltaic cell preform. This embodiment mainly removes the polysilicon layer in the non-conductive area. In this embodiment, a portion of the thickness of the polysilicon layer in the non-conductive area is removed, and the polysilicon layer in the non-conductive area can be removed to a remaining second preset thickness, so as to reduce the influence of the polysilicon layer on the light collection efficiency while ensuring the passivation effect. It should be noted that in this embodiment, when the non-conductive area uses the tunneling layer and the polysilicon layer as the passivation layer, the polysilicon layer of the second preset thickness is required to ensure the passivation ability of the passivation layer in the non-conductive area. When the non-conductive area uses other materials to prepare the passivation layer, the polysilicon layer in the non-conductive area can be gradually thinned, or even the polysilicon layer in the non-conductive area can be completely removed.

[0080] Furthermore, in order to ensure smooth etching of the polysilicon in the non-conductive area, the above-mentioned removal of at least a portion of the polysilicon layer in the non-conductive area may include:

[0081] At least a portion of the thickness of the polysilicon layer in the non-conductive area is removed using an alkaline solution and an additive.

[0082] In this embodiment, an alkaline solution with an additive is used to etch the polysilicon layer in the non-conductive area, which can ensure that the etching step is completed smoothly.

[0083] S103: preparing a back metal gate line in the conductive area; one end of the back metal gate line is disposed in the first polysilicon layer, and the other end of the back metal gate line is exposed on the back side of the photovoltaic cell.

[0084] The steps for preparing the back metal gate lines in the conductive area in this embodiment can refer to the preparation methods in the prior art. In this embodiment, a silicon nitride protective layer can be subsequently formed on the outer side of the back passivation layer, and aluminum oxide and silicon nitride protective layers, as well as the front metal gate lines, can be prepared in sequence on the front side. The preparation methods can refer to the existing preparation methods and will not be detailed here.

[0085] Furthermore, to improve the convenience of preparation, the back side of the substrate in the above photovoltaic cell preform can be configured to have at least a first tunneling layer, a first polysilicon layer, a second tunneling layer, a second polysilicon layer, and a mask layer stacked outward in sequence; the total thickness of the first polysilicon layer and the second polysilicon layer is at least a first preset thickness, and the thickness of the first polysilicon layer is a second preset thickness;

[0086] Accordingly, removing at least a portion of the polysilicon layer in the non-conductive region may include:

[0087] At least the second polysilicon layer in the non-conductive region is removed.

[0088] It should be noted that in this embodiment, by placing the back side of the substrate outward and arranging the first tunneling layer, the first polysilicon layer, the second tunneling layer, the second polysilicon layer and the mask layer in a stacked manner, after removing the mask layer in the non-conductive area, the second polysilicon layer in the non-conductive area is directly removed to complete the removal of the excess polysilicon layer in the non-conductive area, thereby ensuring the efficiency of the preparation. Among them, the second tunneling layer is a separation layer that separates the first polysilicon layer and the second polysilicon layer. When removing the second polysilicon layer, there is no need to consider the accuracy of the thickness of the removed polysilicon layer, thereby reducing the complexity of the removal operation. It should be further noted that in this embodiment, the second tunneling layer located in the non-conductive area can be removed together, or it can be retained in the non-conductive area. When only the second polysilicon layer is removed from the non-conductive area, that is, the non-conductive area retains the polysilicon layer of the second preset thickness to ensure the passivation ability of the passivation layer in the non-conductive area.

[0089] Furthermore, in order to minimize the absorption of long-wave light by the polysilicon layer in the non-conductive region, the entire first polysilicon layer in the non-conductive region may be removed, and a metal oxide passivation layer may be formed on the back side of the substrate.

[0090] In this embodiment, by completely removing the first polysilicon layer in the non-conductive area, the absorption of long-wave light by the back of the photovoltaic cell can be minimized, the photoelectric conversion efficiency can be improved, and the passivation effect of the back of the substrate can be ensured. It should be noted that in this embodiment, the first tunneling layer located in the non-conductive area can be removed, or the first tunneling layer located in the non-conductive area can be retained. In this embodiment, the first tunneling layer located in the non-conductive area is removed, and the structure outside the first tunneling layer located in the non-conductive area is removed. At this time, the back of the substrate in the photovoltaic cell preform can be set to a structure in which the first tunneling layer, the first polysilicon layer and the mask layer are stacked outward in sequence, and the thickness of the first polysilicon layer is at least the first preset thickness to ensure the convenience of preparation. In this embodiment, after completely removing the tunneling layer in the non-conductive area, a metal oxide passivation layer can be directly prepared on the back of the substrate. It should be further explained that when only the first polysilicon layer in the non-conductive area is removed, that is, the first tunneling layer in the non-conductive area is retained, a metal oxide passivation layer is prepared on the back side of the first tunneling layer. In addition, in this embodiment, a metal oxide passivation layer can be simultaneously prepared on the back side of the structure in the conductive area.

[0091] Furthermore, in order to ensure the efficiency of removing the mask layer in the non-conductive area, the above-mentioned dividing the back surface of the photovoltaic cell preform into the conductive area and the non-conductive area, etching away the mask layer in the non-conductive area, and obtaining the first patterned photovoltaic cell preform may include the following steps:

[0092] Step S11: preparing a barrier slurry on the surface of the mask layer in the conductive area to prevent the mask layer in the conductive area from being corroded.

[0093] Step S12: immersing the back surface of the photovoltaic cell preform in an etching solution to remove the mask layer in the non-conductive area.

[0094] In this embodiment, a barrier slurry is prepared on the surface of the mask layer in the conductive area, and then the back side of the photovoltaic cell preform is immersed in an etching solution. This improves the efficiency of etching away the mask layer in the non-conductive area while ensuring the preparation of the first patterned photovoltaic cell preform.

[0095] Furthermore, in order to ensure the smooth preparation of the photovoltaic cell, a BSG mask layer can be provided on the front side of the above-mentioned substrate. When the photovoltaic cell preform is immersed in the etching solution, the BSG mask layer protects the front structure of the photovoltaic cell preform from being etched; the BSG mask layer is the BSG mask layer retained after the front side of the substrate is subjected to boron diffusion treatment.

[0096] In this embodiment, the BSG mask layer retained after the boron diffusion treatment on the front side of the substrate is used to protect the front structure of the photovoltaic cell preform from being etched when the photovoltaic cell preform is immersed in the etching solution, thereby ensuring the smooth preparation of the photovoltaic module and improving the convenience of preparation.

[0097] Furthermore, in order to ensure that the etching solution can remove the mask layer in the non-conductive area, the mask layer may be a phosphosilicate glass layer;

[0098] Accordingly, immersing the back surface of the photovoltaic cell preform in an etching solution to remove the mask layer in the non-conductive area may include:

[0099] The back side of the photovoltaic cell preform is immersed in a hydrofluoric acid etching solution to remove the phosphosilicate glass layer in the non-conductive area.

[0100] In this embodiment, the mask layer is set as a phosphosilicate glass layer, and a hydrofluoric acid etchant is used to etch and remove the phosphosilicate glass layer in the non-conductive area to ensure that the first patterned photovoltaic cell preform is successfully prepared.

[0101] Furthermore, in order to reduce the complexity of the step of etching the mask layer in the non-conductive area, the above-mentioned step of dividing the back surface of the photovoltaic cell preform into the conductive area and the non-conductive area, and etching away the mask layer in the non-conductive area to obtain the first patterned photovoltaic cell preform can also adopt another etching scheme, including:

[0102] The back side of the photovoltaic cell preform is divided into a conductive area and a non-conductive area, and an etching slurry is prepared on the surface of the mask layer in the non-conductive area to remove the mask layer in the non-conductive area using the etching slurry to obtain a first patterned photovoltaic cell preform.

[0103] In this embodiment, the etching slurry is directly prepared on the surface of the mask layer in the non-conductive area, and the mask layer in the non-conductive area can be directly etched away using the etching slurry without subsequently immersing the back of the photovoltaic cell preform in the etching solution, thereby simplifying the step of etching the mask layer.

[0104] The photovoltaic cell preparation method provided by the embodiments of the present application includes providing a photovoltaic cell preform, wherein the back side of the substrate in the photovoltaic cell preform is sequentially stacked with at least a first tunneling layer, a first polysilicon layer, and a mask layer. The total thickness of the polysilicon layer provided on the back side of the photovoltaic cell preform is at least a first predetermined thickness. The polysilicon layer of the first predetermined thickness prevents the metal grid line from burning through the entire polysilicon layer. The back side of the photovoltaic cell preform is divided into a conductive region and a non-conductive region. The mask layer in the non-conductive region is etched away to obtain a first patterned photovoltaic cell preform. At least a portion of the polysilicon layer in the non-conductive region is removed. A back metal grid line is formed in the conductive region. One end of the back metal grid line is disposed in the first polysilicon layer, and the other end of the back metal grid line is exposed on the back side of the photovoltaic cell. The present application reduces the thickness of the polysilicon layer in the non-conductive region to reduce optical parasitic absorption of the polysilicon layer, thereby improving long-wave reflection, improving long-wave quantum response efficiency, and ultimately improving the short-circuit current of the photovoltaic cell. In addition, the embodiment of the present application can ensure the smooth completion of the etching step by etching the polysilicon layer in the non-conductive area with an alkaline solution containing additives; by setting the back side of the substrate outward and arranging the first tunneling layer, the first polysilicon layer, the second tunneling layer, the second polysilicon layer and the mask layer stacked in sequence, then after removing the mask layer in the non-conductive area, the embodiment directly removes the second polysilicon layer in the non-conductive area, completing the removal of the excess polysilicon layer in the non-conductive area, thereby ensuring the preparation efficiency; by completely removing the first polysilicon layer in the non-conductive area, the absorption of long-wave light by the back side of the photovoltaic cell can be minimized, the photoelectric conversion efficiency can be improved, and the passivation effect of the back side of the substrate can be ensured at the same time; by preparing a blocking slurry on the surface of the mask layer in the conductive area, and then immersing the back side of the photovoltaic cell preform in In the etching solution, while ensuring the preparation of the first patterned photovoltaic cell preform, the efficiency of etching and removing the mask layer in the non-conductive area is improved; the BSG mask layer retained after the boron diffusion treatment on the front side of the substrate is used to protect the front structure of the photovoltaic cell preform from being etched, thereby ensuring the smooth preparation of the photovoltaic module and improving the convenience of preparation; the mask layer is set as a phosphosilicate glass layer, and a hydrofluoric acid etching solution is used to etch and remove the phosphosilicate glass layer in the non-conductive area, thereby ensuring the smooth preparation of the first patterned photovoltaic cell preform; by directly preparing an etching slurry on the surface of the mask layer in the non-conductive area, the etching slurry can be directly used to etch and remove the mask layer in the non-conductive area, without the need to subsequently immerse the back side of the photovoltaic cell preform in the etching solution, thereby simplifying the step of etching the mask layer.

[0105] To make this application easier to understand, the photovoltaic cell preparation method may specifically include the following steps:

[0106] Step S1: Double-sided texturing is performed on the N-type substrate silicon wafer, wherein the alkali concentration in the texturing process (the alkali concentration is the volume ratio of the total volume of the tank body) is 2%, the concentration of additive A is 1%, the texturing temperature is 82°C, the texturing time is 420 seconds, and additive A is a commonly used texturing additive on the market; and the silicon wafer after texturing is subjected to single-sided boron diffusion to form a P+ emitter level on the front side of the N-type substrate and generate a BSG (borosilicate glass) layer on both sides of the N-type substrate; using a chain-type BSG removal device, the back side of the N-type substrate is exposed to hydrofluoric acid on one side to remove the BSG layer on the back side of the N-type substrate after the boron diffusion, as the first N-type substrate structure.

[0107] Step S2: Using BSG as a mask layer to form protection on the front side, the back side of the first N-type substrate structure is alkali-etched using a tank-type alkali polishing device to form a back side alkali polished surface morphology, wherein the concentration of the alkali polishing agent is 4%, the concentration of additive B is 0.7%, the temperature of the alkali polishing process is 65°C, the reaction time is 160 seconds, and additive B is a commonly used alkali polishing additive on the market, thereby obtaining a second N-type substrate structure.

[0108] Step S3: Forming at least a first tunneling layer and a first polysilicon layer on the back side of the second N-type substrate structure. When forming multiple tunneling layers and polysilicon layers on the back side of the N-type substrate, an LPCVD double-insert laminated poly process (the laminated poly layer is a double-layer or multi-layer tunneling layer + poly layer) can be used, and a PSG (phosphate glass) layer is formed on the outermost side to obtain a third N-type substrate structure.

[0109] Step S4: The back side of the third N-type substrate structure is stacked with at least one tunneling layer, at least one polysilicon layer, and a PSG layer from the inside to the outside, and the front side is stacked with a PSG layer, at least one polysilicon coating layer, at least one tunneling layer, a BSG layer, and a front velvet surface from the outside to the inside. The outermost PSG layer on the front side is removed to obtain a fourth N-type substrate structure.

[0110] Step S5: removing the front polysilicon wrap-around layer and the front tunneling layer of the fourth N-type substrate structure, and removing the phosphorus at the edge of the N-type substrate structure by alkaline etching to obtain a fifth N-type substrate structure.

[0111] Step S6: Using a screen printer with a mask screen on the back side of the fifth N-type substrate structure, a conductive area and a non-conductive area are printed on the back side of the N-type substrate structure to complete the back side patterning step, and then an oven is used to dry and solidify the printed gate lines to obtain a sixth N-type substrate structure.

[0112] Step S7: Use a chain cleaning machine to perform subsequent processing on the sixth N-type substrate structure. The chain cleaning machine includes an immersion hydrofluoric acid tank, an alkali + BDG (ethylene glycol butyl ether) tank, a high-pressure water washing tank, a water spray cleaning tank, an alkali + hydrogen peroxide post-cleaning tank and a drying tank. In the immersion hydrofluoric acid tank, the PSG in the conductive area where the hydrofluoric acid-resistant barrier slurry is printed is not affected by the corrosion of hydrofluoric acid, and the PSG in the non-conductive area where the hydrofluoric acid-resistant barrier slurry is not printed is completely corroded by hydrofluoric acid. The alkali tank, water tank and drying tank are used to complete the removal of the barrier slurry and the cleaning and drying to obtain the seventh N-type substrate structure.

[0113] Step S8: Using a tank-type RCA cleaning device, an alkaline solution and an additive are used to remove at least a portion of the polysilicon layer in the non-conductive area of ​​the seventh N-type substrate structure, and a polysilicon layer of at most a second preset thickness remains in the non-conductive area, and an RCA process cleaning is performed in an ozone aqueous solution for 8 minutes to obtain an eighth N-type substrate structure.

[0114] Step S9: Aluminum oxide and silicon nitride films are grown on the front and back surfaces of the eighth N-type substrate structure. The aluminum oxide is 6 nanometers thick, and the silicon nitride film is 78 nanometers thick. Screen printing is performed on the front and back surfaces of the N-type substrate structure to form front and back metal grid lines, completing the fabrication of the photovoltaic cell. It should be noted that if the polysilicon layer is completely removed from the non-conductive back surface area, an aluminum oxide layer can also be formed on the back surface as a passivation layer.

[0115] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from the other embodiments. Reference can be made to the descriptions of the identical or similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions of the methods.

[0116] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0117] Finally, it should be noted that, in this document, relationships such as first and second, etc., are used solely to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0118] The above is a detailed introduction to a photovoltaic cell and a method for preparing a photovoltaic cell provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, according to the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A photovoltaic cell, characterized in that, Comprising: A substrate, a first functional layer disposed on the front surface of the substrate, and a second functional layer disposed on the back surface of the substrate; The second functional layer includes a conductive region functional layer and a non-conductive region functional layer; the conductive region functional layer includes a first passivation layer disposed on the back surface of the substrate and a back metal gate line disposed on the back side of the substrate; the non-conductive region functional layer includes a second passivation layer disposed on the back surface of the substrate; Outward along the back surface of the substrate, the first passivation layer at least includes a first tunneling layer and a first polysilicon layer stacked in sequence; the total thickness of the polysilicon layer disposed in the first passivation layer is at least a first preset thickness, and the polysilicon layer with the first preset thickness prevents the metal gate line paste from burning through all the polysilicon layers; A polysilicon layer is correspondingly disposed in the second passivation layer, and the total thickness of the polysilicon layer correspondingly disposed in the second passivation layer is a second preset thickness, and the second preset thickness is less than the first preset thickness; Or the second passivation layer does not have a polysilicon layer; One end of the back metal gate line is disposed in the first polysilicon layer, and the other end of the back metal gate line is exposed on the back side of the photovoltaic cell.

2. The photovoltaic cell according to claim 1, wherein Outward along the back surface of the substrate, the first passivation layer includes the first tunneling layer, the first polysilicon layer, a second tunneling layer, and a second polysilicon layer stacked in sequence; the total thickness of the first polysilicon layer and the second polysilicon layer is at least the first preset thickness; The second passivation layer correspondingly includes a first tunneling layer and a first polysilicon layer, and the thickness of the first polysilicon layer is the second preset thickness.

3. The photovoltaic cell according to claim 1, wherein Outward along the back surface of the substrate, the first passivation layer includes the first tunneling layer, the first polysilicon layer, and a metal oxide passivation layer stacked in sequence; the thickness of the first polysilicon layer is at least the first preset thickness; The second passivation layer is correspondingly a metal oxide passivation layer.

4. The photovoltaic cell according to claim 1, characterized in that, On the side of the first passivation layer and the second passivation layer facing away from the substrate, a silicon nitride protective layer is disposed.

5. The photovoltaic cell according to claim 3, characterized in that, Outward along the front surface of the substrate, the first functional layer includes a front passivation layer and a front metal gate line; The front passivation layer is correspondingly a metal oxide passivation layer.

6. A method for preparing a photovoltaic cell, characterized in that, Applied to the preparation of a photovoltaic cell as described in any one of claims 1 to 5, including: Providing a photovoltaic cell preform, on the back surface of the substrate in the photovoltaic cell preform, at least a first tunneling layer, a first polysilicon layer, and a mask layer are stacked outward in sequence; the total thickness of the polysilicon layer disposed on the back side of the photovoltaic cell preform is at least a first preset thickness, and the polysilicon layer with the first preset thickness prevents the metal gate line paste from burning through all the polysilicon layers; dividing the back surface of the photovoltaic cell preform into a conductive region and a non-conductive region, etching and removing the mask layer in the non-conductive region to obtain a first patterned photovoltaic cell preform; At least removing a part of the thickness of the polysilicon layer in the non-conductive region; Preparing a back metal gate line in the conductive region; one end of the back metal gate line is disposed in the first polysilicon layer, and the other end of the back metal gate line is exposed on the back side of the photovoltaic cell.

7. The method for preparing a photovoltaic cell according to claim 6, wherein, On the back surface of the substrate in the photovoltaic cell preform, at least the first tunneling layer, the first polysilicon layer, the second tunneling layer, the second polysilicon layer, and the mask layer are sequentially stacked outward; the total thickness of the first polysilicon layer and the second polysilicon layer is at least the first preset thickness, and the thickness of the first polysilicon layer is the second preset thickness; Correspondingly, at least removing a part of the thickness of the polysilicon layer in the non-conductive region includes: At least removing the second polysilicon layer in the non-conductive region.

8. The method for preparing a photovoltaic cell according to claim 6, wherein Removing all of the first polysilicon layer in the non-conductive region and preparing a metal oxide passivation layer on the back surface of the substrate.

9. The method for preparing a photovoltaic cell according to claim 6, wherein Dividing the back surface of the photovoltaic cell preform into a conductive region and a non-conductive region, and etching and removing the mask layer in the non-conductive region to obtain a first patterned photovoltaic cell preform, including: Preparing a barrier paste on the surface of the mask layer in the conductive region to prevent the mask layer in the conductive region from being corroded; Immersing the back surface of the photovoltaic cell preform in an etching solution to remove the mask layer in the non-conductive region.

10. The method for preparing a photovoltaic cell according to claim 9, wherein, A BSG mask layer is provided on the front surface of the substrate. When the photovoltaic cell preform is immersed in the etching solution, the BSG mask layer protects the front surface structure of the photovoltaic cell preform from being etched; the BSG mask layer is the BSG mask layer remaining after boron diffusion treatment of the front surface of the substrate.

11. The method for preparing a photovoltaic cell according to claim 9, wherein, The mask layer is a phosphosilicate glass layer; Correspondingly, immersing the back surface of the photovoltaic cell preform in an etching solution to remove the mask layer in the non-conductive region includes: Immersing the back surface of the photovoltaic cell preform in a hydrofluoric acid etching solution to remove the phosphosilicate glass layer in the non-conductive region.

12. The method for preparing a photovoltaic cell according to claim 6, wherein, Dividing the back surface of the photovoltaic cell preform into a conductive region and a non-conductive region, and etching and removing the mask layer in the non-conductive region to obtain a first patterned photovoltaic cell preform, including: Dividing the back surface of the photovoltaic cell preform into the conductive region and the non-conductive region, and preparing an etching paste on the surface of the mask layer in the non-conductive region to use the etching paste to remove the mask layer in the non-conductive region to obtain the first patterned photovoltaic cell preform.

13. The method for preparing a photovoltaic cell according to claim 6, wherein, At least removing a part of the thickness of the polysilicon layer in the non-conductive region includes: Using an alkaline solution and an additive to at least remove a part of the thickness of the polysilicon layer in the non-conductive region.

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