Communication methods and communication apparatuses based on LDPC code

Abstract

Communication methods and communication apparatuses based on an LDPC code. A matrix B of an LDPC base matrix used for coding or decoding comprises an xth row and a yth column, wherein the row weight of the xth row is an integer greater than or equal to 3, the column weight of the yth column is an odd number greater than or equal to 3, a matrix located in the xth row and the yth column in a first square matrix is a zero matrix, and the column weight of each column other than the yth column in the first square matrix is an integer greater than or equal to 2. In other words, a row with the highest row weight and a column with the highest column weight in the matrix B can be misaligned, so that the generation of four cycles in the base matrix can be prevented, thereby accelerating the convergence speed and improving the coding performance.

Description

A communication method and communication device based on LDPC code

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on January 27, 2024, with application number 202410120563.8 and invention name “A communication method and communication device based on LDPC code”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of coding, and more particularly, to a communication method and a communication device based on LDPC codes. Background Art

[0003] Low-density parity check (LDPC) codes are one of the most mature and widely used channel coding schemes. Current LDPC codes often suffer from quad-cycles in the LDPC base matrix, hindering fast convergence and affecting encoding and decoding performance. Summary of the Invention

[0004] The embodiments of the present application provide a communication method and a communication device based on LDPC codes, which help to improve encoding or decoding performance.

[0005] In a first aspect, a communication method based on LDPC codes is provided, which can be executed by a transmitting device or a module or unit in the transmitting device (e.g., a chip). The transmitting device can be a terminal device or a network device.

[0006] The method includes: obtaining an information bit sequence; performing LDPC encoding on the information bit sequence according to an LDPC base matrix to obtain an LDPC codeword sequence, wherein the LDPC base matrix includes a first square matrix, the first square matrix is ​​composed of the 1st to wth rows and the rth to r+w-1th columns of the LDPC base matrix, the first square matrix includes the xth row and the yth column, the row weight of the xth row is an integer greater than or equal to 3, the column weight of the yth column is an odd number greater than or equal to 3, the matrix located in the xth row and yth column of the first square matrix is ​​a zero matrix, the column weight of each column of the first square matrix except the yth column is an integer greater than or equal to 2, and w, r, x, and y are positive integers; and outputting the LDPC codeword sequence.

[0007] In the above method, the xth row is the row with the highest row weight in the first matrix, the yth column is the column with the highest column weight in the first matrix, and the matrix located at the xth row and yth column in the first matrix is ​​a zero matrix, that is, the row with the highest row weight and the column with the highest column weight can be staggered, which can avoid the generation of 4 cycles in the basis matrix, accelerate the convergence speed, and improve the coding performance.

[0008] On the other hand, since the rows with the highest row weight and the columns with the highest column weight can be staggered, parallel encoding can be achieved, thereby improving encoding efficiency.

[0009] In a second aspect, a communication method based on LDPC codes is provided, which can be executed by a receiving device or a module or unit in the receiving device (e.g., a chip). The receiving device can be a terminal device or a network device.

[0010] The method includes: obtaining an LDPC codeword sequence; decoding the LDPC codeword sequence according to an LDPC base matrix to obtain an information bit sequence, wherein the LDPC base matrix includes a first square matrix, the first square matrix is ​​composed of the 1st to wth rows and the rth to r+w-1th columns of the LDPC base matrix, the first square matrix includes the xth row and the yth column, the row weight of the xth row is an integer greater than or equal to 3, the column weight of the yth column is an odd number greater than or equal to 3, the matrix located in the xth row and yth column of the first square matrix is ​​a zero matrix, the column weight of each column of the first square matrix except the yth column is an integer greater than or equal to 2, and w, r, x, and y are positive integers.

[0011] In the above method, the xth row is the row with the highest row weight in the first matrix, the yth column is the column with the highest column weight in the first matrix, and the matrix located at the xth row and yth column in the first matrix is ​​a zero matrix, that is, the row with the highest row weight and the column with the highest column weight can be staggered, which can avoid the generation of 4 cycles in the basis matrix, accelerate the convergence speed, and improve the coding performance.

[0012] On the other hand, since the rows with the highest row weight and the columns with the highest column weight can be staggered, parallel encoding can be achieved, thereby improving encoding efficiency.

[0013] In combination with any of the above aspects, in some implementations, each row of the first matrix except the x-th row has a row weight of 2, and each column of the first matrix except the y-th column has a column weight of 2.

[0014] In combination with any of the above aspects, in some implementations, the row weight of the x-th row is 3, and the column weight of the y-th column is 3.

[0015] In combination with any of the foregoing aspects, in some implementations, the first square matrix is ​​a 4×4 matrix, and the base graph of the first square matrix is ​​an M1 matrix, or the base graph of the first square matrix is ​​a matrix obtained by performing at least one of a row transformation or a column transformation on the M1 matrix, wherein the M1 matrix is ​​the following matrix:

[0016] Among them, "0" represents a zero matrix of Zc×Zc, "1" represents a non-zero matrix of Zc×Zc, and Zc is a positive integer.

[0017] In combination with any of the above aspects, in some implementations, the base image of the first matrix is ​​an M1 matrix, and the first matrix is ​​an M2 matrix, where the M2 matrix is ​​the following matrix:

[0018] Among them, "-1" represents the zero matrix of Zc×Zc, "0" represents the identity matrix in the non-zero matrix of Zc×Zc, "a", "b", and "c" represent the matrices obtained by cyclically shifting the identity matrix of Zc×Zc by a, b, or c positions, respectively. The non-zero matrix of Zc×Zc also includes matrices represented by "a", "b", and "c", where a, b, and c are integers greater than or equal to 0.

[0019] In combination with any of the foregoing aspects, in some implementations, the first square matrix is ​​a 5×5 matrix, and the base graph of the first square matrix is ​​an M1 matrix. Alternatively, the base graph of the first square matrix is ​​a matrix obtained by performing at least one of a row transformation or a column transformation on the M1 matrix, where the M1 matrix is ​​the following matrix:

[0020] Among them, "0" represents a zero matrix of Zc×Zc, "1" represents a non-zero matrix of Zc×Zc, and Zc is a positive integer.

[0021] In combination with any of the above aspects, in some implementations, the base image of the first matrix is ​​an M1 matrix, and the first matrix is ​​an M2 matrix, where the M2 matrix is ​​the following matrix:

[0022] Among them, "-1" represents the zero matrix of Zc×Zc, "0" represents the identity matrix in the non-zero matrix of Zc×Zc, "a", "b", and "c" represent the matrices obtained by cyclically shifting the identity matrix of Zc×Zc by a, b, or c positions, respectively. The non-zero matrix of Zc×Zc also includes matrices represented by "a", "b", and "c", where a, b, and c are integers greater than or equal to 0.

[0023] In combination with any of the above aspects, in some implementations, the base graph of the first square matrix is ​​a matrix obtained by performing at least one of row transformation or column transformation on the M1 matrix, and the first square matrix is ​​a matrix obtained by performing at least one of row transformation or column transformation on the M2 matrix.

[0024] In combination with any of the above aspects, in some implementations, at least two of a, b, and c are equal.

[0025] In combination with any of the above aspects, in some implementations, the LDPC base matrix includes a core matrix, the core matrix includes a first square matrix and a first matrix, the first matrix is ​​composed of the 1st to wth rows and the 1st to r-1th columns of the LDPC base matrix, and the first matrix is ​​determined based on the first square matrix.

[0026] In combination with any of the above aspects, in some implementations, at least two offset values ​​corresponding to non-zero elements in the y-th column may be the same.

[0027] This simplifies the encoding process.

[0028] In combination with any of the above aspects, in some implementations, the offset values ​​corresponding to the non-zero elements in each column except the y-th column are the same.

[0029] In a third aspect, a communication device is provided, configured to execute the method provided by any of the above aspects or implementations thereof. Specifically, the device may include units and / or modules, such as a processing unit and / or a transceiver unit, configured to execute the method provided by any of the above aspects or implementations thereof.

[0030] In one implementation, the apparatus is a transmitting device or a receiving device. When the apparatus is a transmitting device or a receiving device, the transceiver unit may be a transceiver, an input / output interface, a communication interface, or an interface unit; and the processing unit may be at least one processor. Optionally, the transceiver is a transceiver circuit. Optionally, the input / output interface is an input / output circuit.

[0031] In another implementation, the apparatus is a chip, chip system, or circuit used in a transmitting device or a receiving device. When the apparatus is a chip, chip system, or circuit used in a transmitting device or a receiving device, the transceiver unit may be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip, chip system, or circuit; and the processing unit may be at least one processor, processing circuit, or logic circuit.

[0032] In a fourth aspect, a communication device is provided, which includes: at least one processor, the processor is coupled to a memory, the memory is used to store programs, and the processor is used to run the computer program or instructions stored in the memory to execute the method provided by any one of the above aspects or its implementation.

[0033] In one implementation, the apparatus is a transmitting end device or a receiving end device.

[0034] In another implementation, the apparatus is a chip, a chip system, or a circuit used in a transmitting device or a receiving device.

[0035] In a fifth aspect, a communication device is provided, comprising: at least one processor and a communication interface, wherein the at least one processor is configured to retrieve a computer program or instruction stored in a memory through the communication interface to execute the method provided by any of the above aspects or implementations thereof. The communication interface may be implemented in hardware or software.

[0036] In one implementation, the device further includes the memory.

[0037] In a sixth aspect, a processor is provided for executing the methods provided in the above aspects.

[0038] For the operations such as sending and acquiring / receiving involved in the processor, unless otherwise specified, or if they do not conflict with their actual functions or internal logic in the relevant descriptions, they can be understood as operations such as processor output, reception, and input, or as sending and receiving operations performed by the radio frequency circuit and antenna. This application does not limit this.

[0039] In the seventh aspect, a computer-readable storage medium is provided, on which a computer program or instruction is stored. When the computer program or instruction is run on a computer, the computer executes the method provided by any one of the above aspects or its implementation.

[0040] In an eighth aspect, a computer program product comprising instructions is provided, which, when run on a computer, enables the computer to execute the method provided by any one of the above aspects or its implementation.

[0041] In the ninth aspect, a chip or chip system is provided, which includes a processor. The processor runs a computer program or instruction stored in a memory, so that a communication device equipped with the chip or chip system executes the method provided in any one of the above aspects or its implementation.

[0042] Optionally, the chip or chip system further includes a communication interface, through which the processor can run computer programs or instructions in the memory, wherein the communication interface can be implemented by hardware or software.

[0043] Optionally, as an implementation manner, the chip further includes a memory, and the memory is used to store computer programs or instructions.

[0044] When the method provided in this application is executed by a chip, this application does not limit the number of chips that implement the method. For example, the method can be executed by one chip or by two or more chips. Furthermore, when the number of chips implementing the method of this application is two or more, the chip manufacturers are not limited and can be the same manufacturer or different manufacturers.

[0045] In a tenth aspect, a communication system is provided, comprising at least one of the transmitting device or the receiving device described above.

[0046] In an eleventh aspect, a computer program is provided, which, when executed on a computer, enables the method provided by any one of the above aspects or its implementation to be executed. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] FIG1 is a schematic diagram of a network architecture to which embodiments of the present application can be applied.

[0048] FIG2 is a schematic diagram of an LDPC check matrix H.

[0049] FIG3 is a Tanner graph of an LDPC check matrix H.

[0050] FIG4 is a schematic diagram of the structure of a check matrix.

[0051] FIG5 is a schematic diagram of the information transmission process.

[0052] FIG6 is a schematic diagram showing the structures of the base graphs of several B matrices.

[0053] FIG7 is a schematic flowchart of a communication method 700 based on LDPC codes provided in this application.

[0054] 8 and 9 are schematic diagrams of the encoding process provided in the embodiments of the present application.

[0055] FIG10 is a schematic flowchart of a communication method 1000 based on LDPC codes provided in this application.

[0056] FIG11 is a core matrix corresponding to the dual diagonal structure and the M of this application b Comparison chart of the simulation results of the matrix.

[0057] 12 and 13 are schematic structural diagrams of possible communication devices provided in embodiments of the present application.

[0058] FIG14 is a schematic diagram of a chip system 30 provided in an embodiment of the present application. DETAILED DESCRIPTION

[0059] To facilitate understanding of the embodiments of the present application, the following explanations are made before introducing the embodiments of the present application.

[0060] “For indicating” or “indicating” may include being used for direct indication and being used for indirect indication, or “being used for indicating” or “indicating” may be indicated explicitly and / or implicitly.

[0061] The various numerical numbers such as first, second, etc. are only used for the convenience of description and are not used to limit the scope of the embodiments of the present application, for example, to distinguish different messages, different information, etc.

[0062] The “pre-definition” can be implemented by pre-storing corresponding codes, tables or other methods that can be used to indicate relevant information in the device. This application does not limit the specific implementation method.

[0063] The “protocol” involved may refer to a standard protocol in the field of communications, for example, it may include the long term evolution (LTE) protocol, the new radio (NR) protocol, and related protocols used in future communication systems, which are not limited in this application.

[0064] The words "exemplary," "for example," "illustratively," "as another example," etc. are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" in this application should not be interpreted as being preferred or advantageous over other embodiments or designs.

[0065] The terms "include", "comprising", "having" and variations thereof mean "including but not limited to", unless specifically emphasized otherwise.

[0066] "At least one" means one or more, and "more" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b and c can mean: a, or b, or c, or a and b, or a and c, or b and c, or a, b and c. Where a, b and c can be single or multiple, respectively.

[0067] "When...", "if...", "in the case of..." and "if" all mean that the network element will make corresponding processing under certain objective circumstances. It does not limit the time, nor does it require the network element to have a judgment action when it is implemented, nor does it mean that there are other limitations. In addition, in this application, the description of the above-mentioned "when...", "if...", "in the case of..." and "if" conditions can be understood as necessary conditions, and there is no limitation on whether the condition is a sufficient condition or whether it is a necessary and sufficient condition. For example, "in the case of A, execute B" can be understood as "if at least A is satisfied, execute B."

[0068] In addition, the network architecture and business scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Ordinary technicians in this field can know that with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0069] A communication system to which the embodiments of the present application can be applied is described below.

[0070] The embodiments of the present application can be applied to various communication systems, including but not limited to: fifth generation (5G) system or NR system, LTE system, long term evolution-advanced (LTE-A) system, LTE frequency division duplex (FDD) system, LTE time division duplex (TDD) system, etc. It can also be applied to future communication systems, such as the sixth generation mobile communication system. In addition, it can also be applied to device to device (D2D) communication, vehicle-to-everything (V2X) communication, machine to machine (M2M) communication, machine type communication (MTC), Internet of Things (IoT) communication system, narrowband Internet of Things (NB-IoT) system or other communication systems. In addition, the present invention can also be extended to similar wireless communication systems, such as wireless-fidelity (WiFi), worldwide interoperability for microwave access (WIMAX), and communication systems related to the 3rd Generation Partnership Project (3GPP), without limitation.

[0071] A communication system applicable to embodiments of the present application may include one or more transmitting devices and one or more receiving devices. Optionally, one of the transmitting device and the receiving device may be a terminal device, and the other may be a network device. Optionally, both the transmitting device and the receiving device may be terminal devices. Optionally, both the transmitting device and the receiving device may be network devices.

[0072] Exemplarily, FIG1 shows a schematic diagram of a network architecture to which an embodiment of the present application may be applied.

[0073] As shown in Figure 1, the embodiments of the present application can be applied to both uplink data transmission and downlink data transmission. Figure 1 only takes uplink data transmission or downlink data transmission between a network device and two terminal devices (such as terminal device 1 and terminal device 2) as an example. In uplink data transmission, the transmitting device in this article is a terminal device, and the receiving device is a network device; conversely, in downlink data transmission, the transmitting device is a network device, and the receiving device is a terminal device. In addition, the applicability of the embodiments of the present application in other communication scenarios is not limited. For example, it can also be applied to sidelink communications.

[0074] The terminal device of the present application may also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, drone, wireless communication device, user agent or user device, etc. The terminal device in the embodiments of the present application may refer to a device that provides voice and / or data connectivity to a user and can be used to connect people, objects and machines, such as a handheld device with wireless connection function, a vehicle-mounted device, etc. The terminal device in the embodiments of the present application can be a mobile phone, a tablet computer, a laptop computer, a PDA, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, a wireless terminal in a smart home, etc.

[0075] The network device of the present application may be a device with wireless transceiver functions, and the network device may be a device that provides wireless communication function services, usually located on the network side, including but not limited to the next-generation base station (gNodeB, gNB) in the 5G system, the base station in the sixth-generation mobile communication system, the base station in the future mobile communication system, or the access node in the wireless fidelity (WiFi) system, the evolved node B (eNB) in the long-term evolution (LTE) system, the radio network controller (RNC), the node B (NB), the base station controller (BSC), the home base station (for example, home evolved NodeB or home Node B, HNB), the base band unit (BBU), the transmission reception point (TRP), the transmitting point (TP), the base transceiver station (BTS), the satellite, the drone, etc.

[0076] In a network structure, the network device may include a centralized unit (CU) node, or a distributed unit (DU) node, or a RAN device including a CU node and a DU node, or a RAN device including a control plane CU node and a user plane CU node, and a DU node, or the network device may also be a wireless controller, relay station, vehicle-mounted device, and wearable device in a cloud radio access network (CRAN) scenario. In addition, the base station may be a macro base station, a micro base station, a relay node, a donor node, or a combination thereof. The base station may also refer to a communication module, a modem, or a chip for being set in the aforementioned device or apparatus. The base station may also be a mobile switching center and a device that performs the base station function in D2D, V2X, and M2M communications, a network-side device in a 6G network, or a device that performs the base station function in future communication systems. The base station can support networks with the same or different access technologies without limitation.

[0077] Unless otherwise specified, the device used to implement the function of a terminal device or network device in this application may refer to the terminal device or network device itself, or may refer to a device that can support the terminal device or network device to implement the function, such as a chip system or chip, specifically, a system on a chip (SoC) or a modem. The device can be installed in the terminal device or network device. In the embodiments of the present application, the chip system can be composed of chips, or it can include chips and other discrete devices.

[0078] It should also be noted that some embodiments herein use the 5G system as an example to describe specific solution details. It is understood that when this solution is applied to other communication systems, such as the LTE system or future communication systems, the messages, channels, or information in the solution can be replaced with messages, channels, or information in other communication systems that can implement corresponding functions, and this application does not limit this.

[0079] In addition, the embodiments of the present application can be applied to various application scenarios, such as high-throughput scenarios, high-reliability scenarios, low-latency scenarios, high-reliability and low-latency scenarios, or low-power scenarios. Among them, the high-throughput scenario can be, for example, an enhanced mobile broadband (eMBB) scenario, the high-reliability and low-latency scenario can be, for example, an ultra-reliable low-latency communication (URLLC) scenario, and the low-power scenario can be, for example, an M2M scenario, an MTC scenario, or an IoT scenario.

[0080] To facilitate understanding of the embodiments of the present application, several concepts or terms involved in the embodiments of the present application are briefly explained. The concepts or terms introduced below are explained based on the concepts or terms specified in the reference protocol, but this does not mean that the embodiments of the present application can only be applied to existing systems. The concepts or terms involved in the embodiments of the present application can be applied to future systems. The specific names of the concepts or terms (for example, concepts or terms involving functional descriptions) can be adjusted as future systems develop.

[0081] 1. LDPC Code

[0082] LDPC codes are linear block codes whose parity check matrices are sparse. The number of zero elements in an LDPC parity check matrix far outnumbers the number of non-zero elements. In other words, the row and column weights of the parity check matrix are very small compared to the LDPC code length.

[0083] For an LDPC code with an information bit sequence length of K and a code length of N, it can be uniquely determined by its check matrix. The dimension of its check matrix H is (NK)×N. The corresponding codeword c can be defined by the check matrix H as: c={c|Hc T =0,c∈{0,1} N}

[0084] In the check matrix H, each row corresponds to a check equation of the LDPC code, each check equation corresponds to a check node (CN), and NK check equations correspond to NK check nodes of the LDPC code; each column corresponds to a code element (or code word bit) of the LDPC code, each code word bit corresponds to a variable node, and N code elements correspond to N variable nodes (VN) of the LDPC code. The non-zero elements h in the matrix H are i,j Indicates that the i-th check node is connected to the j-th variable node. The number of nonzero elements in each row of the check matrix is ​​the degree of the check node, and the number of nonzero elements in each column is the degree of the variable node. If the degrees of all check nodes are equal, the degrees of all variable nodes are also equal, and the LDPC code corresponding to this matrix is ​​a regular code; otherwise, it is an irregular code. A regular LDPC code check matrix H with a code length of 10 and a code rate of 1 / 2 is shown in Figure 2, where v0, v1, …, v9 represent variable nodes, and c0, c1, …, c4 represent check nodes.

[0085] Figure 2 shows a schematic diagram of an LDPC parity check matrix H. In Figure 2, there are 10 variable nodes and 5 check nodes. If a codeword bit is included in the corresponding parity check equation, a line connects the variable node and the check node involved, resulting in a Tanner graph.

[0086] LDPC codes can be represented using graphical models. Commonly used graphical models include Tanner graphs, factor graphs, and tree graphs. Tanner graphs are relatively concise and intuitive. In 1981, Tanner represented LDPC codewords using a graph, now called a Tanner graph. Tanner graphs correspond one-to-one with parity check matrices. Tanner graphs consist of two types of vertices: one type represents codeword bits, called variable nodes, and the other type is check nodes, representing check constraints. Each check node represents a check constraint, as illustrated below with reference to Figure 3. In Figure 3, the degree of a node corresponds to the definition of degree in a matrix description; the degree of a node can be defined as the number of edges connected to it.

[0087] FIG3 is a Tanner graph of an LDPC check matrix H.

[0088] As shown in Figure 3, the Tanner graph represents the LDPC parity check matrix. For example, for a parity check matrix H with m rows and n columns, the Tanner graph contains two types of nodes: n variable nodes and m check nodes. The n variable nodes correspond to the n columns of the parity check matrix H, and the m check nodes correspond to the m rows of the parity check matrix H. A cycle in a Tanner graph consists of interconnected vertices. The cycle starts and ends at a vertex in this group and passes through each node only once. The length of a cycle is defined as the number of edges it contains, while the girth of the graph, also known as the graph size, is defined as the minimum cycle length in the graph. In Figure 3, the girth is 4, as indicated by the black lines. The variable nodes in the Tanner graph correspond to each column of the parity check matrix H, that is, to each codeword bit of the LDPC codeword. The check nodes in the Tanner graph correspond to each row of the parity check matrix H, that is, to each parity bit of the LDPC codeword. The connections between the two types of nodes correspond to the values ​​of the elements in the H matrix. If there is a connection between the i-th check node and the j-th variable node, the element (i, j) in the H matrix is ​​1. If there is no connection, the corresponding element is 0. The connection between a variable node and a check node can also be called an edge. A connection between a check node and a variable node can also be described as having a connection or edge between the check node and the variable node. The edge relationship between a check node and a variable node can include either the presence of an edge or the absence of an edge.

[0089] As mentioned above, LDPC is a linear block code. It divides the information sequence to be encoded into groups of q bits. The encoder then performs linear operations on these q information bits to obtain m parity bits. These q information bits are then combined with the m parity bits to form a codeword of length n = q + m. The mapping from q information bits to a codeword of length n is typically represented by a corresponding parity check matrix H. Based on the parity check matrix H, a codeword sequence is generated to complete the encoding process. After the codeword sequence is transmitted over the channel, the receiving device decodes the received signal and determines the original information bits.

[0090] 2. QC-LDPC code

[0091] Quasi-cyclic low density parity check (QC-LDPC) codes are a type of structured LDPC codes. Due to the unique structure of its parity check matrix, encoding can be implemented using a simple feedback shift register, reducing the coding complexity of LDPC codes. When the code length is long, the parity check matrix H of the LDPC code will be very large. Therefore, H is usually represented in blocks: the complete parity check matrix H is considered to be composed of multiple Zc ×Z c Specifically, the complete check matrix H can be generated by a base matrix H b Indicates that H b Each element in corresponds to a Z c ×Z c Each submatrix can be represented by the number of cyclic shift bits, thus greatly reducing the storage space required for the complete check matrix H. b The elements in can also be called quasi-cyclic (QC) blocks.

[0092] Based on the basis matrix H b And the improvement value Z c (lifting size), the basis matrix H b Expanded to a complete check matrix for encoding or decoding. c It may also be called expansion factor, lifting factor, expansion value, expansion coefficient, or lifting size, etc.

[0093] Specifically, for the (N, K) QC-LDPC code, the number of check bits is M=NK, and the check matrix H can be expressed as:

[0094] Where N = n b ×Zc,M=m b ×Zc,Zc≥1,P i,j Represents a Zc×Zc cyclic shift matrix or a Zc×Zc all-zero matrix, which can be represented by the corresponding cyclic shift coefficient p i,j To simplify the representation. The cyclic shift matrix here is defined as a cyclic right shift matrix of a unit matrix. The shift factor is determined by the number of bits of the first element shifted right, and the value range is p i,j ∈[-1,Z max -1], where Z max is the maximum value of Zc, that is, Zc≤Z max Therefore, p i,j =-1 represents an all-zero matrix, p i,j =0 represents the unit matrix, 1≤p i,j ≤Z max -1 means that each element in the unit matrix is ​​cyclically shifted right by p i,j The matrix obtained by bit. The conversion function g(p i,j ,Z) usually has the following form:

[0095] Here, % represents the modulo operation.

[0096] For example, the basis matrix H of the QC-LDPC code bAs shown below:

[0097] It can be seen that the basis matrix H b The size of the matrix is ​​4 rows and 24 columns, and the basis matrix H b Each element in represents a Z c The matrix is ​​a square matrix of order. Among them, the basis matrix H b The "-1" in the matrix represents an all-zero matrix, "0" represents the identity matrix, and values ​​such as "13" and "48" represent the cyclic right shift matrix of the identity matrix, with the number of bits shifted right being 13, 48, etc.

[0098] Optionally, the basis matrix H b In addition to "-1", the zero elements in can also be expressed in other forms, such as using "-" or null values ​​to represent an all-zero matrix.

[0099] 3. Non-zero elements and zero elements

[0100] In the check matrix, a zero element indicates that there is no connection relationship between the variable node and the check node, and a non-zero element indicates that there is a connection relationship between the variable node and the check node.

[0101] In the LDPC basis matrix, the zero element represents Z c An all-zero square matrix of order, with non-zero elements representing Z c The identity matrix of order or based on Z c The cyclic permutation matrix of the identity matrix of order , where the values ​​of the non-zero elements represent the cyclic shift values ​​or offset values ​​(SV) relative to the identity matrix. The cyclic shift can be a right cyclic shift or a left cyclic shift.

[0102] This application does not limit the specific representation of zero elements and non-zero elements. For example, in the check matrix H shown in Figure 2, "0" is used to represent zero elements and "1" is used to represent non-zero elements. For another example, as described above, the base matrix H b "-1" is used to represent zero elements, and non-negative values ​​(including 0, 1, 13, 48, etc.) are used to represent non-zero elements.

[0103] When the check matrix only indicates whether a connection relationship exists, the matrix can also be called a base graph (BG). The matrix shown in Figure 2 is a base graph.

[0104] 4. Column weight and row weight

[0105] For a column of a matrix, the column weight can refer to the number of nonzero elements contained in the column. Column weight can also be called column degree or column degree.

[0106] For a row of a matrix, the row weight can refer to the number of non-zero elements contained in the row. Row weight can also be called row degree or row degree.

[0107] For example, as shown in FIG2 , the first column of the check matrix H has a column weight of 2, and the first row has a row weight of 4.

[0108] 5. Structure of the check matrix

[0109] FIG4 is a schematic diagram of the structure of a check matrix.

[0110] As shown in (1) of Figure 4, the check matrix may include a high rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. As shown in (2) of Figure 4, the high rate region may include part A and part B, wherein part A corresponds to information bits (or information bits, system bits, etc.), and part B is a square matrix and corresponds to core check bits (or core check bits). The all-zero region may correspond to part C of (2) of Figure 4, which is an all-zero matrix. The incremental redundancy region may correspond to part D of (2) of Figure 4. The raptor-like region may correspond to part E of (2) of Figure 4, which may be a unit matrix corresponding to the check bits of the low rate extension.

[0111] The parity check matrix of the LDPC code shown in Figure 4 uses a "raptor-like" structure, which can be gradually expanded to lower code rates using a high-code-rate core matrix. In actual use, as shown in Figure 4 (1), the first X1 rows and Y1 columns of the parity check matrix can be intercepted. As the code rate decreases, X1 and Y1 gradually increase, and the area of ​​the matrix used also gradually expands.

[0112] It should be noted that the check matrix can be represented by the LDPC base matrix, so the structure of the LDPC base matrix is ​​similar to that of the check matrix, which will not be described in detail here.

[0113] In the LDPC base matrix, the core rows are the rows corresponding to the core check bits. In other words, the core rows are the rows corresponding to the high code rate region, or the rows corresponding to part A, part B, or part C. The core columns can include all information columns and all core check columns. In other words, the core columns are the columns corresponding to the high code rate region, or the columns corresponding to part A + part B. The kernel matrix is ​​a matrix region composed of all the core rows and all the core columns of the LDPC base matrix. In other words, the kernel matrix is ​​the high code rate region of the LDPC base matrix, or the part composed of part A and part B.

[0114] In this application, the matrix of part A can be referred to as A matrix. Similarly, the matrices of part B, part C, part D, and part E can be referred to as B matrix, C matrix, D matrix, and E matrix, respectively.

[0115] 6. Information transmission process

[0116] Figure 5 is a schematic diagram of the information transmission process. As shown in Figure 5, information is sent by the source, undergoes source coding, channel coding, modulation, air interface transmission, demodulation, channel decoding, source recovery and other processing, and arrives at the destination, completing the transmission of information from the source to the destination. Among them, the processing shown in the upper layer of Figure 5 (including source coding, channel coding and modulation, etc.) is performed at the transmitting end device, and the processing shown in the lower layer (including demodulation, channel decoding, source recovery, etc.) is performed at the receiving end device. The embodiments of the present application mainly relate to source coding, channel coding, channel decoding and source recovery shown in Figure 5.

[0117] In current LDPC codes, there are four cycles in the LDPC base matrix, which is not conducive to fast convergence and affects encoding or decoding performance.

[0118] It should be understood that the shortest loop of a variable node refers to the length of the shortest path, which is equivalent to the minimum number of iterations required for information from the node to be transmitted back to the node itself. Common short loops include 4 loops and 6 loops. The longer the shortest loop, the closer the information transmission algorithm is to the optimal algorithm, and the better the decoding performance.

[0119] For example, the dotted line in FIG2 and FIG3 represents a 4-ring.

[0120] Figure 6 is a schematic diagram of the base graphs of several B matrices currently used in LDPC codes. The shaded areas in Figure 6 represent nonzero elements, the blank areas represent zero elements, and the dashed boxes represent 4-rings. The parity check matrix corresponding to the B matrix in Figure 6 (1) is called BG1, and the parity check matrix corresponding to the B matrix in Figure 6 (2) is called BG2.

[0121] Among them, the B matrix of BG1 is as follows:

[0122] The B matrix of BG2 is as follows:

[0123] Here, "0" represents a zero matrix of Zc×Zc, and "1" represents a non-zero matrix of Zc×Zc, where Zc is a positive integer. In other words, "0" represents a zero element and "1" represents a non-zero element.

[0124] As shown in (1) and (2) of Figure 6, the B matrix adopts a bidiagonal structure, that is, the B matrix is ​​a bidiagonal matrix. This LDPC code has the characteristic of being easy to encode. However, as can be seen from the figure, there are four loops in the B matrix. Since the information transmission decoding algorithm of the LDPC code assumes that the variable nodes are independent of each other, the existence of the four loops destroys the assumption of the independence of the variable nodes. During the iterative decoding process, the variable nodes will frequently transmit information to themselves, which will be detrimental to the convergence of the decoding algorithm and lead to a significant decrease in decoding performance.

[0125] As shown in (3) of FIG6 , in the 802.15.3 standard, the B matrix adopts a lower triangular structure.

[0126] Among them, the B matrix of the lower triangular structure is as follows:

[0127] Here, "0" represents a zero matrix of Zc×Zc, and "1" represents a non-zero matrix of Zc×Zc, where Zc is a positive integer. In other words, "0" represents a zero element and "1" represents a non-zero element.

[0128] Because the lower triangular structure does not need to accumulate all the check equations before recursive encoding like the dual diagonal structure, the lower triangular structure has a lower coding complexity than the dual diagonal structure. However, the lower triangular structure has higher row and column weights (as shown in Figure 6 (1) and (2), the maximum row weight in the base graph is 3, and as shown in Figure 6 (3), the maximum row weight in the base graph is 4), and the number of 4-rings in the lower triangular structure is more than that in the dual diagonal structure (as shown in Figure 6 (1) and (2), there is one 4-ring in the base graph respectively, and as shown in Figure 6 (3), there are two 4-rings in the base graph). During iterative decoding, when node information is updated, the lower triangular structure needs to calculate more information from other nodes, so it has a higher decoding complexity.

[0129] In response to the above problems, the present application provides a communication method and a communication device based on LDPC codes, which can eliminate short loops, thereby achieving rapid convergence and improving encoding or decoding performance.

[0130] The method embodiments of the present application are described below with reference to the accompanying drawings.

[0131] FIG7 is a schematic flowchart of a communication method 700 based on LDPC codes provided in this application.

[0132] Method 700 may be performed by a transmitting device. Unless otherwise specified, "transmitting device" may refer to the transmitting device itself or to a device that supports the transmitting device in implementing its functions. For ease of description, the transmitting device will be used in the following description. The transmitting device may be a terminal device or a network device.

[0133] Method 700 may include at least one of the following steps.

[0134] Step 701: The transmitting device obtains an information bit sequence.

[0135] That is, if the transmitting device needs to communicate with the receiving device, that is, the transmitting device needs to send a signal to the receiving device, the transmitting device needs to first obtain the information bit sequence corresponding to the signal to be sent to the receiving device.

[0136] The transmitting end device obtaining the information bit sequence may refer to: the transmitting end device performing source coding on source symbols to generate the information bit sequence. The transmitting end device obtaining the information bit sequence may also refer to: the transmitting end device receiving the information bit sequence from other communication devices.

[0137] In step 702, the transmitting end device performs LDPC encoding on the information bit sequence according to the LDPC base matrix to obtain an LDPC codeword sequence.

[0138] The LDPC base matrix may be a base matrix stored in the device or a base matrix predefined by the protocol, or may be a base matrix further obtained based on the stored base matrix or the base matrix predefined by the protocol, without limitation.

[0139] In an embodiment of the present application, the LDPC base matrix includes a first square matrix, which is composed of the 1st to wth rows and the rth to r+w-1th columns of the LDPC base matrix, where w and r are positive integers. For example, when the LDPC base matrix can be divided into five parts A, B, C, D, and E as shown in Figure 4, the first square matrix can be part B. The following description of the solution of the present application will take the first square matrix as part B as an example. The first square matrix can also be called a B matrix.

[0140] The first square matrix includes a row whose row weight is an integer greater than or equal to 3 (for the convenience of description, the row is recorded as the x-th row, x is an integer, and 1≤x≤w) and a column whose column weight is an odd number greater than or equal to 3 (for the convenience of description, the column is recorded as the y-th column, y is an integer, and r≤y≤r+w-1), the matrix located at the x-th row and y-th column of the first square matrix is ​​a zero matrix, and the column weight of each column of the first square matrix except the y-th column is an integer greater than or equal to 2.

[0141] Specifically, the matrix located at the xth row and yth column in the first square matrix is ​​a zero matrix. In other words, the element located at the xth row and yth column in the first square matrix is ​​a zero element. The zero element represents a zero matrix. In other words, the non-zero elements corresponding to the row with the highest row weight and the non-zero elements corresponding to the column with the highest column weight can be staggered and there is no overlap.

[0142] It should be understood that in this application, the zero element in the matrix represents a zero matrix or an all-zero square matrix. As shown in Figure 2, the "0" in the matrix H represents a zero element, and the zero element represents an all-zero square matrix. As shown in the above base matrix H b As shown in , “-1” represents a zero element, which represents a square matrix of all zeros.

[0143] Specifically, the xth row can be understood as the row with the highest row weight in the first matrix, and the yth column can be understood as the column with the highest column weight in the first matrix.

[0144] The encoding structure of the first matrix will be described in detail below in conjunction with Figures 8 and 9.

[0145] Step 703: The transmitting device outputs an LDPC codeword sequence.

[0146] The transmitting device may subsequently map the LDPC codeword sequence into an air interface signal and send the air interface signal to the receiving device.

[0147] Based on the above scheme, the matrix located at the xth row and yth column in the first square matrix is ​​a zero matrix, that is, the non-zero elements in the row with the highest row weight and the non-zero elements in the column with the highest column weight are staggered. Since the probability of non-zero elements appearing in rows or columns with higher weights is higher, it is more likely to have a 4-ring. Therefore, staggering the non-zero elements in these rows and columns can avoid the generation of 4-rings in the basis matrix to a certain extent, accelerate the convergence speed, and improve the coding performance.

[0148] On the other hand, since the non-zero elements in the row with the highest row weight and the non-zero elements in the column with the highest column weight can be staggered, parallel encoding can be achieved, thereby improving encoding efficiency.

[0149] In this application, the row weight of each row except the xth row may be the same or different, and this application does not limit this.

[0150] Optionally, the row weight of each row of the first matrix except the x-th row is equal, for example, all are 2.

[0151] In this application, the column weight of each column except the yth column can be the same or different, and this application is not limited.

[0152] Optionally, the column weight of each column of the first matrix except the y-th column is equal, for example, all are 2.

[0153] Optionally, the row weight of the xth row is 3, and the column weight of the yth column is 3.

[0154] The embodiments of the present application focus on improving part B of the LDPC base matrix, that is, improving the coding structure of the LDPC base matrix.

[0155] The encoding structure of the first matrix is ​​described in detail below.

[0156] Optionally, the row weight of the x-th row is 3, the column weight of the y-th column is 3, the row weight of each row except the x-th row is 2, and the column weight of each column except the y-th column is 2.

[0157] As Example 1, the first square matrix is ​​a 4×4 matrix, and the base image of the first square matrix is ​​the M1 matrix, or a matrix obtained by performing at least one of row transformation or column transformation on the M1 matrix, wherein the M1 matrix is ​​the following matrix:

[0158] Here, "0" represents a zero matrix of Zc×Zc, and "1" represents a non-zero matrix of Zc×Zc, where Zc is a positive integer. In other words, "0" represents a zero element and "1" represents a non-zero element.

[0159] In Example 1, matrix M1 is a 4×4 matrix, with row weights of {3, 2, 2, 2} for rows 1 to 4, and column weights of {3, 2, 2, 2} for columns 1 to 4. This means the matrix includes a row with a row weight of 3 (i.e., row 1) and a column with a column weight of 3 (i.e., column 1). Row 1 is the row with the highest row weight, and column 1 is the column with the highest column weight. The row weight of each row except row 1 is 2, and the column weight of each column except column 1 is 2. The element in row 1 and column 1 of matrix M1 is "0," making it a zero matrix. The non-zero elements in row 1 are located in columns 2-4 of row 1, and the non-zero elements in column 1 are located in rows 2-4 of column 1. This means the non-zero elements in the row with the highest row weight and the non-zero elements in the column with the highest column weight can be staggered and have no intersection.

[0160] Looking back at Figure 6, the elements located in the xth row and yth column of these matrices are non-zero elements, that is, the non-zero elements in the row with the highest row weight and the non-zero elements in the column with the highest column weight cannot be staggered, that is, there is an intersection. For example, in (1) of Figure 6, the 2nd row is the row with the highest row weight, the 1st column is the column with the highest column weight, and the elements located in the 2nd row and 1st column of the matrix are non-zero elements. For another example, in (2) of Figure 6, the 3rd row is the row with the highest row weight, the 1st column is the column with the highest column weight, and the elements located in the 3rd row and 1st column of the matrix are non-zero elements. For another example, in (3) of Figure 6, the 4th row is the row with the highest row weight, the 1st column is the column with the highest column weight, and the elements located in the 4th row and 1st column of the matrix are non-zero elements.

[0161] The encoding process is described below with reference to the matrix M1 and FIG8 .

[0162] FIG8 is a schematic diagram of several encoding processes provided in an embodiment of the present application.

[0163] According to the structure of the LDPC code shown in Figure 4, the matrix of part B is the M1 matrix mentioned above. Assume that the input information bit sequence is s and the length of s is n. A , and A[i] represents the i-th row of matrix A, and the values ​​of i are 1, 2, 3, and 4. Assume:

[0164] Among them, d1, d2, d3, and d4 represent the calculation results of A[i] and s, which are intermediate results in the encoding process.

[0165] Assuming that the codeword sequence output by the core matrix encoding is c1, then the equation group holds, so we have: [AB]·[sp] T =0 (2)

[0166] Wherein, p represents a parity bit, p={p0, p1, p2, p3}, and p0, p1, p2, p3 represent the parity bit values ​​corresponding to the 1st to 4th columns respectively.

[0167] Expanding formula (2) yields:

[0168] Where B[i] represents the i-th row of the B matrix.

[0169] As shown in (1) of Figure 8, substitute the values ​​of formula (1) and the M1 matrix into formula (3) and the calculation yields:

[0170] Solving equation (4) yields:

[0171] It should be understood that the above operations are all modulo 2 operations.

[0172] In summary, the encoding process can be divided into two parts:

[0173] In the first part, sum all the equations to get the check bit value p0 corresponding to the first column;

[0174] In the second part, p1 to p3 are calculated based on the obtained check bit value p0 corresponding to the first column. Since the calculation processes of p1 to p3 are not interdependent, the second part can be encoded in parallel, which helps to reduce the encoding delay.

[0175] The following briefly describes parallel coding and serial coding in conjunction with (2) and (3) of FIG8 .

[0176] As shown in (2) of Figure 8, substitute the values ​​of the B matrix of BG1 and Equation (1) into Equation (3) and the calculation yields:

[0177] Solving equation (5) yields:

[0178] It should be understood that the above operations are all modulo 2 operations.

[0179] In summary, the encoding process can include two parts:

[0180] In the first part, sum all the equations to get the check bit value p0 corresponding to the first column;

[0181] In the second part, p1 is calculated based on the parity bit value p0 corresponding to column 1. Furthermore, p2 is calculated based on p0 and p1. Furthermore, p3 is calculated based on p2. Because the calculation of p2 depends on p0 and p1, and the calculation of p3 depends on p2, the second part requires serial encoding, which results in a large delay.

[0182] As shown in (3) of Figure 8, by substituting the values ​​of the B matrix of the lower triangular structure into formula (1), the calculation can be obtained:

[0183] Solving equation (6) yields:

[0184] It should be understood that the above operations are all modulo 2 operations.

[0185] In summary, the encoding process can include two parts:

[0186] In the first part, d1 is used as the check bit value p0 corresponding to the first column;

[0187] In the second part, p1 is calculated based on the parity bit value p0 corresponding to column 1. Furthermore, p2 is calculated based on p0 and p1. Furthermore, p3 is calculated based on p0, p1, and p2. Because the calculation of p2 depends on p0 and p1, and the calculation of p3 depends on p0, p1, and p2, the second part requires serial encoding, which results in a significant delay.

[0188] Optionally, in Example 1, the base image of the first square matrix is ​​the M1 matrix, and correspondingly, the first square matrix is ​​the M2 matrix, where the M2 matrix is ​​the following matrix:

[0189] Here, "-1" represents the zero matrix of Zc×Zc, "0" represents the identity matrix in the non-zero matrix of Zc×Zc, and "a," "b," and "c" represent matrices obtained by cyclically shifting the identity matrix of Zc×Zc by a, b, or c positions, respectively. In addition to the identity matrix represented by "0," the non-zero matrix of Zc×Zc also includes matrices represented by "a," "b," and "c," where a, b, and c are integers greater than or equal to 0. Alternatively, "-1" represents a zero element, "0" represents a non-zero element with an offset of 0, and "a," "b," and "c" represent non-zero elements with offsets of a, b, or c, respectively. That is, a "0" in the M1 matrix is ​​represented by "-1" in the M2 matrix, and a "1" in the M1 matrix is ​​represented by "0," "a," "b," and "c" in the M2 matrix.

[0190] It should be understood that the cyclic shift in the present application may refer to a right cyclic shift or a left cyclic shift, without limitation.

[0191] Optionally, when the base image of the first square matrix is ​​a matrix obtained by performing at least one of row transformation or column transformation on the M1 matrix, the first square matrix is ​​a matrix obtained by performing at least one of row transformation or column transformation on the M2 matrix.

[0192] Exemplarily, Table 1 shows matrices obtained by performing at least one of row transformation or column transformation on the M1 matrix, and each matrix is ​​numbered #1, #2, ..., #24.

[0193] Table 1

[0194] It should be understood that Table 1 only lists a portion of matrices obtained by row transformation or column transformation of the M1 matrix, and the remaining matrices are not described in detail.

[0195] Optionally, in the first square matrix, at least two of the offset values ​​corresponding to the non-zero elements in the y-th column may be the same. For example, in the M2 matrix mentioned above, at least two of a, b, and c may be the same.

[0196] It should be understood that in the encoding process shown in Figure 8, when calculating the check bits of the first column, all rows need to be added together, and duplicate items need to be eliminated to obtain p0. When at least two offset values ​​are the same, the duplicate items corresponding to the same offset value can be eliminated, simplifying the encoding process.

[0197] Optionally, in the first square matrix, the offset values ​​corresponding to the non-zero elements in each column except the yth column are all the same. For example, in the M2 matrix mentioned above, the offset values ​​of the non-zero elements in columns 2-4 are all 0.

[0198] As Example 2, the first square matrix is ​​a 5×5 matrix, and the base graph of the first square matrix is ​​an M3 matrix, or the base graph of the first square matrix is ​​a matrix obtained by performing at least one of row transformation or column transformation on the M3 matrix, wherein the M3 matrix is ​​the following matrix:

[0199] Here, "0" represents a zero matrix of Zc×Zc, and "1" represents a non-zero matrix of Zc×Zc, where Zc is a positive integer. In other words, "0" represents a zero element and "1" represents a non-zero element.

[0200] In Example 2, matrix M3 is a 5×5 matrix, with row weights of {3, 2, 2, 2, 2} for rows 1 through 5, and column weights of {3, 2, 2, 2, 2} for columns 1 through 5. This means the matrix includes a row with a row weight of 3 (i.e., row 1) and a column with a column weight of 3 (i.e., column 1). Row 1 is the row with the highest row weight, and column 1 is the column with the highest column weight. The row weight of each row except row 1 is 2, and the column weight of each column except column 1 is 2. The elements in row 1 and column 1 of matrix M3 are all "0," making it a zero matrix. The non-zero elements in row 1 are located in columns 2-4 of row 1, and the non-zero elements in column 1 are located in rows 3-5 of column 1. This means the non-zero elements in the row with the highest row weight and the non-zero elements in the column with the highest column weight can be staggered and have no intersection.

[0201] Optionally, in Example 2, the base image of the first square matrix is ​​an M3 matrix, and correspondingly, the first square matrix is ​​an M4 matrix, where the M4 matrix is ​​the following matrix:

[0202] Here, "-1" represents the zero matrix of Zc×Zc, "0" represents the identity matrix in the non-zero matrix of Zc×Zc, and "a," "b," and "c" represent matrices obtained by cyclically shifting the identity matrix of Zc×Zc by a, b, or c positions, respectively. In addition to the identity matrix represented by "0," the non-zero matrix of Zc×Zc also includes matrices represented by "a," "b," and "c," where a, b, and c are integers greater than or equal to 0. Alternatively, "-1" represents a zero element, "0" represents a non-zero element with an offset of 0, and "a," "b," and "c" represent non-zero elements with offsets of a, b, or c, respectively. That is, a "0" in the M3 matrix is ​​represented by "-1" in the M4 matrix, and a "1" in the M3 matrix is ​​represented by "0," "a," "b," and "c" in the M4 matrix.

[0203] It should be understood that the cyclic shift in the present application may refer to a right cyclic shift or a left cyclic shift, without limitation.

[0204] Optionally, when the base image of the first square matrix is ​​a matrix obtained by performing at least one of row transformation or column transformation on the M3 matrix, the first square matrix is ​​a matrix obtained by performing at least one of row transformation or column transformation on the M4 matrix.

[0205] Exemplarily, Table 2 shows matrices obtained by performing at least one of row transformation or column transformation on the M3 matrix, and each matrix is ​​numbered #1, #2, ..., #6.

[0206] Table 2

[0207] It should be understood that Table 2 only lists a portion of matrices obtained by row transformation or column transformation of the M3 matrix, and the remaining matrices are not described in detail.

[0208] Optionally, in the first matrix, at least two of the offset values ​​corresponding to the non-zero elements in the yth column may be the same. For example, in the M4 matrix mentioned above, at least two of a, b, and c may be the same, which can simplify the encoding process.

[0209] Optionally, in the first square matrix, the offset values ​​corresponding to the non-zero elements in each column except the yth column are all the same. For example, in the M4 matrix mentioned above, the offset values ​​of the non-zero elements in columns 2-5 are all 0.

[0210] As Example 3, the first square matrix is ​​an 8×8 matrix. For example, the base image of the first square matrix is ​​an M5 matrix, and the M5 matrix is ​​as follows:

[0211] In Example 3, matrix M5 is an 8×8 matrix. The row weights of rows 1 through 8 are {2, 2, 2, 2, 2, 2, 3, 2}, respectively, and the column weights of columns 1 through 8 are {3, 2, 2, 2, 2, 2, 2, 2}, respectively. This means the matrix includes a row with a row weight of 3 (i.e., row 7) and a column with a column weight of 3 (i.e., column 1). Row 7 has the highest row weight, and column 1 has the highest column weight. Every row except row 7 has a row weight of 2, and every column except column 1 has a column weight of 2. The element in row 7 and column 1 of matrix M5 is "0," making it a zero matrix. The nonzero elements in row 7 are located in columns 5, 7, and 8 of row 7, and the nonzero elements in column 1 are located in rows 1, 3, and 8 of column 1. This means the nonzero elements in the row with the highest row weight and the nonzero elements in the column with the highest column weight can be staggered and have no intersection.

[0212] Optionally, the row weight of the x-th row in the first matrix is ​​an integer greater than 3.

[0213] As Example 4, the first square matrix is ​​an 8×8 matrix. For example, the base image of the first square matrix is ​​an M6 matrix, and the M6 ​​matrix is ​​as follows:

[0214] In Example 4, the row weights of rows 1 to 8 are {6, 2, 1, 1, 1, 2, 2, 2}, and the column weights of columns 1 to 8 are {3, 2, 2, 2, 2, 2, 2, 2}. The row weight of row 1 is 6, and the row weights of the remaining rows are 2 or 1, with row 1 having the highest row weight. The column weight of column 1 is 3, and the column weights of the remaining columns are all 2, with column 1 having the highest column weight. The element in row 1 and column 1 of matrix M6 is "0," meaning it is a zero matrix. In other words, the non-zero elements in row 1 and column 1 are staggered and have no intersection.

[0215] Optionally, the column weight of the y-th column in the first square matrix is ​​an odd number greater than 3.

[0216] As Example 5, the first square matrix is ​​a 9×9 matrix, and its base graph is:

[0217] In Example 5, the row weights of rows 1 to 9 are {2, 2, 2, 3, 2, 3, 2, 3, 2}, and the column weights of columns 1 to 9 are {5, 2, 2, 2, 2, 2, 2, 2, 2}. The row weights of rows 4, 6, and 8 are 3, and the row weights of the remaining rows are 2. Rows 4, 6, and 8 have the highest row weights. The column weight of column 1 is 5, and the column weights of the remaining columns are all 2, with column 1 having the highest column weight. The elements in rows 4, 6, and 8 and columns 1 of this matrix are all "0," making it a zero matrix. In other words, the non-zero elements in rows 4, 6, and 8 are staggered with the non-zero elements in column 1 and have no intersection.

[0218] Optionally, the row weight of each row in the first matrix except the x-th row is an integer greater than 2.

[0219] As Example 6, the first square matrix is ​​a 9×9 matrix, and its base graph is:

[0220] In Example 6, the row weights of rows 1 to 9 are {3, 3, 4, 3, 3, 3, 4, 5, 3}, and the column weights of columns 1 to 9 are {5, 3, 4, 3, 3, 4, 3, 3, 3}. The row weight of row 8 is 5, and the row weights of the remaining rows are 3 or 4, with row 8 having the highest row weight. The column weight of column 1 is 5, and the column weights of the remaining columns are 3 or 4, with column 1 having the highest column weight. The element in row 8 and column 1 of this matrix is ​​"0," meaning it is a zero matrix. In other words, the non-zero elements in row 8 and column 1 are staggered and have no intersection.

[0221] Optionally, the column weight of each column except the y-th column in the first matrix is ​​an integer greater than 2.

[0222] As Example 7, the first square matrix is ​​a 9×9 matrix, and its base graph is:

[0223] In Example 7, the row weights of rows 1 to 9 are {2, 2, 5, 3, 4, 3, 4, 3, 3}, and the column weights of columns 1 to 9 are {5, 3, 3, 3, 3, 3, 3, 3}. The row weight of row 3 is 5, and the row weights of the remaining rows are 2, 3, or 4, with row 3 being the row with the highest row weight. The column weight of column 1 is 5, and the column weights of the remaining columns are 3, with column 1 being the column with the highest column weight. The element in row 3 and column 1 of this matrix is ​​"0," meaning it is a zero matrix. In other words, the non-zero elements in row 3 and column 1 are staggered and have no intersection.

[0224] Optionally, the row weight and column weight in the first matrix satisfy the following characteristics: the column weight of the y-th column is an odd number, for example, N, the column weight of each column except the y-th column is 2, the number of rows in the x-th row is 3, the row weight of each row except the x-th row is 3 or 2, and the element located at the x-th row and y-th column is a zero element, that is, the column with column weight N is staggered with a row with row weight 3.

[0225] This can eliminate short loops and improve encoding or decoding performance.

[0226] Among them, in the first square matrix, there are (N-2) rows with a row weight of 3, and there are (w-N+2) rows with a row weight of 2, where w is the dimension of the first square matrix.

[0227] The value of N and the dimension w of the first matrix satisfy the following relationship:

[0228] in, Indicates rounding down.

[0229] As Example 8, the first square matrix is ​​a 9×9 matrix, and its base graph is any matrix shown in Table 3, and each matrix is ​​numbered 1, 2, 3, and 4 respectively.

[0230] Table 3

[0231] In Example 8, the first column of matrices 1-4 has a column weight of 5, and the remaining columns have a column weight of 2.

[0232] In Matrix 1, the rows with a row weight of 3 are rows 5, 7, and 8, and the remaining rows have a row weight of 2. The element in row 8 and column 1 of Matrix 1 is "0," making it a zero matrix. In other words, the non-zero elements in row 8 and column 1 are staggered and have no intersection.

[0233] In Matrix 2, the rows with a row weight of 3 are rows 2, 3, and 7, and the remaining rows have a row weight of 2. The element in the second row and first column of Matrix 2 is "0", which means it is a zero matrix. In other words, the non-zero elements in the second row and the non-zero elements in the first column are staggered and have no intersection.

[0234] In Matrix 3, the rows with a row weight of 3 are rows 4, 5, and 7, and the remaining rows have a row weight of 2. The element in the 5th row and 1st column of Matrix 3 is "0", which means it is a zero matrix. In other words, the non-zero elements in the 5th row and the non-zero elements in the 1st column are staggered and have no intersection.

[0235] In Matrix 4, the rows with a row weight of 3 are rows 3, 6, and 7, and the remaining rows have a row weight of 2. The element in the 7th row and 1st column of Matrix 4 is "0", which means it is a zero matrix. In other words, the non-zero elements in the 7th row and the non-zero elements in the 1st column are staggered and have no intersection.

[0236] In the first square matrix given in Example 8, its row degree distribution is more uniform, easier to encode, and more suitable for hardware implementation of the row decoding algorithm, with better performance.

[0237] It should be understood that in Examples 3 to 8 above, "0" represents a zero matrix of Zc×Zc, and "1" represents a non-zero matrix of Zc×Zc, where Zc is a positive integer. In other words, "0" represents a zero element and "1" represents a non-zero element.

[0238] Optionally, in each of the above examples, at least two offset values ​​corresponding to the non-zero elements in the column with the highest column weight may be the same, which can simplify the encoding process.

[0239] For example, when the column weight of the yth column is N (where N is an odd number), there are N-1 offset values ​​in the yth column that are identical to each other, and the column weight of each column except the yth column is an even number. In this way, duplicate items corresponding to the same offset value can be eliminated, thereby simplifying the encoding process.

[0240] It should be understood that due to the basic characteristics of LDPC codes, the equivalent matrices of the matrices listed in the above examples after the rows and / or columns are swapped also fall within the scope of the embodiments of the present application. The equivalent matrices of the matrices listed in the above examples after the values ​​of the non-zero elements of the matrices are added to an integer for the entire row and / or column (such as adding 1 to the entire first row or adding 2 to the entire first row, etc.) also fall within the scope of the embodiments of the present application.

[0241] It should also be understood that the embodiments of the present application do not limit the storage method of the offset value of the non-zero element. For example, the storage rule can be used, and the stored value can be the value before modulo (i.e., remainder), modulo the boost value when used, or the value after modulo the maximum boost value, without limitation.

[0242] In addition, in this application, the values ​​of the same letter in matrices of different orders can be the same or different, without limitation. For example, in Example 1, the first square matrix is ​​a 4×4 matrix, Zc represents the order of the zero matrix or non-zero matrix in the M1 matrix, and "a", "b" and "c" represent the offset values ​​​​of a, b or c in the M2 matrix respectively. In Example 2, the first square matrix is ​​a 5×5 matrix, Zc represents the order of the zero matrix or non-zero matrix in the M3 matrix, and "a", "b" and "c" represent the offset values ​​​​of a, b or c in the M4 matrix respectively. However, the values ​​of parameters such as Zc, a, b and c in the 4×4 matrix and the 5×5 matrix are not related, and they can be the same or different.

[0243] FIG9 is a schematic diagram of an encoding process provided in an embodiment of the present application.

[0244] Assume that the input information bit sequence of the LDPC encoder is s, with a length of K, and the output coded codeword sequence is d, with a length of N, where N = [K / R] and R is the code rate. According to the LDPC code check matrix in Figure 4, assume that the dimension of the matrix A is n A ×m A , the dimension of the B matrix is ​​m A ×m A , the dimension of the C matrix is ​​m A ×m D , the dimension of the D matrix is ​​m D ×(n A +m A ), the dimension of the E matrix is ​​m D ×m D , as shown in Figure 9, the encoding process includes the following steps:

[0245] Step 901: core matrix encoding.

[0246] Specifically, the transmitting device encodes according to the core matrix [AB] to obtain c1=[s e1], where the length of e1 is m A Zc;

[0247] Step 902: Extend the matrix code.

[0248] Encode the extended matrix [DE] with c1 as the new information bit sequence, and get c = [c1 e2], where the length of e2 is m D Zc, the final check digit is recorded as e = [e1 e2], then K = n A Zc, the codeword length after extended matrix coding is K+(m A +m D )Zc.

[0249] Step 903: rate matching.

[0250] Punch the check bits according to the code length and code rate required by the system, and discard the last K+(m A +m D )Zc-[K / R]bit, and obtain the LDPC code encoding result of N points.

[0251] In the above encoding process, the LDPC code check matrix starts from the second row, and the lower right corner is a single diagonal form. Therefore, the calculation of the corresponding check bits is independent of each other, and parallel encoding can be performed to reduce the coding delay.

[0252] FIG10 is a schematic flowchart of a communication method 1000 based on LDPC codes provided in this application.

[0253] Method 1000 may be performed by a receiving device. Unless otherwise specified, "receiving device" may refer to the receiving device itself or to a device that supports the receiving device in implementing its functions. For ease of description, the following description uses the receiving device. The receiving device may be a terminal device or a network device.

[0254] Method 1000 may include at least part of the following.

[0255] Step 1001: A receiving device obtains an LDPC codeword sequence.

[0256] The receiving device obtains an LDPC codeword sequence, which may refer to the receiving device obtaining an LDPC codeword sequence from a memory. The LDPC codeword sequence may be obtained by the receiving device based on an air interface signal from the transmitting device. The receiving device obtains an LDPC codeword sequence, which may refer to the receiving device receiving an air interface signal from the transmitting device and obtaining the LDPC codeword sequence based on the air interface signal.

[0257] Step 1002: The receiving end device decodes the LDPC codeword sequence according to the LDPC base matrix to obtain an information bit sequence.

[0258] It should be noted that since channel noise signals may be introduced during the transmission of air interface signals, the air interface signal output or sent by the transmitting device may be different from the air interface signal received by the receiving device, and the LDPC codeword sequence obtained thereby may also be different from the LDPC codeword sequence output by the transmitting device.

[0259] Similarly, the LDPC base matrix can be a base matrix stored in the receiving device or a base matrix predefined by the protocol, or can be a base matrix further obtained based on the stored base matrix or the base matrix predefined by the protocol, without limitation. The LDPC base matrix in method 1000 can be referred to the relevant description of the transmitting device and will not be described in detail here.

[0260] Optionally, in the present application, the LDPC base matrix includes a core matrix, the core matrix includes a first square matrix and a first matrix, the first matrix is ​​composed of the 1st to wth rows and the 1st to r-1th columns of the LDPC base matrix, and the first matrix is ​​determined based on the first square matrix.

[0261] For example, when the LDPC base matrix can be divided into five parts A, B, C, D, and E as shown in FIG4 , the first matrix can be part A. The first matrix can be determined according to the first square matrix.

[0262] For example, if the first matrix is ​​the M1 matrix mentioned above, the first matrix can be determined based on the first matrix. For example, the principle of the shortest loop in the basis matrix is ​​the longest can be adopted, and the progressive edge growth (PEG) algorithm can be used to expand the search for the base graph of the core matrix as follows: a As shown:

[0263] Here, "0" represents a zero matrix of Zc×Zc, and "1" represents a non-zero matrix of Zc×Zc, where Zc is a positive integer. In other words, "0" represents a zero element and "1" represents a non-zero element.

[0264] As can be seen, the core matrix has dimensions of 4×16, with the first square matrix located in rows 1 to 4 and columns 13 to 16. The first matrix is ​​located in rows 1 to 4 and columns 1 to 12. The first matrix is ​​found using the PEG algorithm based on the first square matrix. The core matrix has columns of weight 3 or 2, with 13 columns of weight 3 and 3 columns of weight 2.

[0265] Furthermore, the offset values ​​of the corresponding elements of the core matrix can be obtained by searching according to the approximate cycle EMD (ACE, where EMD represents the extrinsic message degree) algorithm, as shown below: b As shown:

[0266] Here, "-1" represents the zero matrix of Zc×Zc, "0" represents the identity matrix of Zc×Zc, and "1163," "1152," and so on represent matrices obtained by cyclically shifting the identity matrix of Zc×Zc by 1163, 1152, and so on. Alternatively, "-1" represents a zero element, "0" represents the identity matrix, and "1163," "1152," and so on represent offset values ​​of 1163, 1152, and so on.

[0267] It can be seen from the core matrix that the maximum offset value is 1519. Since the values ​​supported by the lifting factor include 3, 6, 12, 24, 48, 96, 192, 384, 768, and 1536, the maximum value of the lifting factor Z that can be supported by the core matrix is ​​1536.

[0268] The performance of the LDPC code of the embodiment of the present application is described below in conjunction with simulation results.

[0269] FIG11 is a core matrix corresponding to the dual diagonal structure and the M of this application b The comparison chart of the simulation results of the matrix. The simulation parameters are shown in Table 4.

[0270] Table 4

[0271] Specifically, (1) in FIG11 is the simulation result of the information length of 2304 bits and the lifting factor of 192, (2) in FIG11 is the simulation result of the information length of 1152 bits and the lifting factor of 96, and (3) in FIG11 is the simulation result of the information length of 576 bits and the lifting factor of 48. It can be seen from (1), (2) and (3) in FIG11 that the signal-to-noise ratio (SNR) of different symbols is s N0), M b The block error ratio (BLER) of the matrix is ​​lower than the BLER of the core matrix corresponding to the dual diagonal structure. b The LDPC code constructed by the matrix has a performance gain of about 0.05dB compared to the dual diagonal matrix.

[0272] The above describes in detail the method embodiment provided by the present application in conjunction with Figures 7 to 11 , and the following will describe the device embodiment of the present application in conjunction with Figures 12 to 14 .

[0273] It is understood that, in order to implement the functions in the above embodiments, the apparatuses in Figures 12 to 14 include hardware structures and / or software modules corresponding to the functions. Those skilled in the art should readily appreciate that, in conjunction with the various exemplary units and method steps described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software.

[0274] Figures 12 and 13 are schematic diagrams of possible communication devices provided in embodiments of the present application. These devices can be used to implement the functions of the transmitting device or the receiving device in the above method embodiments, thereby also achieving the beneficial effects of the above method embodiments.

[0275] As shown in FIG. 12 , the device 10 includes a transceiver unit 11 and a processing unit 12 .

[0276] When apparatus 10 is used to implement the functions of a transmitting device in each of the above method embodiments, transceiver unit 11 is used to execute the transmitting and receiving steps of the transmitting device, such as steps 701 and 703, and processing unit 12 is used to execute the processing step 702 of the transmitting device. When apparatus 10 is used to implement the functions of a receiving device in each of the above method embodiments, transceiver unit 11 is used to execute the transmitting and receiving steps of the receiving device, such as step 1001, and processing unit 12 is used to execute the processing steps of the receiving device, such as step 1002.

[0277] For a more detailed description of the transceiver unit 11 and the processing unit 12 , please refer to the relevant description in the above method embodiment, which will not be described again here.

[0278] As shown in FIG13 , apparatus 20 includes a processing circuit 21. Processing circuit 21 is coupled to a memory 23, which is used to store instructions. When apparatus 20 is used to implement the method described above, processing circuit 21 is used to execute the instructions in memory 23 to implement the functions of processing unit 12 described above.

[0279] Optionally, the device 20 further includes a memory 23 .

[0280] Optionally, the apparatus 20 further includes a transceiver circuit 22. The transceiver circuit can be referred to as a communication interface. The processing circuit 21 and the transceiver circuit 22 are coupled to each other. It will be appreciated that the transceiver circuit 22 can be a transceiver or an input / output interface. When the apparatus 20 is used to implement the method described above, the processing circuit 21 is used to execute instructions to implement the functions of the processing unit 12, and the transceiver circuit 22 is used to implement the functions of the transceiver unit 11.

[0281] Optionally, the apparatus 20 may be a transmitting end device or a receiving end device, and correspondingly, the transceiver circuit may be a transceiver.

[0282] Optionally, the apparatus 20 may be a chip applied to a transmitting end device or a receiving end device, and accordingly, the transceiver circuit may be an input / output interface.

[0283] Exemplarily, when apparatus 20 is a chip applied to a transmitting device or a receiving device, the chip implements the functions of the transmitting device or the receiving device in the above-described method embodiments. The chip receives information from other modules (such as a radio frequency module or an antenna) in the transmitting device or the receiving device, where the information is sent to the transmitting device or the receiving device by other devices; or the chip sends information to other modules (such as a radio frequency module or an antenna) in the transmitting device or the receiving device, where the information is sent to other devices by the transmitting device or the receiving device.

[0284] 14 is a schematic diagram of a chip system 30 provided in an embodiment of the present application. The chip system 30 (or also referred to as a processing system) includes a logic circuit 31 and an input / output interface 32.

[0285] The logic circuit 31 may be a processing circuit in the chip system 30. The logic circuit 31 may be coupled to a storage unit and execute instructions in the storage unit, so that the chip system 30 can implement the methods and functions of the various embodiments of the present application. The input / output interface 32 may be an input / output circuit in the chip system 30, outputting information processed by the chip system 30 or inputting data or signaling information to be processed into the chip system 30 for processing.

[0286] As a solution, the chip system 30 is used to implement the operations performed by the transmitting end device or the receiving end device in each of the above method embodiments.

[0287] For example, the logic circuit 31 is used to implement the processing-related operations performed by the sending device or the receiving device in the above method embodiment; the input / output interface 32 is used to implement the sending and / or receiving-related operations performed by the sending device or the receiving device in the above method embodiment.

[0288] The present application also provides a communication device, comprising a processing circuit coupled to a memory, the memory being used to store computer programs or instructions and / or data, and the processing circuit being used to execute the computer programs or instructions stored in the memory, or to read data stored in the memory, to perform the methods described in the above method embodiments. Optionally, there are one or more processing circuits. Optionally, the communication device includes a memory. Optionally, there are one or more memories. Optionally, the memory is integrated with the processing circuit or provided separately.

[0289] The present application also provides a chip including a processing circuit coupled to a memory, the memory being configured to store computer programs or instructions, and the processing circuit being configured to execute the computer programs or instructions stored in the memory to implement the methods performed by the transmitting or receiving device in each of the above method embodiments. The memory may be located within the chip or independently of the chip, external to the chip, without limitation herein.

[0290] The present application also provides a computer-readable storage medium storing computer instructions for implementing the methods executed by a transmitting device or a receiving device in the above-mentioned method embodiments.

[0291] The present application also provides a computer program product comprising instructions, which, when executed by a computer, implement the methods performed by a transmitting device or a receiving device in the above-mentioned method embodiments.

[0292] The present application also provides a communication system, which includes at least one of the transmitting end device or the receiving end device in the above embodiments.

[0293] The explanation of the relevant contents and beneficial effects of any of the above-mentioned devices can be referred to the corresponding method embodiments provided above, which will not be repeated here.

[0294] It is understood that the processing circuit in the embodiments of the present application can be a processor or a circuit in a processor for performing processing operations. The processor can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The general-purpose processor can be a microprocessor or any conventional processor.

[0295] The method steps in the embodiments of the present application can be implemented by hardware or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, and the software modules can be stored in random access memory, flash memory, read-only memory, programmable read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, hard disks, mobile hard disks, compact disc read-only memory (CD-ROM) or any other form of storage medium well known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and storage medium can be located in an ASIC. In addition, the ASIC can be located in a transmitting device or a receiving device. Of course, the processor and storage medium can also be present in a transmitting device or a receiving device as discrete components.

[0296] In the above embodiments, all or part of the embodiments may be implemented using software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments may be implemented in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are performed in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user device, or other programmable device. The computer program or instructions may be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions may be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; an optical medium, such as a digital video disk; or a semiconductor medium, such as a solid-state drive.

[0297] In the various embodiments of the present application, unless otherwise specified or there is a logical conflict, the terms and / or descriptions between different embodiments are consistent and can be referenced by each other. The technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships.

[0298] Unless otherwise indicated, all technical and scientific terms used in the embodiments of the present application have the same meaning as those generally understood by those skilled in the art of the technical field of the application. The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit the scope of the application. It should be understood that the above are for illustration, and the examples above are only for helping those skilled in the art to understand the embodiments of the present application, rather than limiting the application embodiments to the specific numerical values ​​or specific scenarios illustrated. Those skilled in the art can obviously carry out various equivalent modifications or changes based on the examples given above, and such modifications and changes also fall within the scope of the embodiments of the present application.

Claims

1. A communication method based on Low-Density Parity-Check (LDPC) codes, characterized in that, The method includes: Obtaining an information bit sequence; Performing LDPC encoding on the information bit sequence according to an LDPC base matrix to obtain an LDPC codeword sequence, where the LDPC base matrix includes a first square matrix, the first square matrix is composed of the 1st row to the wth row and the rth column to the (r + w - 1)th column of the LDPC base matrix, the first square matrix includes the xth row and the yth column, the row weight of the xth row is an integer greater than or equal to 3, the column weight of the yth column is an odd number greater than or equal to 3, the matrix located at the xth row and the yth column in the first square matrix is a zero matrix, and the column weight of each column of the first square matrix except the yth column is an integer greater than or equal to 2, where w, r, x, and y are positive integers; Outputting the LDPC codeword sequence.

2. A communication method based on Low Density Parity Check (LDPC) codes, characterized in that, The method includes: Obtaining an LDPC codeword sequence; Performing decoding on the LDPC codeword sequence according to an LDPC base matrix to obtain an information bit sequence, where the LDPC base matrix includes a first square matrix, the first square matrix is composed of the 1st row to the wth row and the rth column to the (r + w - 1)th column of the LDPC base matrix, the first square matrix includes the xth row and the yth column, the row weight of the xth row is an integer greater than or equal to 3, the column weight of the yth column is an odd number greater than or equal to 3, the matrix located at the xth row and the yth column in the first square matrix is a zero matrix, and the column weight of each column of the first square matrix except the yth column is an integer greater than or equal to 2, where w, r, x, and y are positive integers.

3. The method according to claim 1 or 2, characterized in that, The row weight of each row of the first square matrix except the xth row is 2, and the column weight of each column of the first square matrix except the yth column is 2.

4. The method according to any one of claims 1 to 3, characterized in that The row weight of the xth row is 3, and the column weight of the yth column is 3.

5. The method according to any one of claims 1 to 4, characterized in that The first square matrix is a 4×4 matrix. The base graph of the first square matrix is the M1 matrix, or the base graph of the first square matrix is a matrix obtained by performing at least one of row transformation or column transformation on the M1 matrix, where the M1 matrix is the following matrix: Wherein, "0" represents the zero matrix of Zc×Zc, "1" represents the non-zero matrix of Zc×Zc, and Zc is a positive integer.

6. The method according to claim 5, characterized in that, The base diagram of the first phalanx is the M1 matrix, and the first phalanx is the M2 matrix, where the M2 matrix is the following matrix: Wherein, "-1" represents the zero matrix of Zc×Zc, "0" represents the identity matrix in the non-zero matrix of Zc×Zc, "a", "b", and "c" respectively represent the matrices obtained by cyclically shifting the identity matrix of Zc×Zc by a, b, or c positions, and the non-zero matrix of Zc×Zc further includes the matrices represented by "a", "b", and "c", where a, b, and c are integers greater than or equal to 0.

7. The method according to any one of claims 1 to 4, characterized in that, The first square matrix is a 5×5 matrix. The base graph of the first square matrix is the M1 matrix, or the base graph of the first square matrix is a matrix obtained by performing at least one of a row transformation or a column transformation on the M1 matrix, where the M1 matrix is the following matrix: Wherein, "0" represents the zero matrix of Zc×Zc, "1" represents the non-zero matrix of Zc×Zc, and Zc is a positive integer.

8. The method according to claim 7, characterized in that, The base diagram of the first phalanx is the M1 matrix, and the first phalanx is the M2 matrix, where the M2 matrix is the following matrix: Wherein, "-1" represents the zero matrix of Zc×Zc, "0" represents the identity matrix in the non-zero matrix of Zc×Zc, "a", "b", and "c" respectively represent the matrices obtained by cyclically shifting the identity matrix of Zc×Zc by a, b, or c positions, and the non-zero matrix of Zc×Zc further includes the matrices represented by "a", "b", and "c", where a, b, and c are integers greater than or equal to 0.

9. The method according to claim 6 or 8, characterized in that, The base graph of the first square matrix is a matrix obtained by performing at least one of row transformation or column transformation on the M1 matrix, and the first square matrix is a matrix obtained by performing at least one of the row transformation or column transformation on the M2 matrix.

10. The method according to any one of claims 6, 8, and 9, characterized in that, At least two of a, b, and c are equal.

11. The method according to any one of claims 1 to 10, characterized in that, The LDPC base matrix includes a core matrix, the core matrix includes the first square matrix and the first matrix, the first matrix is composed of the first row to the w-th row and the first column to the (r - 1)-th column of the LDPC base matrix, and the first matrix is determined according to the first square matrix.

12. A communication device, characterized in that, The device includes a unit for performing the method according to any one of claims 1, 3 to 11, or includes a unit for performing the method according to any one of claims 2 to 11.

13. A communication device, characterized in that, Comprising: A processor for executing a computer program to cause the device to perform the method according to any one of claims 1, 3 to 11, or to cause the device to perform the method according to any one of claims 2 to 11.

14. A computer-readable storage medium, characterized in that, A computer program or instruction is stored in the storage medium, and when the computer program or instruction is executed by a communication device, the method according to any one of claims 1, 3 to 11 is implemented, or the method according to any one of claims 2 to 11 is implemented.

15. A computer program product, characterized in that, Comprising a computer program, and when the computer program is run, the method according to any one of claims 1, 3 to 11 is implemented, or the method according to any one of claims 2 to 11 is implemented.

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