Display panel and preparation method therefor, and display device

Abstract

A display panel and a preparation method therefor, and a display device. The display panel comprises: a base substrate (3) comprising a display area (AA) and a non-display area (NA), the non-display area (NA) comprising a binding area (BA); a power line electrically connected to a plurality of sub-pixels (60) of the display area (AA) and configured to transmit a power signal to the plurality of sub-pixels (60); a power input end (11) extending in a direction away from the display area (AA), located in the binding area (BA), electrically connected to the power line, and configured to transmit the power signal to the power line; at least one isolation groove at least partially located in the binding area (BA), at least part of the power input end (11) being located in the isolation groove; and at least one partition island (161), wherein in a direction perpendicular to the base substrate (3), the partition island (161) is located on the side of the power input end (11) close to the base substrate (3), the orthographic projection of the partition island (161) on the base substrate (3) partially overlaps with the orthographic projection of the isolation groove on the base substrate (3), the side of the power input end (11) partially overlaps with the partition island (161), and the edge of the power input end (11) is disconnected at the overlap with the at least one partition island (161).

Description

Display panel and manufacturing method thereof, and display device

[0001] This application claims priority to the Chinese patent application filed on January 22, 2024, with application number 202410089934.0 and invention name “Display Panel and Display Device”, the content of which should be understood as incorporated into this application by reference. Technical Field

[0002] The present disclosure relates to, but is not limited to, the technical field of display panels, and particularly to a display panel and a manufacturing method thereof, and a display device. Background Art

[0003] The display panel is divided into a display area and a non-display area. An organic light-emitting element is arranged in the display area. The organic light-emitting element is easily oxidized and fails. Once water and oxygen invade the display area from the non-display area, the organic light-emitting element will fail, and dark spots and other adverse problems will appear in the display area. Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, at least one embodiment of the present disclosure provides a display panel, comprising: a substrate, comprising a display area and a non-display area at least partially surrounding the display area, the non-display area comprising a bonding area located on one side of the display area; a plurality of sub-pixels, located on one side of the substrate and located in the display area, at least one of the plurality of sub-pixels comprising a pixel driving circuit and a light-emitting element, the pixel driving circuit being configured to drive the light-emitting element to emit light; a power line, electrically connected to the plurality of sub-pixels, the power line being configured to transmit a power signal to the plurality of sub-pixels; a power input terminal, located in the bonding area and electrically connected to the power line, being configured to transmit the power signal to the power line, the power The input terminal extends in a direction away from the display area; at least one isolation groove is at least partially located in the bonding area, and at least part of the structure in the power input terminal is located in the at least one isolation groove; at least one partition island is located on the side of the power input terminal close to the substrate in a direction perpendicular to the substrate, the orthographic projection of the at least one partition island on the substrate partially overlaps with the orthographic projection of the at least one isolation groove on the substrate, the orthographic projection of the side of the power input terminal on the substrate partially overlaps with the orthographic projection of the at least one partition island on the substrate, and the edge of the power input terminal is disconnected at the overlap with the at least one partition island.

[0006] In some exemplary embodiments, at least one covering portion is further included, and the at least one covering portion is located between the at least one partition island and the power input terminal; the at least one covering portion covers at least a portion of the edge of the at least one partition island close to the display area, or the at least one covering portion covers at least a portion of the edge of the at least one partition island away from the display area.

[0007] In some exemplary embodiments, when the at least one covering portion covers at least a portion of an edge of the at least one partition island close to the display area, the edge of the power input terminal is disconnected on a side of the at least one partition island away from the display area; or, when the at least one covering portion covers at least a portion of an edge of the at least one partition island away from the display area, the edge of the power input terminal is disconnected on a side of the at least one partition island close to the display area.

[0008] In some exemplary embodiments, the pixel driving circuit includes a thin film transistor and a storage capacitor; the thin film transistor includes an active layer located on the substrate, a gate, a gate insulating layer and an interlayer insulating layer located on the side of the active layer away from the substrate, and a source electrode and a drain electrode located on the side of the interlayer insulating layer away from the substrate; the storage capacitor includes a first electrode and a second electrode, the first electrode is arranged in the same layer as the gate, and the second electrode is located between the gate insulating layer and the interlayer insulating layer.

[0009] In some exemplary embodiments, in a direction perpendicular to the base substrate, the at least one partition island includes at least one of a first partition portion, a second partition portion, and a third partition portion, the first partition portion and the gate are arranged on the same layer, the second partition portion and the second plate are arranged on the same layer, and the third partition portion and the source electrode are arranged on the same layer.

[0010] In some exemplary embodiments, the pixel driving circuit includes a second source-drain electrode layer, which is located on a side of the source electrode and the drain electrode away from the base substrate; in a direction perpendicular to the base substrate, the at least one partition island also includes a fourth partition portion, and the fourth partition portion and the second source-drain electrode layer are arranged on the same layer.

[0011] In some exemplary embodiments, at least one circle of blocking dams is further included, and the orthographic projection of the power input terminal on the substrate overlaps with the orthographic projection of the at least one circle of blocking dams on the substrate; and the at least one isolation groove is located on at least one side of the at least one circle of blocking dams.

[0012] In some exemplary embodiments, the bonding area further includes a bending area, wherein the bending area is located on a side of the at least one circle of blocking dams away from the display area; the at least one circle of blocking dams includes a first blocking dam and a second blocking dam, wherein the second blocking dam is located on a side of the first blocking dam away from the display area; the at least one isolation groove is located at at least one of the following positions: located on a side of the first blocking dam close to the display area; located between the first blocking dam and the second blocking dam; located between the second blocking dam and the bending area.

[0013] In some exemplary embodiments, the at least one isolation trench includes at least one of a first isolation trench, a second isolation trench, and a third isolation trench; the first isolation trench is located on a side of the second blocking dam away from the display area, the second isolation trench is located between the first blocking dam and the second blocking dam, and the third isolation trench is located on a side of the first blocking dam close to the display area.

[0014] In some exemplary embodiments, the at least one isolation trench includes the first isolation trench, the second isolation trench, and the third isolation trench; the first isolation trench is located on a side of the second blocking dam away from the display area, the second isolation trench is located between the first blocking dam and the second blocking dam, and the third isolation trench is located on a side of the first blocking dam close to the display area.

[0015] In some exemplary embodiments, the at least one partitioning island includes three partitioning islands, and the three partitioning islands are respectively located in the first isolation trench, the second isolation trench, and the third isolation trench.

[0016] In some exemplary embodiments, two isolation islands are provided in each isolation trench, and the two isolation islands overlap with both side edges of the power input terminal respectively, so that both side edges of the power input terminal are disconnected on a side away from the display area.

[0017] In some exemplary embodiments, the power line includes a first power line, which is configured to transmit a positive voltage power signal. The first power line includes a plurality of first power sub-lines located in the display area and a first power bus located in the bonding area. The plurality of first power sub-lines are electrically connected to the plurality of sub-pixels, and the first power bus is connected to the plurality of first power sub-lines. The power input end includes a first power input end, which is connected to the first power bus.

[0018] In some exemplary embodiments, the power line includes a second power line, which is located in the non-display area and at least partially surrounds the display area; the power input terminal includes a second power input terminal, which is connected to the second power line, and the second power line is configured to transmit a negative voltage power signal.

[0019] In a second aspect, at least one embodiment of the present disclosure provides a method for preparing a display panel, comprising: providing a base substrate, comprising a display area and a non-display area at least partially surrounding the display area, the non-display area comprising a bonding area located on one side of the display area; the bonding area comprising at least one isolation groove area, the isolation groove area comprising at least one first mask area; forming a power input terminal on the base substrate in the bonding area, the power input terminal extending in a direction away from the display area and passing through the at least one isolation groove area; the orthographic projection of the side of the power input terminal on the base substrate and the orthographic projection of the first mask area on the base substrate partially overlap; coating a flat layer film on the base substrate, processing the flat layer film using an exposure process, removing the flat layer film located in the isolation groove area, and retaining the flat layer film located in the first mask area; processing the flat layer film located in the first mask area using a development process, removing the flat layer film located in the first mask area.

[0020] In some exemplary embodiments, the processing of the planarizing layer film using an exposure process includes: exposing the planarizing layer film located in the first mask area using a halftone mask; after retaining the planarizing layer film located in the first mask area, the method further includes: coating a pixel definition layer film on the substrate, processing the pixel definition layer film using an exposure process and a development process, and removing the pixel definition layer film located in the isolation groove area; processing the planarizing layer film located in the first mask area using a development process also includes: removing the planarizing layer film located in the first mask area during the processing of the pixel definition layer film using the development process.

[0021] In a third aspect, at least one embodiment of the present disclosure provides a display panel, comprising: a base substrate, comprising a display area and a non-display area at least partially surrounding the display area, the non-display area comprising a bonding area located on one side of the display area; a plurality of sub-pixels, located on one side of the base substrate and in the display area, at least one of the plurality of sub-pixels comprising a pixel driving circuit and a light-emitting element, the pixel driving circuit being configured to drive the light-emitting element to emit light; a power line, electrically connected to the plurality of sub-pixels, the power line being configured to transmit a power signal to the plurality of sub-pixels; a power input end, located in the bonding area and electrically connected to the power line, configured to transmit the power signal to the power line, a portion of an edge of the power input end being a first warped edge, the angle between the first warped edge and the base substrate being A, A being greater than 0° and less than 90°; and at least one isolation groove, at least partially located in the bonding area, the first warped edge being located in the at least one isolation groove.

[0022] In some exemplary embodiments, A satisfies greater than 10° and less than 30°.

[0023] In some exemplary embodiments, the display panel includes at least one circle of blocking dams located in the non-display area and surrounding the display area, the power input terminal extends in a direction away from the display area, the orthographic projection of the power input terminal on the base substrate partially overlaps with the orthographic projection of the at least one circle of blocking dams on the base substrate, and the at least one isolation groove is located at at least one of the following positions: a side of the at least one circle of blocking dams close to the display area, and a side of the at least one circle of blocking dams away from the display area.

[0024] In some exemplary embodiments, the bonding area includes a bending area, the at least one circle of blocking dams is located between the bending area and the display area, the at least one isolation groove is located on the side of the at least one circle of blocking dams close to the display area, or the at least one isolation groove is located between the at least one circle of blocking dams and the bending area.

[0025] In some exemplary embodiments, the at least one isolation trench includes a first isolation trench and a second isolation trench, the first isolation trench being located between the at least one circle of blocking dams and the bending region, and the second isolation trench being located on a side of the at least one circle of blocking dams close to the display region.

[0026] In some exemplary embodiments, the at least one circle of blocking dams includes a first blocking dam and a second blocking dam, the second blocking dam being located on a side of the first blocking dam away from the display area; the first warped edge is located at at least one of the following positions: on a side of the first blocking dam close to the display area; between the first blocking dam and the second blocking dam; between the second blocking dam and the bending area.

[0027] In some exemplary embodiments, the power line includes a first power line, which is configured to transmit a positive voltage power signal. The first power line includes a plurality of first power sub-lines located in the display area and a first power bus located in the bonding area. The plurality of first power sub-lines are electrically connected to the plurality of sub-pixels, and the first power bus is connected to the plurality of first power sub-lines. The power input end includes a first power input end, which is connected to the first power bus.

[0028] In some exemplary embodiments, the power line includes a second power line, which is located in the non-display area and at least partially surrounds the display area; the power input terminal includes a second power input terminal, which is connected to the second power line, and the second power line is configured to transmit a negative voltage power signal.

[0029] In some exemplary embodiments, the display panel further includes a lifting portion, the first warped edge contacts a sidewall of the lifting portion, and an angle between the first warped edge and the base substrate is the same as an angle between the sidewall of the lifting portion and the base substrate.

[0030] In some exemplary embodiments, the orthographic projection of the power input terminal on the base substrate overlaps with the orthographic projection of the lifting portion on the base substrate, and the lifting portion is arranged at at least one of the following positions: both sides of the power input terminal and the middle part of the power input terminal.

[0031] In some exemplary embodiments, the display area further includes a barrier area and an opening area, the barrier area and the display area surround the opening area, and the barrier area is located between the display area and the opening area; the display panel further includes at least one circle of barrier walls located in the barrier area and surrounding the opening area, the barrier wall includes a metal layer, and a partial edge of the metal layer in the barrier wall is a second warped edge, the second warped edge is located on the side of the metal layer facing and / or away from the opening area, and the angle between the second warped edge and the base substrate is greater than 0° and less than 90°.

[0032] In some exemplary embodiments, the barrier wall further includes a raised portion, the second warped edge contacts the raised portion, and an angle between the second warped edge and the base substrate is the same as an angle between a sidewall of the raised portion and the base substrate.

[0033] In some exemplary embodiments, the pixel driving circuit includes a thin film transistor and a storage capacitor; the thin film transistor includes an active layer located on the substrate, a gate, a gate insulating layer and an interlayer insulating layer located on the side of the active layer away from the substrate, and a source electrode and a drain electrode located on the side of the interlayer insulating layer away from the substrate; the storage capacitor includes a first electrode and a second electrode, the first electrode is arranged in the same layer as the gate, and the second electrode is located between the gate insulating layer and the interlayer insulating layer.

[0034] In some exemplary embodiments, the elevation portion includes an insulating layer structure disposed in the same layer as at least one of the gate insulating layer and the interlayer insulating layer.

[0035] In some exemplary embodiments, the raised portion includes a metal layer structure, and the metal layer structure is disposed in the same layer as at least one of the first electrode plate and the second electrode plate.

[0036] In some exemplary embodiments, the lifting portion includes an insulating layer structure and a metal layer structure, the insulating layer structure is arranged in the same layer as at least one of the gate insulating layer and the interlayer insulating layer, and the metal layer structure is arranged in the same layer as at least one of the first electrode plate and the second electrode plate.

[0037] In a fourth aspect, at least one embodiment of the present disclosure provides a display device, comprising the above-mentioned display panel, or comprising a display panel prepared by the above-mentioned method.

[0038] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0039] Summary of the Figures

[0040] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation of the technical solution of the present disclosure. The following describes the embodiments of the present disclosure in conjunction with the accompanying drawings, in which:

[0041] FIG1 is a schematic cross-sectional view of a power input terminal;

[0042] FIG2 is a schematic plan view of a display panel provided by at least one embodiment of the present disclosure;

[0043] FIG3A is a schematic diagram of a partial structure of a display panel provided by at least one embodiment of the present disclosure;

[0044] FIG3B is a schematic cross-sectional view of the display panel along line AA in FIG3A ;

[0045] FIG3C is a partial structural diagram of the cross section in FIG3B ;

[0046] FIG4A is a schematic diagram of a partial structure of a display panel provided by at least one embodiment of the present disclosure;

[0047] FIG4B is a schematic cross-sectional view of the display panel along line AA in FIG4A ;

[0048] FIG4C is a partial structural diagram of the cross section in FIG4B ;

[0049] FIG5A is a schematic diagram of a partial structure of a display panel provided by at least one embodiment of the present disclosure;

[0050] FIG5B is a schematic cross-sectional view of the display panel along line AA in FIG5A ;

[0051] FIG6A is a schematic cross-sectional view of the display panel along line BB in FIG3A ;

[0052] FIG6B is a first cross-sectional schematic diagram of the display panel along line CC in FIG2 ;

[0053] FIG7A is a schematic diagram of a partial structure of a display panel provided by at least one embodiment of the present disclosure;

[0054] FIG7B is a schematic cross-sectional view of the display panel along line BB in FIG7A ;

[0055] FIG7C is a second cross-sectional schematic diagram of the display panel along line CC in FIG2 ;

[0056] FIG8A is a first cross-sectional schematic diagram of a lifting portion located in a bonding area of ​​a display panel according to at least one embodiment of the present disclosure;

[0057] FIG8B is a second cross-sectional schematic diagram of a lifting portion located in a bonding area of ​​a display panel according to at least one embodiment of the present disclosure;

[0058] FIG8C is a third cross-sectional schematic diagram of a lifting portion located in a bonding area of ​​a display panel according to at least one embodiment of the present disclosure;

[0059] FIG9A is a first cross-sectional schematic diagram of the display panel along line DD in FIG2 ;

[0060] FIG9B is a second cross-sectional schematic diagram of the display panel along line DD in FIG2 ;

[0061] FIG9C is a third cross-sectional schematic diagram of the display panel along line DD in FIG2 ;

[0062] FIG9D is a fourth cross-sectional schematic diagram of the display panel along line DD in FIG2 ;

[0063] FIG10 is a schematic cross-sectional view of a metal layer in a barrier wall of a display panel according to at least one embodiment of the present disclosure;

[0064] FIG11A is a schematic diagram of a partial structure of a display panel provided by at least one embodiment of the present disclosure;

[0065] FIG11B is an enlarged schematic diagram of the dotted area C1 in FIG11A ;

[0066] FIG11C is an enlarged schematic diagram of the dotted area C2 in FIG11A ;

[0067] FIG11D is a first cross-sectional schematic diagram of the display panel along line EE in FIG11B and FIG11C;

[0068] FIG11E is a schematic cross-sectional view of the display panel along line HH in FIG11B and FIG11C ;

[0069] FIG11F is a second cross-sectional schematic diagram of the display panel along line EE in FIG11B ;

[0070] FIG12A is a third cross-sectional schematic diagram of the display panel along line CC in FIG2 ;

[0071] FIG12B is a third cross-sectional schematic diagram of the display panel in FIG11B and FIG11C along line EE under the structure shown in FIG12A;

[0072] FIG13 is an enlarged schematic diagram of the dotted area C1 in FIG11A according to another embodiment;

[0073] 14A to 14D are schematic cross-sectional views of a display panel during its preparation process according to at least one embodiment of the present disclosure.

[0074] Details

[0075] The following will clearly and completely describe the technical solutions of the embodiments of the present disclosure in conjunction with the accompanying drawings of the embodiments of the present disclosure. The described embodiments are part of the embodiments of the present disclosure, not all of them. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0076] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0077] The display panel is divided into a display area and a non-display area surrounding the display area. The non-display area includes a bonding area located to one side of the display area. A pixel array is provided within the display area, comprising a plurality of sub-pixels. The sub-pixels include a pixel driver circuit and a light-emitting element, with the pixel driver circuit configured to drive the light-emitting element to emit light. The display area is provided with a plurality of first power sub-lines, while the non-display area is provided with a first power bus, a second power line, and a power input terminal. The power input terminal includes a first power input terminal and a second power input terminal. The first power input terminal is electrically connected to the plurality of first power sub-lines via the first power bus. Each first power sub-line is electrically connected to a column of sub-pixels. The first power input terminal is capable of transmitting a positive voltage power signal to the plurality of first power sub-lines, while the second power input terminal is capable of transmitting a negative voltage power signal to the plurality of sub-pixels via the second power line. The power input terminal is located in the bonding area. The bonding area also includes at least one isolation trench that at least partially surrounds the display area. Organic film layers, such as the planarization layer and the pixel definition layer, within the isolation trench are removed, thereby blocking the transmission path for water and oxygen to enter the display area from the bonding area, thereby protecting the display area. The power input terminal needs to pass through the isolation slot and then be connected to the corresponding power bus.

[0078] The pixel driver circuit includes a source-drain electrode layer. In some examples, to simplify the display panel manufacturing process, the source-drain electrode layer is provided on the same layer as the power input terminal. A cross-section of the power input terminal is shown in Figure 1. The source-drain electrode layer and the power input terminal generally have a three-layer structure of Ti-Al-Ti.

[0079] Since the display area has more film layers than the non-display area, after the source / drain electrode layer and the power input terminal are formed, a multilayer film layer needs to be formed in the display area through a patterning process. The patterning process mainly includes coating an organic glue (such as photoresist), exposing, developing, etching, and removing the organic glue. Chemical agents may be used in the development, etching, and removal of the organic glue. After the power input terminal is formed, in the process of forming other film layers in the display area through the patterning process, the corresponding organic film layer needs to be removed in the isolation groove. The chemical agents will corrode the side of the metal layer in the power input terminal, among which Al is corroded the fastest, causing the side of the power input terminal to form an inward-concave side etching area. As the number of film layers formed in the display area increases, the number of development and etching processes increases, and the corrosion of the side of the metal layer located in the isolation groove gradually accumulates, and the depth of the side etching area gradually expands. During the process of coating the organic glue in the patterning process, the organic glue will enter the side etching area. During the development or removal process, the organic glue that enters the undercut area has a smaller contact surface with the chemicals, resulting in a slower reaction rate and difficulty in complete removal. The remaining organic glue accumulates in the undercut area. This lack of contact between the organic glue and the chemicals results in inconsistent thickness and shape within each section of the undercut area along the power input terminal. After curing, the accumulated organic glue remains completely within the undercut area, forming a complex and porous organic residue. This makes it easy for water and oxygen to form channels within the organic residue along the side of the power input terminal. Once injected, water and oxygen can intrude along these channels into the display area, causing packaging failure. The display area contains electroluminescent (EL) material used for display. This material fails when intruded by water and oxygen, resulting in dark spots in the display area.

[0080] An embodiment of the present disclosure provides a display panel, including a substrate, a plurality of sub-pixels, a power line and a power input terminal, wherein the substrate includes a display area and a non-display area at least partially surrounding the display area, the non-display area including a bonding area located on one side of the display area; the plurality of sub-pixels are located on one side of the substrate and in the display area, at least one of the plurality of sub-pixels includes a pixel driving circuit and a light-emitting element, and the pixel driving circuit is configured to drive the light-emitting element to emit light; the power line is electrically connected to the plurality of sub-pixels, and the power line is configured to transmit a power signal to the plurality of sub-pixels; the power input terminal is located in the bonding area and connected to the power line, and is configured to transmit a power signal to the power line, a portion of an edge of the power input terminal is a first warped edge, and an angle A between the first warped edge and the substrate is greater than 0° and less than 90°; at least one isolation groove is at least partially located in the bonding area, and the orthographic projection of the first warped edge on the substrate is located within the range of the orthographic projection of the at least one isolation groove on the substrate.

[0081] The display panel provided by the embodiment of the present disclosure can effectively reduce the accumulation of organic glue at the first warped edge and reduce the possibility of forming a continuous water-oxygen channel on the side of the power input terminal by setting a portion of the edge of the power input terminal in the isolation groove as the first warped edge, and the angle between the first warped edge and the base substrate is greater than 0° and less than 90°, thereby improving the packaging reliability of the display panel.

[0082] The display panels and manufacturing methods of some embodiments of the present disclosure are described below through several specific examples.

[0083] FIG2 is a schematic plan view of a display panel provided in at least one embodiment of the present disclosure, and FIG3A is a schematic view of a partial structure of a display panel provided in at least one embodiment of the present disclosure.

[0084] As shown in Figures 2 and 3A, the display panel includes a base substrate 3, which includes a display area AA and a non-display area NA. At least a portion of the non-display area NA surrounds the display area AA. A pixel array is provided within the display area, and the pixel array includes a plurality of sub-pixels 60. The sub-pixels 60 include a pixel driving circuit 70 and a light-emitting element EL. The pixel driving circuit 70 is configured to drive the light-emitting element EL to emit light.

[0085] The display panel also includes power lines, which include a first power line and a second power line 13. The first power line is configured to transmit a positive voltage power signal (e.g., a VDD signal). The first power line includes a plurality of first power sub-lines 12 located in the display area AA and a first power bus 10 located in the bonding area BA. The second power line 13 is located in the non-display area NA and at least partially surrounds the display area AA. The second power line 13 is configured to transmit a negative voltage power signal (e.g., a VSS signal). The non-display area NA is provided with a power input terminal 11, which includes a first power input terminal 111 and a second power input terminal 112. The first power input terminal 111 is electrically connected to the first power bus 10, and the plurality of first power sub-lines 12 are electrically connected to the plurality of sub-pixels 60, wherein each first power sub-line 12 is electrically connected to a column of sub-pixels 60. The first power input terminal 111 is capable of transmitting a positive voltage power signal (e.g., a VDD signal) to the first power bus 10, and the plurality of first power sub-lines 12 are capable of transmitting positive voltage power signals (e.g., a VDD signal) to the plurality of sub-pixels 60. The second power input terminal 112 is electrically connected to the second power line 13 .

[0086] In some examples, the display panel is a flexible display panel, and the bonding area BA includes a bending area 01, which is located away from the display area AA. The bonding area BA bends at the bending area 01, causing a portion of the display panel to flip to the side of the base substrate 3 away from the pixel array. The bonding area BA is provided with a plurality of first solder pads PIN1 for bonding the driver chip and a plurality of second solder pads PIN2 for bonding the flexible circuit board. The plurality of second solder pads PIN2 provide power signals to the power input terminal 11, and the plurality of first solder pads PIN1 provide control signals (such as data signals) to the pixel driver circuit 70. Figure 6B is a first cross-sectional schematic diagram of the display panel along line CC in Figure 2.

[0087] For example, as shown in FIG6B , the pixel driving circuit 70 includes a thin film transistor 4 and a storage capacitor 5. The thin film transistor 4 includes an active layer 41, a gate electrode 42, a gate insulating layer 43 (for example, including a first gate insulating layer 431 and a second gate insulating layer 432), an interlayer insulating layer 44, and a source-drain electrode layer 45, which are sequentially arranged on the base substrate 3. The storage capacitor 5 includes a first electrode 51 and a second electrode 52. The first electrode 51 is arranged in the same layer as the gate electrode 42, and the second electrode 52 is located between the gate insulating layer 43 and the interlayer insulating layer 44. For example, the power input terminal 11 is arranged in the same layer as the source-drain electrode layer 45. The source-drain electrode layer 45 includes a source electrode S and a drain electrode D.

[0088] In the embodiments of the present disclosure, two or more functional layers are arranged in the same layer, which means that these functional layers arranged in the same layer can be formed using the same material layer and the same preparation process (such as patterning process, etc.), thereby simplifying the preparation process of the display panel.

[0089] For example, the source electrode S, drain electrode D, and power input terminal 11 each comprise three metal layers, such as titanium / aluminum / titanium or molybdenum / aluminum / molybdenum. The three metal layers of the power input terminal 11 correspond one-to-one with the three metal layers of the source / drain electrode layer 45 and are made of the same material. Thus, the power input terminal 11 and the source / drain electrode layer 45 can be formed using the same three metal layers and the same patterning process.

[0090] For example, the display area AA of the display panel further includes a planar layer 61, a pixel defining layer 62, and a spacer 63. The planar layer 61 is used to planarize the pixel driving circuit 70, and the pixel defining layer 62 is on the side of the planar layer 61 away from the thin film transistor 4. The pixel defining layer 62 is used to define a plurality of sub-pixels 60. The spacer 63 is on the side of the pixel defining layer 62 away from the planar layer 61. For example, the light-emitting element EL included in each sub-pixel 60 in the display area AA includes an anode layer 64, a light-emitting layer 65, and a cathode layer 66. The anode layer 64 is connected to the drain electrode D of the thin film transistor 4 through a via in the planar layer 61. For example, the cathode layer 66 is formed on the entire surface of the base substrate 3. For example, an auxiliary light-emitting layer (not shown in the figure) that helps the light-emitting layer 65 emit light may be included between the anode layer 64 and the light-emitting layer 65 and between the cathode layer 66 and the light-emitting layer 65, for example, including one or more of an electron transport layer, an electron injection layer, a hole transport layer, and a hole injection layer. The auxiliary light-emitting layer is, for example, an organic material layer. For example, the auxiliary light-emitting layer may be formed on the entire surface of the base substrate 3 .

[0091] For example, the display panel may further include an encapsulation layer 7 , and the encapsulation layer 7 may include a three-layer stacked structure of inorganic encapsulation layer / organic encapsulation layer / inorganic encapsulation layer, for encapsulating the display area AA.

[0092] After forming the power input terminal 11 and the source-drain electrode layer 45, the display panel needs to at least form a flat layer 61, a pixel defining layer 62, a spacer 63, an anode layer 64, and a cathode layer 66 in the display area AA through a patterning process. During the process of forming the flat layer 61, the pixel defining layer 62, the spacer 63, the anode layer 64, and the cathode layer 66 in the display area AA through the patterning process, the power input terminal 11 in the isolation groove is exposed. The edge of the power input terminal 11 will be corroded by the solution used in the patterning process, especially the aluminum that serves as the intermediate metal layer of the power input terminal 11, which corrodes at a faster rate, causing the side of the power input terminal 11 to form a concave side etched area 110 at the aluminum layer (as shown in FIG. 3C ). After the side etched area 110 is formed, the organic glue used in the patterning process will enter the side etched area 110, forming organic residue.

[0093] FIG3B is a schematic cross-sectional view of the display panel along line AA in FIG3A , and FIG3C is a partial structural view of the cross-sectional view in FIG3B .

[0094] As shown in Figures 3B and 3C , a portion of the edge of the power input terminal 11 within the isolation trench forms a first warped edge 113. For example, the height h of the first warped edge 113 can be any value greater than 0 and less than or equal to 5 μm, such as 2.5 μm or 4 μm. The projected length d of the first warped edge 113 on the base substrate 3 can be any value greater than 0 and less than or equal to 10 μm, such as 5 μm or 6 μm. The angle A between the first warped edge 113 and the base substrate 3 is greater than 0° and less than 90°. In some examples, A is greater than 0° and less than 60°; in other examples, A is greater than 0° and less than 45°; and in some examples of the present disclosure, A is greater than 10° and less than 45°, or A is greater than 10° and less than 30°. Of course, the embodiments of the present disclosure do not impose specific limitations on the dimensions of the various structures, as long as they can achieve the corresponding functions.

[0095] In some examples, as shown in Figures 3B and 3C, the first warped edge 113 warps upward, that is, warps in a direction away from the base substrate 3. After the first warped edge 113 warps upward, the undercut region 110 located at the first warped edge 113 faces upward. The organic adhesive surface within the undercut region 110 at the first warped edge 113 becomes smoother and thinner, making it difficult to form a continuous organic residue after curing, and even more difficult to form a continuous water-oxygen channel within the organic residue. Therefore, the water-oxygen channel in the organic residue within the undercut region 110 located on the side of the power input terminal 11 is no longer continuous, at least at the warped edge. This prevents water and oxygen from invading the display area along the water-oxygen channel within the undercut region 110 at the power input terminal 11, effectively improving the reliability of the package.

[0096] 4A is a schematic diagram of a partial structure of a display panel provided in at least one embodiment of the present disclosure, FIG4B is a schematic diagram of a cross-section of the display panel along line AA in FIG4A , and FIG4C is a partial structural diagram of the cross-section in FIG4B .

[0097] In other examples, as shown in Figures 4A to 4C, the first warped edge 113 warps downward, that is, warps toward the base substrate 3. After the first warped edge 113 warps downward, the water and oxygen channels in the organic residue within the undercut region 110 located on the side of the power input terminal 11 are discontinued, at least at the warped edge. This prevents water and oxygen from invading the display area AA along the water and oxygen channels within the undercut region 110 of the power input terminal 11, effectively improving the reliability of the package.

[0098] FIG. 6A is a schematic cross-sectional view of the display panel along line BB in FIG. 3 .

[0099] For example, as shown in Figures 2, 3, and 6A, the display panel further includes at least one ring of barrier dams 20, which is located in the non-display area NA and surrounds the display area AA. During the encapsulation of the display area AA, the at least one ring of barrier dams 20 can block the flow of the organic encapsulation layer in the encapsulation layer 7. The power input terminal 11 extends away from the display area, and the orthographic projection of the power input terminal 11 on the base substrate 3 partially overlaps with the orthographic projection of the at least one ring of barrier dams 20 on the base substrate 3. A first warped edge 113 is located on the side of the at least one ring of barrier dams 20 that is close to and / or away from the display area AA. For example, the first warped edge 113 is located on both the side of the at least one ring of barrier dams 20 that is close to the display area and the side that is away from the display area AA; alternatively, the first warped edge 113 is located on the side of the at least one ring of barrier dams 20 that is close to the display area AA; alternatively, the first warped edge 113 is located on the side of the at least one ring of barrier dams 20 that is away from the display area AA.

[0100] In some examples, at least one circle of barrier dams 20 is located between the display area and the bending area 01, and the first warped edge 113 is located on the side of the at least one circle of barrier dams 20 closer to the display area, and / or the first warped edge 113 is located between the at least one circle of barrier dams 20 and the bending area 01. For example, the first warped edge 113 is located on the side of the at least one circle of barrier dams 20 closer to the display area and between the at least one circle of barrier dams 20 and the bending area 01; or, the first warped edge 113 is located on the side of the at least one circle of barrier dams 20 closer to the display area; or, the first warped edge 113 is located between the at least one circle of barrier dams 20 and the bending area 01.

[0101] For example, at least one circle of barrier dams 20 includes a first barrier dam 201 and a second barrier dam 202, with the second barrier dam 202 located on the side of the first barrier dam 201 away from the display area. The first warped edge 113 is located at at least one of the following locations: the side of the first barrier dam 201 close to the display area, between the first barrier dam 201 and the second barrier dam 202, and between the second barrier dam 202 and the bending region 01. Of course, the at least one circle of barrier dams 20 may also include three or more barrier dams 20, and the first warped edge 113 may be located on the side of any one or more barrier dams 20 close to and / or away from the display area.

[0102] For example, the first barrier dam 201 is disposed in the same layer as at least one of the planar layer 61 and the pixel defining layer 62 , and the second barrier dam 202 is disposed in the same layer as at least one of the planar layer 61 and the pixel defining layer 62 .

[0103] In some examples, as shown in Figures 3A, 4A, and 5A, the bonding area BA further includes at least one isolation trench. The at least one isolation trench is located between the display area AA and the bending area 01 and at least partially surrounds the display area AA. For example, the at least one isolation trench surrounds the display area AA. The at least one isolation trench can include at least one of a first isolation trench 151, a second isolation trench 152, and a third isolation trench 153. The first isolation trench 151 can be located on the side of the second barrier dam 202 away from the display area AA, the second isolation trench 152 can be located between the first and second barrier dams 201, 202, and the third isolation trench 153 can be located on the side of the first barrier dam 201 closer to the display area AA. For example, the at least one isolation trench can include the first isolation trench 151, or the at least one isolation trench can include the second isolation trench 152 and the third isolation trench 153. The number and distribution of the isolation trenches can be determined as needed and are not limited in this disclosure. The orthographic projection of the first warped edge 113 on the base substrate 3 can be located within the orthographic projection of the corresponding isolation trench on the base substrate 3.

[0104] 7A is a schematic diagram of a partial structure of a display panel provided in at least one embodiment of the present disclosure, FIG. 7B is a schematic cross-sectional view of the display panel along line BB in FIG. 7A , and FIG. 7C is a second schematic cross-sectional view of the display panel along line CC in FIG. 2 .

[0105] In some examples, as shown in Figures 7A to 7C , the source-drain electrode layer 45 includes a first source-drain electrode layer 451 and a second source-drain electrode layer 452, and the planar layer 61 includes a first planar layer 611 and a second planar layer 612. The first planar layer 611 is located between the first source-drain electrode layer 451 and the second source-drain electrode layer 452, and the second source-drain electrode layer 452 is connected to the first source-drain electrode layer 451 through vias in the first planar layer 611. The second planar layer 612 is located between the anode layer 64 and the second source-drain electrode layer 452, and the anode layer 64 is connected to the second source-drain electrode layer 452 through vias in the second planar layer 612. The power input terminal 11 is provided on the same layer as the first source-drain electrode layer 451 and / or the second source-drain electrode layer 452. In these examples, the first barrier dam 201 is disposed in the same layer as at least one of the first planar layer 611 , the second planar layer 612 , and the pixel defining layer 62 , and the second barrier dam 202 is disposed in the same layer as at least one of the second planar layer 612 and the pixel defining layer 62 .

[0106] In some examples, as shown in Figures 3A to 3C , the display panel further includes a lifting portion 2, and a first warped edge 113 contacts the sidewalls of the lifting portion 2. The angle between the first warped edge 113 and the base substrate 3 is the same as the angle between the sidewalls of the lifting portion 2 and the base substrate 3, i.e., the first warped edge 113 is affixed to the sidewalls of the lifting portion 2. Under the action of the lifting portion 2, a portion of the power input terminal 11 is lifted to form the first warped edge 113. For example, the lifting portion 2 is disposed on both sides of the power input terminal 11, thereby lifting the side edges of the power input terminal 11 upward, forming the first warped edge 113 that is warped away from the base substrate 3. For example, as shown in Figures 4A and 4C , the lifting portion 2 is disposed in the middle of the power input terminal 11, lifting the middle portion of the power input terminal 11 upward, thereby causing the side edges of the power input terminal 11 to warp downward, forming the first warped edge 113 that is warped toward the base substrate 3. The orthographic projection of the lifting portion 2 on the base substrate 3 may be located within the range of the orthographic projection of the corresponding isolation groove on the base substrate 3 .

[0107] Figure 5A is a schematic diagram of a partial structure of a display panel provided by at least one embodiment of the present disclosure. Figure 5B is a schematic diagram of a cross-section of the display panel along line AA in Figure 5A.

[0108] In some examples, as shown in Figures 5A and 5B , when the lifting portions 2 are provided on both sides of the power input terminals 11, two spaced-apart lifting portions 2 are provided between two adjacent power input terminals 11 to prevent short circuiting of the two adjacent power input terminals 11 through the lifting portions 2, especially when the surface where the lifting portions 2 and the first warped edge 113 contact each other is a metal layer. Of course, when the surface where the lifting portions 2 and the first warped edge 113 contact each other is an insulating layer, only one lifting portion 2 can be provided between two adjacent power input terminals 11 (as shown in Figures 5A and 5B ), with the same lifting portion 2 simultaneously lifting the sides of the two adjacent power input terminals 11.

[0109] FIG8A is a first cross-sectional schematic diagram of a lifting portion located in a bonding area of ​​a display panel provided by at least one embodiment of the present disclosure.

[0110] In some examples, as shown in Figures 6A, 6B, and 8A, the raised portion 2 includes an insulating layer structure 22. For example, the insulating layer structure 22 is disposed in the same layer as at least one of the gate insulating layer 43 (the first gate insulating layer 431 and / or the second gate insulating layer 432) and the interlayer insulating layer 44. For example, the insulating layer structure 22 includes a single insulating sublayer (e.g., the first insulating sublayer 221 or the second insulating sublayer 222), and the first insulating sublayer 221 or the second insulating sublayer 222 is disposed in the same layer as one of the gate insulating layer 43 (the first gate insulating layer 431 and / or the second gate insulating layer 432) or the interlayer insulating layer 44; or the insulating layer structure 22 includes a first insulating sublayer 221 and a second insulating sublayer 222, and one of the first insulating sublayer 221 and the second insulating sublayer 222 is disposed in the same layer as the gate insulating layer 43 (the first gate insulating layer 431 and / or the second gate insulating layer 432), and the other is disposed in the same layer as the interlayer insulating layer 44.

[0111] FIG8B is a second cross-sectional schematic diagram of a lifting portion located in a bonding area of ​​a display panel provided by at least one embodiment of the present disclosure.

[0112] In other examples, as shown in Figures 6A, 6B and 8B, the lifting portion 2 includes a metal layer structure 21. For example, the metal layer structure 21 is arranged in the same layer as at least one of the first electrode plate 51 and the second electrode plate 52. For example, the metal layer structure 21 includes a single metal sublayer (for example, a first metal sublayer 211 or a second metal sublayer 212), and the first metal sublayer 211 or the second metal sublayer 212 is arranged in the same layer as one of the first electrode plate 51 and the second electrode plate 52; or, the metal layer structure 21 includes a first metal sublayer 211 and a second metal sublayer 212, and one of the first metal sublayer 211 and the second metal sublayer 212 is arranged in the same layer as the first electrode plate 51, and the other is arranged in the same layer as the second electrode plate 52. Therefore, in the preparation process, these functional layers arranged in the same layer can be formed using the same material layer through the same patterning process.

[0113] FIG8C is a third cross-sectional schematic diagram of the lifting portion located in the bonding area of ​​the display panel provided by at least one embodiment of the present disclosure.

[0114] For example, in some other examples, as shown in Figures 6A, 6B, and 8C, the lifting portion 2 includes a metal layer structure 21 and an insulating layer structure 22. For example, the metal layer structure 21 includes a first metal sublayer 211 or a second metal sublayer 212, and the insulating layer structure 22 includes a first insulating sublayer 221 or a second insulating sublayer 222. The first metal sublayer 211 or the second metal sublayer 212 is provided in the same layer as the first electrode 51 or the second electrode 52, and the first insulating sublayer 221 or the second insulating sublayer 222 is provided in the same layer as the gate insulating layer 43 (the first gate insulating layer 431 and / or the second gate insulating layer 432) or the interlayer insulating layer 44; or, the metal layer structure 21 includes a first metal sublayer 211 or a second metal sublayer 212, and the insulating layer 221 or the second insulating sublayer 222 includes a first metal sublayer 211 or a second metal sublayer 212, and the first metal sublayer 211 or the second metal sublayer 21 .... The structure 21 includes a first metal sublayer 211 or a second metal sublayer 212, and the first metal sublayer 211 or the second metal sublayer 212 is provided in the same layer as the first electrode 51 or the second electrode 52, and the insulating layer structure 22 includes a first insulating sublayer 221 and a second insulating sublayer 222, and one of the first insulating sublayer 221 and the second insulating sublayer 222 is provided in the same layer as the gate insulating layer 43 (the first gate insulating layer 431 and / or the second gate insulating layer 432), and the other is provided in the same layer as the interlayer insulating layer 44; or, The metal layer structure 21 includes a first metal sublayer 211 and a second metal sublayer 212, one of the first metal sublayer 211 and the second metal sublayer 212 is provided on the same layer as the first electrode 51, and the other is provided on the same layer as the second electrode 52, and the insulating layer structure 22 includes a first insulating sublayer 221 or a second insulating sublayer 222, and the first insulating sublayer 221 or the second insulating sublayer 222 is provided on the same layer as one of the gate insulating layer 43 or the interlayer insulating layer 44; or the metal layer structure 21 includes a first metal sublayer 211 and a second metal sublayer 212. sublayer 211 and the second metal sublayer 212, one of the first metal sublayer 211 and the second metal sublayer 212 is arranged on the same layer as the first electrode 51, and the other is arranged on the same layer as the second electrode 52, the insulating layer structure 22 includes a first insulating sublayer 221 and a second insulating sublayer 222, one of the first insulating sublayer 221 and the second insulating sublayer 222 is arranged on the same layer as the gate insulating layer 43 (the first gate insulating layer 431 and / or the second gate insulating layer 432), and the other is arranged on the same layer as the interlayer insulating layer 44.

[0115] In some examples, as shown in FIG2 , the display area AA includes a blocking area 40 and an aperture area 50. The display area AA and the blocking area 40 surround the aperture area 50, with the blocking area 40 located between the display area AA and the aperture area 50. The display panel may also include an image sensor and / or an infrared sensor, which is incorporated into the non-display side of the display panel, and whose orthographic projection on the base substrate 3 at least partially overlaps with the aperture area 50. Thus, the image sensor and / or infrared sensor can implement various functions such as photography, facial recognition, and infrared sensing through the aperture area 50.

[0116] FIG. 9A is a first cross-sectional schematic diagram of the display panel along line DD in FIG. 2 .

[0117] As shown in Figures 2 and 9A , at least one barrier wall 401 is disposed within the barrier region 40. The barrier wall 401 surrounds the aperture region 50 to prevent moisture and oxygen from penetrating from the aperture region 50 into the display region. For example, the barrier wall 401 includes a metal layer 4012 and a stacked structure 4011, with the stacked structure 4011 positioned below the metal layer 4012. The metal layer 4012 is disposed co-located with the source / drain electrode layer 45. A portion of the edge of the metal layer 4012 forms a second warped edge 40120, located on the side of the metal layer 4012 that faces toward or away from the aperture region 50. After the second warped edge 40120 is set on the side of the metal layer 4012 facing the opening area 50, the organic residue of the metal layer 4012 in the side erosion area 110 facing the opening area 50 is difficult to form a continuous water and oxygen channel at least at the second warped edge 40120, thereby reducing the possibility of water and oxygen invading the circumference of at least one circle of barrier walls 401 in the side erosion area 110 close to the opening area 50, thereby reducing the invasion of water and oxygen from at least one circle of barrier walls 401 into the display area.

[0118] For example, if water and oxygen invade a certain area of ​​the barrier area 40, due to the setting of the second warped edge 40120, it is difficult for water and oxygen to continue to invade along the circumference of the barrier area 40 through the side erosion area 110 of the metal layer 4012, thereby reducing the possibility of water and oxygen invading the display area from other areas, thereby improving the packaging effect of the display panel.

[0119] For example, the angle between the second warped edge 40120 and the base substrate 3 is greater than 0° and less than 90°. In some examples, the angle between the second warped edge 40120 and the base substrate 3 is greater than 0° and less than 60°; in other examples, the angle between the second warped edge 40120 and the base substrate 3 is greater than 0° and less than 45°; in preferred embodiments of the present invention, the angle between the second warped edge 40120 and the base substrate 3 is greater than 10° and less than 45°, or greater than 10° and less than 30°. Of course, the embodiments disclosed herein do not impose specific limitations on the angle between the second warped edge 40120 and the base substrate 3, as long as the corresponding function can be achieved.

[0120] In an exemplary embodiment, a second warped edge 40120 is also provided on the side of the metal layer 4012 facing the display area to further reduce the intrusion of water and oxygen along the circumference of the barrier area 40 through the undercut area 110 of the metal layer 4012 .

[0121] FIG. 9B is a second schematic cross-sectional view of the display panel along line DD in FIG. 2 .

[0122] In some examples, as shown in FIG9B , at least one circle of barrier walls 401 includes a first barrier wall 402 and a second barrier wall 403, with the first barrier wall 402 located on the side of the second barrier wall 403 away from the display area. The second warped edge 40120 is located on at least one of the following: the side of the first barrier wall 402 near the opening area 50, the side of the first barrier wall 402 near the display area, the side of the second barrier wall near the opening area 50, and the side of the second barrier wall 403 near the display area. Of course, the at least one circle of barrier walls 401 may also include three or more barrier walls 401, and the second warped edge 40120 may be located on the side of any one or more barrier walls 401 near the opening area 50 and / or the side near the display area.

[0123] As shown in FIG9A , a lifting portion 2 is also provided within the barrier wall 401. The lifting portion 2 contacts the second warped edge 40120. The angle between the second warped edge 40120 and the base substrate 3 is the same as the angle between the sidewalls of the lifting portion 2 and the base substrate 3. That is, the second warped edge 40120 is in contact with the sidewalls of the lifting portion 2. Under the action of the lifting portion 2, a portion of the metal layer 4012 is lifted to form the second warped edge 40120. For example, as shown in FIG9A , the lifting portion 2 is provided on both sides of the metal layer 4012, thereby lifting the side edges of the metal layer 4012 upward, forming the second warped edge 40120 that is warped away from the base substrate 3. For example, as shown in FIG10 , the lifting portion 2 is provided in the middle of the metal layer 4012, lifting the middle portion of the metal layer 4012 upward, thereby causing the side edges of the metal layer 4012 to warp downward, forming the first warped edge 113 that is warped toward the base substrate 3.

[0124] In some examples, as shown in FIG9A , the stacked structure 4011 includes a first insulating layer 40111 and a second insulating layer 40112. The first insulating layer 40111 is located on a side of the second insulating layer 40112 that is closer to the base substrate 3. The first insulating layer 40111 is disposed on the same layer as the gate insulating layer 43, and the second insulating layer 40112 is disposed on the same layer as the interlayer insulating layer 44. The raised portion 2 includes an insulating layer structure, which is at least one of the first insulating layer 40111 and the second insulating layer 40112. That is, the insulating layer structure is disposed on the same layer as at least one of the gate insulating layer 43 and the interlayer insulating layer 44. For example, the insulating layer structure includes the second insulating layer 40112; or, the insulating layer structure includes the first insulating layer 40111 and the second insulating layer 40112. Thus, these functional layers disposed on the same layer can be formed using the same material layer and the same patterning process, thereby simplifying the manufacturing process of the display panel.

[0125] FIG. 9C is a third cross-sectional schematic diagram of the display panel along line DD in FIG. 2 .

[0126] In other examples, as shown in FIG9C , the stacked structure 4011 includes a first metal layer 40113 and a second metal layer 40114 sequentially disposed on the base substrate 3. For example, the first metal layer 40113, the gate 42, and the first electrode 51 are disposed on the same layer, and the second metal layer 40114 is disposed on the same layer as the second electrode 52. The raised portion 2 includes a metal layer structure, which is at least one layer of the first metal layer 40113 and the second metal layer 40114. That is, the metal layer structure is disposed on the same layer as at least one layer of the first electrode 51 and the second electrode 52. Thus, these functional layers disposed on the same layer can be formed using the same material layer and the same patterning process, thereby simplifying the display panel manufacturing process.

[0127] FIG9D is a fourth cross-sectional schematic diagram of the display panel along line DD in FIG2 .

[0128] In some other examples, as shown in FIG9D , the stacked structure 4011 includes a first metal layer 40113, a first insulating layer 40111, a second metal layer 40114, and a second insulating layer 40112 sequentially arranged on the base substrate 3. For example, the first metal layer 40113, the gate electrode 42, and the first electrode plate 51 are arranged on the same layer, the first insulating layer 40111 and the gate insulating layer 43 are arranged on the same layer, the second metal layer 40114 and the second electrode plate 52 are arranged on the same layer, and the second insulating layer 40112 and the interlayer insulating layer 44 are arranged on the same layer. The lifting portion 2 includes a metal layer structure and an insulating layer structure, the metal layer structure being at least one layer of the first metal layer 40113 and the second metal layer 40114, and the insulating layer structure being at least one layer of the first insulating layer 40111 and the second insulating layer 40112. Thus, these functional layers arranged on the same layer can be formed using the same material layer and the same patterning process to simplify the manufacturing process of the display panel. Of course, without departing from the principles of the present disclosure, the stacked structure 4011 may include any one or more layers of the first metal layer 40113 , the first insulating layer 40111 , the second metal layer 40114 and the second insulating layer 40112 .

[0129] For example, the longitudinal cross-section of the raised portion 2 is trapezoidal, which facilitates the formation of the raised portion 2 and also facilitates the first warping edge 113 or the second warping edge 40120 to be in a warped state after contacting the side of the raised portion 2. The film layer located above the raised portion 2 will be raised at the raised portion 2 without being flattened.

[0130] For example, the display panel may further include a barrier layer 31 and a buffer layer 32 disposed on the base substrate 3. The barrier layer 31 may prevent impurities such as water and oxygen from penetrating from the base substrate 3 into functional structures such as the thin-film transistor 4. The buffer layer 32 may provide a flat surface to facilitate the placement of other functional layers of the display panel. The barrier layer 31 and the buffer layer 32 may jointly protect the other functional structures on the base substrate 3.

[0131] The embodiment of the present disclosure also provides a display panel, including a substrate, including a display area and a non-display area at least partially surrounding the display area, the non-display area including a bonding area located on one side of the display area; a plurality of sub-pixels located on one side of the substrate and located in the display area, at least one of the plurality of sub-pixels including a pixel driving circuit and a light-emitting element, the pixel driving circuit being configured to drive the light-emitting element to emit light; a power line electrically connected to the plurality of sub-pixels, the power line being configured to transmit a power signal to the plurality of sub-pixels; a power input terminal located in the bonding area and electrically connected to the power line, being configured to transmit the power signal to the power line, the power input terminal being connected to the bonding area. Extending in a direction away from the display area; at least one isolation groove, at least partially located in the bonding area, at least part of the structure in the power input terminal is located in the at least one isolation groove; at least one partition island, in a direction perpendicular to the substrate, the at least one partition island is located on a side of the power input terminal close to the substrate, the orthographic projection of the at least one partition island on the substrate partially overlaps with the orthographic projection of the at least one isolation groove on the substrate, the orthographic projection of the side of the power input terminal on the substrate partially overlaps with the orthographic projection of the at least one partition island on the substrate, and the edge of the power input terminal is disconnected at the overlap with the at least one partition island.

[0132] The display panel provided by the embodiment of the present disclosure is configured such that at least one partition island is arranged on a side of the power input terminal close to the base substrate, the orthographic projection of the at least one partition island on the base substrate partially overlaps with the orthographic projection of the at least one isolation groove on the base substrate, the orthographic projection of the side of the power input terminal on the base substrate partially overlaps with the orthographic projection of the partition island on the base substrate, and the edge of the power input terminal is disconnected at the intersection with the at least one partition island, so that the organic residue on the side of the first power input terminal is disconnected, thereby isolating the water and oxygen channel.

[0133] Figure 11A is a schematic diagram of a partial structure of a display panel provided in at least one embodiment of the present disclosure. Figure 11B is an enlarged schematic diagram of the dashed area C1 in Figure 11A. Figure 11C is an enlarged schematic diagram of the dashed area C2 in Figure 11A. As shown in Figure 11A, the bonding area BA may include at least one of a first isolation trench 151, a second isolation trench 152, and a third isolation trench 153. The dashed area C1 illustrates the arrangement of a partitioning island 161 at the right edge of the first power input terminal 111 in the first isolation trench 151. The dashed area C2 illustrates the arrangement of a partitioning island 161 at the left edge of the first power input terminal 111 in the first isolation trench 151. In other embodiments, the partitioning island 161 may be arranged only at the right edge of the first power input terminal 111, or only at the left edge of the first power input terminal 111, and this disclosure is not limited thereto. At different isolation slots, the number of isolation islands 161 and their positional relationship with the first power input terminal 111 can be the same, or the number and position distribution of the isolation islands 161 at different isolation slots can be set as needed, and the present disclosure does not limit this.

[0134] As shown in FIG11B , the display panel includes at least one partition island 161. In a direction perpendicular to the base substrate 3, the partition island 161 is located on a side of the first power input terminal 111 that is close to the base substrate 3. The orthographic projection of the partition island 161 on the base substrate 3 and the orthographic projection of the isolation trench on the base substrate 3 at least partially overlap. For example, the orthographic projection of the partition island 161 on the base substrate 3 is located within the orthographic projection of the isolation trench on the base substrate 3. The orthographic projection of the side edge of the first power input terminal 111 on the base substrate 3 and the orthographic projection of the partition island 161 on the base substrate 3 at least partially overlap. By providing a partition island 161 on the side of the first power input terminal 111 near the base substrate 3, the height of the side edge of the first power input terminal 111 near the isolation trench can be increased, so that part of the side edge of the first power input terminal 111 is isolated by the height difference formed by the partition island 161. In turn, the height difference formed by the partition island 161 isolates organic residue on the side edge of the first power input terminal 111. The organic residue located near the edge of the display area AA of the partition island 161 is disconnected from the organic residue located away from the edge of the display area AA of the partition island 161, thereby isolating the water and oxygen channels. The structure of FIG11C is similar to that of FIG11B, and reference can be made to the description of FIG11B, which will not be repeated here.

[0135] In an exemplary embodiment, as shown in FIG. 11A , two isolation islands 161 may be provided at the isolation trench, and each isolation island 161 overlaps with one side of the first power input terminal 111 , which is not limited in the present disclosure.

[0136] In an exemplary embodiment, the structure of the display panel in the display area AA may be as shown in FIG7C , wherein the isolation island 161 may be provided on the first source-drain electrode layer 451, and the first power input terminal 111 may be provided on the second source-drain electrode layer 452. As shown in FIG11B , the orthographic projection of the isolation island 161 on the base substrate 3 may be located within the range of the isolation trench. The display panel may further include a covering portion 171, the orthographic projection of the covering portion 171 on the base substrate 3 covering the edge of one side of the partition island 161 close to the display area AA. The covering portion 171 may be provided on the same layer as the first flat layer 611. By providing the covering portion 171, the height change experienced by the first power input terminal 111 in the process of extending from the edge of one side of the partition island 161 close to the display area AA to above the partition island 161 is smoother, and the first power input terminal 111 will not be broken due to the large step difference, which helps to ensure the continuity of the first power input terminal 111. In addition, since the edge of the first power input terminal 111 is raised by the partition island 161, in the subsequent process of forming the pixel defining layer 62, organic residue is not likely to appear in the first power input terminal 111, or when organic residue exists in the first power input terminal 111, the water-oxygen channel formed by the organic residue is disconnected at the partition island 161. In other embodiments, the partition island 161 may overlap with the edge of the isolation groove close to the display area AA, or the partition island 161 may overlap with the edge of the isolation groove away from the display area AA, or the partition island 161 may pass through the isolation groove in a direction away from the display area AA. The present disclosure does not limit this.

[0137] Figure 11D is a first cross-sectional schematic diagram of the display panel along line EE in Figures 11B and 11C, illustrating that the right edge of the first power input terminal 111 is isolated by the partition island 161, with the disconnection located in the dashed area Dk. Figure 11E is a cross-sectional schematic diagram of the display panel along line HH in Figures 11B and 11C, illustrating the center of the first power input terminal 111. As shown in Figure 11D, the orthographic projection of the partition island 161 on the base substrate 3 is located within the first isolation trench 151. The edge of the partition island 161 near the display area AA is covered by the covering portion 171. The covering portion 171 can be provided on the same layer as the first planar layer 611 of the display panel. The second planar layer 612 and pixel defining layer 62 within the first isolation trench 151 are removed. The first power input terminal 111 is continuous on the side of the partition island 161 close to the display area AA, and is disconnected at the edge of the partition island 161 away from the display area AA. By setting the first power input terminal 111 to be disconnected at the edge of the partition island 161 away from the display area AA, the organic residue on the side of the first power input terminal 111 can be disconnected, thereby isolating the water and oxygen channel. For example, during the preparation process, the first power input terminal 111 can be disconnected at the edge of the partition island 161 away from the display area AA by forming a step difference on the partition island 161, or the first power input terminal 111 can be disconnected at the edge of the partition island 161 away from the display area AA by controlling the parameters of related processes such as the deposition process (DE). The present disclosure does not limit this. In other embodiments, the first power input terminal 111 can be disconnected at the edge of the side of the partition island 161 close to the display area AA. In this case, the covering portion 171 can be covered on the edge of the side of the partition island 161 away from the display area AA. The present disclosure does not limit this. As shown in Figure 11E, since the first power input terminal 111 does not overlap with the partition island 161 in the middle part, the first power input terminal 111 can remain continuous in the middle part, thereby ensuring the normal transmission of electrical signals while blocking the water and oxygen channels. The cross-section of the display panel along line EE in Figure 11C is the same as the cross-section of the display panel along line EE in Figure 11B. The structure in which the left edge of the first power input terminal 111 is blocked by the partition island 161 can refer to the description of Figure 11D and will not be repeated here.

[0138] As shown in Figures 11B and 11D, taking the three-layer structure in which the materials of the first source-drain electrode layer 451 and the second source-drain electrode layer 452 are both Ti-Al-Ti as an example, the organic residue on the side of the first power input terminal 111 is located in the Al layer of the Ti-Al-Ti three-layer structure of the first power input terminal 111, and the organic residue on the side of the partition island 161 is located in the Al layer of the Ti-Al-Ti three-layer structure of the partition island 161. Under the isolation of the Ti layer of the first power input terminal 111 and the Ti layer of the partition island 161, the organic residue on the side of the first power input terminal 111 will not be connected with the organic residue on the side of the partition island 161, and the organic residue on the side of the first power input terminal 111 will not be connected with the covering portion 171. After the first power input terminal 111 is raised by the isolation island 161, basically no organic residue will appear in the process of forming the pixel defining layer 62, or when there is organic residue in the first power input terminal 111, combined with the three-layer structure material design, the water-oxygen channel formed by the organic residue is disconnected at the isolation island 161.

[0139] 11F is a second cross-sectional schematic diagram of the display panel along line EE in FIG11B . The difference between FIG11F and FIG11D is that the partition island 161 includes different film layers. The rest of the content can refer to the aforementioned description of FIG11D and will not be repeated here.

[0140] As shown in FIG11F , in a direction perpendicular to the base substrate 3 , the partition island 161 may include at least one of a first partition portion 1611, a second partition portion 1612, and a third partition portion 1613. The first partition portion 1611 may be provided on the same layer as the gate 42 and the first electrode plate 51, the second partition portion 1612 may be provided on the same layer as the second electrode plate 52, and the third partition portion 1613 may be provided on the same layer as the first source-drain electrode layer 451. The first power input terminal 111 may be provided on the same layer as the second source-drain electrode layer 452. A gate insulating layer 432 may be provided between the first partition portion 1611 and the second partition portion 1612, and an interlayer insulating layer 44 may be provided between the second partition portion 1612 and the third partition portion 1613. In this embodiment, the partition island 161 is higher, and the edge of the first power input terminal 111 is raised to a higher height, making it less likely that organic residue will form during the formation of the pixel defining layer 62. On the side of the partition island 161 away from the display area AA, the edge of the first power input terminal 111 is more easily disconnected due to the step difference, disconnecting the organic residue at the edge of the first power input terminal 111 and, in turn, disconnecting the water-oxygen channel. The cross-section of the display panel along line EE in Figure 11C is the same as the cross-section of the display panel along line EE in Figure 11B. The structure of the partition island 161 provided on the left edge of the first power input terminal 111 can be referred to the description of Figure 11F and will not be repeated here.

[0141] Figure 12A is a third cross-sectional schematic diagram of the display panel along line CC in Figure 2. Figure 12B is a third cross-sectional schematic diagram of the display panel in Figures 11B and 11C along line EE in the structure shown in Figure 12A.

[0142] As shown in FIG12A , the source / drain electrode layer 45 further includes a third source / drain electrode layer 453, and the planarizing layer 61 further includes a third planarizing layer 613. The third source / drain electrode layer 453 is located on a side of the second source / drain electrode layer 452 away from the substrate 3, and the third planarizing layer 613 is located on a side of the third source / drain electrode layer 453 away from the substrate 3. The anode layer 64 is connected to the third source / drain electrode layer 453 via vias in the third planarizing layer 613, and the third source / drain electrode layer 453 is connected to the second source / drain electrode layer 452 via vias in the second planarizing layer 612, thereby connecting the anode layer 64 to the drain electrode D of the corresponding transistor. In these examples, the first blocking dam 201 is disposed in the same layer as at least one of the first planarizing layer 611, the second planarizing layer 612, the third planarizing layer 613, and the pixel defining layer 62, and the second blocking dam 202 is disposed in the same layer as at least one of the second planarizing layer 612, the third planarizing layer 613, and the pixel defining layer 62. The cross section of the display panel along line EE in Figure 11C is the same as the cross section of the display panel along line EE in Figure 11B. The structure of the partition island 161 set at the left edge of the first power input terminal 111 can refer to the description of Figure 12B and will not be repeated here.

[0143] As shown in FIG12B , the partition island 161 may further include a fourth partition portion 1614. The fourth partition portion 1614 may be provided in the same layer as the second source / drain electrode layer 452, and the first power input terminal 111 may be provided in the same layer as the third source / drain electrode layer 453. FIG12B illustrates an example in which the partition island 161 includes the third partition portion 1613 and the fourth partition portion 1614. In other embodiments, the partition island 161 may include at least one of the first partition portion 1611, the second partition portion 1612, the third partition portion 1613, and the fourth partition portion 1614, and this disclosure is not limited thereto. In this embodiment, the height of the partition island 161 is higher, and the edge of the first power input terminal 111 is raised to a higher height, so that organic residue is less likely to appear in the process of forming the pixel defining layer 62. In addition, on the side of the partition island 161 away from the display area AA, the edge of the first power input terminal 111 is more easily disconnected under the influence of the step difference, so that the organic residue at the edge of the first power input terminal 111 is disconnected, and then the water-oxygen channel is disconnected.

[0144] Figure 13 is an enlarged schematic diagram of the dashed area C1 in Figure 11A in another embodiment. As shown in Figure 13 , at least one first mask area F1 is provided within the bonding area BA. The orthographic projection of the first mask area F1 on the base substrate 3 at least partially overlaps with the orthographic projection of the isolation trench on the base substrate 3. The orthographic projection of the side edge of the first power input terminal 111 on the base substrate 3 at least partially overlaps with the orthographic projection of the first mask area F1 on the base substrate 3. In this exemplary embodiment, the position of the first mask area F1 can be referred to in the aforementioned description of the position of the partition portion 161. After forming the first power input terminal 111, in the subsequent process of forming the planar layer, after coating the planar layer film, the light intensity of the first mask area F1 can be controlled to form a temporary shielding layer (not shown) on the planar layer within the first mask area F1. This temporary shielding layer covers the side of the first power input terminal 111. In the subsequent development process, this temporary shielding layer is removed, but it can make the side of the first power input terminal 111 less corroded during the development process of forming the planar layer, and the resulting side erosion area is shallower, making the organic glue in the side erosion area easier to remove. In the subsequent process of forming the pixel definition layer, since the side erosion area of ​​the first power input terminal 111 is shallower, less pixel definition layer material accumulates in the side erosion area and can be removed, thereby reducing organic residue in the side erosion area and cutting off the water and oxygen channel at the first mask area F1. For example, during exposure of the planar layer film, a halftone mask may be used in the first mask area F1 and a normal mask may be used in other areas to control the light intensity of the first mask area F1 , which is not limited in the present disclosure.

[0145] In an exemplary embodiment, the temporary shielding layer can be retained during the development of the planar layer, and in the subsequent development of the pixel definition layer, the temporary shielding layer can be removed together with the pixel definition layer, so that the side of the first power input terminal 111 can be less corroded during the development process of forming the planar layer and the pixel definition layer, the side erosion area formed is shallower, the organic glue in the side erosion area is easier to remove, and it is less likely to form a water-oxygen channel.

[0146] In an exemplary embodiment, as shown in FIG13 , when the first mask area F1 is provided within the bonding area BA, the display panel may not be provided with the partition island 161 and the cover portion 171. By controlling the illumination intensity of the first mask area F1, the water and oxygen passages on the sides of the first power input terminal 111 can be blocked. In other embodiments, the first mask area F1 may be provided within the bonding area BA, and the partition island 161 and the cover portion 171 may be provided on the display panel. These arrangements can be made as needed and are not limited by this disclosure.

[0147] In an exemplary embodiment, as shown in FIG13 , in the extension direction from the display area AA to the binding area BA, the minimum size L1 of the first mask area F1 may be greater than or equal to 0.8 microns. For example, the minimum size L1 of the first mask area F1 may be greater than or equal to 1 micron. The residual effect of the organic residue at the side of the first power input terminal 111 can be adjusted by controlling the minimum size L1 of the first mask area F1. Within a certain range, the larger the minimum size L1 of the first mask area F1, the less organic residue there is on the side of the first power input terminal 111. The range of the minimum size L1 of the first mask area F1 can be set as needed. For example, the minimum size L1 of the first mask area F1 may be greater than or equal to 0.8 microns and less than or equal to 2.2 microns. The present disclosure does not impose any restrictions on this.

[0148] Figures 11A through 12B illustrate the example of a partition island 161 positioned at the first power input terminal 111. The partition island 161 and the covering portion 171 may also be positioned at a corresponding location on the second power input terminal 112. The first mask region F1 in Figure 13 may also be positioned at a corresponding location on the second power input terminal 112, and this disclosure is not limited thereto. In forming the display panel structure shown in Figures 11A through 13, no additional process steps are required; only minor adjustments to the corresponding mask plates are required to complete the fabrication process, resulting in lower costs and easier application.

[0149] At least one embodiment of the present disclosure also provides a method for preparing a display panel, comprising: providing a base substrate, comprising a display area and a non-display area at least partially surrounding the display area, the non-display area comprising a bonding area located on one side of the display area; the bonding area comprising at least one isolation groove area, the isolation groove area comprising at least one first mask area; forming a power input terminal on the base substrate in the bonding area, the power input terminal extending in a direction away from the display area and passing through the at least one isolation groove area; the orthographic projection of the side of the power input terminal on the base substrate and the orthographic projection of the first mask area on the base substrate partially overlap; coating a flat layer film on the base substrate, processing the flat layer film using an exposure process, removing the flat layer film located in the isolation groove area, and retaining the flat layer film located in the first mask area; processing the flat layer film located in the first mask area using a development process, removing the flat layer film located in the first mask area. In an exemplary embodiment, the processing of the planarizing layer film using an exposure process includes: exposing the planarizing layer film located in the first mask area using a halftone mask; after retaining the planarizing layer film located in the first mask area, the method further includes: coating a pixel definition layer film on the substrate, processing the pixel definition layer film using an exposure process and a development process, and removing the pixel definition layer film located in the isolation groove area; processing the planarizing layer film located in the first mask area using a development process also includes: removing the planarizing layer film located in the first mask area during the processing of the pixel definition layer film using the development process.

[0150] In forming the display panel shown in Figures 2, 6A, 6B and 8C, the preparation method includes: providing a base substrate, forming a display area AA and a non-display area NA on the base substrate; wherein, forming the non-display area NA includes forming a power input terminal and a lifting portion, and the power input terminal is formed behind the lifting portion; a portion of the edge of the power input terminal is a first warped edge, and the first warped edge is formed on at least one side wall of the lifting portion.

[0151] Next, the method for manufacturing the display panel provided by the embodiment of the present disclosure is introduced by taking the display panel shown in FIG. 2 , FIG. 6A , FIG. 6B and FIG. 8C as an example.

[0152] 14A to 14D are schematic cross-sectional views of a display panel during its preparation process according to at least one embodiment of the present disclosure.

[0153] First, a base substrate 3 is provided. For example, when the display panel is a flexible display panel, the provided base substrate 3 can be a flexible substrate such as polyimide (PI). When the display panel is a rigid substrate, the base substrate 3 can be a rigid substrate such as glass or quartz.

[0154] For example, the barrier layer 31 and the buffer layer 32 can be sequentially formed on the base substrate 3 by deposition or other methods. For example, the barrier layer 31 and the buffer layer 32 can be formed entirely on the base substrate 3. For example, the barrier layer 31 can be made of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and the buffer layer 32 can also be made of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0155] For example, after the barrier layer 31 and the buffer layer 32 are formed, as shown in Figures 14A and 14B, structures such as a thin film transistor 4 and a storage capacitor 5 are formed in the display area AA, and a power input terminal 11 and a lifting portion 2 are formed in the binding area BA, wherein the power input terminal 11 is formed after the lifting portion 2, and a portion of the edge of the power input terminal 11 contacts the side wall of the lifting portion 2 to form a first warped edge 113.

[0156] For example, as shown in FIG14A , an active layer 41 is formed on a substrate 3 using a patterning process; a first gate insulating layer 431 is formed on the active layer 41 by deposition or other methods; a gate 42, a first electrode 51, and a first metal sub-layer 211 are simultaneously formed on the first gate insulating layer 431 using a patterning process; a second gate insulating layer 432 and a first insulating sub-layer 221 are simultaneously formed on the gate 42, the first electrode 51, and the first metal sub-layer 211 by deposition or other methods; a second electrode 52 and a second metal sub-layer 212 are simultaneously formed using a patterning process; an interlayer insulating layer 44 and a second insulating sub-layer 222 are simultaneously formed on the second electrode 52 and the second metal sub-layer 212 by deposition or other methods; and then, the gate insulating layer 43 and the interlayer insulating layer 44 are etched to form a via hole exposing the active layer 41. For example, a single patterning process includes processes such as forming a photoresist, exposing, developing, and etching.

[0157] In this case, the first metal sublayer 211 is formed in the same layer as the first electrode 51, the first insulating sublayer 221 is formed in the same layer as the second gate insulating layer 432, the second metal sublayer 212 is formed in the same layer as the second electrode 52, and the second insulating sublayer 222 is formed in the same layer as the interlayer insulating layer 44. This simplifies the manufacturing process of the display panel.

[0158] For example, the gate 42, first electrode 51, and first metal sublayer 211 may be made of a metal or alloy such as aluminum, titanium, or cobalt. During fabrication, a layer of gate 42 material is first formed by sputtering or evaporation, and then the gate 42 material layer is patterned to form a patterned gate 42, first electrode 51, and first metal sublayer 211. The formation of other structures formed in the same layer is similar and will not be further described.

[0159] For example, the active layer 41 can be made of materials such as polysilicon and metal oxide, the first insulating sublayer 221 and the gate insulating layer 43 can be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride, the second electrode 52 and the second metal sublayer 212 can be made of metals or alloys such as aluminum, titanium, and cobalt, and the interlayer insulating layer 44 and the second insulating sublayer 222 can be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The embodiments of the present disclosure do not limit the materials of the functional layers, and the materials of the functional layers are not limited to the above examples.

[0160] 14C and 14D , after the via holes are formed in the interlayer insulating layer 44 , the source-drain electrode layer 45 , the power line and the power input terminal 11 are formed, thereby simplifying the manufacturing process of the display panel.

[0161] For example, the source / drain electrode layer 45 may be formed as a multi-layer metal structure, such as a three-layer metal structure. For example, in one example, a titanium material layer, an aluminum material layer, and a titanium material layer may be sequentially formed by sputtering or evaporation, and then the three material layers may be patterned using the same patterning process to form a titanium / aluminum / titanium three-layer metal structure constituting the source electrode S and the drain electrode D.

[0162] As shown in FIG. 14C and FIG. 6B , after the film layers of the thin film transistor 4 and the storage capacitor 5 are formed, a planarization layer 61 , an anode layer 64 , a pixel definition layer 62 and a spacer 63 are formed in sequence.

[0163] For example, a planar layer 61 is formed by a patterning process. For example, the material of the planar layer 61 can be an organic insulating material such as polyimide or epoxy resin. The planar layer 61 has a via hole so that the anode layer 64 formed later is electrically connected to the drain electrode D through the via hole.

[0164] For example, an anode layer 64 is formed on the planar layer 61 in the display area AA using a patterning process. The anode layer 64 is electrically connected to the drain electrode D through a via hole in the planar layer 61. For example, the material of the anode layer 64 includes metal oxides such as ITO and IZO, or metals such as Ag, Al, Mo, or alloys thereof.

[0165] For example, a pixel defining layer 62 is formed by a patterning process. The pixel defining layer 62 has an opening that exposes the anode layer 64, so that structures such as the light-emitting layer 65 and the cathode layer 66 of the light-emitting element EL can be formed later. For example, the material of the pixel defining layer 62 can include an organic insulating material such as polyimide or epoxy resin.

[0166] For example, the spacers 63 are formed by a patterning process. The spacers 63 are made of organic insulating materials such as polyimide and epoxy resin.

[0167] For example, a light-emitting layer 65 can be formed in the opening of the pixel defining layer 62 by inkjet printing or evaporation, and then a cathode layer 66 can be formed. For example, an auxiliary light-emitting layer (not shown) can be formed between the light-emitting layer 65 and the anode layer 64 or between the light-emitting layer 65 and the cathode layer 66. The auxiliary light-emitting layer can include, for example, one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer. For example, the cathode layer 66 and the auxiliary light-emitting layer can be formed on the entire surface of the display panel.

[0168] For example, the material of the light-emitting layer 65 and the material of the auxiliary light-emitting layer are organic materials. The material of the light-emitting layer 65 can be selected as a light-emitting material that can emit a certain color of light (such as red, blue, or green light) according to the needs. The material of the cathode layer 66 can include metals such as Mg, Ca, Li, or Al, or alloys thereof, or metal oxides such as IZO and ZTO, or conductive organic materials such as PEDOT / PSS (polyethylenedioxythiophene / polystyrene sulfonate).

[0169] For example, after the light emitting element EL is formed, the encapsulation layer 7 may be formed on the display area AA.

[0170] The display panel formed by the manufacturing method provided in the embodiments of the present disclosure includes a power input terminal 11 and a raised portion 2. The power input terminal 11 is formed in the same layer as the source / drain electrode layer 45 of the display area AA, and the raised portion 2 is formed behind the power input terminal 11. Within the isolation trench, the raised portion 2 can elevate a portion of the power input terminal 11, forming a first warped edge 113 on both sides of the power input terminal 11. The first warped edge 113 can reduce the possibility of organic residue forming a continuous water-oxygen channel in the undercut region 110 of the power input terminal 11, thereby improving the packaging reliability of the display panel.

[0171] In the above process of forming the display panel shown in Figures 2, 6A, 6B and 8C, the partition island 161 and the covering part 171 in Figures 11A to 12B can be prepared simultaneously with the film layers set in the same layer according to the actual settings, which will not be repeated here.

[0172] The display panel provided by the embodiments of the present disclosure or the display panel obtained using the preparation method provided by the embodiments of the present disclosure can be used in a display device, which can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc. The embodiments of the present disclosure are not limited to this.

[0173] In the embodiments of the present disclosure:

[0174] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0175] (2) In the drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions are exaggerated or reduced, i.e., these drawings are not drawn to scale. When an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly on" or "under" the other element or intervening elements may be present.

[0176] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0177] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel, comprising: A substrate substrate, including a display area and at least a non-display area partially surrounding the display area, the non-display area including a bonding area located on one side of the display area; A plurality of sub-pixels, located on one side of the substrate substrate and within the display area, at least one of the plurality of sub-pixels including a pixel driving circuit and a light-emitting element, the pixel driving circuit being configured to drive the light-emitting element to emit light; A power supply line, electrically connected to the plurality of sub-pixels, the power supply line being configured to transmit a power signal to the plurality of sub-pixels; A power input terminal, located in the bonding area and electrically connected to the power supply line, configured to transmit the power signal to the power supply line, the power input terminal extending in a direction away from the display area; At least one isolation groove, at least partially located in the bonding area, at least a part of the structure of the power input terminal being located in the at least one isolation groove; At least one partition island, in a direction perpendicular to the substrate substrate, the at least one partition island being located on a side of the power input terminal close to the substrate substrate, a positive projection of the at least one partition island on the substrate substrate and a positive projection of the at least one isolation groove on the substrate substrate partially overlap, a positive projection of a side edge of the power input terminal on the substrate substrate and a positive projection of the at least one partition island on the substrate substrate partially overlap, and an edge of the power input terminal is disconnected at the overlapping portion with the at least one partition island.

2. The display panel according to claim 1, further comprising at least one covering portion, the at least one covering portion being located between the at least one partition island and the power input terminal; the at least one covering portion covers at least a part of an edge of the at least one partition island on a side close to the display area, or, the at least one covering portion covers at least a part of an edge of the at least one partition island on a side away from the display area.

3. The display panel according to claim 2, wherein: In the case where the at least one covering portion covers at least a part of an edge of the at least one partition island on a side close to the display area, an edge of the power input terminal is disconnected on a side of the at least one partition island away from the display area; or, in the case where the at least one covering portion covers at least a part of an edge of the at least one partition island on a side away from the display area, an edge of the power input terminal is disconnected on a side of the at least one partition island close to the display area.

4. The display panel according to claim 3, wherein: The pixel driving circuit includes a thin film transistor and a storage capacitor; The thin film transistor includes an active layer located on the substrate substrate, a gate, a gate insulating layer, and an interlayer insulating layer located on a side of the active layer away from the substrate substrate where it is located, and a source electrode and a drain electrode located on a side of the interlayer insulating layer away from the substrate substrate; The storage capacitor includes a first electrode plate and a second electrode plate, the first electrode plate is arranged on the same layer as the gate, and the second electrode plate is located between the gate insulating layer and the interlayer insulating layer.

5. The display panel according to claim 4, wherein, In a direction perpendicular to the base substrate, the at least one isolation island includes at least one of a first isolation portion, a second isolation portion and a third isolation portion, the first isolation portion and the gate are arranged on the same layer, the second isolation portion and the second plate are arranged on the same layer, and the third isolation portion and the source electrode are arranged on the same layer.

6. The display panel according to claim 5, wherein, The pixel driving circuit includes a second source-drain electrode layer, and the second source-drain electrode layer is located on a side of the source electrode and the drain electrode away from the substrate; In a direction perpendicular to the base substrate, the at least one partition island further includes a fourth partition portion, and the fourth partition portion is provided in the same layer as the second source-drain electrode layer.

7. The display panel according to any one of claims 1 to 6, further comprising at least one circle of blocking dams, wherein the orthographic projection of the power input terminal on the base substrate partially overlaps with the orthographic projection of the at least one circle of blocking dams on the base substrate; and the at least one isolation groove is located on at least one side of the at least one circle of blocking dams.

8. The display panel according to claim 7, wherein: The bonding area further includes a bending area, the bending area being located on a side of the at least one barrier dam away from the display area; the at least one barrier dam includes a first barrier dam and a second barrier dam, the second barrier dam being located on a side of the first barrier dam away from the display area; The at least one isolation groove is located at at least one of the following positions: Located on a side of the first barrier dam close to the display area; located between the first barrier dam and the second barrier dam; Located between the second blocking dam and the bending area.

9. The display panel according to claim 8, wherein, The at least one isolation trench includes at least one of a first isolation trench, a second isolation trench and a third isolation trench; the first isolation trench is located on a side of the second blocking dam away from the display area, the second isolation trench is located between the first blocking dam and the second blocking dam, and the third isolation trench is located on a side of the first blocking dam close to the display area.

10. The display panel according to claim 9, wherein, The at least one isolation trench includes the first isolation trench, the second isolation trench and the third isolation trench; the first isolation trench is located on the side of the second blocking dam away from the display area, the second isolation trench is located between the first blocking dam and the second blocking dam, and the third isolation trench is located on the side of the first blocking dam close to the display area.

11. The display panel according to claim 10, wherein, The at least one partition island includes three partition islands, and the three partition islands are respectively located in the first isolation trench, the second isolation trench, and the third isolation trench.

12. The display panel according to claim 10, wherein, Two isolation islands are provided in each isolation groove, and the two isolation islands overlap with both side edges of the power input terminal respectively, so that both side edges of the power input terminal are disconnected at a side away from the display area.

13. The display panel according to claim 1, wherein, The power line includes a first power line, the first power line is configured to transmit a positive voltage power signal, the first power line includes a plurality of first power sub-lines located in the display area and a first power bus located in the bonding area, the plurality of first power sub-lines are electrically connected to the plurality of sub-pixels, and the first power bus is connected to the plurality of first power sub-lines; The power input terminal includes a first power input terminal, and the first power input terminal is connected to the first power bus.

14. The display panel according to claim 1, wherein, The power supply line includes a second power supply line, and the second power supply line is located in the non-display area and at least partially surrounds the display area; The power input terminal includes a second power input terminal, the second power input terminal is connected to the second power supply line, and the second power supply line is configured to transmit a negative voltage power signal.

15. A method for manufacturing a display panel, comprising: Providing a substrate, including a display area and a non-display area at least partially surrounding the display area, the non-display area including a bonding area on one side of the display area; the bonding area includes at least one isolation groove area, and the isolation groove area includes at least one first mask area; Forming a power input terminal on the substrate in the bonding area, the power input terminal extending in a direction away from the display area and passing through the at least one isolation groove area; a positive projection of a side of the power input terminal on the substrate and a positive projection of the first mask area on the substrate partially overlap; Coating a planarization layer film on the substrate, and using an exposure process to process the planarization layer film, removing the planarization layer film located in the isolation groove area, and retaining the planarization layer film located in the first mask area; Using a development process to process the planarization layer film located in the first mask area, removing the planarization layer film located in the first mask area.

16. According to the manufacturing method of claim 15, the using an exposure process to process the planarization layer film includes: Exposing the planarization layer film located in the first mask area using a halftone mask; After retaining the planarization layer film located in the first mask area, the method further includes: Coating a pixel definition layer film on the substrate, and using an exposure process and a development process to process the pixel definition layer film, removing the pixel definition layer film located in the isolation groove area; The using a development process to process the planarization layer film located in the first mask area further includes: During the process of using a development process to process the pixel definition layer film, removing the planarization layer film located in the first mask area.

17. A display panel, comprising: A substrate, including a display area and a non-display area at least partially surrounding the display area, the non-display area including a bonding area on one side of the display area; A plurality of sub-pixels, located on one side of the substrate and in the display area, at least one of the plurality of sub-pixels includes a pixel driving circuit and a light-emitting element, and the pixel driving circuit is configured to drive the light-emitting element to emit light; A power supply line, electrically connected to the plurality of sub-pixels, and the power supply line is configured to transmit a power signal to the plurality of sub-pixels; A power input terminal, located in the bonding area and electrically connected to the power supply line, configured to transmit the power signal to the power supply line, a partial edge of the power input terminal is a first warped edge, and an included angle A between the first warped edge and the substrate satisfies greater than 0° and less than 90°; At least one isolation trench is at least partially located in the bonding area, and the first warped edge is located in the at least one isolation trench.

18. The display panel according to claim 17, wherein, A satisfies the requirement of being greater than 10° and less than 30°.

19. The display panel according to claim 17, comprising at least one barrier dam located in the non-display area and surrounding the display area, the power input terminal extending in a direction away from the display area, the orthographic projection of the power input terminal on the base substrate partially overlapping the orthographic projection of the at least one barrier dam on the base substrate, and the at least one isolation trench being located in at least one of the following positions: The at least one circle of barrier dams is close to one side of the display area, and the at least one circle of barrier dams is far away from one side of the display area.

20. The display panel according to claim 19, wherein, The bonding area includes a bending area, the at least one circle of blocking dams is located between the bending area and the display area, the at least one isolation groove is located on the side of the at least one circle of blocking dams close to the display area, or the at least one isolation groove is located between the at least one circle of blocking dams and the bending area.

21. The display panel according to claim 20, wherein: The at least one isolation trench includes a first isolation trench and a second isolation trench. The first isolation trench is located between the at least one circle of blocking dams and the bending area. The second isolation trench is located on a side of the at least one circle of blocking dams close to the display area.

22. The display panel according to claim 21, wherein, The at least one circle of barrier dams includes a first barrier dam and a second barrier dam, wherein the second barrier dam is located on a side of the first barrier dam away from the display area; The first warped edge is located at at least one of the following positions: Located on a side of the first barrier dam close to the display area; located between the first barrier dam and the second barrier dam; Located between the second blocking dam and the bending area.

23. The display panel according to claim 22, wherein, The power line includes a first power line, the first power line is configured to transmit a positive voltage power signal, the first power line includes a plurality of first power sub-lines located in the display area and a first power bus located in the bonding area, the plurality of first power sub-lines are electrically connected to the plurality of sub-pixels, and the first power bus is connected to the plurality of first power sub-lines; The power input terminal includes a first power input terminal, and the first power input terminal is connected to the first power bus.

24. The display panel according to claim 22, wherein: The power line includes a second power line, the second power line is located in the non-display area and at least partially surrounds the display area; The power input terminal includes a second power input terminal, the second power input terminal is connected to the second power line, and the second power line is configured to transmit a negative voltage power signal.

25. The display panel according to any one of claims 17-24, wherein, The display panel further includes a lifting portion, the first warped edge contacts a sidewall of the lifting portion, and an angle between the first warped edge and the base substrate is the same as an angle between the sidewall of the lifting portion and the base substrate.

26. The display panel according to claim 25, wherein: The orthographic projection of the power input terminal on the base substrate overlaps with the orthographic projection of the lifting portion on the base substrate, and the lifting portion is provided at at least one of the following positions: Both sides of the power input terminal and the middle part of the power input terminal.

27. The display panel according to claim 17, wherein, The display area further includes a blocking area and an opening area, wherein the blocking area and the display area surround the opening area, and the blocking area is located between the display area and the opening area; The display panel also includes at least one circle of barrier walls located in the barrier area and surrounding the opening area, the barrier wall includes a metal layer, and a portion of the edge of the metal layer in the barrier wall is a second warped edge. The second warped edge is located on the side of the metal layer facing and / or away from the opening area, and the angle between the second warped edge and the base substrate is greater than 0° and less than 90°.

28. The display panel according to claim 27, wherein, The barrier wall further includes a raised portion, the second warped edge contacts the raised portion, and an angle between the second warped edge and the base substrate is the same as an angle between the sidewall of the raised portion and the base substrate.

29. The display panel according to claim 26 or 28, wherein, The pixel driving circuit includes a thin film transistor and a storage capacitor; The thin film transistor includes an active layer located on the substrate, a gate electrode, a gate insulating layer and an interlayer insulating layer located on a side of the active layer away from the substrate, and a source electrode and a drain electrode located on a side of the interlayer insulating layer away from the substrate; The storage capacitor includes a first plate and a second plate. The first plate is provided in the same layer as the gate electrode, and the second plate is located between the gate insulating layer and the interlayer insulating layer.

30. The display panel according to claim 29, wherein, The raised portion includes an insulating layer structure, and the insulating layer structure is provided in the same layer as at least one of the gate insulating layer and the interlayer insulating layer.

31. The display panel according to claim 29, wherein: The lifting portion includes a metal layer structure, and the metal layer structure is provided in the same layer as at least one of the first electrode plate and the second electrode plate.

32. The display panel according to claim 29, wherein, The lifting portion includes an insulating layer structure and a metal layer structure. The insulating layer structure is arranged in the same layer as at least one of the gate insulating layer and the interlayer insulating layer. The metal layer structure is arranged in the same layer as at least one of the first electrode plate and the second electrode plate.

33. A display device comprising the display panel according to any one of claims 1 to 14; or comprising a display panel prepared by the method according to any one of claims 15 to 16; or comprising the display panel according to any one of claims 17 to 32.

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