Frame rate adjustment method and related device

Abstract

A frame rate adjustment method and a related device, capable of realizing frame rate matching of an FPGA. The method may comprise: receiving video data; acquiring forwarded clock information corresponding to the video data; on the basis of the forwarded clock information and local clock information, determining a target mode from among a plurality of frame rate adjustment modes; on the basis of the target mode, writing the video data and reading the video data; and outputting the read video data to a display panel.

Description

A frame rate adjustment method and related equipment

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on January 25, 2024, with application number 202410106227.8 and invention name "A frame rate adjustment method and related equipment", the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of electronic technology and discloses a frame rate adjustment method and related equipment. Background Art

[0004] In a typical audio and video processing system, a system on chip (SOC) typically achieves frame rate matching by dynamically switching a V-by-One (VBO) reference clock.

[0005] However, the dedicated high-speed serial transceiver interface of the Field Programmable Gate Array (FPGA) system cannot dynamically switch the reference clock. Therefore, the FPGA uses the method of switching the VBO reference clock to achieve frame rate matching. Summary of the Invention

[0006] The embodiments of the present application provide a frame rate adjustment method and related devices that can implement frame rate matching on an FPGA.

[0007] In a first aspect, an embodiment of the present application provides a frame rate adjustment method, which may include:

[0008] receiving video data;

[0009] Obtaining the associated clock information corresponding to the video data;

[0010] Determining a target mode from a plurality of frame rate adjustment modes based on the associated clock information and the local clock information;

[0011] writing the video data and reading the video data according to the target mode;

[0012] The read video data is output to the display panel.

[0013] In one possible implementation, in a frame rate adjustment method provided in an embodiment of the present application, any one of the multiple frame rate adjustment modes is configured with a condition corresponding to any one of the modes, wherein the accompanying clock information and the local clock information meet the condition corresponding to the target mode.

[0014] In one possible implementation, in a frame rate adjustment method provided in an embodiment of the present application, the multiple frame rate adjustment modes include at least two of the following modes:

[0015] Line synchronization mode, frame synchronization mode, frame chase mode.

[0016] In a possible implementation, in a frame rate adjustment method provided in an embodiment of the present application, the video data includes at least one frame data, and the frame data includes at least one line data;

[0017] The first mode condition corresponding to the line synchronization mode is determined based on the total horizontal length and horizontal resolution of the line data; or,

[0018] The second mode condition corresponding to the frame synchronization mode is determined based on the horizontal total length and horizontal resolution of the line data, and the vertical total length and vertical resolution of the frame data; or,

[0019] The third mode condition corresponding to the frame chase mode is determined based on the horizontal total length and horizontal resolution of the line data, and the vertical total length and vertical resolution of the frame data.

[0020] In a possible implementation, in an embodiment of the present application, a frame rate adjustment method is provided, wherein writing the video data and reading the video data according to the target mode includes:

[0021] If the target mode is a line synchronization mode, the video data is written into a line buffer according to the accompanying signal and the accompanying timing corresponding to the video data, and at the start moment of writing any line of data into the line buffer, the previous line of data of any line of data is read out from the line buffer based on the local clock signal.

[0022] In a possible implementation, in an embodiment of the present application, a frame rate adjustment method is provided, wherein writing the video data and reading the video data according to the target mode includes:

[0023] If the target mode is a frame synchronization mode, the video data is written into a memory according to a frame synchronization signal corresponding to the video data, and the video data is read out from the memory according to a first readout signal, wherein the waveform of the first readout signal is the same as the waveform of the frame synchronization signal, and the starting time of the first readout signal is the same as any falling edge time of the frame synchronization signal.

[0024] In a possible implementation, in an embodiment of the present application, a frame rate adjustment method is provided, wherein writing the video data and reading the video data according to the target mode includes:

[0025] If the target mode is the frame chase mode, frame data is written into the frame address space one by one in the writing order of the multiple frame address spaces in the memory, wherein, after writing the frame data into the first frame address space corresponding to the first writing order, the frame data is written into the second frame address space corresponding to the second writing order, and the frame data is read out from the first frame address space, and the second writing order is the next order of the first writing order.

[0026] In a second aspect, an embodiment of the present application provides a frame rate adjustment device, which may include:

[0027] Receiving interface, used for receiving video data;

[0028] Output interface, used to output video data to the display panel;

[0029] A processing module is used to: receive video data; obtain the accompanying clock information corresponding to the video data; determine a target mode from multiple frame rate adjustment modes based on the accompanying clock information and local clock information; write the video data and read the video data according to the target mode; and output the read video data to a display panel.

[0030] In one possible implementation, an embodiment of the present application provides a frame rate adjustment device, wherein any one of the multiple frame rate adjustment modes is configured with a condition corresponding to any one of the modes, wherein the accompanying clock information and the local clock information meet the condition corresponding to the target mode.

[0031] In one possible implementation, in an embodiment of the present application, an apparatus for adjusting a frame rate is provided, wherein the multiple frame rate adjustment modes include at least two of the following modes:

[0032] Line synchronization mode, frame synchronization mode, frame chase mode.

[0033] In a possible implementation, in an embodiment of the present application, an apparatus for adjusting a frame rate is provided, wherein the video data includes at least one frame of data, and the frame of data includes at least one line of data;

[0034] The first mode condition corresponding to the line synchronization mode is determined based on the total horizontal length and horizontal resolution of the line data; or,

[0035] The second mode condition corresponding to the frame synchronization mode is determined based on the horizontal total length and horizontal resolution of the line data, and the vertical total length and vertical resolution of the frame data; or,

[0036] The third mode condition corresponding to the frame chase mode is determined based on the horizontal total length and horizontal resolution of the line data, and the vertical total length and vertical resolution of the frame data.

[0037] In one possible implementation, in a frame rate adjustment device provided in an embodiment of the present application, when the processing module executes writing the video data and reading the video data according to the target mode, it is specifically configured to:

[0038] If the target mode is a line synchronization mode, the video data is written into a line buffer according to the accompanying signal and the accompanying timing corresponding to the video data, and at the start moment of writing any line of data into the line buffer, the previous line of data of any line of data is read out from the line buffer based on the local clock signal.

[0039] In one possible implementation, in a frame rate adjustment device provided in an embodiment of the present application, when the processing module executes writing the video data and reading the video data according to the target mode, it is specifically configured to:

[0040] If the target mode is a frame synchronization mode, the video data is written into a memory according to a frame synchronization signal corresponding to the video data, and the video data is read out from the memory according to a first readout signal, wherein the waveform of the first readout signal is the same as the waveform of the frame synchronization signal, and the starting time of the first readout signal is the same as any falling edge time of the frame synchronization signal.

[0041] In one possible implementation, in a frame rate adjustment device provided in an embodiment of the present application, when the processing module executes writing the video data and reading the video data according to the target mode, it is specifically configured to:

[0042] If the target mode is the frame chase mode, frame data is written into the frame address space one by one in the writing order of the multiple frame address spaces in the memory, wherein, after writing the frame data into the first frame address space corresponding to the first writing order, the frame data is written into the second frame address space corresponding to the second writing order, and the frame data is read out from the first frame address space, and the second writing order is the next order of the first writing order.

[0043] In a possible implementation, in an embodiment of the present application, an apparatus for adjusting a frame rate is provided, wherein the processing module includes a line buffer.

[0044] In a possible implementation, in an embodiment of the present application, a frame rate adjustment device is provided, wherein the processing module is connected to a memory, and the memory is used to store any frame data in the video data.

[0045] In a third aspect, an embodiment of the present application provides an electronic device, including:

[0046] a processor, a memory, and one or more programs;

[0047] Wherein, the one or more programs are stored in the memory, and the one or more programs include instructions. When the instructions are executed by the processor, the electronic device performs the steps of the frame rate adjustment method provided in the first aspect and any one of its embodiments.

[0048] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, which is used to store a computer program. When the computer program runs on a processor, the processor executes the steps of the frame rate adjustment method provided in the first aspect and any one of its embodiments.

[0049] The beneficial effects of the embodiments of the present application are as follows:

[0050] The present application provides a frame rate adjustment method and related equipment. Based on the accompanying clock information and local clock information corresponding to the video data, a target mode is determined from multiple frame rate adjustment modes. The video data is written and read according to the target mode. This process can utilize an FPGA to implement the frame rate adjustment process, which involves switching the reference clock. Furthermore, by utilizing the accompanying clock information and local clock information corresponding to the video data, the target mode is determined from multiple frame rate adjustment modes, enabling dynamic adjustment of the frame rate of the received video data to match the frame rate of the video data output to the display panel.

[0051] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. The purposes and other advantages of the present application can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0053] FIG1 is a schematic flow chart of a frame rate adjustment method provided in an embodiment of the present application;

[0054] FIG2 is a schematic diagram of video data, a line synchronization signal, and a frame synchronization signal;

[0055] FIG3 is a schematic flow chart of a frame rate adjustment method provided in an embodiment of the present application;

[0056] FIG4 is a schematic diagram of a row synchronization mode provided in an embodiment of the present application;

[0057] FIG5 is a schematic diagram of a frame synchronization mode provided in an embodiment of the present application;

[0058] FIG6 is a schematic diagram of a frame chasing mode provided in an embodiment of the present application;

[0059] FIG7 is a structural diagram of a frame rate adjustment device provided in an embodiment of the present application;

[0060] FIG8 is a logical diagram of a row synchronization mode provided in an embodiment of the present application;

[0061] FIG9 is a logical diagram of a frame synchronization mode provided in an embodiment of the present application;

[0062] FIG10 is a logic diagram of a frame chasing mode provided in an embodiment of the present application;

[0063] FIG11 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0064] In the embodiments of the present application, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, b, c, a and b, a and c, b and c, or a, b and c, where a, b, c can be single or multiple.

[0065] As used in the embodiments of the present application, the terms “when…” or “after…” may be interpreted to mean “if…” or “after…” or “in response to determining…” or “in response to detecting…”, depending on the context. Similarly, the phrases “upon determining…” or “if (stated condition or event) is detected” may be interpreted to mean “if determining…” or “in response to determining…” or “upon detecting (stated condition or event)” or “in response to detecting (stated condition or event)”, depending on the context.

[0066] In addition, in the embodiments of the present application, relational terms such as "first" and "second" are used to distinguish one entity from another entity. This is only used for the purpose of distinguishing the description and cannot be understood as indicating or implying relative importance or order.

[0067] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in yet other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0068] This application provides a frame rate adjustment method and related device for implementing frame rate matching based on an FPGA. The method and device are based on the same technical concept. Since the method and device solve similar problems, the implementation of the device and method can refer to each other, and the repeated parts will not be repeated.

[0069] FIG1 exemplifies a frame rate adjustment method that can be performed by a processor. The processor involved in the embodiments of the present application can be a central processing unit (CPU), a general-purpose processor, a graphics processing unit (GPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), an FPGA or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof.

[0070] It should be understood that the frame rate adjustment method provided in the embodiments of the present application can be used to implement frame rate matching based on an FPGA. Other circuits with data processing or computing capabilities can also implement the frame rate matching method. This embodiment of the present application does not specifically limit this.

[0071] As shown in FIG1 , the frame rate adjustment method provided in the embodiment of the present application may include the following steps:

[0072] S101, receiving video data.

[0073] In a specific implementation, the video data may come from a signal based on a digital component serial digital interface (SDI). Typically, an SDI signal may include video data, an associated clock, an associated timing, a frame synchronization signal, and the like.

[0074] S102: Obtain channel-associated clock information corresponding to the video data.

[0075] In a specific implementation, the associated clock information corresponding to the video data in the SDI signal can represent the associated clock in the SDI signal. Optionally, the associated clock information can be the frequency of the associated clock, and the local clock information can be the frequency of the local clock. Alternatively, the associated clock information can be the period of the associated clock, and the local clock information can be the period of the local clock.

[0076] For ease of introduction, the embodiments of the present application are described using an example in which the accompanying clock information is the frequency of the accompanying clock and the local clock information is the frequency of the local clock. Because the relationship between the frequency and period of a clock signal is fixed, that is, the frequency is equal to the inverse of the period, the period of the local clock and the period of the accompanying clock can be used, or the frequency of the local clock and the frequency of the accompanying clock can be used.

[0077] S103: Determine a target mode from a plurality of frame rate adjustment modes based on the associated clock information and the local clock information.

[0078] In specific implementations, the processor may be pre-configured with multiple frame rate adjustment modes, each of which has a different method for writing and reading video data. The processor may select a frame rate adjustment mode as the target mode based on the associated clock information and local clock information corresponding to the video data.

[0079] S104 , writing the video data and reading the video data according to the target mode.

[0080] During specific implementation, the processor can write the video data into the storage structure using the data writing method corresponding to the target mode, and read the video data from the storage structure using the data reading method corresponding to the target mode. By controlling the process of writing and reading the video data, the technical effect of matching the output frame rate with the input frame rate is achieved.

[0081] S105: Output the read video data to the display panel.

[0082] In one possible implementation, in step S103, the processor is preconfigured with multiple frame rate adjustment modes and conditions corresponding to each frame rate adjustment mode. The processor can determine whether the associated clock information and local clock information of the video data meet the conditions corresponding to any frame rate adjustment mode. The processor then determines the frame rate adjustment mode corresponding to the conditions met by the associated clock information and local clock information of the video data as the target mode.

[0083] In one possible design, the multiple frame rate adjustment modes may include at least two of the following modes: a line synchronization mode, a frame synchronization mode, and a frame catch-up mode.

[0084] Optionally, the multiple frame rate adjustment modes may include a line synchronization mode and a frame synchronization mode. Alternatively, the multiple frame rate adjustment modes may include a frame synchronization mode and a frame catch-up mode. Alternatively, the multiple frame rate adjustment modes may include a line synchronization mode and a frame catch-up mode. Alternatively, the multiple frame rate adjustment modes may include a line synchronization mode, a frame synchronization mode, and a frame catch-up mode.

[0085] For ease of introduction, the condition corresponding to the row synchronization mode is recorded as the first mode condition, the condition corresponding to the frame synchronization mode is recorded as the second mode condition, and the mode condition corresponding to the frame chase mode is recorded as the third mode condition.

[0086] If the associated clock information and local clock information of the video data meet the first mode condition, the processor may determine the line synchronization mode as the target mode. The processor may execute the line synchronization mode to process the video data. Optionally, if the associated clock information and local clock information of the video data meet the first mode condition, the processor may execute the line synchronization mode to process the video data. In other words, the processor may not output information or information regarding the line synchronization mode, but may directly execute operations in the line synchronization mode.

[0087] If the associated clock information and local clock information of the video data meet the second mode condition, the processor may determine the frame synchronization mode as the target mode. The processor may execute the frame synchronization mode to process the video data. Optionally, if the associated clock information and local clock information of the video data meet the second mode condition, the processor may execute the frame synchronization mode to process the video data. In other words, the processor may not output information or information regarding the frame synchronization mode, but may directly execute operations in the frame synchronization mode.

[0088] If the associated clock information and local clock information of the video data meet the third mode condition, the processor may determine the frame catch-up mode as the target mode. The processor may execute the frame catch-up mode to process the video data. Optionally, if the associated clock information and local clock information of the video data meet the third mode condition, the processor may execute the frame catch-up mode to process the video data. In other words, the processor may not output information or information regarding the frame catch-up mode, but may directly execute operations in the frame catch-up mode.

[0089] Typically, video data includes at least one frame of data, which in turn includes at least one line of data. Optionally, the processor can parse the SDI signal to obtain the horizontal total length and horizontal resolution of the line data in the video data, as well as the vertical total length and vertical resolution of the frame data. In this field, frame data is also referred to as field data.

[0090] SDI signals can include video data (video), horizontal synchronization signal (HSync) and frame synchronization signal (VSync). As shown in Figure 2, the FHD standard timing is used as an example to introduce.

[0091] The horizontal total length (HTT) of a line's data, which includes the line's valid data and blanking period, represents the total number of pixel clocks in a line. The horizontal front porch (HFP) represents the number of pixel clocks between the rising edge of the line sync signal and the falling edge of the valid data. The horizontal sync width (HSW) represents the effective width of the line sync signal. The horizontal back porch (HBP) represents the number of pixel clocks between the falling edge of the line sync signal and the rising edge of the valid data. The vertical total length (VTT) of a frame's data, which includes the frame's valid data plus the frame blanking period, represents the total HTT of a frame. The vertical front porch (VFP) represents the number of pixel clocks between the rising edge of the frame sync signal and the falling edge of the valid data. The vertical sync width (VSW) represents the effective width of the frame sync signal. The vertical back porch (VBP) can represent the number of pixel clocks between the falling edge of the frame synchronization signal and the rising edge of the valid data.

[0092] In some examples, a first mode condition corresponding to the row synchronization mode is determined based on a horizontal total length HTT and a horizontal resolution HAC of the row data. A second mode condition corresponding to the frame synchronization mode is determined based on a horizontal total length HTT and a horizontal resolution HAC of the row data, a vertical total length VTT and a vertical resolution VAC of the frame data. A third mode condition corresponding to the frame chase mode is determined based on a horizontal total length HTT and a horizontal resolution HAC of the row data, a vertical total length VTT and a vertical resolution VAC of the frame data.

[0093] Optionally, the first mode condition may be that the ratio S of the frequency of the accompanying clock of any video data to the frequency of the local clock is less than The HTT represents the total horizontal length of the line data of the video data, and the HAC represents the horizontal resolution of the line data of the video data.

[0094] In step S103, the processor may determine Is it less than Among them, f1 represents the frequency of the accompanying clock of the video data, and f2 represents the frequency of the local clock. Less than It can be determined that the accompanying clock information and the local clock information of the video data meet the first mode condition.

[0095] Optionally, the second mode condition may be that the ratio S of the frequency of the accompanying clock of any video data to the frequency of the local clock is greater than or equal to and less than Among them, HTT represents the total horizontal length of the line data of the video data, HAC represents the horizontal resolution of the line data of the video data, VTT represents the total vertical length of the frame data of the video data, and VAC represents the vertical resolution of the frame data of the video data.

[0096] In step S103, the processor may determine Is greater than or equal to and Is it less than Among them, f1 represents the frequency of the accompanying clock of the video data, and f2 represents the frequency of the local clock. It can be determined that the accompanying clock information and the local clock information of the video data meet the second mode condition.

[0097] Optionally, the third mode condition may be that the ratio S of the frequency of the accompanying clock of any video data to the frequency of the local clock is greater than or equal to Among them, HTT represents the total horizontal length of the line data of the video data, HAC represents the horizontal resolution of the line data of the video data, VTT represents the total vertical length of the frame data of the video data, and VAC represents the vertical resolution of the frame data of the video data.

[0098] In step S103, the processor may determine Is greater than or equal to Among them, f1 represents the frequency of the accompanying clock of the video data, and f2 represents the frequency of the local clock. It can be determined that the accompanying clock information and the local clock information of the video data meet the third mode condition.

[0099] Based on the introduction in the foregoing embodiments, FIG3 shows a frame rate adjustment method, which can be executed by a processor and may include the following methods:

[0100] S301, receiving video data.

[0101] S302: Obtain channel-associated clock information corresponding to the video data.

[0102] S303, based on the mode conditions corresponding to each frame rate adjustment mode in the multiple frame rate adjustment modes, determine the target mode condition satisfied by the frequency of the associated clock and the frequency of the local clock, and determine the frame rate adjustment mode corresponding to the target mode condition as the target mode.

[0103] S304: Writing the video data and reading the video data according to the target mode.

[0104] S305: Output the read video data to the display panel.

[0105] Based on the frame rate adjustment method provided in any of the above embodiments, when the processor executes the operations of writing video data and reading video data according to the target mode, the operations in any of the following examples may be adopted.

[0106] In some examples, the target mode is a horizontal synchronization mode. FIG4 shows a schematic diagram of the horizontal synchronization mode when the timing parameters of the video data are HTT=2200, VTT=1125, HAC=1920, VAC=1080, HFP=88, VFP=4, HSW=44, VSW=5, HBP=148, and VBP=36.

[0107] When the processor writes and reads video data in accordance with the line synchronization mode, the error caused by the different clocks on the input side (which is also the device that provides the SDI signal) and the output side (which is also the device that provides video data to the display panel, such as the processor) can be eliminated by shortening the line blanking period within one line time.

[0108] For example, when the processor writes and reads video data in a line synchronization mode, the processor may write the video data into the line buffer according to the accompanying signal and the accompanying timing corresponding to the video data. The processor may read the line data from the line buffer according to the local clock and the timing of valid data in the line data.

[0109] The operation of the processor writing data to the row buffer and the operation of reading data have a temporal correlation. Among them, at the start moment of writing any row of data into the row buffer, the processor reads out the previous row of data of any row of data from the row buffer based on the local clock signal. In conjunction with Figure 4, the processor can write the first row of data and the second row of data into the row buffer in sequence. At the start moment of writing the second row of data into the row buffer, the processor triggers the processor to read the previous row of data of the second row of data from the row buffer, that is, triggers the processor to read the first row of data from the row buffer. Such an operation can enable the processor to trigger the reading of the row data that was written most recently at the start moment of writing the next row of data. That is, the previous row of data of the next row of data can ensure that the read row data strictly follows the written row data, thereby achieving frame rate matching between the output side and the output side.

[0110] In some examples, the target mode is a frame synchronization mode. FIG5 shows a schematic diagram of the frame synchronization mode when the timing parameters of the video data are HTT=2200, VTT=1125, HAC=1920, VAC=1080, HFP=88, VFP=4, HSW=44, VSW=5, HBP=148, and VBP=36.

[0111] When the processor writes and reads video data in frame synchronization mode, the error caused by different clocks on the input side (also the device that provides SDI signals) and the output side (also the device that provides video data to the display panel, such as the processor) can be eliminated by shortening the frame blanking period within one line.

[0112] For example, in an operation in which the processor writes and reads video data in a frame synchronization mode, the processor may write the video data into a memory according to a frame synchronization signal corresponding to the video data, and read the video data from the memory according to a first readout signal.

[0113] The operation of the processor writing frame data to the memory and the operation of reading frame data from the memory are temporally associated. The waveform of the first readout signal is the same as the waveform of the frame synchronization signal, and the starting time of the first readout signal is the same as any falling edge time of the frame synchronization signal.

[0114] 5, the processor can write the first frame data and the second frame data into the memory in sequence according to the frame synchronization signal. Usually, the frame synchronization signal is a periodic pulse signal, and each pulse signal can represent the end of the previous frame and the beginning of the next frame in two adjacent frames.

[0115] The processor can write each frame of data into the memory according to the frame synchronization signal. The waveform of the first readout signal is the same as the waveform of the frame synchronization signal, and the starting time of the first readout signal is the same as the falling edge time of the pulse signal in any frame synchronization signal. The first readout timing corresponding to the first readout signal can be pre-configured, and the processor can read the frame data in the video data from the memory according to the first readout signal and the first readout timing.

[0116] In some examples, the aforementioned target mode is a frame synchronization mode. FIG6 is a schematic diagram of the frame chase mode. When the processor writes and reads video data in accordance with the frame chase mode, the frame data may be written sequentially to the frame address space according to the write order of the multiple frame address spaces in the memory. After writing the frame data to a first frame address space corresponding to a first write order, the frame data is written to a second frame address space corresponding to a second write order, and the frame data is read from the first frame address space. The second write order is the next order after the first write order.

[0117] Multiple frame address spaces can be recorded as address 0, address 1, address 2, and the writing order of the multiple frame address spaces can be address 0, address 1, address 2, address 0, address 1, address 2, ..., address 0, address 1, address 2. It can be seen that the writing order of the multiple address spaces can be a cycle of sorting (address 0, address 1, address 2).

[0118] For example, the first frame address space may be address 1, and the second frame address space may be address 2. When the processor writes frame data to address 2, the processor reads frame data from address 1.

[0119] The processor may update the write frame address according to the write order, wherein the updated write frame address WDMA_ADD(new)=the current write frame address WDMA_ADD(old)+1.

[0120] It can be seen that there is an association relationship between the processor write frame address and the read frame address, and the read frame address = the updated write frame address WDMA_ADD(new)-1.

[0121] The processor can update the write frame address according to the write order of the multiple frame address spaces at the rising edge of the frame synchronization signal. For example, the frame address of the next order after the current write order is updated as the write frame address, and the frame data is written to the space of the updated write frame address. The processor can also update the read address according to the rising edge of the second read signal, and the updated read address is the same as the frame address corresponding to the current write order.

[0122] To facilitate understanding of the frame rate adjustment method provided in an embodiment of the present application, FIG7 shows a structural diagram of a frame rate adjustment device. The frame rate adjustment device may include a receiving interface SDI_RX, an output interface VBOTX, and a processing module. The receiving interface may be used to receive an SDI signal. The output interface may be connected to a display panel to provide video data to the display panel.

[0123] The processing module can be used to obtain the accompanying clock information corresponding to the video data, wherein the video data includes at least one frame data; determine a target mode from multiple frame rate adjustment modes based on the accompanying clock information and local clock information; write the video data and read the video data according to the target mode; and output the read video data to the display panel.

[0124] The processing module can execute the implementation method or process of writing the video data and reading the video data according to the target mode. Please refer to the relevant introduction in the above embodiment and will not be repeated here.

[0125] In addition, Figure 7 also shows a schematic diagram of the logic units within a processing module. It should be understood that the block diagram within the processing module in Figure 7 can be used as a logic unit to understand the frame rate adjustment method provided in the embodiments of the present application, rather than being a specific limitation on the components contained within the processing module. In actual application scenarios, the processing module can be composed of one or more electronic devices to implement the frame rate adjustment method provided in the embodiments of the present application.

[0126] In some examples, the processing module may include a line buffer and the processing module may write and read video data according to a line synchronization mode.

[0127] In some examples, the processing module can be connected to a memory. The memory can be any type of memory, or any size of memory. For example, a synchronous dynamic random access memory (SDRAM). The memory shown in FIG7 can be implemented as a third-generation synchronous dynamic random access memory (double-data-rate 3 synchronous dynamic RAM, DDR3).

[0128] In one possible design, the processing module may include multiple logic units, as shown in Figure 7, and the multiple logic units may include a clock detection unit CLK_DET, a first timing output subunit VTG1, a second timing output subunit VTG2, a timing selection unit MUX_1, a write memory controller WDMA, a read memory controller RDMA, a bus arbiter AXI_INTERCONNECT, and a video data selection unit MUX_2.

[0129] The video data selection unit MUX_2 may be configured to selectively output video data from the line alignment unit LINE_SYNC and the read memory controller RDMA to the output interface VBOTX.

[0130] The timing selection unit MUX_1 may be configured to selectively output a read timing from the first timing output sub-unit VTG1 and the second timing output sub-unit VTG2 to the read memory controller RDMA.

[0131] The following describes the frame rate adjustment method provided in the embodiment of the present application executed by the processing module based on the logic unit in the processing module shown in FIG7 .

[0132] The receiving interface SDI_RX can provide the parsed SDI signal to the processing module, or provide the received SDI signal to the processing module, which then parses the SDI signal to obtain video data and the associated clock information corresponding to the video data. Optionally, the processing module can obtain the associated clock information corresponding to the video data through detection. This embodiment of the present application does not specifically limit this.

[0133] The clock detection unit CLK_DET may be used to determine the relationship between the associated clock information and the local clock information and the mode conditions corresponding to each adjustment mode.

[0134] The dotted arrows in FIG8 show the data flow when the processing module executes the line synchronization mode. If the accompanying clock information and the local clock information meet the mode conditions corresponding to the line synchronization mode, the processing module adopts the line synchronization mode to write and read the video data. Specifically, please refer to FIG8 , the line adjustment unit LINE_SYNC writes the video data into the line buffer according to the accompanying clock and the accompanying timing, and reads the data from the line buffer according to the local clock and valid data, wherein, at the start moment of writing the current line data into the line buffer, the previous line data of the current line data is triggered to be read from the line buffer, so that each line read strictly follows each line written.

[0135] The dotted arrows in Figure 9 show the data flow when the processing module executes the frame synchronization mode. If the accompanying clock information and the local clock information meet the mode conditions corresponding to the frame synchronization mode, the processing module adopts the frame synchronization mode to write and read the video data. Specifically, please refer to Figure 9. The first timing output subunit VTG1 can output a first readout signal, wherein the waveform of the first readout signal is the same as the waveform of the frame synchronization signal. When the processing module adopts the frame synchronization mode, the first timing output subunit VTG1 can be reset so that the starting time of the first readout signal output by the first timing output subunit VTG1 is the same as any falling edge time in the frame synchronization signal. That is, the first readout signal is output from the falling edge time of the frame synchronization signal. Among them, the first readout timing corresponding to the first readout signal is the default configuration, and the first readout signal maintains the self-running logic output after being reset.

[0136] The write memory controller WDMA writes video data to the memory DDR3 according to the frame synchronization signal. The timing selection unit MUX_1 provides the first read signal output by the first timing output subunit VTG1 to the read memory controller RDMA. The read memory controller RDMA reads the frame data from the memory DDR3 according to the first read signal.

[0137] The dashed arrows in Figure 10 indicate the data flow when the processing module executes frame catch-up mode. If the associated clock information and the local clock information meet the corresponding conditions of frame catch-up mode, the processing module uses frame catch-up mode to write and read video data. Specifically, referring to Figure 10, the second timing output subunit VTG2 can output a second readout signal, where the second readout signal is preconfigured.

[0138] The processing module can allocate multiple frame address spaces in the memory. For example, the processing module can allocate three frame address spaces in the memory, and perform cyclic read and write operations on the read and write addresses within the range of [address 0, address 1, address 2]. The write order of the multiple addresses is address 0, address 1, address 2.

[0139] The write memory controller WDMA can write data to the memory according to the path clock and path timing. The write memory controller WDMA updates the write address at the rising edge of the frame synchronization signal and updates according to the preset write order. The updated write address WDMA_ADD(new) = the write address WDMA_ADD(old) before the update + 1.

[0140] The second timing output subunit VTG2 can output a second read signal, and update the read address at the rising edge of the second read signal. The updated read address RDMA_ADD(new)=WDMA_ADD(new)+1.

[0141] Based on the same technical concept, an embodiment of the present application provides an electronic device that executes the frame rate adjustment method in the above embodiment and can achieve the same technical effect, which will not be repeated here.

[0142] Referring to Figure 11, the electronic device includes a processor 1101, a memory 1102 and a communication interface 1103. The processor 1101, the memory 1102 and the communication interface are connected via a bus 1104. The communication interface 1103 is used to communicate with the opposite electronic device, including but not limited to sending requests and receiving responses. The memory 1102 stores a computer program, and the processor 1101 executes the frame rate adjustment method steps in the above embodiment according to the computer program.

[0143] The processor involved in Figure 11 of the embodiment of the present application can be a central processing unit (CPU), a general-purpose processor, a graphics processing unit (GPU), an application-specific integrated circuit (ASIC), an FPGA or other programmable logic device, a transistor logic device, a hardware component or any combination thereof.

[0144] On the other hand, the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions. When the computer instructions are executed on an electronic device, the electronic device executes a frame rate adjustment method.

[0145] On the other hand, an embodiment of the present application provides a computer program product, comprising a computer program, which implements the steps of the above-mentioned frame rate adjustment method when executed by an electronic device.

[0146] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware, or any combination thereof. When implemented by software, all or part of the embodiments may be implemented in the form of a computer program product.

[0147] The present application also provides a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrations. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)). In the absence of conflict, the solutions of the above embodiments can be used in combination.

[0148] It will be understood by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Thus, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0149] The present invention is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0150] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0151] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0152] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0153] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A frame rate adjustment method, wherein, including: receiving video data; acquiring the clock information associated with the video data; determining a target mode from multiple frame rate adjustment modes based on the associated clock information and local clock information; writing and reading the video data according to the target mode; outputting the read video data to a display panel.

2. The method according to claim 1, wherein Among the multiple frame rate adjustment modes, any one of the modes is configured with conditions corresponding to that mode, where the associated clock information and the local clock information satisfy the conditions corresponding to the target mode.

3. The method according to claim 2, wherein, The multiple frame rate adjustment modes include at least two of the following modes: line synchronization mode, frame synchronization mode, frame chasing mode.

4. The method according to claim 3, wherein The video data includes at least one frame of data, and the frame of data includes at least one line of data; The first mode condition corresponding to the line synchronization mode is determined based on the horizontal total length and horizontal resolution of the line of data; or, The second mode condition corresponding to the frame synchronization mode is determined based on the horizontal total length and horizontal resolution of the line of data, the vertical total length and vertical resolution of the frame of data; or, The third mode condition corresponding to the frame chasing mode is determined based on the horizontal total length and horizontal resolution of the line of data, the vertical total length and vertical resolution of the frame of data.

5. The method according to any one of claims 1-4, wherein, The writing and reading the video data according to the target mode includes: If the target mode is the line synchronization mode, writing the video data into a line buffer according to the associated signal and the associated timing of the video data, and at the start time when any line of data is written into the line buffer, reading the previous line of data of the any line of data from the line buffer based on the local clock signal.

6. The method according to any one of claims 1-4, wherein, The writing and reading the video data according to the target mode includes: If the target mode is the frame synchronization mode, writing the video data into a memory according to the frame synchronization signal corresponding to the video data, and reading the video data from the memory according to a first reading signal, where the waveform of the first reading signal is the same as the waveform of the frame synchronization signal, and the start time of the first reading signal is the same as any falling edge time of the frame synchronization signal.

7. The method according to any one of claims 1-4, wherein The writing and reading the video data according to the target mode includes: If the target mode is the frame chasing mode, writing frame data into frame address spaces successively according to the writing order of multiple frame address spaces in the memory. Among them, after writing frame data into a first frame address space corresponding to a first writing order, writing frame data into a second frame address space corresponding to a second writing order, and reading frame data from the first frame address space, where the second writing order is the next order of the first writing order.

8. A frame rate adjustment device, wherein, including: a receiving interface for receiving video data; an output interface for outputting video data to a display panel; a processing module for: receiving video data; acquiring the clock information associated with the video data; determining a target mode from multiple frame rate adjustment modes based on the associated clock information and local clock information; Write the video data and read the video data according to the target pattern; Output the read video data to the display panel.

9. The apparatus according to claim 8, wherein The processing module includes a line buffer.

10. The device according to claim 8, wherein, The processing module is connected to a memory, and the memory is used to store any frame data in the video data.

11. An electronic device, wherein, Comprising: A processor, a memory, and one or more programs; Wherein, the one or more programs are stored in the memory, and the one or more programs include instructions that, when executed by the processor, cause the electronic device to perform the method steps described in any one of claims 1-7.

12. A computer-readable storage medium, wherein, The computer-readable storage medium is used to store a computer program, and when the computer program runs on a processor, the processor is caused to perform the method described in any one of claims 1-7.

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