Method and device for visually displaying surface of wafer

Abstract

A method for visually displaying the surface of a wafer, comprising: acquiring at least one parameter, wherein the at least one parameter comprises a first parameter L, a second parameter N, a third parameter, and a fourth parameter ε; on the basis of the first parameter L, the second parameter N, and the third parameter, generating a reference pattern corresponding to the surface of the wafer, wherein the reference pattern consists of square cell grids with equal side lengths; and displaying the reference pattern on the basis of a segmentation value S, such that the surface of the wafer is visually displayed, wherein the segmentation value S is obtained on the basis of the third parameter and the fourth parameter ε, and S∈[0,1]. The wafer is segmented by means of the uniform cell grids, and the cell grids are distinguished by using different segmentation values, so that the surface of the wafer can be visually displayed, facilitating viewing and quick understanding of information shown in the grids, improving the degree of visualization, enhancing human-machine cooperation performance.

Description

A wafer surface visualization display method and device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on January 24, 2024, with application number 202410098420.1 and invention name “A method and device for visualizing the surface of a wafer”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the technical field of integrated circuit equipment, and in particular to a method and device for visually displaying the surface of a wafer. Background Art

[0003] Wafers are the basis for chip manufacturing, and the need for wafer surface inspection or processing visualization is becoming increasingly important in the chip manufacturing process.

[0004] At present, the visualization processing of wafers usually pays special attention to the edge part, does not pay enough attention to edge processing or irregular triangulation, cannot adapt to the needs of wafers of different sizes, multiple reference surfaces and granularity, has a low degree of visualization and weak human-computer collaboration performance. Summary of the Invention

[0005] The present application provides a method and device for visually displaying the surface of a wafer, which divides the wafer into uniform grid units to avoid the intersection and overlap of the divided parts, and uses the dividing values ​​to distinguish different types of unit grids, adapting to the needs of wafers of different sizes, multiple reference surfaces and granularity, improving the degree of visualization, and enhancing the performance of human-computer collaboration.

[0006] In a first aspect, an embodiment of the present application provides a method for visually displaying a wafer surface, comprising:

[0007] Obtaining at least one parameter, the at least one parameter including a first parameter L, a second parameter N, a third parameter, and a fourth parameter ε, wherein the first parameter L is used to indicate a diameter of a wafer, the second parameter N is used to indicate a granularity of division of the wafer, the third parameter is used to indicate a reference surface of the wafer, and the fourth parameter ε is used to indicate an edge threshold of the wafer;

[0008] Generate a reference pattern corresponding to the wafer surface according to the first parameter L, the second parameter N, and the third parameter, wherein the diameter of the reference pattern is L, and the reference pattern is composed of square unit grids with equal sides, and the side length of the unit grid is L / N, where N is an integer greater than 0;

[0009] The reference pattern is displayed according to the segmentation value S, so that the wafer surface is visualized, wherein the segmentation value S is obtained according to the third parameter and the fourth parameter ε, and S∈[0,1].

[0010] In a second aspect, an embodiment of the present application provides a wafer surface visualization display device, comprising:

[0011] an acquisition unit, configured to acquire at least one parameter, the at least one parameter including a first parameter L, a second parameter N, a third parameter, and a fourth parameter ε, wherein the first parameter L is used to indicate a diameter of the wafer, the second parameter N is used to indicate a granularity of the wafer, the third parameter is used to indicate a reference surface of the wafer, and ε is used to indicate an edge threshold of the wafer;

[0012] A generating unit, configured to generate a reference pattern corresponding to the wafer surface according to the first parameter L, the second parameter N, and the third parameter, wherein the diameter of the reference pattern is L, and the reference pattern is composed of a square unit grid with equal sides, and the side length of the unit grid is L / N, where N is an integer greater than 0;

[0013] The display unit is used to display a reference pattern according to a segmentation value S, so that the wafer surface is visually displayed, wherein the segmentation value S is obtained according to the third parameter and the fourth parameter ε, and S∈[0,1].

[0014] In a third aspect, an embodiment of the present application provides an electronic device comprising a processor, a memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the processor, and the one or more programs include instructions for executing the steps in the above method.

[0015] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium on which a computer program is stored, and the computer program is executed by a processor to implement the steps of the above method.

[0016] It can be seen that in this application, at least one parameter is first obtained, and the at least one parameter includes a first parameter L, a second parameter N, a third parameter, and a fourth parameter ε. The first parameter L is used to indicate the diameter of the wafer, the second parameter N is used to indicate the division granularity of the wafer, the third parameter is used to indicate the reference surface of the wafer, and the fourth parameter ε is used to indicate the edge threshold of the wafer. Then, a reference pattern corresponding to the wafer surface is generated according to the first parameter L, the second parameter N, and the third parameter. The diameter of the reference pattern is L, and the reference pattern is composed of square unit grids with equal side lengths. The side length of the unit grid is L / N, and N is an integer greater than 0. Finally, the reference pattern is displayed according to the segmentation value S, so that the wafer surface is visualized, wherein the segmentation value S is obtained according to the third parameter and ε, and S∈[0,1]. In this way, the wafer is segmented by a unified grid unit to avoid the intersection and overlap of the segmented parts, obtain the segmentation value of each grid unit, and intuitively display the wafer surface. It is convenient to view and quickly understand the information shown in the grid, improve the degree of visualization, and enhance the human-computer collaboration performance.

[0017] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0019] FIG1 is a schematic diagram of a process for visually displaying a wafer surface according to an embodiment of the present application;

[0020] FIG2 is a schematic diagram of a unified representation method for different reference surface morphologies of a wafer provided by an embodiment of the present application;

[0021] FIG3 is a schematic diagram of a wafer surface display provided in an embodiment of the present application;

[0022] FIG4 is a schematic diagram of another wafer surface display provided in an embodiment of the present application;

[0023] FIG5 is a schematic diagram of different situations of a unit grid partially included in a reference pattern provided by an embodiment of the present application;

[0024] FIG6 is a schematic diagram of a wafer surface profile result provided in an embodiment of the present application;

[0025] FIG7 is a schematic diagram of another wafer surface profiling result provided in an embodiment of the present application;

[0026] FIG8 is a block diagram of the functional units of a wafer surface visualization display device provided in an embodiment of the present application;

[0027] FIG9 is a block diagram of the functional units of another wafer surface visualization display device provided in an embodiment of the present application. Specific embodiments

[0028] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0029] The terms "first," "second," and the like in the specification and claims of this application and the accompanying drawings are used to distinguish between different objects, not to describe a particular order. Furthermore, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.

[0030] References to "embodiments" herein mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0031] In the embodiments of this application, "and / or" describes the relationship between associated objects and indicates that three relationships can exist. For example, "A and / or B" can represent the following three situations: A exists alone; A and B exist simultaneously; and B exists alone. A and B can be singular or plural.

[0032] In the embodiments of the present application, the symbol " / " can indicate that the preceding and following objects are in an "or" relationship. In addition, the symbol " / " can also represent a division sign, that is, performing a division operation. For example, A / B can mean A divided by B.

[0033] In the embodiments of this application, "equal to" can be used in conjunction with "greater than" and is applicable to the technical solution adopted when "greater than" is used, and can also be used in conjunction with "less than" and is applicable to the technical solution adopted when "less than" is used. When "equal to" is used in conjunction with "greater than", it should not be used in conjunction with "less than"; when "equal to" is used in conjunction with "less than", it should not be used in conjunction with "greater than".

[0034] Currently, wafer visualization typically uses larger grids for regular areas and smaller grids for irregular areas such as edges. Furthermore, there are two or more layers of grids with different resolutions and accuracies, which is not conducive to human-computer interaction and visualization understanding at a single grid scale. It is also impossible to easily view and quickly understand the information shown on the grid (for example, defect statistics).

[0035] In response to the above problems, an embodiment of the present application provides a method and device for visually displaying the surface of a wafer. The embodiment of the present application is described in detail below with reference to the accompanying drawings.

[0036] Please refer to Figure 1, which is a flow chart of a method for visually displaying a wafer surface provided by an embodiment of the present application. As shown in Figure 1, the method includes the following steps.

[0037] Step S101, obtain at least one parameter of the wafer, the at least one parameter includes a first parameter L, a second parameter N, a third parameter and a fourth parameter ε, the first parameter L is used to indicate the diameter of the wafer, the second parameter N is used to indicate the division granularity of the wafer, the third parameter is used to indicate the reference surface of the wafer, and the fourth parameter ε is used to indicate the edge threshold of the wafer.

[0038] Among them, the first parameter L can represent the size of different wafers. Specifically, the first parameter L can represent the diameter of the wafer. The diameter of the wafer can be 2 inches, 4 inches, 6 inches, 8 inches, 12 inches and any specifications or measurement units.

[0039] The second parameter N is an integer greater than 0, and generally does not exceed 1000. The recommended range of N may be 5 to 100. Generally, N may be preset to a default value, for example, N=23 for a typical screen resolution of 800×600 and N=33 for a typical screen resolution of 1260×1024.

[0040] Among them, the reference surface of the wafer can include different types of reference surfaces such as a flush surface, a symmetrical V-groove cut, and an asymmetrical V-groove cut. Please refer to Figure 2, which is a schematic diagram of a unified representation method for different reference surface forms of a wafer provided by an embodiment of the present application. As shown in Figure 2, the wafer reference surface parameters h, α, and β can unify different types of reference surfaces, and α and β can respectively represent the angles on both sides of the bow high line, with values ​​between 0° and 90°; when α and β are both 90°, the reference surface of the wafer is a reference edge, when at least one of α and β is not 90° but α and β are equal, the reference surface of the wafer is a symmetrical V-groove cut, and when α and β are not equal, the reference surface of the wafer is an asymmetrical V-groove cut, and h can represent the bow height or the depth of the V-groove ground off the reference edge.

[0041] The edge threshold can range from 0 to 1, representing the ratio of the area of ​​the cell grid contained in the reference pattern to the cell grid. The edge threshold can also range from 2 to 3, which can be represented by 2+e, where e is a value between 0 and 1. In this case, the edge threshold indicates that the reference pattern contains a circle with a center point of the cell grid and a radius of e.

[0042] Step S102, generating a reference pattern corresponding to the wafer surface according to the first parameter L, the second parameter N and the third parameter, wherein the diameter of the reference pattern is L, and the reference pattern is composed of square unit grids with equal side lengths, and the side length of the unit grid is L / N, where N is an integer greater than 0.

[0043] The reason why the unit grid is a square is that the square can form a non-intersection and cover the circular surface of the wafer compared to the circle, and can more naturally display positioning and perform local magnification in the square screen coordinate system than the triangle.

[0044] The partitioning granularity N divides the wafer diameter into N equal parts. The entire visible area is divided into a grid of units with a side length of L / N, so that the unit grid size is an integer ratio to the wafer diameter. This ensures that the user-defined N has a clear visual correspondence with the overall proportions of the actual object, adapting to wafers of different sizes and flexibly responding to different granularity requirements. This makes it very easy to understand and facilitates more abstract, higher-level decision-making.

[0045] The reference circular surface is not a perfect circle. Because the diameter parameter is required to express this shape, it is referred to as the "reference circular surface" in this example. During wafer production, a mark is typically made on the growing wafer. The direction of the mark indicates the wafer's growth orientation. The wafer is then mechanically cut based on this mark to produce wafers.

[0046] It can be seen that in some embodiments, the wafer surface is divided by setting a uniform square unit grid, and the unit grid has a certain relationship with the wafer diameter, which is conducive to adapting to the needs of wafers of different sizes, various reference surfaces and granularity, and is convenient for displaying or enlarging the unit grid, thereby improving the degree of visualization and enhancing the performance of human-computer interaction.

[0047] Step S103 , displaying a reference pattern according to the segmentation value S, so as to visualize the wafer surface, wherein the segmentation value S is obtained according to the third parameter and the fourth parameter ε, and S∈[0,1].

[0048] Among them, “[” and “]” can represent inclusion, so S∈[0, 1] can represent that the value of the partition value S is any value between 0 and 1 and includes 0 and 1.

[0049] It can be seen that in some embodiments, the wafer is divided into uniform grid units to avoid the intersection and overlap of the divided parts, and the division values ​​are used to distinguish different types of unit grids to adapt to the needs of wafers of different sizes, multiple reference surfaces and granularity, thereby improving the degree of visualization and enhancing the human-computer collaboration performance.

[0050] In a possible embodiment, displaying the reference graphic according to the subdivision value S includes: displaying the color of the unit grid in the reference graphic according to the subdivision value S.

[0051] Color can be another name for grayscale, and different colors correspond to different grayscales.

[0052] Specifically, the color of the unit grid in the reference graphic is displayed according to the subdivision value S, including: displaying the first type of unit grid contained entirely in the reference graphic as a first color, the subdivision value S corresponding to the first color is 0, and displaying the second type of unit grid partially contained in the reference graphic as a second color, the subdivision value S corresponding to the second color is 1.

[0053] Among them, the first color and the second color can be selected according to the user's preference, please refer to Figure 3, which is a schematic diagram of a wafer surface display provided by an embodiment of the present application. As shown in Figure 3, the rightmost rectangle is the relationship between color and segmentation value. All the first-type unit grids included in the reference figure are displayed in the same color, and the segmentation value corresponding to the color is 1, indicating that these unit grids are located inside the circle on the wafer surface. The second-type unit grids partially included in the reference figure are displayed in a different color from the first-type unit grids and are all the same color. The segmentation value corresponding to the color is 0, indicating that these unit grids are not located inside the circle on the wafer surface, that is, these unit grids are located at the edge of the wafer.

[0054] Specifically, displaying the color of the unit grid in the reference graphic according to the subdivision value S includes: displaying the unit grid in a gradient color, where the gradient color corresponds to the subdivision value S of the unit grid.

[0055] Wherein, please refer to Figure 4, which is a schematic diagram of another wafer surface display provided by an embodiment of the present application. As shown in Figure 4, the rightmost rectangle is the relationship between color and segmentation value. All unit grids included in the reference pattern are displayed in the same color, and the segmentation value corresponding to the color is 1, indicating that these unit grids are located inside the circle on the wafer surface. Some unit grids included in the reference pattern display the same and / or different colors, and the segmentation values ​​of these unit grids correspond to the relationship between color and segmentation value, indicating that these unit grids are not located inside the circle on the wafer surface, that is, these unit grids are located at the edge of the wafer.

[0056] As can be seen, in some embodiments, colors are used to represent the subdivision values ​​of different unit grids. 0 and 1 can be used to determine whether all unit grids are included in the reference pattern, and any value between 0 and 1 can also be used to determine whether a unit grid is included in the reference pattern. This adapts to the needs of wafers of different sizes, multiple reference surfaces, and granularity, improves visualization, and enhances human-machine collaboration.

[0057] In some possible embodiments, the color of the unit grid in the reference pattern is displayed according to the segmentation value S, including: displaying the wafer grid defect density corresponding to the non-edge unit grid based on the non-edge unit grid being displayed as a gradient color other than the first color, wherein the edge unit grid is a unit grid adjacent to or across the edge of the reference pattern, and the non-edge unit grid is a grid other than the edge unit grid.

[0058] Among them, for the method of using 0 and 1 to represent the wafer surface, the non-edge unit grid can represent the unit grid inside the circle on the wafer surface. If there is a defect in the unit grid inside the circle on the wafer surface, the unit grid corresponding to the defective wafer grid cannot be represented by 1, that is, it can only be represented by 0, so the color of the unit grid can only be the second color, indicating that the unit grid has a defect. The defect can be a crack on the wafer surface, a displacement on the wafer surface, or a redundancy on the wafer surface. In particular, when there are defects in multiple wafer grids, multiple second colors will appear in the first color area in the reference graphic. The user can intuitively see the distribution inside the circle on the wafer surface based on the distribution of the second colors. For example, when multiple second-color unit grids are adjacent, it can be judged that the defects of the wafer are more concentrated. When the second-color unit grids are scattered in the first color area, it can be judged that the defects of the wafer are more dispersed.

[0059] It can be seen that in some embodiments, the presence of defects in the wafer can be intuitively displayed through the change of two colors, and the user can easily view and understand the information shown in the grid. Not only that, the distribution of colors can also show the distribution of defects inside the circle on the surface of the wafer, thereby improving the degree of visualization and enhancing the performance of human-computer interaction.

[0060] In some possible embodiments, the color of the unit grid in the reference graphic is displayed according to the segmentation value S, including: based on the edge unit grid and the non-edge unit grid being displayed as gradient colors, the defect density of the wafer grid corresponding to the edge unit grid and the defect density of the wafer grid corresponding to the non-edge unit grid are respectively displayed, wherein the edge unit grid is a unit grid adjacent to or across the edge of the reference graphic, and the non-edge unit grid is a grid other than the edge unit grid.

[0061] The edge cell grid may be a cell grid through which the edge of the reference figure passes, or a cell grid with one side being tangent to the edge of the reference figure.

[0062] Among them, the defective wafer may be a wafer grid that is completely included in the reference pattern and has cracks, or a wafer grid that is partially included in the reference pattern and has defects such as edge collapse and damage.

[0063] Among them, for the method of representing the wafer surface with any value between 0 and 1, the non-edge unit grid can represent the unit grid inside the circle on the wafer surface, and the edge unit grid can represent the unit grid at the edge of the reference pattern. Generally speaking, the splitting value of the non-edge grid is usually 1, so the color of the non-edge unit grid is the same color. The splitting value of the edge grid can be the same and / or different. The splitting value is related to the inclusion relationship between the unit grid and the reference pattern, and the color of the edge unit grid corresponds to the splitting value. If there is a defect in the unit grid on the wafer surface, the color of the defective unit grid changes, that is, the splitting value changes. In particular, when multiple non-edge unit grids with changed colors are adjacent, it can be judged that the defects inside the circle on the wafer surface are more concentrated. When the non-edge unit grids with changed colors are scattered in the circular part of the reference pattern, it can be judged that the defects inside the circle on the wafer surface are more dispersed. Similarly, when multiple edge unit grids with changed colors are adjacent, it can be judged that the defects at the edge of the wafer surface are more concentrated. When the edge unit grids with changed colors are scattered at the edge of the reference pattern, it can be judged that the defects at the edge of the wafer surface are more dispersed.

[0064] The gradient color can be set by the user or automatically generated by the system. Since the color corresponds to the segmentation value, the specific changes in the segmentation value of the defective unit grid can be known, thus more accurately identifying the existing defects.

[0065] As can be seen, in some embodiments, a gradient color change can be used to intuitively display whether a wafer has defects, allowing users to easily view and understand the information displayed by the grid. Furthermore, the gradient color distribution can also show the distribution of defects within and around the circular shape on the wafer surface, improving visualization and enhancing human-computer interaction.

[0066] In some possible embodiments, the method further includes: if the reference surface includes an irregular edge, obtaining a first value corresponding to the irregular edge, the first value being the distance between the irregular edge and the corresponding regular edge; obtaining a first ratio of the area of ​​the irregular edge on at least one adjacent unit grid based on the first value; determining a difference ratio between an initial ratio and the first ratio of each adjacent unit grid in at least one adjacent unit grid, the initial ratio being the ratio of each adjacent unit grid contained in the reference graphic; determining a subdivision value S based on the ratio in the reference graphic; and displaying a color corresponding to each adjacent unit grid according to the subdivision value S.

[0067] As shown in FIG2 , the first value may be h, which may represent the height of the arch removed from the reference edge or the depth of the V-groove. For a wafer whose reference surface is the reference edge, W may represent the bottom length of the arch corresponding to the reference edge. When the wafer diameter is d, h is calculated by the following formula:

[0068] In this case, α = β = 90°. For a V-groove, D1 and D2 can represent the left and right lengths of the groove, respectively, and θ can represent the groove opening angle. When the wafer diameter d = 2r, the relationship between h, α, β, D1, D2, r, and θ can be expressed by the following equations:

[0069] Substituting the above equations into cosβ=cos(θ-α)=cosθcosα-sinθsinα, we can generate the following formula:

[0070] Since the final analytical expression is relatively complex, for the sake of simplicity, the following notation is used: U1:=r 2 -D1 2 , U3:=r 2 +D1 2 , Z: = (rh) 2 , T:=D-ctgθ, S:=U1ctgθ-U2, where ":=" can be expressed as a definition, for example, E:=F can be expressed as defining E as F. So it can be simplified to: 2U3Z-U1 2 Z 2 =(TZ+S) 2 (1+T 2 )Z 2 +2(ST-U3)Z+(U1 2 +S 2 )=0

[0071] Since Z is a positive number, we can find Z as:

[0072] So I asked Then, α and β are obtained by adding the cosine formula to the inverse trigonometric function. In particular, when D1=D2, α=β. At this time, it can be determined that the reference surface of the wafer is a symmetrical V-groove cut. Otherwise, it can be determined that the reference surface of the wafer is an asymmetrical V-groove cut.

[0073] The first ratio may represent the ratio of the area of ​​at least one unit grid contained in the irregular edge to the area of ​​at least one unit grid itself, and the initial ratio may represent the ratio of the area of ​​the at least one unit grid contained in the reference pattern to the area of ​​the unit grid itself. The irregular edge may be related to the shape of the wafer reference surface. For example, when the wafer reference surface is a reference edge, the irregular edge may be an arcuate shape; when the wafer reference surface is a symmetrical V-groove cut, the irregular edge may be a fan-shaped shape; when the wafer surface is an asymmetrical V-groove cut, the irregular edge may be an irregular fan-shaped shape. For each unit grid associated with the irregular edge, the first ratio is subtracted from the initial ratio to remove the unit grids not contained in the wafer surface. For example, as shown in FIG4 , the wafer reference surface is a symmetrical V-groove cut, and the unit grids passed through by the left and right lengths are the same. The ratio of the unit grid contained in the reference pattern, i.e., the initial ratio, is 95%, and the ratio of the unit grid contained in the fan-shaped shape, i.e., the first ratio, is 50%. Therefore, the difference ratio of the unit grid should be 45%. Finally, the color corresponding to the unit grid is displayed according to the obtained difference ratio.

[0074] Among them, since the reference surface of the wafer has an irregular edge, it is not easy to see where the defect is when observing the irregular edge with the human eye. The user can determine whether there is a defect at the irregular edge of the wafer by the change in color. For example, when a certain irregular edge of the wafer has a knocked edge, the difference ratio of the corresponding unit grid will change, and thus the color of the unit grid will change. The user can determine which unit grid of the wafer has the knocked edge by observing whether the color changes. In particular, since the wafer is generally circular, its edge part will have defects such as broken edges and knocked edges. The same principle as above can be used, that is, observing whether the color of the unit grid corresponding to the edge of the wafer changes, to determine whether there is a defect at the edge of the wafer.

[0075] As can be seen, in some embodiments, the wafer surface visualization method includes various situations, such as the presence or absence of a reference edge, symmetrical V-grooves, and asymmetrical V-grooves. Using different colors to represent the cell grids in different situations intuitively displays the wafer surface, allowing users to easily view and understand the information displayed by the grids. This improves visualization, allows users to directly see changes, and enhances human-machine collaboration.

[0076] In some possible embodiments, the proportion of the edge unit grid contained in the reference pattern is calculated based on the coordinates of the intersection between the second type of grid and the edge of the reference pattern.

[0077] Among them, since the visualization interface is a coordinate system, the coordinates of the intersection of the edge unit grid and the edge of the reference figure can be determined. For the coordinates of the grid, during the calculation process, in order to ensure that the grid coordinates are proportional to the diameter of the reference figure, the two points of the grid coordinates can be first enlarged N times, and then the two points are calculated, and then the obtained grid coordinates are reduced N times to obtain the actual coordinate value.

[0078] Specifically, the proportion of the unit grid in the first part of the reference graphic included in the reference graphic is obtained, and the proportion of the unit grid in the other part of the reference graphic included in the reference graphic is determined based on the proportion of the unit grid in the first part of the reference graphic. The other part of the reference graphic is symmetrical to the first part of the reference graphic.

[0079] Among them, since the wafer corresponds to the reference pattern, the reference pattern can be divided into 8 equal parts. In this way, the meshing result of the entire reference pattern can be obtained from the meshing result of one-eighth area. Taking the lower triangular area of ​​the first quadrant as an example, the relationship between each grid unit and the reference pattern can be calculated. For the unit grids that are partially included in the reference pattern, the coordinates of the intersection of the reference pattern and the unit grid in the lower triangular area of ​​the first quadrant are first calculated. It should be noted that due to It is not a rational number, so the intersection point cannot appear on y=x. The point symmetrical about y=x that is closest to y=x in the intersection set is also added to the intersection set, and then arranged in descending order by the horizontal coordinate. There are 5 possible situations for two adjacent intersections. Please refer to Figure 5. Figure 5 is a schematic diagram of different situations of a unit grid partially included in a reference figure provided by an embodiment of the present application. As shown in Figure 5, this situation is the situation of the lower triangular area of ​​the fourth quadrant, and the upper triangular area of ​​the first quadrant is symmetrical about the x-axis with the situation shown in Figure 5. The lower triangular area of ​​the first quadrant is symmetrical about y=x with the upper triangular area of ​​the first quadrant. In particular, if the point symmetrical about y=x that is closest to y=x in the intersection set is not considered to be added to the intersection set, 8 situations will occur. For the convenience of calculation, the situation of two adjacent intersections is simplified. For the inclusion of the center circle, it is necessary to use the center point position of the unit grid. For example, set the coordinates of the grid center point to (x, y) (with the center of the circular diagram as the origin) to determine whether the following formula is true:

[0080] Where L is the diameter of the reference shape, and E can be any number between 0 and 1. If the above formula holds, the small circle with a radius of E in the unit grid is included in the reference shape.

[0081] It should be noted that the relationship between the reference figure and the unit grid in the lower triangular area of ​​the first quadrant can be determined through the above. The unit grid division result of the upper triangular area of ​​the first quadrant can be obtained by symmetry along y = x, that is, by exchanging the horizontal and vertical coordinates. In this way, the division result of the first quadrant can be obtained. The second quadrant division result is then obtained by symmetry along the y axis, the fourth quadrant division result is obtained by symmetry along the x axis, and the third quadrant division result is obtained by symmetry along the origin. In particular, when N is an odd number, it is necessary to include or supplement the unit grids that are penetrated by the coordinate axis. The vertical coordinate of the unit grid cannot be directly expressed in terms of the diameter of the reference figure. It needs to be converted through a certain relationship so that the relationship between the vertical coordinates is the same.

[0082] In some embodiments, when the reference pattern is a unit circle, it indicates that the reference pattern has a certain relationship with the wafer surface, that is, the reference pattern enlarges or reduces the wafer. Therefore, for the area ratio threshold condition, when obtaining the segmentation result of the wafer surface, it is also necessary to restore and scale the unit circle to the actual size of the wafer, that is, multiply the area ratio by Obtain the wafer surface mesh subdivision result under actual size;For the center circle threshold condition, obtain whether it is included in the reference figure (0 represents not included, 1 represents included) wafer surface mesh subdivision result. Refer to Figure 6, Figure 6 is a schematic diagram of a wafer surface subdivision result provided by an embodiment of the present application. As shown in Figure 6, for the center circle threshold condition, the subdivision result follows the principle that 0 represents that the center circle is not included in the reference figure, and 1 represents that the center circle is included in the reference figure, refer to Figure 7, Figure 7 is a schematic diagram of another wafer surface subdivision result provided by an embodiment of the present application. As shown in Figure 7, the wafer is the same as the wafer shown in Figure 6, and for the area ratio threshold condition, the wafer is represented by the color represented by 1 for the unit grid completely included in the reference figure, and the color represented by different proportions for the unit grid partially included in the reference figure.

[0083] In particular, in order to further improve the degree of visualization, there may be different downstream software interfaces or grid additional information displays, which can be conveniently carried out based on the wafer surface visualization display results generated by this application. For example, a defect is detected in a specific unit grid. The unit grid serves as the entrance to accurately view the defect on the interactive interface. It naturally has unit grid coordinates and visual positions for additional clicks or other interactive actions. It can also be colored or have additional visual effects such as hover text, so that the wafer surface visualization display results can simultaneously display the overall overview information and provide rich and accurate information entrances. A historical record can also be locally statistically displayed in the unit grid. For example, only the reference surface or edge of the wafer will have defects such as edge collapse and edge knocking. Summarizing the distribution of defect types in the unit grid over a period of time can show whether processing defects are more likely to form near the reference surface or edge.

[0084] As can be seen, in some embodiments, precise calculation formulas are derived for the edge portion under various possible threshold conditions, including full coverage, any coverage ratio between 0 and 1, or inclusion of the center point, and symmetry is used to simplify the calculation. This accuracy is important for analyzing and displaying wafer defect detection results, and is adaptable to the needs of wafers of different sizes, various reference surfaces, and granularity. Furthermore, this solution, combined with different threshold conditions, can conveniently and intuitively display the maximum number of chips during chip design, improving visualization and enhancing human-computer interaction performance.

[0085] Consistent with the above embodiment, please refer to Figure 8, which is a functional unit block diagram of a wafer surface visualization display device provided in an embodiment of the present application. As shown in Figure 8, the wafer surface visualization display device 80 includes: an acquisition unit 801 for acquiring at least one parameter, the at least one parameter including a first parameter L, a second parameter N, a third parameter and a fourth parameter ε, the first parameter L is used to indicate the diameter of the wafer, the second parameter N is used to indicate the division granularity of the wafer, the third parameter is used to indicate the reference surface of the wafer, and ε is used to indicate the edge threshold of the wafer; a generation unit 802 for generating a reference graphic corresponding to the wafer surface according to the first parameter L, the second parameter N and the third parameter, the diameter of the reference graphic is L, and the reference graphic is composed of square unit grids with equal side lengths, the side length of the unit grid is L / N, and N is an integer greater than 0; a display unit 803 for displaying the reference graphic according to the segmentation value S, so that the wafer surface is visualized, wherein the segmentation value S is obtained according to the third parameter and the fourth parameter ε, and S∈[0,1].

[0086] In some possible embodiments, in terms of displaying the reference graphic according to the segmentation value S, the display unit 803 is specifically configured to: display the color of the unit grid in the reference graphic according to the segmentation value S.

[0087] In some possible embodiments, in terms of displaying the color of the unit grid in the reference graphic according to the subdivision value S, the display unit 803 is specifically used to: display the first type of unit grid contained entirely in the reference graphic as a first color, the subdivision value S corresponding to the first color is 0, and display the second type of unit grid partially contained in the reference graphic as a second color, the subdivision value S corresponding to the second color is 1.

[0088] In some possible embodiments, in terms of displaying the color of the unit grid in the reference graphic according to the subdivision value S, the display unit 803 is specifically used to: display the unit grid with a gradient color, and the gradient color corresponds to the subdivision value S of the unit grid.

[0089] In some possible embodiments, in terms of displaying the color of the unit grid in the reference graphic according to the segmentation value S, the display unit 803 is specifically used to: display the wafer grid defect density corresponding to the non-edge unit grid based on the non-edge unit grid being displayed as a second color, wherein the edge unit grid is a unit grid adjacent to or across the edge of the reference graphic, and the non-edge unit grid is a grid other than the edge unit grid.

[0090] In some possible embodiments, in terms of displaying the color of the unit grid in the reference graphic according to the segmentation value S, the display unit 803 is specifically used to: display the defect density of the wafer grid corresponding to the edge unit grid and the defect density of the wafer grid corresponding to the non-edge unit grid based on the edge unit grid and the non-edge unit grid being displayed as gradient colors, wherein the edge unit grid is a unit grid adjacent to or across the edge of the reference graphic, and the non-edge unit grid is a grid other than the edge unit grid.

[0091] In some possible embodiments, the display unit 803 is specifically used to: if the reference surface includes an irregular edge, obtain a first value corresponding to the irregular edge, the first value being the distance between the irregular edge and the corresponding regular edge; obtain a first ratio of the area of ​​the irregular edge on at least one adjacent unit grid based on the first value; determine the difference ratio between the initial ratio of each adjacent unit grid in at least one adjacent unit grid and the first ratio, the initial ratio being the ratio of each adjacent unit grid included in the reference figure; determine a subdivision value S based on the ratio in the reference figure; and display the color corresponding to each adjacent unit grid according to the subdivision value S.

[0092] It can be understood that since the method embodiment and the device embodiment are different presentation forms of the same technical concept, the content of the method embodiment part in this application should be synchronously adapted to the device embodiment part and will not be repeated here.

[0093] In the case of adopting an integrated unit, please refer to Figure 9, which is a block diagram of the functional unit composition of another wafer surface visualization display device provided in an embodiment of the present application. As shown in Figure 9, the wafer surface visualization display device 80 includes: a processing module 812 and a communication module 811. The processing module 812 is used to control the actions of the wafer surface visualization display device for control and management, for example, the acquisition unit 801, the generation unit 802, the display unit 803 steps, and / or other processes for executing the technology described herein. The communication module 811 is used for interaction between the wafer surface visualization display device and other devices. As shown in the figure, the wafer surface visualization display device 80 may also include a storage module 813, which is used to store program code and data of the wafer surface visualization display device.

[0094] The processing module 812 may be a processor or controller, such as a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an ASIC, an FPGA, or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof. It may implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and the like. The communication module 811 may be a transceiver, an RF circuit, or a communication interface, and the like. The storage module 813 may be a memory.

[0095] All relevant contents of each scenario involved in the above method embodiment can be referred to the functional description of the corresponding functional module, and will not be repeated here. The above wafer surface visualization display device 80 can execute the wafer surface visualization display method shown in FIG1 .

[0096] The above mainly introduces the solution of the embodiment of the present application from the perspective of the execution process on the method side. It is understandable that, in order to realize the above functions, the controller includes hardware structures and software modules corresponding to the execution of each function. Those skilled in the art should easily realize that, in combination with the units and algorithm steps of each example described in the embodiment provided herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0097] The embodiment of the present application can divide the controller into functional units according to the above method example. For example, each functional unit can be divided according to each function, or two or more functions can be integrated into one processing unit. The above integrated unit can be implemented in the form of hardware or in the form of software functional units. It should be noted that the division of units in the embodiment of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation.

[0098] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0099] In the several embodiments provided in this application, it should be understood that the disclosed methods, devices, and systems can be implemented in other ways. For example, the device embodiments described above are merely schematic; for example, the division of the unit is merely a logical function division, and there may be other division methods in actual implementation; for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0100] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0101] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may be physically included separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0102] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to perform some steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: a USB flash drive, a mobile hard disk, a magnetic disk, an optical disk, a volatile memory or a non-volatile memory. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM) or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM), among other media that can store program code.

[0103] The above is a detailed introduction to the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for those skilled in the art, according to the idea of ​​the present application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

[0104] Although the present application discloses the above, the present application is not limited thereto. Any person skilled in the art may readily conceive of variations or substitutions, and may make various changes and modifications, including combinations of the above-mentioned functions and implementation steps, including software and hardware implementations, without departing from the spirit and scope of the present application, and all are within the scope of protection of the present application.

Claims

1. A method for visual display of the surface of a wafer, characterized in that, Including: Obtaining at least one parameter of a wafer, where the at least one parameter includes a first parameter L, a second parameter N, a third parameter, and a fourth parameter ε. The first parameter L is used to indicate the diameter of the wafer, the second parameter N is used to indicate the division granularity of the wafer, the third parameter is used to indicate the reference plane of the wafer, and the fourth parameter ε is used to indicate the edge threshold of the wafer; Generating a reference pattern corresponding to the wafer surface according to the first parameter L, the second parameter N, and the third parameter. The diameter of the reference pattern is L, and the reference pattern is composed of a square unit grid with equal side lengths. The side length of the unit grid is L / N, and N is an integer greater than 0; Displaying the reference pattern according to a dissection value S to visually display the wafer surface, where the dissection value S is obtained according to the third parameter and the fourth parameter ε, and S ∈ [0, 1].

2. The method according to claim 1, characterized in that, The displaying the reference pattern according to the dissection value S includes: displaying the color of the unit grid in the reference pattern according to the dissection value S.

3. The method according to claim 2, wherein The displaying the color of the unit grid in the reference pattern according to the dissection value S includes: displaying all first-class unit grids completely contained in the reference pattern as a first color, where the dissection value S corresponding to the first color is 0, and displaying second-class unit grids partially contained in the reference pattern as a second color, where the dissection value S corresponding to the second color is 1.

4. The method according to claim 2, wherein the step of displaying the colors of the unit meshes in the reference graph according to the splitting numerical value S includes: Displaying a gradient color for the unit grid, where the gradient color corresponds to the dissection value S of the unit grid.

5. The method according to claim 3, characterized in that, The method further includes: Displaying the wafer grid defect density corresponding to the non-edge unit grid based on the non-edge unit grid being displayed as the second color. Here, the edge unit grid is a unit grid adjacent to or straddling the edge of the reference pattern, and the non-edge unit grid is other grids except the edge unit grid.

6. The method according to claim 4, characterized in that, The method further includes: Displaying the defect density of the wafer grid corresponding to the edge unit grid and the defect density of the wafer grid corresponding to the non-edge unit grid respectively based on the edge unit grid and the non-edge unit grid being displayed as a gradient color. Here, the edge unit grid is a unit grid adjacent to or straddling the edge of the reference pattern, and the non-edge unit grid is other grids except the edge unit grid.

7. The method according to any one of claims 1-6, characterized in that, The method further includes: If the reference plane includes an irregular edge, obtaining a first value corresponding to the irregular edge, where the first value is the distance between the irregular edge and the corresponding regular edge; Obtaining a first ratio of the area of the irregular edge on at least one adjacent unit grid based on the first value; Determining the difference ratio between the initial ratio of each adjacent unit grid in the at least one adjacent unit grid and the first ratio, where the initial ratio is the ratio of each adjacent unit grid contained in the reference pattern; Determining the dissection value S based on the ratio in the reference pattern; Displaying the color corresponding to each adjacent unit grid according to the dissection value S.

8. The method according to claim 6, wherein The proportion of the edge unit grid contained in the reference figure is calculated based on the intersection coordinates of the edge unit grid and the edge of the reference figure.

9. The method according to claim 7, wherein Obtain the proportion of the unit grid in the first part of the reference figure contained in the reference figure, and determine the proportion of the unit grid in other parts of the reference figure contained in the reference figure according to the proportion of the unit grid in the first part of the reference figure in the reference figure, wherein the other parts of the reference figure and the first part of the reference figure have a symmetry relationship.

10. A wafer surface visualization display device, characterized in that, Comprising: An acquisition unit, configured to acquire at least one parameter, the at least one parameter including a first parameter L, a second parameter N, a third parameter, and a fourth parameter ε, the first parameter L being used to indicate the diameter of the wafer, the second parameter N being used to indicate the division granularity of the wafer, the third parameter being used to indicate the reference plane of the wafer, and ε being used to indicate the edge threshold of the wafer; A generation unit, configured to generate a reference figure corresponding to the surface of the wafer according to the first parameter L, the second parameter N, and the third parameter, the diameter of the reference figure being L, the reference figure being composed of square unit grids with equal side lengths, and the side length of the unit grid being L / N, where N is an integer greater than 0; A display unit, configured to display the reference figure according to the dissection value S, so that the surface of the wafer is visually displayed, wherein the dissection value S is obtained according to the third parameter and the fourth parameter ε, and S ∈ [0, 1].

11. An electronic device, characterized in that, Comprising a processor, a memory, and one or more programs, the one or more programs being stored in the memory and configured to be executed by the processor, the one or more programs including instructions for performing the steps in the method according to any one of claims 1-9.

12. A computer-readable storage medium, characterized in that, A computer program is stored thereon, and the computer program is executed by a processor to implement the steps of the method according to any one of claims 1-9.

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