Pixel circuit, display device, and method of driving pixel circuit

Abstract

Provided is a pixel circuit for an organic EL display device, wherein a drive transistor is configured so that: a drain terminal is connected to a high voltage-side power source line via a power source supply transistor; a source terminal is connected to an anode of an organic EL element via a light emission control transistor; and a gate terminal is connected to a reference voltage line via a first voltage setting transistor. A retention capacitor is configured so that a first terminal is connected to the gate terminal, and a second terminal is connected to the source terminal. A coupling capacitor is configured so that a first terminal is connected to the source terminal, and a second terminal is connected to the reference voltage line via a second voltage setting transistor and is also connected to a data signal line via a write control transistor. The organic EL terminal is configured so that an anode is connected to an initialization voltage line via a transistor, and a cathode connected to a low voltage-side power source line.

Description

Pixel circuit, display device, and pixel circuit driving method

[0001] The present disclosure relates to a display device, and more particularly to a current-driven display device including display elements driven by current, such as an organic EL (Electro Luminescence) display device, a pixel circuit used in the display device, and a driving method thereof.

[0002] In recent years, organic EL display devices (also called "OLED display devices") equipped with pixel circuits including organic EL elements (also called organic light-emitting diodes (OLEDs)) have been put to practical use. The pixel circuits of organic EL display devices include, in addition to the organic EL elements, drive transistors, write control transistors, and storage capacitors. Thin-film transistors are used for the drive transistors and write control transistors, and a storage capacitor is connected to the gate terminal of the drive transistor. A voltage corresponding to a data signal representing an image to be displayed (more specifically, a voltage indicating the gradation value of a pixel to be formed by the pixel circuit, hereinafter referred to as "data voltage") is applied to the storage capacitor via a data signal line from the drive circuit. The organic EL elements are self-luminous display elements that emit light at a brightness corresponding to the current flowing through them. The drive transistor is connected in series with the organic EL element and controls the current flowing through the organic EL element according to the voltage stored in the storage capacitor.

[0003] Variations and fluctuations occur in the characteristics of organic EL elements and drive transistors. Therefore, in order to achieve high-quality display in an organic EL display device, it is necessary to compensate for these variations and fluctuations in the characteristics of these elements. Known methods for organic EL display devices include methods in which compensation for element characteristics is performed internally in the pixel circuit and methods in which compensation is performed externally in the pixel circuit. A known pixel circuit using the former method (hereinafter referred to as the "internal compensation method") is a pixel circuit configured to initialize the voltage at the gate terminal of the drive transistor, i.e., the voltage held in the hold capacitor, and then charge the hold capacitor with a data voltage via a diode-connected drive transistor (hereinafter referred to as the "diode-connected internal compensation pixel circuit"). In such a diode-connected internal compensation pixel circuit, variations and fluctuations in the threshold voltage of the drive transistor are internally compensated.

[0004] US Patent Application Publication No. 2022 / 0284860 US Patent Application Publication No. 2017 / 0193919 US Patent Application Publication No. 2023 / 0042963

[0005] In the diode-connected internal compensation pixel circuit, threshold compensation of the drive transistor is performed simultaneously with writing the data voltage to the storage capacitor. In an organic EL display device using such a pixel circuit, the period for threshold compensation of the drive transistor (hereinafter referred to as the "threshold compensation period") is limited by the period for writing the data voltage to the storage capacitor (hereinafter referred to as the "data write period"), making it difficult to ensure a sufficient threshold compensation period. Furthermore, in a diode-connected internal compensation pixel circuit, during the data write period, the storage capacitor is charged via three thin-film transistors (TFTs) connected in series: the write control transistor, the drive transistor, and the diode-connected transistor, making it difficult to increase the charging speed. Therefore, when an organic EL display device using a diode-connected internal compensation pixel circuit is driven at high speed, one horizontal period becomes shorter, which can lead to incomplete threshold compensation and a deterioration in display quality.

[0006] On the other hand, in a pixel circuit in which the threshold voltage sampling operation (threshold detection operation) is separated from the data voltage writing operation, such as the internal compensation pixel circuit described in Patent Document 1 (U.S. Patent Application Publication No. 2022 / 0284860), it is possible to ensure the time required for threshold compensation even when driving at high speed. However, in this pixel circuit, the difference between the maximum and minimum voltages that can be assumed by a node including the gate terminal (hereinafter referred to as "node Ng") or a node including the source terminal (hereinafter referred to as "node Ns") of the driving transistor is large (details will be described later). For this reason, the high-level voltage Vgh to be applied to the gate terminals of transistors operating as switching elements in this pixel circuit must be set to a value greater than the maximum value, and the low-level voltage Vgl to be applied to the gate terminals of these transistors must be set to a value less than the minimum value. As a result, in an organic EL display device using this pixel circuit, the amplitude of the signals to be applied to the gate terminals of these transistors becomes large (for example, a peak-to-peak value of approximately 10 Vpp), resulting in increased power consumption.

[0007] Therefore, in display devices such as organic EL display devices that use pixel circuits of an internal compensation system, it is desirable to appropriately compensate the threshold voltage of the drive transistor without increasing the voltage amplitude of the signal that drives the pixel circuit, even when the device is driven at high speed.

[0008] A pixel circuit according to some embodiments of the present invention is a pixel circuit included in a display unit provided in a display device, the pixel circuit comprising: a display element driven by current; an N-channel drive transistor; a write control transistor as a switching element; a first voltage setting transistor as a switching element; a second voltage setting transistor as a switching element; a holding capacitor; and a coupling capacitor; wherein the display unit further comprises a high-voltage side power line, a low-voltage side power line, and at least one reference voltage line for supplying at least one reference voltage which is a predetermined fixed voltage; the drive transistor has a drain terminal connected to the high-voltage side power line, a source terminal connected to the display element, and a gate terminal connected to one of the at least one reference voltage line via the first voltage setting transistor; and the holding capacitor has a first terminal connected to the gate terminal of the drive transistor and a second terminal connected to the source terminal of the drive transistor; The coupling capacitor has a first terminal connected to the second terminal of the holding capacitor, and a second terminal that receives a data voltage to be applied to the pixel circuit via the write control transistor and is connected to one of the at least one reference voltage line or another reference voltage line via the second voltage setting transistor, and the display element has a first terminal connected to the source terminal of the drive transistor and a second terminal connected to the low-voltage side power supply line.

[0009] According to some embodiments of the present invention, a display device comprises: a display section including a plurality of pixel circuits, a high-voltage side power supply line, a low-voltage side power supply line, and at least one reference voltage line for supplying at least one reference voltage which is a predetermined fixed voltage; and a drive circuit for driving the plurality of pixel circuits, wherein each of the plurality of pixel circuits includes: a display element driven by a current, an N-channel drive transistor, a write control transistor as a switching element, a first voltage setting transistor as a switching element, a second voltage setting transistor as a switching element, a holding capacitor, and a coupling capacitor, wherein the drive transistor has a drain terminal connected to the high-voltage side power supply line, a source terminal connected to the display element, and a gate terminal connected to one of the at least one reference voltage line via the first voltage setting transistor, and the holding capacitor has a first terminal connected to the gate terminal of the drive transistor and a second terminal connected to the source terminal of the drive transistor, the coupling capacitor has a first terminal connected to the second terminal of the holding capacitor, and a second terminal that receives a data voltage to be applied to the pixel circuit via the write control transistor and is connected to the one of the at least one reference voltage line or another reference voltage line via the second voltage setting transistor; the display element has a first terminal connected to the source terminal of the drive transistor and a second terminal connected to the low-voltage side power supply line; an initialization period, a threshold voltage sampling period, a write period, and a light-emitting period are provided for each of the plurality of pixel circuits in this order; and the drive circuit, during the initialization period, holds a voltage greater than the threshold voltage of the drive transistor in the holding capacitor as an initial holding voltage; and during the threshold sampling period, the voltage held in the holding capacitor changes from the initial holding voltage towards the threshold voltage of the drive transistor;During the write period, the voltage of the second terminal of the coupling capacitor is switched from a reference voltage supplied by a reference voltage line connected to the second terminal of the coupling capacitor via the second voltage setting transistor among the one reference voltage line or the other reference voltage line to the data voltage, thereby changing the voltage held in the holding capacitor to a threshold compensation data voltage which is a voltage corresponding to the data voltage subjected to threshold compensation of the drive transistor, and during the light emission period, the switching operations of the first voltage setting transistor, the second voltage setting transistor, and the write control transistor are controlled so that a drive current corresponding to the threshold compensation data voltage held in the holding capacitor is supplied from the high-voltage side power supply line to the display element via the drive transistor.

[0010] A method for driving a pixel circuit according to some embodiments of the present invention is a method for driving a pixel circuit included in a display unit provided in a display device, wherein the display unit further includes a high-voltage power supply line, a low-voltage power supply line, and a reference voltage line for supplying a predetermined fixed voltage as a reference voltage, the pixel circuit includes a display element driven by current, an N-channel drive transistor connected in series with the display element, a holding capacitor, and a coupling capacitor, the holding capacitor having a first terminal connected to a gate terminal of the drive transistor and a second terminal connected to a source terminal of the drive transistor, the coupling capacitor having a first terminal connected to the second terminal of the holding capacitor and a second terminal, the pixel circuit being provided with an initialization period, a threshold voltage sampling period, a writing period, and a light-emitting period in that order, the driving method comprising the steps of: during the initialization period, causing the holding capacitor to hold a voltage greater than the threshold voltage of the drive transistor as an initial holding voltage; and during the threshold sampling period, changing the voltage held in the holding capacitor from the initial holding voltage towards the threshold voltage of the drive transistor. During the writing period, the voltage of the second terminal of the coupling capacitor is switched from the reference voltage to a data voltage to be applied to the pixel circuit, thereby changing the voltage held in the holding capacitor to a threshold-compensated data voltage that is a voltage corresponding to the data voltage to which threshold compensation of the drive transistor has been applied; and during the light-emitting period, a drive current corresponding to the threshold-compensated data voltage held in the holding capacitor is supplied from the high-voltage side power supply line to the display element via the drive transistor.

[0011] In a display device including a pixel circuit according to some of the above embodiments of the present invention, an initialization period, a threshold voltage sampling period, a writing period, and an emission period are sequentially provided for the pixel circuit, and the on / off (switching operations) of the writing control transistor, the first voltage setting transistor, and the second voltage setting transistor in the pixel circuit are controlled in accordance with each of these periods, thereby making it possible to operate the pixel circuit as follows: in the initialization period, a voltage greater than the threshold voltage of the drive transistor is held in the holding capacitor as an initial holding voltage, in the threshold sampling period, the voltage held in the holding capacitor changes from the initial holding voltage toward the threshold voltage of the drive transistor, in the writing period, the voltage at the second terminal of the coupling capacitor switches from the reference voltage to the data voltage, thereby changing the voltage held in the holding capacitor to a threshold-compensated data voltage that is a voltage corresponding to the data voltage subjected to threshold compensation of the drive transistor, and in the emission period, a drive current corresponding to the threshold-compensated data voltage held in the holding capacitor is supplied from a high-voltage power supply line to the display element via the drive transistor, and the display element emits light at a brightness corresponding to the drive current. As can be seen from this operation, in this pixel circuit, the threshold sampling period for detecting the threshold voltage of the drive transistor and the write period for writing data are separated, so that the threshold voltage of the drive transistor can be detected in each pixel circuit without being restricted by the write period. Furthermore, during the write period, the voltage at the second terminal of the coupling capacitor is switched from the reference voltage to the data voltage, so that a voltage corresponding to the data voltage is applied to the source terminal of the drive transistor via the coupling capacitor, thereby performing data writing and holding the threshold compensation data voltage in the holding capacitor. This causes the voltage range (VthCR) for threshold compensation to overlap with the voltage range (VdatR) for the data voltage, thereby reducing the differences between the maximum and minimum values ​​for the voltage (VnG) at the node including the gate terminal of the drive transistor, the voltage (VnS) at the node including the source terminal of the drive transistor, and the voltage (VnA) at the node including the second terminal of the coupling capacitor (see FIG. 12, described below).This suppresses an increase in the amplitude of the drive signals to be applied to the gate terminals of the first voltage setting transistor, the second voltage setting transistor, and the write control transistor as control signals for the switching operations of these transistors.

[0012] In the display device according to some of the above embodiments of the present invention, an initialization period, a threshold voltage sampling period, a writing period, and an emission period are sequentially provided for each pixel circuit. During the initialization period, an initial holding voltage is held in the holding capacitor. During the threshold sampling period, the holding voltage of the holding capacitor changes from the initial holding voltage toward the threshold voltage of the drive transistor. Then, during the writing period, data writing with threshold compensation is performed using the holding voltage of the holding capacitor at the end of the threshold sampling period as the detected value of the threshold voltage of the drive transistor, thereby holding a threshold compensation data voltage in the holding capacitor. Because the threshold sampling period for detecting the threshold voltage of the drive transistor and the writing period for writing data are thus separated in each pixel circuit, the threshold voltage of the drive transistor can be detected in each pixel circuit without being restricted by the writing period. Therefore, even when driving at high speed, threshold compensation can be appropriately performed within each pixel circuit, thereby preventing degradation of display quality. Furthermore, in the display device according to some of the above-described embodiments of the present invention, during the write period, the voltage at the second terminal of the coupling capacitor is switched from the reference voltage to the data voltage, and a voltage corresponding to the data voltage is applied to the source terminal of the drive transistor via the coupling capacitor, thereby performing data writing and holding the threshold compensation data voltage in the holding capacitor. As a result, the voltage range (VthCR) for which threshold compensation is possible overlaps with the voltage range (VdatR) for which the data voltage can be used (see FIG. 12 described below), thereby suppressing increases in the amplitude of the drive signals to be applied to the gate terminals of the first voltage setting transistor, the second voltage setting transistor, and the write control transistor as control signals for the switching operations of these transistors. Therefore, even when high-speed driving is performed, appropriate threshold compensation can be performed within each pixel circuit, suppressing degradation of display quality, without increasing power consumption due to an increase in the amplitude of the drive signals for driving each pixel circuit.

[0013] 1 is a block diagram showing the overall configuration of a display device according to a first embodiment. FIG. 2 is a timing chart for explaining a schematic operation of the display device according to the first embodiment. FIG. 3 is a circuit diagram showing the configuration of a pixel circuit in a first comparative example. FIG. 4 is a circuit diagram showing the configuration of a pixel circuit in a second comparative example. FIG. 5 is a timing chart for explaining the operation of the pixel circuit in the second comparative example. FIG. 6 is a circuit diagram showing the configuration of a pixel circuit in the first embodiment. FIG. 7 is a timing chart for explaining the operation of the pixel circuit in the first embodiment. FIG. 8 is a circuit diagram for explaining the operation of the pixel circuit in the first embodiment during an initialization period (initialization operation). FIG. 9 is a circuit diagram for explaining the operation of the pixel circuit in the first embodiment during a threshold sampling period (threshold sampling operation). FIG. 10 is a circuit diagram for explaining the operation of the pixel circuit in the first embodiment during a write period (data write operation). FIG. 11 is a circuit diagram for explaining the operation of the pixel circuit in the first embodiment during an emission period (emission operation). FIG. 12 is a diagram for explaining the effects of the pixel circuit in the first embodiment. FIG. 13 is a timing chart for explaining a schematic operation in a pause drive mode of a display device according to a second embodiment. FIG. 14 is a timing chart (A) for explaining the operation of the pixel circuit in the second embodiment during a refresh frame period, and FIG. 15 is a timing chart (B) for explaining the operation of the pixel circuit in the second embodiment during a non-refresh frame period. FIG. 10 is a circuit diagram for explaining an anode initialization operation during a non-refresh frame period of the pixel circuit in the second embodiment. FIG. 11 is a timing chart (A) for explaining operation during a refresh frame period of the pixel circuit in a display device according to a third embodiment, and a timing chart (B) for explaining operation during a non-refresh frame period. FIG. 11 is a circuit diagram for explaining a discharge operation of a source node (source terminal of a drive transistor) before a threshold sampling operation of the pixel circuit in the third embodiment. FIG. 12 is a timing chart (A, B) for explaining operation of the pixel circuit in a display device according to a fourth embodiment.FIG. 10 is a timing chart (A) illustrating driving of a pixel circuit in a fresh frame period in a display device according to a fifth embodiment, and a timing chart (B) illustrating driving of the pixel circuit in a non-refresh frame period. FIG. 11 is a circuit diagram showing the configuration of a pixel circuit in a display device according to a sixth embodiment. FIG. 12 is a block diagram showing the overall configuration of a display device according to a seventh embodiment. FIG. 13 is a circuit diagram showing the configuration of a pixel circuit in a display device according to the seventh embodiment. FIG. 14 is a timing chart (A) illustrating driving of a pixel circuit in a fresh frame period in a display device according to the seventh embodiment, and a timing chart (B) illustrating driving of the pixel circuit in a non-refresh frame period. FIG. 15 is a circuit diagram showing the configuration of a pixel circuit in a display device according to an eighth embodiment. FIG. 16 is a timing chart (A) illustrating driving of a pixel circuit in a fresh frame period in a display device according to the eighth embodiment, and a timing chart (B) illustrating driving of the pixel circuit in a non-refresh frame period. FIG. 17 is a timing chart illustrating a modified configuration in which selection periods of adjacent second scanning signal lines partially overlap. FIG. 18 is a timing chart illustrating another modified configuration in which selection periods of adjacent second scanning signal lines partially overlap. FIG. 19 is a circuit diagram showing the configuration of a modified pixel circuit in the first embodiment.

[0014] Each embodiment will be described below with reference to the accompanying drawings. The transistors in each embodiment are, for example, thin-film transistors, but the present invention is not limited thereto. Furthermore, the term "connection" in this specification means "electrical connection" unless otherwise specified, and includes not only direct connection but also indirect connection via another element, within the scope of the present invention.

[0015] 1 is a block diagram showing the overall configuration of a display device 10 according to a first embodiment. The display device 10 is an organic EL display device of an internal compensation type, and is configured such that by writing a data voltage as pixel data to each pixel circuit, a voltage corresponding to the pixel data is subjected to threshold compensation of the drive transistor and is held in each pixel circuit.

[0016] As shown in FIG. 1 , this display device 10 includes a display unit 11, a display control circuit 20, a data-side drive circuit 30, a scanning-side drive circuit 40, and a power supply circuit 50. The data-side drive circuit 30 functions as a data signal line drive circuit (also referred to as a “data driver”). The scanning-side drive circuit 40 functions as a scanning signal line drive circuit (also referred to as a “gate driver”) and a light-emitting control circuit (also referred to as an “emission driver”). In the configuration shown in FIG. 1 , these two scanning-side circuits are implemented as a single scanning-side drive circuit 40, but these two circuits may be appropriately separated, or may be arranged separately on one side and the other side of the display unit 11. Furthermore, at least a portion of the scanning-side drive circuit 40 and the data-side drive circuit 30 may be formed integrally with the display unit 11. These points also apply to other embodiments described below. The power supply circuit 50 generates a high-level power supply voltage ELVDD, a low-level power supply voltage ELVSS, an initialization voltage Vini, and a reference voltage Vref, which will be described later, to be supplied to the display unit 11, as well as power supply voltages (not shown) to be supplied to the display control circuit 20, the data side drive circuit 30, and the scanning side drive circuit 40.

[0017] The display unit 11 is provided with m (m is an integer of 2 or more) data signal lines D1 to Dm, and n (n is an integer of 2 or more) first scanning signal lines SC11 to SC1n, n second scanning signal lines SC21 to SC2n, n first light-emitting control lines EM11 to EM1n, and n second light-emitting control lines EM21 to EM2n that intersect with the data signal lines D1 to Dm. The display unit 11 is also provided with n×m pixel circuits 15 arranged in a matrix along m data signal lines D1 to Dm and n first scanning signal lines SC11 to SC1n, and each pixel circuit 15 corresponds to one of the m data signal lines D1 to Dm and one of the n first scanning signal lines SC11 to SC1n (hereinafter, when distinguishing between the pixel circuits 15, the pixel circuit corresponding to the ith first scanning signal line SC1i and the jth data signal line Dj will be referred to as the "pixel circuit in the ith row and jth column" and denoted by the symbol "Pix(i, j)"). Each pixel circuit 15 also corresponds to one of the n second scanning signal lines SC21 to SC2n, one of the n first light-emission control lines EM11 to EM1n, and one of the n second light-emission control lines EM21 to EM2n. The data side drive circuit 30 that drives the data signal lines D1 to Dm, and the scan side drive circuit 40 that drives the first scanning signal lines SC11 to SC1n, the second scanning signal lines SC21 to SC2n, the first light-emitting control lines EM11 to EM1n, and the second light-emitting control lines EM21 to EM2n constitute a drive circuit that drives n×m pixel circuits 15 in the display unit 11 (see Figure 1).

[0018] The display unit 11 is also provided with power supply lines (not shown) that are common to each pixel circuit 15. That is, a high-voltage power supply line (denoted by the symbol "ELVDD" like the high-level power supply voltage) for supplying a high-level power supply voltage ELVDD for driving the organic EL elements (described below), and a low-voltage power supply line (denoted by the symbol "ELVSS" like the low-level power supply voltage) for supplying a low-level power supply voltage ELVSS for driving the organic EL elements are provided. The display unit 11 is also provided with an initialization voltage line (denoted by the symbol "Vini" like the initialization voltage) for supplying an initialization voltage Vini used in a reset operation (also referred to as an "initialization operation") for initializing each pixel circuit 15, and a reference voltage line (denoted by the symbol "Vref" like the reference voltage) for supplying a reference voltage Vref in the initialization operation and data write operation (described below) in each pixel circuit 15. The high-level power supply voltage ELVDD, the low-level power supply voltage ELVSS, the initialization voltage Vini, and the reference voltage Vref are supplied from a power supply circuit 50. In this embodiment, these voltages ELVDD, ELVSS, Vini, and Vref are all fixed voltages.

[0019] The display control circuit 20 receives an input signal Sin from outside the display device 10, which includes image information representing the image to be displayed and timing control information for image display, generates a data-side control signal Scd and a scanning-side control signal Scs based on this input signal Sin, and outputs the data-side control signal Scd to the data-side driving circuit 30 and the scanning-side control signal Scs to the scanning-side driving circuit 40, respectively.

[0020] The data side drive circuit 30 drives the data signal lines D1 to Dm based on a data side control signal Scd from the display control circuit 20. That is, based on the data side control signal Scd, the data side drive circuit 30 outputs m data signals D(1) to D(m) in parallel, which represent an image to be displayed, and applies them to the data signal lines D1 to Dm, respectively.

[0021] The scanning side drive circuit 40 functions as a scanning signal line drive circuit that drives n first scanning signal lines SC11 to SC1n and n second scanning signal lines SC21 to SC2n based on a scanning side control signal Scs from the display control circuit 20, and also functions as a light emission control circuit that drives n first light emission control lines EM11 to EM1n and n second light emission control lines EM21 to EM2n.

[0022] More specifically, the scanning-side driving circuit 40, as a scanning signal line driving circuit, sequentially selects n first scanning signal lines SC11 to SC1n for a predetermined period each, and sequentially selects n second scanning signal lines SC21 to SC2n for a predetermined period each, based on the scanning-side control signal Scs, during each frame period, applies an active signal (high-level voltage in this embodiment) to the selected first scanning signal line SC1p (p is an integer satisfying 1≦p≦n) and the selected second scanning signal line SC2q (q is an integer satisfying 1≦q≦n), and applies an inactive signal (low-level voltage in this embodiment) to the unselected first scanning signal lines and the unselected second scanning signal lines. By driving the first and second scanning signal lines SC11 to SC1n, SC21 to SC2n in this manner, a voltage corresponding to the data voltage, which is the voltage of the corresponding data signal lines D1 to Dm, is written to the pixel circuits Pix(p,1) to Pix(p,m) corresponding to the selected pth first scanning signal line SC1p (hereinafter also referred to as the "pixel circuits in the pth row") as a data voltage to which threshold compensation has been applied as described below (p=1 to n).

[0023] In addition, during each frame period, the scanning side drive circuit 40 drives the n first light-emitting control lines EM11 to EM1n and the n second light-emitting control lines EM21 to EM2n so that they are selectively deactivated in conjunction with the above-mentioned driving of the first and second scanning signal lines SC11 to SC1n, SC21 to SC2n. That is, the scanning side drive circuit 40, as a light emission control circuit, sequentially selects n first light emission control lines EM11 to EM1n for a predetermined period each based on the scanning side control signal Scs during each frame period, and sequentially selects n second light emission control lines EM21 to EM2n for a predetermined period each, and applies a light emission control signal (low-level voltage in this embodiment) indicating no light emission to the selected first light emission control line EM1p (p is an integer satisfying 1≦p≦n) and the selected second light emission control line EM2q (q is an integer satisfying 1≦q≦n), and applies a light emission control signal (high-level voltage in this embodiment) indicating light emission to the unselected first light emission control lines and the unselected second light emission control lines. The organic EL elements in the pixel circuits Pix(i,1) to Pix(i,m) in the i-th row emit light at a brightness corresponding to the data voltages written to the pixel circuits Pix(i,1) to Pix(i,m) in the i-th row while the voltages of the first light-emitting control line EM1i and the second light-emitting control line EM2i are both at a high level (activated state) (i = 1 to n).

[0024] 2 is a timing chart for explaining the overall operation of the display device 10 according to this embodiment. The scanning-side control signal Scs provided from the display control circuit 20 to the scanning-side drive circuit 40 includes a multi-phase clock signal made up of multiple clock signals of different phases. Based on this multi-phase clock signal, the scanning-side drive circuit 40 generates first scanning signals SC1(1) to SC1(n) and second scanning signals SC2(1) to SC2(n) as shown in FIG. 2, applies the first scanning signals SC1(1) to SC1(n) to the first scanning signal lines SC11 to SC1n, respectively, and applies the second scanning signals SC2(1) to SC2(n) to the second scanning signal lines SC21 to SC2n, respectively. Furthermore, the scanning side drive circuit 40 generates first light-emitting control signals EM1(1) to EM1(n) and second light-emitting control signals EM2(1) to EM2(n) as shown in FIG. 2 based on this multi-phase clock signal, and applies the first light-emitting control signals EM1(1) to EM1(n) to the first light-emitting control lines EM11 to EM1n, respectively, and applies the second light-emitting control signals EM2(1) to EM2(n) to the second light-emitting control lines EM21 to EM2n, respectively.

[0025] On the other hand, the data-side drive circuit 30 generates data signals D(1) to D(m) that change in conjunction with the second scanning signals SC2(1) to SC2(n) based on the data-side control signal Scd from the display control circuit 20, as shown in FIG. 2, and applies these to the data signal lines D1 to Dm, respectively. In this manner, the first scanning signal lines SC11 to SC1n, the second scanning signal lines SC21 to SC2n, the first light-emission control lines EM11 to EM1n, the second light-emission control lines EM21 to EM2n, and the data signal lines D1 to Dm in the display unit 11 are driven, whereby initialization, threshold sampling, and data writing are performed for each pixel circuit Pix(i,j) during the non-light-emitting period. Note that in FIG. 2, the symbol "Trf" indicates a frame period. In this embodiment, a refresh operation is repeated in which data voltages indicated by the data signals D(1) to D(m) are written to the n×m pixel circuits 15 in the display unit 11 during one frame period. For this reason, the frame period Trf in this embodiment is also called a refresh frame period Trf.

[0026] In this manner, the scanning side drive circuit 40 drives the first scanning signal lines SC11 to SC1n, the second scanning signal lines SC21 to SC2n, the first light-emitting control lines EM11 to EM1n, and the second light-emitting control lines EM21 to EM2n, and the data side drive circuit 30 drives the data signal lines D1 to Dm, whereby a data voltage based on the image information contained in the input signal Sin is written to each pixel circuit 15, and the organic EL element OL in each pixel circuit 15 emits light at a brightness corresponding to the data voltage, thereby displaying an image represented by the image information on the display unit 11.

[0027] <1.3 Configuration and operation of pixel circuit> Below, we will first explain the configuration and operation of a known pixel circuit using an internal compensation method in a display device as a first comparative example of this embodiment and a known pixel circuit using an internal compensation method in a display device as a second comparative example of this embodiment, and then explain the configuration and operation of pixel circuit 15 in this embodiment.

[0028] 3 is a circuit diagram showing the configuration of a pixel circuit 13 in the first comparative example, and more specifically, the configuration of the pixel circuit 13 corresponding to the ith scanning signal line Gi and the jth data signal line Dj, i.e., the pixel circuit Pix(i, j) in the ith row and jth column (1≦i≦n, 1≦j≦m). Note that in the display section of the display device of the first comparative example, scanning signal lines G0 to Gn are arranged in place of the first scanning signal lines SC11 to SC1 n and the second scanning signal lines SC21 to SC2 n of the present embodiment, and light-emission control lines E1 to En are arranged in place of the first light-emission control lines EM11 to EM1 n and the second light-emission control lines EM21 to EM2 n.

[0029] 3, the pixel circuit 13 includes an organic EL element OL as a display element, a drive transistor M1, a write control transistor M2, a threshold compensation transistor M3, a first initialization transistor M4, a power supply transistor M5, a light-emission control transistor M6, a second initialization transistor M7, and a holding capacitor Cs. In this pixel circuit 13, the transistors M2 to M7 other than the drive transistor M1 function as switching elements.

[0030] The pixel circuit 13 is connected to a corresponding scanning signal line Gi (hereinafter, also referred to as a "corresponding scanning signal line" in the description focusing on the pixel circuit), a scanning signal line Gi-1 immediately preceding the corresponding scanning signal line Gi (the scanning signal line immediately preceding in the scanning order of the scanning signal lines G1 to Gn, and hereinafter, also referred to as a "preceding scanning signal line" in the description focusing on the pixel circuit), a corresponding light-emitting control line Ei (hereinafter, also referred to as a "corresponding light-emitting control line" in the description focusing on the pixel circuit), a corresponding data signal line Dj (hereinafter, also referred to as a "corresponding data signal line" in the description focusing on the pixel circuit), an initialization voltage line Vini, a high-voltage side power supply line ELVDD, and a low-voltage side power supply line ELVSS.

[0031] The pixel circuit Pix(i, j), which is the pixel circuit 13 in the ith row and jth column in the first comparative example, has a configuration in which the organic EL element OL, the drive transistor M1, the write control transistor M2, the threshold compensation transistor M3, the first initialization transistor M4, the power supply transistor M5, the light-emission control transistor M6, the second initialization transistor M7, the holding capacitor Cs, the corresponding scanning signal line Gi, the preceding scanning signal line Gi-1, the corresponding light-emission control line Ei, the corresponding data signal line Dj, the initialization voltage line Vini, the high-voltage side power supply line ELVDD, and the low-voltage side power supply line ELVSS are connected as shown in FIG.

[0032] In the first comparative example, each pixel circuit 13 includes a non-light-emitting period during each frame period in which the organic EL element OL is off. The non-light-emitting period includes, in order, an initialization period and a write period. In each pixel circuit 13, the power supply transistor M5 and the light-emitting control transistor M6 are off during the non-light-emitting period. During the initialization period, the first initialization transistor M4 is turned on, thereby initializing the voltage Vg at the gate terminal of the drive transistor M1 and the holding capacitor Cs. Subsequently, the first initialization transistor M4 is turned off, and the write control transistor M2 and the threshold compensation transistor M3 are turned on. As a result, during the write period, the voltage of the corresponding data signal line Dj is written as a data voltage to the holding capacitor Cs via the write control transistor M2, the drive transistor M1, and the threshold compensation transistor M3 (see the dotted-line path in FIG. 3 ). At this time, the drive transistor M1 is diode-connected by the on-state threshold compensation transistor M3, so that this write operation causes a voltage corresponding to the threshold-compensated data voltage to be held in the holding capacitor. Subsequently, when the non-light-emitting period ends and the light-emitting period begins, the write control transistor M2 and threshold compensation transistor M3 are turned off, the power supply transistor M5 and light-emitting control transistor M6 are turned on, and a drive current I1 corresponding to the voltage held in the holding capacitor Cs is supplied from the drive transistor M1 to the organic EL element OL. The organic EL element OL emits light at a luminance corresponding to the drive current I1. At this time, the data voltage that has been subjected to threshold compensation is held in the holding capacitor Cs, so the organic EL element OL emits light at a luminance corresponding to the data voltage applied from the corresponding data signal line Dj during the write period, regardless of the threshold voltage of the drive transistor M1.

[0033] As described above, in the pixel circuit 13 of the first comparative example, during the write period, the voltage of the corresponding data signal line Dj is written as a data voltage to the storage capacitor Cs via the write control transistor M2, the drive transistor M1, and the threshold compensation transistor M3. That is, threshold compensation of the drive transistor M1 and writing of the data voltage are performed simultaneously. Therefore, the period for threshold compensation of the drive transistor M1 (threshold compensation period) is limited by the data voltage write period, making it difficult to ensure a sufficient threshold compensation period. Furthermore, to write the data voltage to the storage capacitor Cs, a current flows between the corresponding data signal line Dj and the storage capacitor via the three thin-film transistors M2, M1, and M3 connected in series, along the path indicated by the dotted lines in FIG. 3 , making it difficult to increase the data voltage write speed. Therefore, in the display device of the first comparative example using the pixel circuit 13 with the internal compensation method shown in FIG. 3 , when driven at high speed, one horizontal period becomes shorter, which tends to result in incomplete threshold compensation and a deterioration in display quality.

[0034] 4 is a circuit diagram showing the configuration of a pixel circuit in a display device as a second comparative example of this embodiment. This pixel circuit is an internal compensation pixel circuit corresponding to pixel 22 disclosed in Patent Document 1 (U.S. Patent Application Publication No. 2022 / 0284860) (see Figures 8A and 8B of the same document). Hereinafter, the pixel circuit in this second comparative example will be referred to as "14."

[0035] The display section of the display device serving as the second comparative example is provided with a plurality of horizontal control lines G in place of the first scanning signal lines SC11 to SC1n, the second scanning signal lines SC21 to SC2n, the first light-emission control lines EM11 to EM1n, and the second light-emission control lines EM21 to EM2n of the present embodiment, and is also provided with a plurality of data lines D corresponding to the data signal lines D1 to Dm of the present embodiment. Each pixel circuit 14 is supplied with three scanning signals SCAN1 to SCAN3 and two light-emission control signals EM1 and EM2 via the horizontal control lines G, and with one data signal (data voltage) Vdata via the data line D. Also, as in the present embodiment, a positive power supply voltage VDDEL corresponding to the high-level power supply voltage ELVDD is supplied via the positive power supply line, a ground power supply voltage VSSEL corresponding to the low-level power supply voltage ELVSS is supplied via the ground power supply line, a reference voltage Vref is supplied via the reference voltage line, and an initialization voltage Vini is supplied via the initialization voltage line.

[0036] As shown in Figure 4, the pixel circuit 14 includes an organic light-emitting diode 26, a drive transistor Trive, a data loading transistor Tdata, two light-emission control transistors Tem1 and Tem2, a gate voltage setting transistor Tgate, an initialization transistor Tini, an anode reset transistor Tar, a storage capacitor Cst, and an additional capacitor Cboost, and these electrical elements are connected as shown in Figure 4. Note that scanning signals SCAN1 and SCAN2, and light-emission control signals EM1 and EM2 are respectively applied to the gate terminals of the data loading transistor Tdata, the gate voltage setting transistor Tgate, and the light-emission control transistors Tem1 and Tem2, and a scanning signal SCAN3 is applied to the gate terminals of the initialization transistor Tini and the anode reset transistor Tar. Note that Vdc applied to one terminal (the upper terminal in the figure) of the additional capacitor Cboost represents any of the existing DC voltages such as VDDEL, VSSEL, Vref, Var, and Vini.

[0037] In this second comparative example, each pixel circuit 13 also has a non-light-emitting period during each frame period in which the organic light-emitting diode 26 is turned off. FIG. 5 is a diagram for explaining the operation of the pixel circuit 14 during the non-light-emitting period. In this pixel circuit 14, initialization, threshold sampling (Vt sampling), and data programming are performed during the non-light-emitting period by changing the scan signals SCAN1 to SCAN3 and the light-emitting control signals EM1 and EM2 provided to the pixel circuit 14 as shown in FIG. 5. That is, in the pixel circuit 14 of the second comparative example, an initialization period Ti, a threshold sampling period Tvtsmp, and a data programming period Tdpg, which correspond to the three operations of initialization, threshold sampling, and data programming, are provided in this order during the non-light-emitting period.

[0038] 4 and 5 , in the pixel circuit 14 of the second comparative example, during the initialization period Ti, a reference voltage Vref is applied to a first terminal of the storage capacitor Cst (the terminal connected to the gate terminal of the drive transistor Tdrive) via the gate voltage setting transistor Tgate, and an initialization voltage Vini is applied to a second terminal of the storage capacitor Cst (the terminal connected to the source terminal of the drive transistor Tdrive) via the initialization transistor Tini. This causes the storage capacitor Cst to be charged to a voltage Vref-Vini. Thereafter, during the threshold sampling period Tvtsmp, a current flows into the storage capacitor Cst from the positive power supply line VDDEL via the drive transistor Tdrive, causing the held voltage of the storage capacitor Cst to decrease from Vref-Vini toward the threshold voltage Vth. When the held voltage decreases to a voltage substantially equal to the threshold voltage Vth of the drive transistor Tdrive, the flow of current into the storage capacitor Cst stops. As a result, at the end time t3 of the threshold sampling period Tvtsmp, the threshold voltage Vth of the drive transistor Tdrive is held in the storage capacitor Cst. During the subsequent data programming period Tdpg, the gate voltage setting transistor Tgate, the light-emitting control transistors Tem1 and Tem2, and the initialization transistor Tini are turned off, and the data loading transistor Tdata is turned on, so that the voltage VnG of the node including the gate terminal of the drive transistor Tdrive (hereinafter referred to as the "node G voltage") changes from the reference voltage Vref to the data voltage Vdata at time t4. Due to this change in the node G voltage VnG, the voltage VnS of the node including the source terminal of the drive transistor Tdrive (hereinafter referred to as the "node S voltage") also changes, as follows: VnS=Vref-Vth+{Cst / (Cst+Cboost)}(Vdata-Vref) ... (1) At this time, the voltage held in the storage capacitor Cst, that is, the gate-source voltage Vgs of the drive transistor Tdrive, is given by the following equation:Vgs = VnG - VnS = {Cst / (Cst + Cboost)} (Vdata - Vref) + Vth ... (2) At the end of the data programming period Tdpg, the voltage expressed by the above formula, i.e., the voltage corresponding to the data voltage Vdata to which threshold compensation has been applied (hereinafter referred to as the "threshold compensation data voltage"), is maintained.

[0039] Thereafter, when the non-light-emitting period ends and the light-emitting period begins (after time t5), a current corresponding to the voltage held in the storage capacitor Cst is supplied from the drive transistor Tdrive to the organic light-emitting diode 26, and the organic light-emitting diode 26 emits light at a brightness corresponding to that current. At this time, the storage capacitor Cst holds the voltage calculated by the above equation (2), so the organic light-emitting diode 26 emits light at a brightness corresponding to the data voltage vdata, regardless of the threshold voltage Vth of the drive transistor Tdrive.

[0040] 5 shows waveforms of the node G voltage VnG and the node S voltage VnS in addition to a timing chart illustrating changes in the scan signals SCAN1, SCAN2 and the light-emission control signals EM1, EM2 provided to pixel circuit 14 in the second comparative example. As shown in FIG. 5, the node G voltage Vng is at its minimum when the reference voltage Vref is provided during the initialization period Ti or the threshold sampling period Tvtsmp, and is at its maximum when the data voltage Vdata is provided during the data programming period Tdpg. The node S voltage VnS is at its minimum when the initialization voltage Vini is provided during the initialization period Ti, and is at its maximum when it rises from the initialization voltage Vini to Vref-Vth during the threshold sampling period Tvtsmp and then further rises during the data programming period Tdpg due to the application of the data voltage Vdata to node Ng. 5, VthCR indicates the voltage range in which threshold compensation is possible, and VdataR indicates the voltage range that the data voltage Vdata can take. When the node G voltage VnG and the node S voltage VnS are considered together, the maximum value is Vdata and the minimum value is Vini. Therefore, in pixel circuit 14 of the second comparative example, in order for the transistors connected to node Ng or node Ns, i.e., the data loading transistor Tdata, the gate voltage setting transistor Tgate, the light-emission control transistor Tem2, and the initialization transistor Tini, to operate normally as switching elements, the H-level voltages and L-level voltages of the scan signals SCAN1 to SCAN3 and the light-emission control signal EM2, i.e., the gate high voltage VgH and the gate low voltage VgL, must be set to satisfy the following equations: VgH>Vdata (3) VgL<Vini (4)

[0041] For example, if the reference voltage Vref is 0V, the initialization voltage Vini is −5V, and the data voltage Vdata ranges from 0 to 5V, the amplitude (peak-to-peak value) of the scan signals SCAN1 to SCAN3 must be 10Vpp or more.

[0042] As described above, according to the second comparative example, the amplitudes of the scan signals SCAN1 to SCAN3 and the light-emission control signal EM2 for driving the pixel circuit 14 must be increased, which increases the power consumption of the drive circuit. In other words, a pixel circuit with an internal compensation method configured as shown in FIG. 4 is disadvantageous in terms of power reduction. This is due to the operation of increasing the node G voltage VnG by Vref-Vini relative to the node S voltage VnS during the initialization period Ti, followed by a threshold sampling operation, and then applying the data voltage Vdata to the node Ng during the data programming period Tdpg, thereby increasing the node G voltage VnG from Vref to Vdata (see FIG. 5).

[0043] 6 shows the configuration of a pixel circuit 15 corresponding to the ith first scanning signal line SC1i and the jth data signal line Dj in this embodiment, i.e., the pixel circuit Pix(i, j) in the ith row and jth column (1≦i≦n, 1≦j≦m). As shown in Fig. 6, the pixel circuit 15 includes one organic EL element OL as a display element, seven transistors (typically thin-film transistors) T1 to T6 (hereinafter referred to as the "first voltage-setting transistor T1," the "write control transistor T2," the "second voltage-setting transistor T3," the "drive transistor T4," the "power-supply transistor T5," the "emission control transistor T6," and the "initialization transistor T7"), and two capacitors Cst and Cc (hereinafter referred to as the "holding capacitor Cst" and the "coupling capacitor Cc"). The transistors T1 to T7 are N-channel transistors, such as thin-film transistors (hereinafter referred to as "IGZO-TFTs") whose channel layers are formed of indium gallium zinc oxide (InGaZnO) as an oxide semiconductor. However, this is not limiting. The storage capacitor Cst and the coupling capacitor Cc are both capacitive elements having two terminals (a first terminal and a second terminal). In the pixel circuit 15, the transistors T1 to T3 and T5 to T7 other than the drive transistor T4 function as switching elements. Thin-film transistors whose channel layers are formed of an oxide semiconductor, such as IGZO-TFTs, have small off-leak currents and are therefore suitable as switching elements in the pixel circuit 15.

[0044] As shown in FIG. 6 , a pixel circuit Pix(i, j) in the i-th row and j-th column in this embodiment is connected to a corresponding first scanning signal line SC1i (hereinafter, referred to as the “corresponding first scanning signal line” in the description focusing on the pixel circuit) a corresponding second scanning signal line SC2i (hereinafter, referred to as the “corresponding second scanning signal line” in the description focusing on the pixel circuit) a corresponding first light-emitting control line EM1i (hereinafter, also referred to as the “corresponding first light-emitting control line” in the description focusing on the pixel circuit) a corresponding second light-emitting control line EM2i (hereinafter, also referred to as the “corresponding second light-emitting control line” in the description focusing on the pixel circuit) a corresponding data signal line Dj (hereinafter, also referred to as the “corresponding data signal line” in the description focusing on the pixel circuit) an initialization voltage line Vini, a reference voltage line Vref, a high-voltage side power supply line ELVDD, and a low-voltage side power supply line ELVSS. The transistor T5 has the function of controlling the light emission (on / off) of the organic EL element OL based on the first light-emission control signal EM1(i), but is in an on-state during a threshold sampling period Tvhsmp within the non-light-emission period Tne, during which a high-level power supply voltage ELVDD is supplied to the pixel circuit Pix(i,j) via the transistor T5 (see Figures 7 and 9 described below). Therefore, in this specification, the transistor T5 is referred to as the "power supply transistor T5" as described above, and therefore the first light-emission control signal may also be referred to as a "voltage supply control signal" and the first light-emission control line may also be referred to as a "power supply control line." In this case, the second light-emission control signal may also be simply referred to as a "light-emission control signal" and the second light-emission control line may also be simply referred to as a "light-emission control line."

[0045] 6 , the drive transistor T4 in the pixel circuit 15 has a drain terminal connected to the high-voltage power line ELVDD via the power supply transistor T5, a source terminal connected to the organic EL element OL via the emission control transistor T6, and a gate terminal connected to the reference voltage line Vref via the first voltage setting transistor T1. The organic EL element OL has an anode electrode as a first terminal connected to the source terminal of the drive transistor T4 via the emission control transistor T6 and to the initialization voltage line Vini via the initialization transistor T7, and a cathode electrode as a second terminal connected to the low-voltage power line ELVSS. The storage capacitor Cst has a first terminal connected to the gate terminal of the drive transistor T4 and a second terminal connected to the source terminal of the drive transistor T4. The coupling capacitor Cc has a first terminal connected to the second terminal of the storage capacitor Cst and a second terminal connected to the reference voltage line Vref via the second voltage setting transistor T3 and to the corresponding data signal line Dj via the write control transistor T2. A corresponding first scanning signal line SC1i is connected to the gate terminal of the first voltage setting transistor T1, a corresponding second scanning signal line SC2i is connected to the gate terminals of the write control transistor T2 and the initialization transistor T7, a corresponding first light-emitting control line (power supply control line) EM1i is connected to the gate terminals of the second voltage setting transistor T3 and the power supply transistor T5, and a corresponding second light-emitting control line EM2i is connected to the gate terminal of the light-emitting control transistor T6.

[0046] Next, the operation of the pixel circuit 15 shown in FIG. 6 , i.e., the pixel circuit Pix(i,j) in the i-th row and j-th column in this embodiment, will be described with reference to FIG. 6 , as well as FIG. 7 and FIGS. 8 to 11 . FIG. 7 is a timing chart for explaining the operation of the pixel circuit Pix(i,j). In this embodiment, a non-emission period Tne is provided in each frame period (refresh frame period Trf shown in FIG. 2 ) for each pixel circuit 15. FIG. 7 shows changes in the scanning-side drive signals during this non-emission period Tne, i.e., changes in the first scanning signal SC1(i), the second scanning signal SC2(i), the first light-emission control signal EM1(i), and the second light-emission control signal EM2(i). Furthermore, as shown in FIG. 7 , the non-emission period Tne of this pixel circuit Pix(i,j) includes, in order, an initialization period Ti, a threshold sampling period Tvtsmp, and a writing period Tw. FIG. 8 is a circuit diagram for explaining the operation of the pixel circuit Pix(i,j) during the initialization period Ti, i.e., the initialization operation; FIG. 9 is a circuit diagram for explaining the operation of the pixel circuit Pix(i,j) during the threshold sampling period Tvtsmp, i.e., the threshold sampling operation; FIG. 10 is a circuit diagram for explaining the operation of the pixel circuit Pix(i,j) during the write period Tw, i.e., the data write operation; and FIG. 11 is a circuit diagram for explaining the operation of the pixel circuit Pix(i,j) during the light-emitting period Te after the non-light-emitting period Tne, i.e., the light-emitting operation. In FIGS. 8 to 11, a dotted circle indicates that the transistor therein is in the on state, and a dotted x indicates that the corresponding transistor is in the off state. This representation method is also adopted in FIGS. 15 and 17, which will be described later.

[0047] In this embodiment, the first light-emitting control line (power supply control line) EM1i, the second light-emitting control line EM2i, the first scanning signal line SC1i, and the second scanning signal line SC2i are driven by the scanning-side drive circuit 40 as shown in FIG. 7, whereby the pixel circuit Pix(i, j) in the i-th row and j-th column in this embodiment operates as follows.

[0048] As shown in FIG. 7, just before time t0, the first light-emission control signal EM1(i) provided via the corresponding first light-emission control line EM1i and the second light-emission control signal EM2(i) provided via the corresponding second light-emission control line EM2i are at a high level (H level), the first scanning signal SC1(i) ​​provided via the corresponding first scanning signal line SC1i is at an H level, and the second scanning signal SC2(i) provided via the corresponding second scanning signal line SC2i is at an L level, and the pixel circuit Pix(i, j) is in an emitting state.

[0049] The first light-emitting control signal EM1(i) changes from H level to L level at time t0 and remains L level until time t3, then changes to H level at time t3 and remains H level until time t4, then changes to L level at time t4 and remains L level until time t8, then changes to H level at time t8, and then remains H level until the start of the non-light-emitting period in the next frame period Trf (see FIGS. 2 and 7). The second light-emitting control signal EM2(i) remains H level until time t2, then changes from H level to L level at time t2 and remains L level until time t8, then changes to H level at time t8, and then remains H level until the time corresponding to time t2 within the non-light-emitting period in the next frame period Trf (see FIGS. 2 and 7). Thus, during the period from time t0 to time t8, one or both of the first light-emitting control signal EM1(i) and the second light-emitting control signal EM2(i) are L level, so that one or both of the power supply transistor T5 and the light-emitting control transistor T6 are in the off state. Therefore, this pixel circuit Pix(i, j) is in a non-light emitting state during the period from time t0 to time t8.

[0050] Furthermore, of the first scanning signal SC1(i) ​​and the second scanning signal SC2(i) provided to this pixel circuit Pix(i,j), the first scanning signal SC1(i) ​​is at L level at time t0, changes from L level to H level at time t1, remains at H level until time t7, changes to L level at time t7, and then remains at L level until the time corresponding to time t1 within the non-light-emitting period of the next frame period Trf (see FIGS. 2 and 7). The second scanning signal SC2(i) is at L level at time t0, remains at L level until time t5, changes to H level at time t5, remains at H level for a predetermined period corresponding to one horizontal period, changes from H level to L level at time t6, and then remains at L level until the time corresponding to time t5 within the non-light-emitting period of the next frame period Trf (see FIGS. 2 and 7).

[0051] During the non-emission period Tne from time t0 to time t1, the first scanning signal SC1(i), the second scanning signal SC2(i), and the first emission control signal EM1(i) are at the L level, and the second emission control signal EM2(i) is at the H level. Therefore, the first voltage setting transistor T1, the second voltage setting transistor T3, and the power supply transistor T5 are in the OFF state, and the emission control transistor T6 is in the ON state. This causes the node S voltage VnS to drop to a level ELVSS+Vth(led), which is close to the low-level power supply voltage ELVSS. Here, Vth(led) is the threshold voltage of the organic EL element OL.

[0052] The period from time t1 to time t2 is the initialization period Ti of this pixel circuit Pix(i,j). During this initialization period Ti, as shown in FIG. 7, the second scanning signal SC2(i) and the first light-emitting control signal EM1(i) are at the L level, and the first scanning signal SC1(i) ​​and the second light-emitting control signal EM2(i) are at the H level. Therefore, as shown in FIG. 8, the second voltage setting transistor T3, the write control transistor T2, the initialization transistor T7, and the power supply transistor T5 are in the OFF state, and the first voltage setting transistor T1 and the light-emitting control transistor T6 are in the ON state. As a result, the reference voltage Vref is applied to the first terminal of the holding capacitor Cst, and the node S voltage VnS is at a level ELVSS+Vth(led) close to the low-level power supply voltage ELVSS, so that a voltage Vref-ELVSS-Vth(led) is held in the holding capacitor Cst (hereinafter, this held voltage will be referred to as the "initial holding voltage").

[0053] The period from time t3 to time t4 is the threshold sampling period Tvtsmp for this pixel circuit Pix(i,j). During this threshold sampling period Tvtsmp, as shown in FIG. 7, the second scanning signal SC2(i) and the second light-emitting control signal EM2(i) are at the L level, and the first scanning signal SC1(i) ​​and the first light-emitting control signal EM1(i) serving as a power supply control signal are at the H level. Therefore, as shown in FIG. 9, the write control transistor T2, the initialization transistor T7, and the light-emitting control transistor T6 are in the OFF state, and the first voltage setting transistor T1, the second voltage setting transistor T3, and the power supply transistor T5 are in the ON state. At the start time t3 of this threshold sampling period Tvtsmp, the voltage between the gate and source of the drive transistor T4 is equal to the initial holding voltage Vref-ELVSS-Vth(led) of the holding capacitor Cst, which is greater than the threshold voltage Vth of the drive transistor T4. Therefore, the drive transistor T4 is in the ON state. As a result, the charge stored in the holding capacitor Cst is discharged via the power supply transistor T5, the drive transistor T4, and the first voltage setting transistor T1. In response to this discharge, the holding voltage of the holding capacitor Cst, i.e., the voltage between the gate and source of the drive transistor T4, decreases, and when it decreases to the threshold voltage Vth of the drive transistor T4, the drive transistor T4 is turned off. This operation during the threshold sampling period Tvtsmp results in a state in which a voltage equal to the threshold voltage Vth of the drive transistor T4 is held in the holding capacitor Cst.

[0054] The period from time t5 to time t6 is the write period Tw of this pixel circuit Pix(i,j), which has a length of approximately one horizontal period (approximately 1H). During this write period Tw, the data voltage Vdata to be written to the pixel circuit Pix(i,j) is applied as a data signal D(j) to the corresponding data signal line Dj from the data-side drive circuit 30 (see FIG. 2). Also, during this write period Tw, as shown in FIG. 7, the first light-emission control signal EM1(i) and the second light-emission control signal EM2(i) are at the L level, and the first scanning signal SC1(i) ​​and the second scanning signal SC2(i) are at the H level. Therefore, as shown in FIG. 10, the second voltage-setting transistor T3, the power-supply transistor T5, and the light-emission control transistor T6 are in the OFF state, and the first voltage-setting transistor T1, the write control transistor T2, and the initialization transistor T7 are in the ON state. As a result, the voltage of the data signal line Dj (the voltage of the data signal D(j)) is applied as the data voltage to the second terminal of the coupling capacitor Cc instead of the reference voltage Vref. Also, during the write period Tw, as in the threshold sampling period Tvtsmp, the reference voltage Vref is still applied to the first terminal of the holding capacitor Cst. Immediately before this write period Tw, the first light-emitting control signal EM1(i) and the second light-emitting control signal EM2(i) are both at the L level (see FIG. 7), so the power supply transistor T5 and the light-emitting control transistor T6 are both in the off state, and a voltage equal to the threshold voltage Vth of the driving transistor T4 is held in the holding capacitor Cst. Therefore, the voltage of the source terminal of the driving transistor T4, i.e., the node S voltage VnS, is Vref-Vth. Here, if the node S voltage VnS immediately before the write period Tw is defined as VnS0, the node S voltage VnS at end time t6 of the write period Tw is defined as VnS1, and the data voltage provided to the pixel circuit Pix(i, j) from the data signal line Dj by the data write operation is defined as Vdata, the following equation holds for the node Ns including the source terminal of the drive transistor T4 according to the law of conservation of charge: Cst(Vref-Vs1)+Cc(Vdata-Vs1)=Cst·Vth+Cc(Vref-Vs0) (5) Substituting Vs0=Vref-Vth into the above equation and rearranging, the following equation is obtained.Vs1=Vref-Vth+{Cc / (Cst+Cc)}(Vdata-Vref) ... (6) The gate-source voltage Vgs of the drive transistor T4 at the end time t6 of the write period Tw is expressed by the following equation from the above equation (2): Vgs=Vref-Vs1={Cc / (Cst+Cc)}(Vref-Vdata)+Vth ... (7) The capacitance value of the storage capacitor Cst is set to an appropriate value from the perspective of stabilizing the gate-source voltage Vgs of the drive transistor T4 and the layout design of the pixel circuit. Furthermore, from the above equation (7), it is preferable that the capacitance value of the coupling capacitor Cc is larger than the capacitance value of the storage capacitor Cst, and for example, it is set so that Cc / (Cst+Cc) is approximately 0.5 to 0.7.

[0055] 10, since the initialization transistor T7 is in an on state during the write period Tw, in addition to the data voltage write operation as described above, the anode (first terminal) of the organic EL element OL is also initialized. That is, the charge stored in the parasitic capacitance of the organic EL element OL is discharged via the initialization transistor T7, thereby blocking the influence of the past display history on the light-emitting operation of the organic EL element OL.

[0056] At time t6, when the write period Tw ends, the second scanning signal SC2(i) changes from H level to L level, causing both the write control transistor T2 and the initialization transistor T7 to change from ON to OFF. At time t7, the first scanning signal SC1(i) ​​changes from H level to L level, causing the first voltage setting transistor T1 to change from ON to OFF. At time t8, the first light-emission control signal EM1(i) and the second light-emission control line EM2(i) change from L level to H level, causing both the power supply transistor T5 and the light-emission control transistor T6 to change from OFF to ON, thereby starting the light-emission period Te. Just before time t8, when the light-emission period Te begins, the first voltage setting transistor T1 is in the OFF state. Therefore, even if the power supply transistor T5 and the light-emission control transistor T6 change to ON at time t8, the holding voltage of the holding capacitor Cst, i.e., the gate-source voltage Vgs of the drive transistor T4, does not change.

[0057] The light-emitting period Te, which begins at time t8, continues until the first light-emitting control signal EM1(i) changes from H level to L level in the next frame period (see FIG. 2 ). During this light-emitting period Te, as shown in FIG. 7 , the first scanning signal SC1(i) ​​and the second scanning signal SC2(i) are L level, and the first light-emitting control signal EM1(i) and the second light-emitting control signal EM2(i) are H level. Therefore, as shown in FIG. 11 , the first voltage-setting transistor T1, the write control transistor T2, and the initialization transistor T7 are OFF, and the second voltage-setting transistor T3, the power supply transistor T5, and the light-emitting control transistor T6 are ON. Therefore, during this light-emitting period Te, a driving current I1 corresponding to the voltage held in the holding capacitor Cst, i.e., the gate-source voltage Vgs expressed by the above equation (7), flows from the high-voltage power line ELVDD to the low-voltage power line ELVSS via the power supply transistor T5, the driving transistor T4, the light-emitting control transistor T6, and the organic EL element OL. At this time, the driving current I1 flowing through the organic EL element OL is given by the following equation because the driving transistor T4 operates in the saturation region: I1=(β / 2)(Vgs-Vth) 2...(8) β=μ×(W / L)×Cox ...(9) In the above equations (8) and (9), Vth, μ, W, L, and Cox represent the threshold voltage, mobility, gate width, gate length, and gate insulating film capacitance per unit area of ​​the driving transistor T4, respectively. By substituting the above-mentioned equation (7) into the above equation (8), the following equation is obtained: I1=(β / 2){Cc / (Cst+Cc)}(Vref-Vdata) ...(10)

[0058] According to the above formula (10), the drive current I1 does not depend on the threshold voltage Vth. Therefore, during the light-emitting period Te, the organic EL element OL emits light with a luminance corresponding to the data voltage Vdata applied from the corresponding data signal line Dj, regardless of the threshold voltage Vth of the drive transistor T4.

[0059] 7 , the threshold sampling period Tvtsmp for detecting the threshold voltage Vth of the drive transistor T4 and the writing period Tw for writing the data voltage Vdata are separated from each other in the pixel circuit 15. Therefore, the threshold sampling period Tvtsmp can be set without being restricted by the writing period Tw for the pixel circuit 15. Therefore, even when high-speed driving is performed, appropriate threshold compensation can be performed within the pixel circuit 15, and degradation of display quality can be suppressed.

[0060] Furthermore, in this embodiment, pixel circuit Pix(i,j) configured as shown in Fig. 6 is driven by first scanning signal SC1(i), second scanning signal SC2(i), first light-emission control signal EM1(i), and second light-emission control signal EM2(i) as shown in Fig. 7, and as a result, it is possible to reduce the voltage amplitude of scanning-side drive signals SC1(i), SC2(i), EM1(i), and EM2(i) for driving pixel circuit 15, compared to pixel circuit 14 (Fig. 4) of the internal compensation type in the second comparative example. This point will be described below with reference to Fig. 12 as well as Figs. 6 and 10.

[0061] 12 shows a timing chart illustrating changes in the scanning drive signals SC1(i), SC2(i), EM1(i), and EM2(i) for driving the pixel circuit Pix(i,j) of the present embodiment shown in FIG. 6 , as well as voltage waveforms representing changes in the voltage at node Ng (node ​​G voltage VnG), the voltage at node Ns (node ​​S voltage VnS), and the voltage at node Na (node ​​A voltage VnA) in the pixel circuit Pix(i,j). Here, node Na refers to a node including the connection point between the coupling capacitor Cc and the write control transistor T2. In the pixel circuit Pix(i,j) of the present embodiment, after the initialization operation and threshold sampling operation, the node A voltage VnA changes from the reference voltage Vref to the data voltage Vdata at time t5 during the write period Tw, and a voltage corresponding to the data voltage Vdata is applied to the source terminal of the drive transistor T4 via the coupling capacitor Cc. As a result, as shown by the dotted line in Figure 10, a current flows through a path from the reference voltage line Vref to the corresponding data signal line Dj via the holding capacitor Cst, the coupling capacitor Cc, and the write control transistor T2, and a voltage corresponding to the data voltage Vdata is subjected to threshold compensation and written to the holding capacitor Cst (see the above-mentioned equation (7)). Therefore, in this embodiment, the node G voltage VnG, the node S voltage VnS, and the node A voltage VnA in the pixel circuit Pix(i,j) change as shown in Figure 12 due to the initialization operation, threshold sampling operation, and data write operation. Note that in Figure 12, the node G voltage VnG is indicated by a thick dotted line, the waveform of the node S voltage VnS is indicated by a thick dashed line, and the waveform of the node A voltage VnA is indicated by a thick solid line.

[0062] As described above, in this embodiment, during the write period Tw, a voltage corresponding to the data voltage Vdata is applied to the source terminal of the drive transistor T4 via the coupling capacitor Cc. Therefore, unlike the second comparative example (FIGS. 4 and 5) in which the data voltage Vdata is applied to the node Ng during the data programming period Tdpg, as shown in FIG. 12, the voltage range VtCR in which threshold compensation is possible and the voltage range VdataR in which the data voltage Vdata can take on overlap, and the maximum value of the value that the node G voltage vnG, the value that the node S voltage VnS, and the value that the node A voltage VnA can take on is Vref and the minimum value is ELVSS. Therefore, in order for the transistors connected to any of the nodes Ng, Ns, and Na, i.e., the first voltage setting transistor T1, the second voltage setting transistor T3, the write control transistor T2, and the light-emission control transistor T6, to operate normally as switching elements, it is necessary to set the H-level voltages and L-level voltages of the scanning-side drive signals SC1(i), SC2(i), EM1(i), and EM2(i), i.e., the gate high voltage VgH and the gate low voltage VgL, so as to satisfy the following equations: VgH>Vref (11) VgL<ELVSS (12)

[0063] For example, if the reference voltage Vref is 5 V, the low-level power supply voltage ELVSS is 0 V, and the range of the data voltage Vdata is 0 to 5 V, it is sufficient to ensure that the amplitude (peak-to-peak value) of the scanning side drive signals SC1(i), SC2(i), EM1(i), and EM2(i) is 5 Vpp or more. Therefore, according to this embodiment, the amplitude of the signal for driving the pixel circuit can be made smaller than in the second comparative example, thereby reducing power consumption.

[0064] In this way, according to the embodiment, even when high-speed driving is performed, threshold compensation can be appropriately performed within pixel circuit 15, and degradation of display quality can be suppressed, without increasing power consumption due to an increase in the amplitude of scanning-side drive signals SC1(i), SC2(i), EM1(i), and EM2(i) for driving pixel circuit 15.

[0065] 2. Second Embodiment A display device that performs pause driving is known as a low-power display device. Pause driving is a driving method in which, when continuously displaying the same image, a drive period (refresh period) and a pause period (non-refresh period) are set, and the drive circuit operates during the drive period and stops operating during the pause period. This method is also called "low-frequency driving." Hereinafter, an organic EL display device that performs pause driving using a pixel circuit having the same configuration as the pixel circuit 15 in the first embodiment will be described as a second embodiment. Note that the configuration and operation of this embodiment that are not newly described below are the same as those of the first embodiment.

[0066] The overall configuration of the display device and the configuration of the pixel circuits in this embodiment are the same as those in the first embodiment (see FIGS. 1 and 6), and the same or corresponding parts are assigned the same reference numerals. The display device 10 in this embodiment has two operating modes: a normal drive mode and a pause drive mode. In the normal drive mode, as in the first embodiment, the display device 10 operates such that refresh frame periods Trf, in which the image data of the display unit 11, i.e., the data voltage in each pixel circuit 15 (more precisely, the holding voltage of the holding capacitor Cst shown in Equation (7)) are successively repeated (see FIG. 2). In the pause drive mode, the display device 10 operates such that a drive period TD consisting only of a refresh frame period (hereinafter also referred to as an "RF frame period") Trf and a pause period TP consisting of a plurality of non-refresh frame periods (hereinafter also referred to as an "NRF frame period") Tnrf, in which the rewriting of the image data of the display unit 11 is stopped, alternate (see FIG. 13, described later).

[0067] In this embodiment, the input signal Sin externally provided to the display control circuit 20 includes an operation mode signal Sm that indicates whether the display unit 11 is to be driven in the normal drive mode or the pause drive mode. This operation mode signal Sm is provided from the display control circuit 20 to the scanning drive circuit 40 as part of the scan-side control signal Scs, and to the data-side drive circuit 30 as part of the data-side control signal Scd. The display control circuit 20 controls the data-side drive circuit 30 and the scanning drive circuit 40 using this operation mode signal Sm. As a result, the first scanning signal lines SC11 to SC1n, the second scanning signal lines SC21 to SC2n, the first light-emission control lines EM11 to EM1n, and the second light-emission control lines EM21 to EM2n are driven so that RF frame periods are continuous in the normal drive mode, and so that drive periods TD and pause periods TP alternate in the pause drive mode.

[0068] FIG. 13 is a timing chart for explaining the general operation in the pause drive mode of this embodiment. As shown in FIG. 13 , in the pause drive mode, a drive period TD consisting of an RF frame period Trf and a pause period TP consisting of multiple NRF frame periods Tnrf are alternately repeated. During the NRF frame period Tnrf, the scan-side drive circuit 40 stops driving the first scan signal lines SC11 to SC1n and the data-side drive circuit 30 stops driving the data signal lines D1 to Dm, and display continues based on the image data written during the RF frame period Trf in the immediately preceding drive period TD. Therefore, the pause drive mode is effective in reducing the power consumption of the display device 10 when displaying a still image. The second scan signal lines SC21 to SC2n, the first light-emission control lines EM11 to EM1n, and the second light-emission control lines EM21 to EM2n are driven during the NRF frame period Tnrf in the same way as during the RF frame period Trf. In this embodiment, the data signals D(1) to D(m) transmitted by the data signal lines D1 to Dm, respectively, are in a high impedance state during the NRF frame period Tnrf.

[0069] Hereinafter, the operation of the pixel circuit 15 shown in FIG. 6 in this embodiment, that is, the pixel circuit Pix(i, j) in the ith row and jth column in this embodiment will be described with reference to FIG. 6 as well as FIG.

[0070] FIG. 14A is a timing chart illustrating the operation of the pixel circuit Pix(i,j) during the non-emission period Tne included in the refresh frame period (RF frame period) Trf. As shown in FIG. 14A , in this embodiment, the scanning drive signals SC1(i), SC2(i), EM1(i), and EM2(i) change during the RF frame period Trf in the same manner as the scanning drive signals SC1(i), SC2(i), EM1(i), and EM2(i) in the first embodiment (see FIG. 7 ). As a result, during the RF frame period Trf, the pixel circuit Pix(i,j) in this embodiment performs an initialization operation (holding an initial hold voltage by the hold capacitor) during the initialization period Ti, a threshold sampling operation during the threshold sampling period Tvhsmp, and a data write operation during the write period Tw, just like the first embodiment. Note that the anode of the organic EL element OL is also initialized during the write period Tw. During the subsequent light-emission period Te, a drive current I1 corresponding to the voltage held in the holding capacitor Cst is supplied to the organic EL element OL via the drive transistor T4, causing the organic EL element OL to emit light. The operations of the pixel circuit Pix(i, j) during the initialization period Ti, threshold sampling period Tvtsmp, writing period Tw, and light-emission period Te are the same as those of the pixel circuit Pix(i, j) in the first embodiment, and therefore will not be described in detail (see FIGS. 8 to 11).

[0071] FIG. 14B is a timing chart illustrating the operation of the pixel circuit Pix(i,j) during the non-emission period Tne included in the non-refresh frame period (NRF frame period) Tnrf. As shown in FIG. 14B and FIG. 13, during the NRF frame period Tnrf, the first scanning signal SC1(i) ​​is maintained at the L level, and the second scanning signal SC2(i), the first light-emission control signal EM1(i), and the second light-emission control signal EM2(i) change in the same manner as during the RF frame period. As a result, during the NRF frame period Tnrf, no initialization operation, threshold sampling operation, or data writing operation is performed, but the anode of the organic EL element OL is initialized during the period corresponding to the writing period Tw in the RF frame period Trf. Hereinafter, this period during the NRF frame period (the period from time t5 to time t6 in FIG. 14B) will be referred to as the "anode initialization period Tai." During this anode initialization period Tai, the state of the pixel circuit Pix(i, j) is the same as that during the writing period Tw in the RF frame period, as shown in FIG. 15, except that the first voltage supply transistor T1 is in an off state, and the anode is initialized by discharging the charge accumulated in the parasitic capacitance of the organic EL element OL via the initialization transistor T7.

[0072] In the subsequent light-emitting period Te, a light-emitting operation similar to that in the light-emitting period Te after the writing period Tw in the RF frame period Trf is performed (see FIGS. 14 and 11).

[0073] According to the present embodiment as described above, power consumption can be reduced by performing pause driving (low frequency driving) while achieving the same effects as in the first embodiment. Note that in this pause driving, a non-emission period Tne is provided in the NRF frame period Tnrf as in the RF frame period Trf, and anode initialization is performed as in the RF frame period Trf, so that still images can be displayed satisfactorily in the pause driving mode.

[0074] In the second embodiment, the first light-emitting control signal EM1(i) and the second light-emitting control signal EM2(i) change during the NRF frame period Tnrf in the same way as during the RF frame period Trf. However, these signals EM1(i) and EM2(i) may also be changed as shown by the dotted lines in (B) of FIG. 14. That is, the level of the first light-emitting control signal EM1(i) may be changed from H level to L level from time 3 to time 4 and maintained at L level from time t0 to time t8, and the level of the second light-emitting control signal EM2(i) may be changed from L level to H level from time 2 to time 8 and maintained at H level during the NRF frame period Tnrf. With this configuration, the first light-emitting control signal EM1(i) and the second light-emitting control signal EM2(i) change less as scanning-side drive signals, thereby further reducing power consumption during pause drive.

[0075] Furthermore, in the second embodiment, the data signal lines D1 to Dm may be driven so that the voltage of the corresponding data signal line Dj of the pixel circuit Pix(i,j) is the reference voltage Vref during the NRF frame period Tnrf. With this configuration, in the pixel circuit Pix(i,j), the node A voltage VnA is the reference voltage Vref regardless of the states of the second scan signal SC2(i) and the first light-emission control signal EM1(i) (see FIG. 6). This stabilizes the voltage of the node Ns connected to the node Na via the coupling capacitor Cc, i.e., the node S voltage VnS. As a result, fluctuations in the drive current I1 due to the on / off operation of the write control transistor T2 and the second voltage-setting transistor T3 are suppressed, stabilizing the light-emitting operation of the organic EL element OL during the NRF frame period Tnrf.

[0076] 3. Third Embodiment Next, a display device according to a third embodiment will be described. Like the second embodiment, the display device according to this embodiment is an organic EL display device that performs pause driving. Its overall configuration and pixel circuit configuration are also similar to those of the second embodiment (see FIGS. 1, 6, and 13), and the same or corresponding parts are designated by the same reference numerals. In the second embodiment, as shown in FIGS. 14A and 14B, anode initialization is performed in the writing period Tw within the RF frame period Trf and the anode initialization period Tai within the NRF frame period Tnrf. In this embodiment, anode initialization is also performed immediately before the initialization period Ti. This embodiment will be described below, focusing on the configuration and operation related to such anode initialization. Note that configurations and operations of this embodiment that are not specifically described below are similar to those of the second embodiment.

[0077] Hereinafter, the operation of the pixel circuit 15 shown in FIG. 6 in this embodiment, that is, the pixel circuit Pix(i,j) in the ith row and jth column in this embodiment will be described with reference to FIG. 6 as well as FIGS.

[0078] 16A is a timing chart for explaining the operation of the pixel circuit Pix(i,j) during the non-emission period Tne included in the RF frame period Trf. As shown in FIG. 16A, in this embodiment, the second scanning signal SC2(i) among the scanning-side drive signals is at the H level not only during the writing period Tw, but also during the period from time t0 to time t1 immediately before the initialization period Ti (hereinafter referred to as the "node S discharge period Tdch"). In other respects, the scanning-side drive signals SC1(i), SC2(i), EM1(i), and EM2(i) during the RF frame period Trf in this embodiment are the same as the scanning-side drive signals SC1(i), SC2(i), EM1(i), and EM2(i) during the RF frame period Trf in the second embodiment.

[0079] In this embodiment, during the RF frame period Trf, in the node S discharge period Tdch immediately before the initialization period Ti, as shown in (A) of FIG. 16, the first scanning signal SC1(i) ​​and the first light-emission control signal EM1(i) are at the L level, and the second scanning signal SC2(i) and the second light-emission control signal EM2(i) are at the H level. Therefore, as shown in FIG. 17, the first voltage setting transistor T1, the second voltage setting transistor T3, and the power supply transistor T5 are in the OFF state, and the write control transistor T2, the light-emission control transistor T6, and the initialization transistor T7 are in the ON state. As a result, during this node S discharge period Tdch, the coupling capacitor Cc is charged by a current flowing from the corresponding data signal line Dj to the initialization voltage line Vini via the coupling capacitor Cc, the light-emission control transistor T6, and the initialization transistor T7, and the charge accumulated in the parasitic capacitance of the organic EL element OL is discharged via the initialization transistor T7. During the initialization period Ti immediately thereafter, the pixel circuit Pix(i,j) is in the state shown in FIG. 8 , similar to the initialization period Ti of the pixel circuit Pix(i,j) in the first and second embodiments. Therefore, in this embodiment, after the node S voltage VnS is set to the initialization voltage Vini by discharging during the node S discharge period Tdch, during the initialization period Ti, the retention capacitor Cst is charged by a current that flows from the reference voltage line Vref through the first voltage setting transistor T1, the retention capacitor Cst, the light-emission control transistor T6, and the organic EL element OL to the low-voltage power line ELVSS. Therefore, at the end point t2 of the initialization period Ti, a voltage greater than the voltage Vref−ELVSS+Vth(led) retained in the retention capacitor at the end point t2 of the initialization period Ti in the first and second embodiments is retained.

[0080] 16B is a timing chart for explaining the operation of the pixel circuit Pix(i,j) during the non-emission period Tne included in the NRF frame period Tnrf. In this embodiment, a node S discharge period Tdch is also provided in the NRF frame period Tnrf, and the same operation as above is performed, but the initialization operation (FIG. 8) is not performed during the NRF frame period Tnrf. Therefore, the operation of the pixel circuit Pix(i,j) during the NRF frame period Tnrf is the same as that of the pixel circuit Pix(i,j) during the NRF frame period Tnrf in the second embodiment.

[0081] As described above, according to this embodiment, by providing the node S discharge period Tdch in the non-emission period Tne included in the RF frame period Trf, a large voltage is held in the holding capacitor Cst by the initialization operation regardless of the threshold voltage Vth(led) of the organic EL element OL, compared to the first and second embodiments, and therefore a sufficient threshold compensation margin can be ensured. Note that, in this embodiment, the node S discharge period Tdch is provided immediately before the initialization period Ti in the RF frame period Trf in the second embodiment, but the node S discharge period Tdch may be provided immediately before the initialization period Ti in the frame period Trf in the first embodiment, and even in such a configuration, the same effect regarding threshold compensation can be obtained.

[0082] 4. Fourth Embodiment Next, a display device according to a fourth embodiment will be described. The overall configuration of the display device and the configuration of the pixel circuits according to this embodiment are the same as those of the first embodiment (see FIGS. 1 and 6), and the same or corresponding parts are designated by the same reference numerals. In the first embodiment, the length of the writing period Tw in each RF frame period Trf is approximately one horizontal period (approximately 1H). During this writing period Tw, the corresponding second scanning signal SC2(i) is at an H level, so that the voltage of the corresponding data signal line Dj is applied to each pixel circuit Pix(i,j) as the data voltage Vdata (see FIGS. 2 and 7). In contrast, in this embodiment, the scanning-side driving circuit 40 is configured so that the length of the writing period Tw in each RF frame period Trf is approximately two horizontal periods (approximately 2H). The following description of this embodiment will focus on the operation of the pixel circuits during such writing period Tw. For ease of explanation, the length of the writing period Tw included in each frame period in this embodiment will be assumed to be 2H. The configuration and operation of this embodiment that are not newly explained below are the same as those of the first embodiment.

[0083] The operation of the pixel circuit 15 shown in FIG. 6 in this embodiment, i.e., the pixel circuit Pix(i,j) in the i-th row and j-th column in this embodiment, will be described below with reference to FIG. 18 as well as FIG. 6. (A) of FIG. 18 is a timing chart for explaining the operation of the pixel circuit Pix(i,j) during the non-emission period Tne included in the RF frame period Trf. (B) of FIG. 18 is a timing chart for explaining the second scanning signals SC2(1) to SC2(n) for sequentially selecting the second scanning signal lines SC21 to SC2n, showing the change in the signal SC2(i) of the corresponding second scanning signal line SC2i together with the changes in the signals SC2(i−1), SC2(i+1), SC2(i+2), and SC2(i+3) of several adjacent second scanning signal lines and the signal D(j) of the corresponding data signal line Dj.

[0084] As shown in FIG. 18A, in this embodiment, the scanning side drive signals SC1(i), SC2(i), EM1(i), and EM2(i) basically change at the same timing as the scanning side drive signals SC1(i), SC2(i), EM1(i), and EM2(i) in the first embodiment (see FIG. 7), but differ from the scanning side drive signals SC1(i), SC2(i), EM1(i), and EM2(i) in the first embodiment in that the length of the writing period Tw is 2H.

[0085] More specifically, in this embodiment, the scanning-side drive circuit 40 sequentially selects the second scanning signal lines SC21 to SC2n for two horizontal periods (2H) in each frame period Trf, overlapping the selected second scanning signal lines SC21 to SC2n by one horizontal period (1H), based on the scanning-side control signal Scs, applies an active signal (H-level voltage) to the selected second scanning signal line SC2k, and applies an inactive signal (L-level voltage) to the unselected scanning signal lines. That is, as shown in FIG. 18B , the second scanning signal lines SC21 to SC2n are driven so that the i-th second scanning signal line SC2i, which is the corresponding second scanning signal line, is in a selected state during the (i-1)-th horizontal period THa and the i-th horizontal period THb, and the selection period T2H of the corresponding second scanning signal line SC2i becomes the writing period Tw of the pixel circuit Pix(i, j). 18B, (p, q) shown in the timing chart of data signal D(j) indicates the data voltage Ddata to be applied to the pixel circuit Pix(p, q) in the pth row and qth column (p=1 to n, q=1 to m). Note that a "horizontal period" is generally a period corresponding to one line of a display image in a video signal based on horizontal scanning and vertical scanning, and in this case corresponds to the period during which image data for one line of a display image (data representing m pixels constituting one line) is output from data-side drive circuit 30 as data signals D(1) to D(m).

[0086] In this embodiment, pixel circuits Pix(i, j) are driven by scanning-side drive signals SC1(i), SC2(i), EM1(i), and EM2(i) shown in Figure 18A, which include the second scanning signal SC2(i) as described above. As a result, during the (i-1)-th horizontal period THa, the (i-1)-th and i-th second scanning signals SC2(i-1), SC2(i) are both active (H level) (see Figure 18B), so that the voltage on the data signal line Dj charges the holding capacitor Cst in the pixel circuit Pix(i-1, j) in the (i-1)-th row and the j-th column, and also charges the holding capacitor Cst in the pixel circuit Pix(i, j) in the i-1-th row and the j-th column. Furthermore, during the ith horizontal period THb, the ith and (i+1)th second scanning signals SC2(i), SC2(i+1) are both active (H level) (see (B) of FIG. 18), so that the voltage of the data signal line Dj charges the holding capacitor Cst in the pixel circuit Pix(i, j) in the ith row and jth column, and also charges the holding capacitor Cst in the pixel circuit Pix(i+1, j) in the (i+1)th row and jth column. Therefore, focusing on the pixel circuit Pix(i,j) in the ith row and jth column, its internal storage capacitor Cst is charged with the data voltage Vdata (hereinafter, referred to as "d(i-1,j)" to be supplied to the pixel circuit Pix(i-1,j) in the i-1th row and jth column during the first half period THa of its write period Tw, i.e., the selection period T2H of the corresponding second scanning signal line SC2i, and with the data voltage Vdata (hereinafter, referred to as "d(i,j)" to be supplied to the pixel circuit Pix(i,j)) during the second half period THb. Here, the data voltages d(i-1,j) and d(i,j) are voltages indicating the gradation values ​​of adjacent pixels, and therefore their voltage values ​​are close. Therefore, a long charging time (2H) is essentially secured for writing the data voltage into the storage capacitor Cst of the pixel circuit Pix(i,j). Therefore, according to this embodiment, it is possible to achieve even higher speed driving while achieving the same effects as the first embodiment.

[0087] In an internal compensation pixel circuit such as pixel circuit 13 in the first comparative example (see FIG. 3), the data voltage Vdata provided from the data signal line is written to the storage capacitor Cst via a diode-connected drive transistor M1. Therefore, when the selection periods of adjacent scanning signal lines are made to partially overlap in order to lengthen the write period Tw, as in the present embodiment, the data voltage Vdata may not be written correctly to the pixel circuit. Therefore, a diode-connected internal compensation pixel circuit such as pixel circuit 13 in the first comparative example cannot be driven at high speed using the driving method of the present embodiment ( FIG. 18 ).

[0088] 5. Fifth Embodiment Next, a display device according to a fifth embodiment will be described. The display device according to this embodiment is an organic EL display device that performs pause driving, and its overall configuration and pixel circuit configuration are basically the same as those of the second embodiment (see FIGS. 1, 6, and 13), and the same or corresponding parts are designated by the same reference numerals. In the first embodiment, in each pixel circuit Pix(i,j), of the scanning drive signals SC1(i), SC2(i), EM1(i), and EM2(i) generated by the scanning drive circuit 40, the first light-emission control signal EM1(i) controls the on / off of the second voltage setting transistor T3 and the power supply transistor T5, and the second light-emission control signal EM2(i) controls the on / off of the light-emission control transistor T6. In contrast, in this embodiment, the scanning-side drive circuit 40 does not generate the second light-emitting control signals EM2(i) to EM2(n), and in each pixel circuit Pix(i,j), the on / off of the light-emitting control transistor T6 is controlled by a first light-emitting control signal EM1(i+X), which is different from the first light-emitting control signal EM1(i) corresponding to that pixel circuit Pix(i,j). Here, X is a positive integer, and the selection of the value of X will be described later. This embodiment will be described below with reference to FIG. 19 as well as FIGS. 1 and 6. Note that the configuration and operation of this embodiment that are not newly described below are the same as those of the second embodiment.

[0089] 19 is a timing chart for explaining driving of the pixel circuit 15 shown in FIG. 6 in this embodiment, i.e., the pixel circuit Pix(i,j) in the i-th row and j-th column, in the pause drive mode. (A) of FIG. 19 shows changes in the scanning drive signals SC1(i), SC2(i), EM1(i), and EM2(i) for driving the pixel circuit Pix(i,j) during a refresh frame period (RF frame period) Trf. (B) of FIG. 19 shows changes in the scanning drive signals SC1(i), SC2(i), EM1(i), and EM2(i) for driving the pixel circuit Pix(i,j) during a non-refresh frame period (NRF frame period) Tnrf.

[0090] 19 , in this embodiment, a first light-emitting control signal EM1(i+X) that is different from the first light-emitting control signal EM1(i) provided from the corresponding first light-emitting control line EM1i (hereinafter referred to as the “corresponding first light-emitting control signal” in the description focusing on the pixel circuit) is used as the second light-emitting control signal EM2(i) to be used in the pixel circuit Pix(i,j). Note that, as will be described later, a positive integer is selected as X, and therefore this first light-emitting control signal EM1(i+X) is the first light-emitting control signal (power supply control line) that follows the corresponding first light-emitting control signal EM1(i), and hereinafter, in the description focusing on the pixel circuit, this first light-emitting control signal EM1(i+X) will be referred to as the “following first light-emitting control signal” or “following power supply control signal.”

[0091] As shown in FIG. 19A , similar to the second embodiment, the non-emission period Tne within each RF frame period Trf for each pixel circuit Pix(i,j) includes an initialization period Ti, a threshold sampling period Tvtsmp, and a writing period Tw. The first light-emission control signal EM1(k) has two periods (hereinafter referred to as “inactive periods”) in which it is in an inactive state (L level) within each RF frame period Trf (k=1 to n). Hereinafter, of these two inactive periods, the earlier inactive period will be referred to as the “leading inactive period Tda1,” and the later inactive period will be referred to as the “following inactive period Tda2.” In this embodiment, the pixel circuit Pix(i,j) operates in the same manner using the following first light-emission control signal EM1(i+X) instead of the second light-emission control signal EM2(i) corresponding to the pixel circuit Pix(i,j). 19A, the value of X is selected as a positive integer so that the preceding inactive period Tda1 in the subsequent first light-emitting control signal EM1(i+X) includes a threshold sampling period Tvhsmp and a writing period Tw, the start time t2 of the preceding inactive period Tda1 in the subsequent first light-emitting control signal EM1(i+X) is later than the time t1 at which the first scanning signal SC1(i) ​​changes from L level to H level, and the end time t8 of the preceding inactive period Tda1 in the subsequent first light-emitting control signal EM1(i+X) is later than the time t7 at which the first scanning signal SC1(i) ​​changes from H level to L level. However, it is assumed that the length of the preceding inactive period Tda1 is set so that such a value of X can be selected.

[0092] 19B , during the NRF frame period Tnrf, the first scanning signal SC1(i) ​​is maintained at the L level, as in the second embodiment, but the other scanning drive signals SC2(i), EM1(i), and EM2(i) = EM1(i+X) change in the same way as during the RF frame period Trf. As a result, the pixel circuit Pix(i,j) in this embodiment operates during the NRF frame period in the same way as in the second embodiment.

[0093] According to the present embodiment as described above, the number of scanning-side drive signals used to drive pixel circuits Pix(i, j) in the first to fourth embodiments is reduced by one, so that it is sufficient to generate three types of signals SC1(i), SC2(i), and EM1(i) as the scanning-side drive signal. This reduces the circuit scale of the scanning-side drive circuit 40 without impairing the effects of the second embodiment, and enables the frame area of ​​the display device to be narrowed.

[0094] 6. Sixth Embodiment Next, a display device according to a sixth embodiment will be described. The overall configuration and pixel circuit configuration of the display device according to this embodiment are basically the same as those of the first embodiment (see FIGS. 1, 2, and 6), and the same or corresponding parts are designated by the same reference numerals. In the first embodiment, a reference voltage line Vref is provided in the display unit 11, and each pixel circuit 15 is supplied with a reference voltage Vref via the reference voltage line Vref. In contrast, in this embodiment, a reference voltage line Vref is not provided, and a high-level power supply voltage ELVDD supplied via a high-voltage side power supply line ELVDD is used as the reference voltage Vref in the first embodiment. Note that configurations and operations of this embodiment that are not newly described below are the same as those of the first embodiment.

[0095] 20 is a circuit diagram showing the configuration of a pixel circuit 16 in this embodiment, more specifically, the configuration of the pixel circuit Pix(i,j) in the ith row and jth column. Comparing FIG. 20 with FIG. 6, this pixel circuit 16 has the same configuration as the pixel circuit 15 in the first embodiment, except that the part of the pixel circuit 15 in the first embodiment that was connected to the reference voltage line Vref is connected to the high-voltage power supply line ELVDD. The pixel circuit 16 in this embodiment, having such a configuration, is driven and operates in the same manner as the first embodiment (see FIG. 7). However, since each pixel circuit 16 is supplied with a high-level power supply voltage ELVDD instead of the reference voltage Vref, the gate-source voltage Vgs of the drive transistor T4 immediately after the writing period Tw is given by the following equation: Vgs={Cc / (Cst+Cc)}(ELVDD-Vdata)+Vth (13) However, as can be seen from FIG. 7 and the above formula, in this embodiment as well, similarly to the first embodiment, the internal compensation and data write operation are performed in a form in which the threshold sampling period Tvtsmp and the write period Tw are separated, and the same effect as in the first embodiment can be obtained.

[0096] 7. Seventh Embodiment Next, a display device according to a seventh embodiment will be described. The display device according to this embodiment is an organic EL display device that performs pause driving, and its configuration is basically the same as that of the second embodiment (see FIGS. 1, 6, and 13), and the same or corresponding parts are designated by the same reference numerals. In the first and second embodiments, in each pixel circuit Pix(i,j), the on / off of the write control transistor T2 and the initialization transistor T7 is controlled by the second scanning signal SC2(i) of the scanning-side driving signals SC1(i), SC2(i), EM1(i), and EM2(i) generated by the scanning-side driving circuit 40. In contrast to this, in this embodiment, the scanning side drive circuit 40 generates a third scanning signal SC3(i) in addition to the scanning side drive signals SC1(i), SC2(i), EM1(i), and EM2(i), and in each pixel circuit Pix(i, j), the on / off of the initialization transistor T7 is controlled by the third scanning signal SC3(i) rather than the second scanning signal SC2(i).

[0097] FIG. 21 is a block diagram showing the overall configuration of this embodiment, and FIG. 22 is a circuit diagram showing the configuration of a pixel circuit 15 in a display device 10 according to this embodiment. As shown in FIG. 21 , in this embodiment, unlike the first embodiment (see FIG. 1 ), the scanning-side driving circuit 40 outputs third scanning signals SC3(1) to SC3(n), and third scanning signal lines SC31 to SC3n are arranged in the display unit 11 as signal lines for transmitting these third scanning signals SC3(1) to SC3(n) to the pixel circuits 15. Also, as shown in FIG. 22 , the pixel circuit 15 in the i-th row and j-th column of this embodiment, i.e., pixel circuit Pix(i,j), is connected to the i-th third scanning signal line SC3i. This embodiment will be described below with reference to FIGS. 21 and 22 as well as FIG. 23 (described later). Note that configurations and operations of this embodiment that are not specifically described below are similar to those of the second embodiment.

[0098] As can be seen by comparing Fig. 22 with Fig. 6, in the pixel circuit Pix(i,j) in the i-th row and j-th column of this embodiment, the i-th third scanning signal line SC3i as the corresponding third scanning signal line SC3i is connected to the gate terminal of the initialization transistor T7, which differs in this respect from the pixel circuit Pix(i,j) in the first embodiment in which the corresponding second scanning signal line SC2i is connected to the gate terminal of the initialization transistor T7. Except for this point, the pixel circuit 15 in this embodiment has the same configuration as the pixel circuit 15 in the first and second embodiments (Fig. 6). The operation of the pixel circuit 15 in this embodiment shown in Fig. 22, i.e., the pixel circuit Pix(i,j) in the i-th row and j-th column of this embodiment, will be described below with reference to Fig. 22 and Fig. 23.

[0099] 23A is a timing chart illustrating the operation of the pixel circuit Pix(i,j) during the non-emission period Tne included in the refresh frame period (RF frame period) Trf. As shown in FIG. 23A, during the RF frame period Trf, the scanning drive signals SC1(i), SC2(i), EM1(i), and EM2(i) other than the third scanning signal SC3(i) change in the same manner as the scanning drive signals SC1(i), SC2(i), EM1(i), and EM2(i) in the first and second embodiments (see FIGS. 7 and 14). As a result, during the RF frame period Trf, the pixel circuit Pix(i,j) in this embodiment performs an initialization operation (holding an initial hold voltage by the hold capacitor) during the initialization period Ti, a threshold sampling operation during the threshold sampling period Tvhsmp, and a data write operation during the write period Tw, similar to the first and second embodiments. During the subsequent light-emission period Te, a drive current I1 corresponding to the voltage held in the holding capacitor Cst is supplied to the organic EL element OL via the drive transistor T4, causing the organic EL element OL to emit light. The operations of the pixel circuit Pix(i, j) during the initialization period Ti, threshold sampling period Tvtsmp, writing period Tw, and light-emission period Te are similar to the operations of the pixel circuit Pix(i, j) during the RF frame Trf in the first and second embodiments, and therefore will not be described in detail (see FIGS. 8 to 11).

[0100] In this embodiment, the third scanning signal line SC3i is connected to the gate terminal of the initialization transistor T7 instead of the second scanning signal line SC2i. Therefore, unlike the first and second embodiments in which the anode of the organic EL element is initialized during the writing period Tw (hereinafter simply referred to as "anode initialization"), anode initialization can be performed during any period of the non-emission period Tne within each frame period. In the example shown in Figure 23, the corresponding third scanning signal SC3(i) is at an H level during the period t0 to t1 immediately before the initialization period Ti, and anode initialization is performed during this period t0 to t1. Hereinafter, in this embodiment, the period during which such corresponding third scanning signal SC3(i) is at an H level (the period t0 to t1 in Figure 23) will be referred to as the "anode initialization period Tai."

[0101] 23B is a timing chart illustrating the operation of the pixel circuit Pix(i,j) during the non-light-emitting period Tne included in the non-refresh frame period (NRF frame period) Tnrf. As shown in FIG. 23B, during the NRF frame period Tnrf, not only the first scanning signal SC1(i) ​​but also the second scanning signal SC2(i) are maintained at the L level, and the third scanning signal SC3(i), the first light-emitting control signal EM1(i), and the second light-emitting control signal EM2(i) change in the same manner as during the RF frame period. As a result, no initialization operation, threshold sampling operation, or data writing operation is performed during the NRF frame period Tnrf. However, similar to the RF frame period Trf, anode initialization is performed during the period when the corresponding third scanning signal SC3(i) is at the H level (period t0-t1 in FIG. 23 ). (Hereinafter, the period when the corresponding third scanning signal SC3(i) is at the H level during the non-light-emitting period Tne within the NRF frame period will also be referred to as the "anode initialization period Tai.")

[0102] According to the present embodiment as described above, in each pixel circuit Pix(i,j), the second scanning signal SC2(i) controls only the on / off of the write control transistor T2, and the on / off of the initialization transistor T7 is controlled by the third scanning signal SC3(i). Therefore, compared to the first and second embodiments in which the second scanning signal SC2(i) controls the on / off of both the write control transistor T2 and the initialization transistor T7, the load on the second scanning signal line SC2i is reduced. Therefore, according to the present embodiment, it is possible to achieve the same effects as the first and second embodiments while further increasing the driving speed of the pixel circuit.

[0103] As shown by the solid lines in Fig. 23B, the first light-emission control signal EM1(i) and the second light-emission control signal EM2(i) change in the NRF frame period Tnrf in the same way as in the RF frame period Trf, but these signals EM1(i) and EM2(i) may also be changed as shown by the dotted lines in Fig. 23B. With this configuration, there is less change in the first light-emission control signal EM1(i) and the second light-emission control signal EM2(i) as scanning-side drive signals, further reducing power consumption in pause drive.

[0104] 8. Eighth Embodiment Next, a display device according to an eighth embodiment will be described. The display device according to this embodiment is an organic EL display device that performs pause driving. The overall configuration and pixel circuit configuration are basically the same as those of the seventh embodiment (see FIGS. 21, 22, and 13), and the same or corresponding parts are designated by the same reference numerals. In each pixel circuit Pix(i,j), in the seventh embodiment, the on / off state of the initialization transistor T7 is controlled by a third scanning signal SC3(i), and the on / off state of the second voltage setting transistor T3 is controlled by a first light-emission control signal EM1(i). However, in this embodiment, the on / off state of both the initialization transistor T7 and the second voltage setting transistor T3 is controlled by a third scanning signal SC3(i). This embodiment will be described below with reference to FIGS. 24 and 25 as well as FIG. 21. Note that the configuration and operation of this embodiment that are not specifically described below are the same as those of the seventh embodiment.

[0105] Fig. 24 is a circuit diagram showing the configuration of a pixel circuit 15 in this embodiment, more specifically the configuration of the pixel circuit Pix(i,j) in the ith row and jth column. As can be seen by comparing Fig. 24 with Fig. 22 , in the pixel circuit Pix(i,j) in this embodiment, the ith third scanning signal line SC3i is connected not only to the gate terminal of the initialization transistor T7 but also to the gate terminal of the second voltage setting transistor T3, unlike in the seventh embodiment. Except for this point, the pixel circuit Oix(i,j) in this embodiment has the same configuration as the pixel circuit Pix(i,j) in the seventh embodiment.

[0106] 25A is a timing chart illustrating the operation of the pixel circuit Pix(i,j) during the non-emission period Tne included in the refresh frame period (RF frame period) Trf. As shown in FIG. 25A, during the RF frame period Trf, the scanning drive signals SC1(i), SC2(i), EM1(i), and EM2(i) other than the third scanning signal SC3(i) change in the same manner as the scanning drive signals SC1(i), SC2(i), EM1(i), and EM2(i) in the first and second embodiments (see FIGS. 7 and 14). In this embodiment, the third scanning signal SC3(i) must be maintained in the H state during the anode initialization period (period t0 to t1 shown in FIG. 25) to turn on the initialization transistor T7, and must also be maintained in the H state during the threshold sampling period Tvtsmp (period t3 to t4 shown in FIG. 25) to turn on the second voltage setting transistor T3. In the example shown in Figure 25, the third scanning signal SC3(i) is generated by the scanning side drive circuit 40, maintaining an H level from the start time t0 of the anode initialization period Tai to the end time t4 of the threshold sampling period Tvtsmp and being at an L level during other periods.

[0107] In this embodiment, the pixel circuit Pix(i,j) performs an initialization operation (holding an initial hold voltage by the hold capacitor) during the initialization period Ti, a threshold value sampling operation during the threshold value sampling period Tvhsmp, and a data writing operation during the write period Tw in the RF frame period Trf, similarly to the first, second, and seventh embodiments, using the scanning-side drive signals SC1(i), SC2(i), SC3(i), EM1(i), and EM2(i) including the third scanning signal SC3(i). During the subsequent light-emission period Te, a drive current I1 corresponding to the voltage held in the hold capacitor Cst is supplied to the organic EL element OL via the drive transistor T4, causing the organic EL element OL to emit light. The operation of the pixel circuit Pix(i, j) during the initialization period Ti, threshold sampling period Tvtsmp, writing period Tw, and light-emission period Te is substantially similar to the operation of the pixel circuit Pix(i, j) during the RF frame Trf in the first and second embodiments and the seventh embodiment, and therefore a detailed description thereof will be omitted (see FIGS. 8 to 11 ). However, as shown in FIG. 25A , during the light-emission period Te, the third scanning signal SC3(i) is at an L level, and therefore the second voltage-setting transistor T3 is in an off state. In this respect, the state of the pixel circuit Pix(i, j) in this embodiment differs from the state of the pixel circuit Pix(i, j) in the first and second embodiments and the seventh embodiment ( FIG. 11 ). However, at the start point 8 of this light-emitting period Te, the first scanning signal SC1(i) ​​is at L level and the first voltage setting transistor T1 is in the off state, so the threshold compensation data voltage that was written and held in the holding capacitor Cst during the writing period Tw is applied between the gate and source of the drive transistor T4 during the light-emitting period Te. In this embodiment, since the third scanning signal SC3(i) is at H level during the period t0 to t4 in the non-emission period Tne, this period t0 to t4 is the anode initialization period Tai.

[0108] 25B is a timing chart illustrating the operation of the pixel circuit Pix(i,j) during the non-light-emitting period Tne included in the non-refresh frame period (NRF frame period) Tnrf. As shown in FIG. 25B, during the NRF frame period Tnrf, not only the first scanning signal SC1(i) ​​but also the second scanning signal SC2(i) are maintained at the L level, and the third scanning signal SC3(i), the first light-emitting control signal EM1(i), and the second light-emitting control signal EM2(i) change in the same manner as during the RF frame period. As a result, no initialization operation, threshold sampling operation, or data writing operation is performed during the NRF frame period Tnrf. However, similar to the RF frame period Trf, anode initialization is performed during the period (period t0 to t4 in FIG. 25) during which the corresponding third scanning signal SC3(i) is at the H level. (Hereinafter, the period during which the corresponding third scanning signal SC3(i) is at the H level during the non-light-emitting period Tne within the NRF frame period will also be referred to as the "anode initialization period Tai.") Furthermore, if at least the first scanning signal SC1(i) ​​is maintained at the L level during the NRF frame period Tnrf, the threshold compensation data voltage that was written to and held in the holding capacitor Cst during the write period Tw in the immediately preceding RF frame period is applied between the gate and source of the driving transistor T4 during the NRF frame period Tnrf.

[0109] According to the present embodiment as described above, similarly to the seventh embodiment, the second scanning signal SC2(i) controls only the on / off of the write control transistor T2 in each pixel circuit Pix(i, j), and therefore it is possible to achieve the same effects as the first and second embodiments while further increasing the driving speed of the pixel circuits.

[0110] As shown by the solid lines in Figure 25(B), the first light-emitting control signal EM1(i) and the second light-emitting control signal EM2(i) change during the NRF frame period Tnrf in the same way as they do during the RF frame period Trf, but in order to further reduce power consumption during pause driving, these signals EM1(i) and EM2(i) may be changed as shown by the dotted lines in Figure 25(B).

[0111] 9. Others The present invention is not limited to the above-described embodiments and modifications, and various modifications can be made without departing from the scope of the present invention.

[0112] For example, in the pixel circuit Pix(i, j) in each of the above embodiments, the first voltage-setting transistor T1, the write control transistor T2, the second voltage-setting transistor T3, the power supply transistor T5, the light-emission control transistor T6, and the initialization transistor T7, which function as switching elements, are all N-channel transistors, but some or all of these may be P-channel transistors. However, the write control transistor T2 and the initialization transistor T7 are transistors of the same conductivity type, and the second voltage-setting transistor T3 and the power supply transistor T5 are also transistors of the same conductivity type. Furthermore, in the above fifth embodiment, the power supply transistor T5 and the light-emission control transistor T6 are also transistors of the same conductivity type.

[0113] Furthermore, although the pixel circuit Pix(i, j) in each of the above embodiments is an internal compensation pixel circuit (see FIGS. 6 , 20 , 22 , and 24 ), it does not employ a configuration in which the data voltage Vdata provided from the data signal line is written to the storage capacitor Cst via the diode-connected drive transistor M1, as in the internal compensation pixel circuit 13 in the first comparative example (see FIG. 3 ). For this reason, as in the fourth embodiment, during the RF frame period Trf, the second scanning signal lines SC21 to SC2n connected to the gate terminals of the write control transistors T2 in the pixel circuits Pix(1, j) to Pix(n, j) (1≦j≦m) are driven so that the selection periods of two adjacent second scanning signal lines SC2k-1, SC2k (the H-level periods of two second scanning signals SC2(k−1), SC2(k)) partially overlap, thereby enabling high-speed driving while substantially ensuring a long charging time for writing the data voltage to each pixel circuit Pix(i, j) (see FIG. 18 ). However, the number of second scanning signal lines whose selection periods should overlap in order to substantially secure a long charging time for writing the data voltage is not limited to two, and the second scanning signal lines SC21 to SC2n may be driven so that the selection periods of three or more adjacent second scanning signal lines partially overlap.

[0114] For example, when the second scanning signal lines SC21 to SC2n are driven so that the selection periods of three adjacent second scanning signal lines SC2k-1, SC2k, and SC2k+1 partially overlap, the length of the write period Tw in the RF frame period is set to three horizontal periods (3H periods), and as shown in FIG. 26, the second scanning signals SC2(1) to SC2(n) may be generated by the scanning-side drive circuit 40 so that the H-level periods of two second scanning signals SC2(k-1), SC2(k) to be applied to adjacent second scanning signal lines SC2k-1, SC2k (k = . . . , i, i+1, i+2, i+3, i+4, . . ) overlap by two horizontal periods (2H periods), and the second scanning signals SC2(1) to SC2(n) sequentially go to the H level for three horizontal periods (3H periods) at a time. Furthermore, when the second scanning signal lines SC21 to SC2n are driven so that the selection periods of four adjacent second scanning signal lines SC2k-1, SC2k, SC2k+1, and SC2k+2 partially overlap, the length of the write period Tw in the RF frame period is set to four horizontal periods (4H periods), and the second scanning signals SC2(1) to SC2(n) may be generated by the scanning-side drive circuit 40 so that the H-level periods of the two second scanning signals SC2(k-1), SC2(k) to be applied to the adjacent second scanning signal lines SC2k-1, SC2k, respectively, overlap by three horizontal periods (3H periods), and the second scanning signals SC2(1) to SC2(n) sequentially go to H level for four horizontal periods (4H periods) at a time, as shown in FIG.

[0115] In the pixel circuit Pix(i,j) in the first to sixth embodiments, the period during which the second scanning signal SC2(i) is at H level within the non-light-emitting period Tne is the anode initialization period Tai during which the initialization transistor T7 is turned on. Furthermore, in the pixel circuit Pix(i,j) in the seventh and eighth embodiments, the period during which the third scanning signal line SC3(i) is at H level within the non-light-emitting period Tne is the anode initialization period Tai during which the initialization transistor T7 is turned on. However, the anode initialization period Tai is not limited to these periods, and the anode initialization period Tai may be set by turning on the initialization transistor T7 during any period included in the non-light-emitting period Tne of the pixel circuit Pix(i,j).

[0116] Furthermore, in the pixel circuits Pix(i,j) in the first to sixth embodiments, the on / off (switching operation) of the second voltage setting transistor T3 is controlled by a first light-emitting control signal EM1(i) serving as a power supply control signal, and the on / off of the initialization transistor T7 is controlled by a second scanning signal SC2(i). Alternatively, in the pixel circuits Pix(i,j) in the first to sixth embodiments, the on / off of the initialization transistor T7 may be controlled by a third scanning signal SC3(i) as in the seventh embodiment (see FIG. 22), or the on / off of the initialization transistor T7 and the second voltage setting transistor T3 may be controlled by a third scanning signal SC3(i) as in the eighth embodiment (see FIG. 24).

[0117] Furthermore, in the first to eighth embodiments, the display unit 10 is provided with a reference voltage line Vref for supplying one reference voltage Vref, and in each pixel circuit Pix(i, j), the conduction terminals (source terminals or drain terminals) of the first voltage setting transistor T1 and the second voltage setting transistor T3 are both connected to the reference voltage line Vref. However, instead of this, a first reference voltage line (denoted by the symbol "Vref1" like the first reference voltage) and a second reference voltage line (denoted by the symbol "Vref2" like the second reference voltage) for supplying two reference voltages Vref1, Vref2 (hereinafter referred to as the "first reference voltage Vref1" and the "second reference voltage Vref2"), which are different fixed voltages, respectively, may be provided in the display unit 10, and the conduction terminals of the first voltage setting transistor T1 and the second voltage setting transistor T3 may be connected to the first reference voltage line Vref1 and the second reference voltage line Vref2, respectively, so that the gate terminal of the drive transistor T4 is connected to the first reference voltage line Vref1 via the first voltage setting transistor T1, and the source terminal of the drive transistor T4 is connected to the second reference voltage line Vref2 via the coupling capacitor Cc and the second voltage setting transistor T3. For example, by modifying the pixel circuit Pix(i,j) (FIG. 6) in the first embodiment in this way, a pixel circuit Pix(i,j) having the configuration shown in FIG. 28 can be obtained. With this configuration, the operating margin for detecting the threshold voltage Vth in the threshold sampling period Tvtsmp can be adjusted by setting the first reference voltage Vref1, and the magnitude of the data voltage to be written in the write period Tw can be adjusted by setting the second reference voltage Vref2. This makes it possible to increase the operating margin of the pixel circuit Pix(i,j) overall.

[0118] Furthermore, any of the first to eighth embodiments and their modifications may be combined within the scope of the present invention and technically compatible therewith.

[0119] While the embodiments and their modifications have been described above using an organic EL display device as an example, the present invention is not limited to organic EL display devices and can be applied to any internal compensation display device that uses a current-driven display element. Display elements that can be used here are display elements whose brightness or transmittance is controlled by a current, and examples of such display elements include organic EL elements, i.e., organic light-emitting diodes (OLEDs), inorganic light-emitting diodes, quantum dot light-emitting diodes (QLEDs), and the like.

[0120] DESCRIPTION OF SYMBOLS 10...organic EL display device 11...display unit 15, 16...pixel circuit 20...display control circuit 30...data side drive circuit (data signal line drive circuit) 40...scanning side drive circuit (scanning signal line drive / light emitting control circuit) Pix(i, j)...pixel circuit (i=1 to n, j=1 to m) Dj...data signal line (j=1 to m) SC1i...first scan signal line (i=1 to n) SC2i...second scan signal line (i=1 to n) EM1i...first light emitting control line (power supply control line) (i=1 to n) EM2i...second light emitting control line (light emitting control line) (i=1 to n) ELVDD...high voltage side power supply line, high level power supply voltage ELVSS...low voltage side power supply line, low level power supply voltage Vini...initialization voltage line, initialization voltage Vref...reference voltage line, reference voltage VnG...node G voltage VnS...node S voltage VnA...node A voltage T1...first voltage setting transistor T2...write control transistor T3...second voltage setting transistor T4...drive transistor T5...power supply transistor T6...light emission control transistor T7...initialization transistor OL...organic EL element (display element) Cst...hold capacitor Cc...coupling capacitor Ti...initialization period Tvtsmp...threshold sampling period Tw...write period

Claims

1. A pixel circuit included in a display unit provided in a display device, comprising: a display element driven by current; an N-channel drive transistor; a write control transistor as a switching element; a first voltage setting transistor as a switching element; a second voltage setting transistor as a switching element; a holding capacitor; and a coupling capacitor, wherein the display unit further includes a high-voltage side power line, a low-voltage side power line, and at least one reference voltage line for supplying at least one reference voltage which is a predetermined fixed voltage, the drive transistor has a drain terminal connected to the high-voltage side power line, a source terminal connected to the display element, and a gate terminal connected to one of the at least one reference voltage lines via the first voltage setting transistor, the holding capacitor has a first terminal connected to the gate terminal of the drive transistor and a second terminal connected to the source terminal of the drive transistor, the coupling capacitor has a first terminal connected to the second terminal of the holding capacitor, and a second terminal which receives a data voltage to be applied to the pixel circuit via the write control transistor and is connected to the one reference voltage line or another reference voltage line of the at least one reference voltage lines via the second voltage setting transistor, and the display element has a first terminal connected to the source terminal of the drive transistor and a second terminal connected to the low-voltage side power line.

2. The pixel circuit according to claim 1, further comprising a power supply transistor as a switching element and a light emission control transistor as a switching element, wherein the drain terminal of the drive transistor is connected to the high-voltage side power line via the power supply transistor, the source terminal of the drive transistor is connected to the display element via the light emission control transistor, and the first terminal of the display element is connected to the source terminal of the drive transistor via the light emission control transistor.

3. The display unit further includes a plurality of data signal lines, a plurality of first scanning signal lines, a plurality of second scanning signal lines, a plurality of power supply control lines, and a plurality of light emission control lines. The first voltage setting transistor has a gate terminal connected to one of the plurality of first scanning signal lines. The writing control transistor has a gate terminal connected to one of the plurality of second scanning signal lines. The power supply transistor has a gate terminal connected to one of the plurality of power supply control lines. The light emission control transistor has a gate terminal connected to one of the plurality of light emission control lines. The second terminal of the coupling capacitor is connected to one of the plurality of data signal lines via the writing control transistor. The pixel circuit according to claim 2.

4. The display unit further includes a plurality of data signal lines, a plurality of first scanning signal lines, a plurality of second scanning signal lines, and a plurality of power supply control lines. The first voltage setting transistor has a gate terminal connected to one of the plurality of first scanning signal lines. The writing control transistor has a gate terminal connected to one of the plurality of second scanning signal lines. The power supply transistor has a gate terminal connected to one of the plurality of power supply control lines. The light emission control transistor has a gate terminal connected to a predetermined power supply control line that transmits a signal with a phase delay compared to the signal of the one power supply control line among the plurality of power supply control signals. The pixel circuit according to claim 2.

5. The conductivity type of the second voltage setting transistor is the same as that of the power supply transistor. The second voltage setting transistor has a gate terminal connected to the one power supply control line. The pixel circuit according to claim 3 or 4.

6. The display unit further includes a plurality of third scanning signal lines. The second voltage setting transistor has a gate terminal connected to one of the plurality of third scanning signal lines. The pixel circuit according to claim 3 or 4.

7. The pixel circuit according to any one of claims 2 to 6, further comprising an initialization transistor as a switching element, wherein the display unit further includes an initialization voltage line for supplying a predetermined fixed voltage as an initialization voltage, and the first terminal of the display element is connected to the initialization voltage line via the initialization transistor.

8. The pixel circuit according to any one of claims 1 to 6, wherein the high-voltage side power supply line also serves as the one reference voltage line or the other reference voltage line.

9. The pixel circuit according to any one of claims 2 to 8, wherein the conductivity types of the first voltage setting transistor, the two-voltage setting transistor, the writing control transistor, the power supply transistor, and the light emission control transistor are all N-channel types.

10. A display unit including a plurality of pixel circuits, a high-voltage side power supply line, a low-voltage side power supply line, and at least one reference voltage line for supplying at least one reference voltage which is a predetermined fixed voltage, and a driving circuit for driving the plurality of pixel circuits, wherein each of the plurality of pixel circuits includes a display element driven by current, an N-channel driving transistor, a write control transistor as a switching element, a first voltage setting transistor as a switching element, a second voltage setting transistor as a switching element, a holding capacitor, and a coupling capacitor, the driving transistor has a drain terminal connected to the high-voltage side power supply line, a source terminal connected to the display element, and a gate terminal connected to one of the at least one reference voltage lines via the first voltage setting transistor, the holding capacitor has a first terminal connected to the gate terminal of the driving transistor and a second terminal connected to the source terminal of the driving transistor, the coupling capacitor has a first terminal connected to the second terminal of the holding capacitor and a second terminal that receives a data voltage to be applied to the pixel circuit via the write control transistor and is connected to the one reference voltage line or another reference voltage line of the at least one reference voltage lines via the second voltage setting transistor, the display element has a first terminal connected to the source terminal of the driving transistor and a second terminal connected to the low-voltage side power supply line, for each of the plurality of pixel circuits, an initialization period, a threshold voltage sampling period, a writing period, and a light-emitting period are provided in order, and the driving circuit includes: during the initialization period, a voltage higher than the threshold voltage of the driving transistor is held in the holding capacitor as an initial holding voltage; during the threshold sampling period, the voltage held in the holding capacitor changes from the initial holding voltage toward the threshold voltage of the driving transistor.During the writing period, the voltage of the second terminal of the coupling capacitor changes from the reference voltage supplied by the reference voltage line connected to the second terminal of the coupling capacitor via the second voltage setting transistor among the one reference voltage line or the other reference voltage line to the data voltage, so that the voltage held in the holding capacitor changes to a threshold compensation data voltage which is a voltage corresponding to the data voltage subjected to threshold compensation of the driving transistor. During the light emitting period, a driving current corresponding to the threshold compensation data voltage held in the holding capacitor is supplied from the high voltage side power supply line to the display element via the driving transistor. A display device that controls the switching operations of the first voltage setting transistor, the second voltage setting transistor, and the writing control transistor.

11. Each of the plurality of pixel circuits further includes a power supply transistor as a switching element and a light emission control transistor as a switching element. The drain terminal of the drive transistor is connected to the high-voltage side power line via the power supply transistor, and the source terminal of the drive transistor is connected to the display element via the light emission control transistor. The first terminal of the display element is connected to the source terminal of the drive transistor via the light emission control transistor. The drive circuit is configured such that: during the initialization period, a voltage greater than the threshold voltage of the drive transistor is held in the holding capacitor as an initial holding voltage; during the threshold sampling period, the initial holding voltage held in the holding capacitor changes from the initial holding voltage toward the threshold voltage of the drive transistor; during the writing period, the voltage of the second terminal of the coupling capacitor switches from the reference voltage supplied by the reference voltage line connected to the second terminal of the coupling capacitor via the second voltage setting transistor among the one reference voltage line or the other reference voltage line to the data voltage, so that the voltage held in the holding capacitor changes to a threshold compensation data voltage corresponding to the data voltage subjected to threshold compensation of the drive transistor; during the light emission period, a drive current corresponding to the threshold compensation data voltage held in the holding capacitor is supplied from the high-voltage side power line to the display element via the drive transistor. The display device according to claim 10, further controlling the switching operations of the power supply transistor and the light emission control transistor in addition to the switching operations of the first voltage setting transistor, the second voltage setting transistor, and the writing control transistor.

12. The drive circuit drives the plurality of pixel circuits such that, in each of the plurality of pixel circuits, during the initialization period, the first voltage setting transistor and the light emission control transistor are in an on state and the power supply transistor is in an off state; during the threshold sampling period, the first voltage setting transistor, the second voltage setting transistor, and the power supply transistor are in an on state and the light emission control transistor and the writing control transistor are in an off state; during the writing period, the first voltage setting transistor and the writing control transistor are in an on state and the second voltage setting transistor, the power supply transistor, and the light emission control transistor are in an off state; and during the light emission period, the power supply transistor and the light emission control transistor are in an on state and the first voltage setting transistor and the writing control transistor are in an off state. The display device according to claim 11.

13. The display unit further includes a plurality of data signal lines, a plurality of first scanning signal lines, a plurality of second scanning signal lines, a plurality of power supply control lines, and a plurality of light emission control lines. The first voltage setting transistor has a gate terminal connected to one of the plurality of first scanning signal lines. The writing control transistor has a gate terminal connected to one of the plurality of second scanning signal lines. The power supply transistor has a gate terminal connected to one of the plurality of power supply control lines. The light emission control transistor has a gate terminal connected to the one light emission control line. The second terminal of the coupling capacitor is connected to one of the plurality of data signal lines via the writing control transistor. The driving circuit controls the switching operations of the first voltage setting transistor, the writing control transistor, the power supply transistor, and the light emission control transistor in each of the plurality of pixel circuits by driving the plurality of first scanning signal lines, the plurality of second scanning signal lines, the plurality of power supply control lines, and the plurality of light emission control lines, and supplies the data voltage to each of the plurality of pixel circuits by driving the plurality of data signal lines in conjunction with the driving of the plurality of second scanning signal lines. The display device according to claim 12.

14. The display unit further includes a plurality of data signal lines, a plurality of first scanning signal lines, a plurality of second scanning signal lines, and a plurality of power supply control lines. The first voltage setting transistor has a gate terminal connected to one of the plurality of first scanning signal lines. The writing control transistor has a gate terminal connected to one of the plurality of second scanning signal lines. The power supply transistor has a gate terminal connected to one of the plurality of power supply control lines. The light emission control transistor has a gate terminal connected to a predetermined subsequent power supply control line. The driving circuit selectively drives the plurality of first scanning signal lines and selectively drives the plurality of second scanning signal lines, and selectively deactivates the plurality of power supply control lines. The predetermined subsequent power supply control line is one of the power supply control lines that becomes deactivated after the one power supply control line among the plurality of power supply control lines, changes from an activated state to a deactivated state after the start point of the selection period of the one first scanning signal line, is in a deactivated state during the threshold sampling period and the writing period, and changes from a deactivated state to an activated state after the end point of the selection period of the one first scanning signal line. The second terminal of the coupling capacitor is connected to one of the plurality of data signal lines via the writing control transistor. The driving circuit controls the switching operations of the first voltage setting transistor, the writing control transistor, the power supply transistor, and the light emission control transistor in each of the plurality of pixel circuits by driving the plurality of first scanning signal lines, the plurality of second scanning signal lines, the plurality of power supply control lines, and the plurality of light emission control lines, and supplies the data voltage to each of the plurality of pixel circuits by driving the plurality of data signal lines in conjunction with the driving of the plurality of second scanning signal lines. The display device according to claim 12.

15. The conductivity type of the second voltage setting transistor is the same as that of the power supply transistor. The second voltage setting transistor has a gate terminal connected to the one power supply control line. The driving circuit controls the switching operation of the second voltage setting transistor in each of the plurality of pixel circuits by driving the plurality of power supply control lines. The display device according to claim 13 or 14.

16. The display unit further includes a plurality of third scanning signal lines. The second voltage setting transistor has a gate terminal connected to one of the plurality of third scanning signal lines. The driving circuit controls the switching operation of the second voltage setting transistor in each of the plurality of pixel circuits by driving the plurality of third scanning signal lines. The display device according to claim 13 or 14.

17. The driving circuit drives the plurality of second scanning signal lines such that the selection periods of two or more second scanning signal lines adjacent to each other in the scanning order of the plurality of second scanning signal lines partially overlap with each other. In each of the plurality of pixel circuits, the selection period of the one second scanning signal line connected to the gate terminal of the writing control transistor is the writing period. The display device according to claim 13 or 14.

18. The high-voltage side power line also serves as the one reference voltage line or the other reference voltage line. The display device according to any one of claims 10 to 17.

19. The display unit further includes an initialization voltage line for supplying a predetermined fixed voltage as an initialization voltage. Each of the plurality of pixel circuits further includes an initialization transistor as a switching element. The first terminal of the display element is connected to the initialization voltage line via the initialization transistor. The driving circuit controls the initialization transistor such that the initialization transistor is in an on state during any period other than the light emission period and is in an off state during the light emission period. The display device according to any one of claims 11 to 17.

20. The driving circuit controls the initialization transistor and the light emission control transistor such that the initialization transistor and the light emission control transistor are in an on state during a predetermined period immediately before the initialization period. The display device according to claim 19.

21. The display control circuit further controls the drive circuit such that a drive period consisting of one or more refresh frame periods for writing data based on the data voltage to the plurality of pixel circuits and a pause period consisting of one or more non-refresh frame periods for stopping the data writing to the plurality of pixel circuits appear alternately. The display control circuit includes, in each refresh frame period, the initialization period, the threshold voltage sampling period, the writing period, and the light emission period, and in each non-refresh frame period, controls the drive circuit such that none of the initialization period, the threshold voltage sampling period, and the writing period is included and the light emission period is included. The display device according to any one of claims 10 to 18.

22. The display unit further includes an initialization voltage line for supplying a predetermined fixed voltage as an initialization voltage. Each of the plurality of pixel circuits further includes an initialization transistor as a switching element. The first terminal of the display element is connected to the initialization voltage line via the initialization transistor. The display control circuit controls the drive circuit such that the initialization transistor is in an on state in any period other than the light emission period and in an off state during the light emission period in both the refresh frame period and the non-refresh frame period. The display device according to claim 21.

23. A method for driving a pixel circuit included in a display unit provided in a display device, wherein the display unit further includes a high-voltage side power supply line, a low-voltage side power supply line, and a reference voltage line for supplying a predetermined fixed voltage as a reference voltage; the pixel circuit includes a display element driven by a current, an N-channel type driving transistor connected in series with the display element, a holding capacitor, and a coupling capacitor; the holding capacitor has a first terminal connected to a gate terminal of the driving transistor and a second terminal connected to a source terminal of the driving transistor; the coupling capacitor has a first terminal connected to the second terminal of the holding capacitor and a second terminal; for the pixel circuit, an initialization period, a threshold voltage sampling period, a writing period, and a light emission period are provided in sequence; the driving method includes: in the initialization period, a step of causing the holding capacitor to hold, as an initial holding voltage, a voltage higher than a threshold voltage of the driving transistor; in the threshold sampling period, a step of changing the voltage held in the holding capacitor from the initial holding voltage toward the threshold voltage of the driving transistor; in the writing period, a step of switching the voltage of the second terminal of the coupling capacitor from the reference voltage to a data voltage to be applied to the pixel circuit, thereby changing the voltage held in the holding capacitor to a threshold compensation data voltage that is a voltage corresponding to the data voltage compensated for the threshold of the driving transistor; and in the light emission period, a step of supplying, from the high-voltage side power supply line through the driving transistor, a driving current corresponding to the threshold compensation data voltage held in the holding capacitor to the display element.

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