Structure of semiconductor memory and method for operating same

Abstract

The present invention has a memory cell array structure in which: a group of MOS transistors that are insulated from a substrate and arranged horizontally are vertically stacked in multiple layers; each memory cell has disposed thereon one silicon channel layer, a source diffusion layer connected to a pair of source lines sandwiching the silicon channel layer, and a drain diffusion layer connected to a bit line; the silicon channel layer, the diffusion layers, and a metal layer are each formed to have the same thickness; the pair of source lines and the bit line extend long and in parallel with one another, and are connected to the source diffusion layer and the drain diffusion layer of a large number of memory cells present on the same horizontal plane; furthermore, a gate conductor layer is formed from a vertical column so as to be sharable from an uppermost-layer MOS transistor to a lowermost-layer MOS transistor present at the same position in plan view; two gate conductor layers are arranged in one MOS transistor, with a gate insulation film interposed therebetween, so as to sandwich the silicon channel layer; the gate end of one gate conductor layer extends to the source diffusion layer and the drain diffusion layer; and the other gate conductor layer is short.

Description

Semiconductor memory structure and operation method

[0001] The present invention relates to semiconductor memory devices and the operation of semiconductor memory devices.

[0002] In recent years, there has been a demand for higher integration and performance of memory elements in LSI (Large Scale Integration). Capacitor-connected dynamic random access memories (DRAMs, e.g., Non-Patent Document 1) have difficulty achieving high integration because memory cells cannot be stacked three-dimensionally. On the other hand, a method for creating a capacitor-free DRAM cell using a single MOS transistor with a silicon film (SOI: Silicon-On-Insulator) formed on an insulating film has been proposed (Non-Patent Documents 2 and 3). However, problems with data retention and other aspects have prevented this method from being put to practical use.

[0003] Figure 12-1 shows the "1" write operation of a DRAM cell without a capacitor, Figure 12-2 shows the state of the cell after "1" has been written, and Figure 12-3 shows the "0" write operation (see Non-Patent Document 2). Figure 12-1 shows the "1" write operation. Here, the memory cell is formed on an SOI substrate 300, and has a source N connected to a source line SL. ＋ layer 303 (hereinafter, the semiconductor region containing a high concentration of donor impurities is referred to as "N ＋ The semiconductor region containing the acceptor impurities is called the "P layer.") The drain N ＋ The memory cell of the DRAM is composed of a gate conductive layer 304, a gate conductive layer 305 to which a word line WL is connected, and a floating body 302 which is the P layer of the MOS transistor 310-1. There is no capacitor, and a single MOS transistor 310-1 constitutes the memory cell of the DRAM. The SiO2 layer 301 of the SOI substrate is in contact directly below the floating body 302. When writing "1" to a memory cell composed of this single MOS transistor 310-1, the MOS transistor 310-1 is operated in the saturation region. That is, the source N ＋ An inversion layer 307 extending from layer 303 is connected to the drain N＋ The drain N ＋ When the bit line BL connected to the layer 304 and the word line WL connected to the gate conductive layer 305 are both set to a high voltage and the gate voltage is set to about 2 / 3 of the drain voltage to operate the MOS transistor 310-1, the drain N ＋ The electric field strength is at a maximum at the pinch-off point where there is no inversion layer near the layer 304. ＋ Layer 303 to drain N ＋ The electrons flowing toward the layer 304 are accelerated and collide with the Si lattice, and the kinetic energy lost at that time generates electron-hole pairs (impact ionization phenomenon). Most of the generated electrons (not shown) are released into the drain N ＋ The generated electrons reach the layer 304. Also, a small portion of the hot electrons jump over the gate oxide film 309 and reach the gate conductive layer 305. At the same time, the generated holes 306 charge the floating body 302. In this case, the generated holes contribute to an increase in the number of majority carriers because the floating body 302 is made of P-type Si. The floating body 302 is filled with the generated holes 306, and the voltage of the floating body 302 rises to the source N ＋ When the potential of the source N ＋ discharge to layer 303, where Vb is the source N ＋ This is the built-in voltage of the PN junction between the layer 303 and the P-layer floating body 302, which is about 0.7 V. Figure 12-2 shows the floating body 302 saturated with the generated holes 306.

[0004] Next, the "0" write operation of the memory cell 310 will be explained using FIG. 12-3. For a common selected word line WL, there are randomly "1" written memory cells 310-1 and "0" written memory cells 310-2. FIG. 12-3 shows how the "1" write state is rewritten to the "0" write state. When writing "0", the voltage of the bit line BL is set to -0.9V, the source line SL is set to 0V, and the word line WL is set to 1V, thereby＋ The PN junction between the layer 304 and the floating body 302 of the P layer is forward biased. As a result, holes 306 generated in the floating body 302 in the previous cycle are transferred to the drain N connected to the bit line BL. ＋ The potential of the floating body 302 of the memory cell 310-1 filled with holes 306 is higher than that of the floating body 302-2, which does not contain any holes. Therefore, the threshold voltage of the memory cell 310-1 is lower than that of the memory cell 310-2. This is shown in Figure 12-4.

[0005] FIG. 13 shows a read operation (see Non-Patent Document 2). FIG. 13-1 shows the "0" write state, and FIG. 13-2 shows the "1" write state. The voltage of the bit line BL is set to a positive voltage (for example, 0.2 V), and the source N ＋ Apply 0 V to the layer 303 and a positive bias (for example, 0.8 V) to the gate conductive layer 305. Because the thresholds are different between the "0" write state and the "1" write state, the cell current (Icell) during readout is detected to be different between the two, as shown in Figure 13-3, and the value is judged to be "1" or "0."

[0006] One of the problems with memory cells using SOI is their short data retention time after data is written (see Non-Patent Document 2). Figure 14 shows an example of the problem with the data retention characteristics of a "0"-state memory cell. Figure 14-1 shows two memory cells, one above the other, sharing a bit line. When writing a "0" to the lower cell, -0.9V is applied to the bit line BL, 0V to the source line, and 1V to the word line WL. Meanwhile, the upper cell is a non-selected cell for writing a "0." Even if the bit line is -0.9V and the source line is 0V, -1.5V is applied to the word line to turn off the memory transistor. To quickly apply -1.5V to all non-selected word lines when writing a "0," the bit line and source line are kept at 0V while the memory cell array is in standby mode (when no write or read operations are taking place), and -1.5V is steadily applied to the word line. By applying -1.5V to the word line during standby, holes stored in the channel of a "1"-state memory cell gather directly below the gate, suppressing recombination of holes and electrons, allowing the holes to remain in the channel for a long time. Therefore, when a memory cell is read after waiting one second after writing data, Icell in the "1" state remains almost unchanged compared to immediately after writing. On the other hand, for a "0"-state memory cell, Icell gradually increases during standby. For example, at a standby temperature of 85°C, Icell reaches roughly the same value as in the "1" state in about 100 ms. Since a small difference between Icell ("1") and Icell ("0") increases the likelihood of misreading data, the upper limit of standby time is set at around 50 ms. However, in large-scale LSIs, variations between memory cells must be taken into account, and the upper limit of standby time is likely to be even lower. A short data retention capacity requires frequent data rewriting and increases standby current consumption, making it unsuitable for mass production.

[0007] The reason why the read current of a "0" cell increases during standby is shown in Figure 14-2. When a negative voltage of -1.5V is applied to the gate 305, the silicon electric field under the gate insulating film increases at the boundary between the source 303 and channel 302 and the boundary between the drain 304 and channel 302, causing a breakdown in the silicon and generating electron-hole pairs. The generated electrons are absorbed by the source and drain, and holes accumulate in the channel, increasing Icell.

[0008] H. Ishiuchi, T. Yoshida, H. Takato, K. Tomioka, K. Matsuo, H. Momose, S. Sawada, K. Yamazaki and K. Maeguchi: International Electron Devices Meeting, pp. 33-36 (1997)T. Ohsawa, K. Fujita, T. Higashi, Y. Iwata, T. Kajiyama, Y. Asao, and K. Sunouchi: “Memory Design Using(a) One-Transistor Gain Cell on SOI,” IEEE Journal of Solid-State Circuits, Vol. 37, No. 11, pp. 1510-1522 (2002)MG Ertosun, K. Lim, C. Park, J. Oh, P. Kirsch, and KC Saraswat: “Novel Capacitorless Single-Transistor Charge-Trap DRAM (1T CT DRAM) Utilizing Electrons,” IEEE Device Letter, Vol. 31, No.5, pp. 405-407 (2010)

[0009] DRAMs consisting only of MOS transistors, which do not use capacitors, have a shorter data retention time than DRAMs that use capacitors, making them difficult to put into practical use. Also, the area of ​​each memory cell in MOS transistors on SOI is large, making it impossible to increase capacity.

[0010] To solve the above problems, the present invention provides a method for manufacturing a memory device using semiconductor elements. A group of horizontally arranged MOS transistors, insulated from a substrate, is vertically stacked in multiple layers, with an insulating film between each transistor layer. Each horizontally arranged MOS transistor group is several tens of nanometers thick. Each MOS transistor forms a memory cell, which includes a silicon channel layer and a pair of source and drain diffusion layers sandwiching the silicon channel layer. A metal source line is connected to the source diffusion layer, and a metal bit line is connected to the drain diffusion layer, each of which has the same thickness. The pair of source and bit lines extends long and parallel to each other, connecting the source and drain diffusion layers of multiple memory cells located on the same horizontal plane. In a plan view, a pair of elongated source and bit lines extends parallel to each other, but multiple similar source and bit line pairs exist in parallel to form a cell array. The upper and lower bit lines are electrically isolated and receive independent voltages from the column decoder at the edge of the memory cell array, while all source lines within a single cell array receive a common voltage. Furthermore, the gate conductor layer is formed as a vertical pillar so that it can be shared by MOS transistors from the top layer to the bottom layer, all of which are located in the same position in a plan view. Each MOS transistor has two gate conductor layers sandwiched between gate insulators, sandwiching the silicon channel layer. The channel layer of a single memory cell is sandwiched between source and drain diffusion layers at both ends, and the opposite ends of the channel layer, which are oriented 90 degrees apart, are surrounded by two gate conductor layers via gate insulators. The gate end of one gate conductor layer extends to the source and drain diffusion layers, sandwiching the gate insulator, and is known as the memory gate, as it switches the MOS transistor on and off. The other gate conductor layer is shorter, and its ends do not extend to the source and drain diffusion layers. It retains holes accumulated in the channel, and is known as the storage gate. Two insulating film pillars different from the gate insulating film are separately arranged between the storage gate and the source diffusion layer and between the storage gate and the drain diffusion layer, so that the storage gate does not come into direct contact with the source diffusion layer and the drain diffusion layer.The insulating film pillars are thicker than the gate insulating film in plan view, and the width of the silicon channel layer perpendicular to the memory gate at the two locations where the insulating film pillars are present is narrower than at the locations without the insulating film pillars. Like the gate conductor layer, these insulating film pillars are formed so that they can be shared by MOS transistors from the top layer to the bottom layer, all of which are located at the same position in plan view. An interlayer insulating film is laid above the top MOS transistor layer, and the memory gate extends above this insulating film and connects to gate wiring called word lines. The storage gate also extends above this insulating film and connects to gate wiring called storage gate lines. These two gate wirings run parallel to each other and connect to the row decoder at the edge of the memory cell array. The two types of gate wiring are perpendicular to the bit lines and source lines, and the memory gates and storage gates in each memory cell are all connected to the gate wiring directly above them. In other words, the two types of gate wiring all run parallel to each other and connect to the row decoder, and each gate wiring is assigned an independent potential depending on its operation.

[0011] In one embodiment, the source line is always supplied with 0V. The storage gate line is supplied with a certain negative voltage except when "0" data is written to the memory cell connected to the storage gate line. When "0" data is written to the memory cell connected to the storage gate line, a certain positive voltage is applied to the storage line. When "0" or "1" data is written to the memory cell connected to the word line or when data is read, a certain positive voltage is applied to the word line, and 0V is applied during other standby periods. When "1" data is written to the memory cell connected to the bit line or when data is read, a certain positive voltage is applied to the bit line, and 0V is applied otherwise.

[0012] Because multiple memory cell layers are stacked vertically, the number of memory cells in a given memory area in a planar view is proportional to the number of stacked memory cell layers. Increasing the number of memory cell layers increases memory capacity, enabling the creation of high-capacity memory chips. Furthermore, when a memory cell is in the "1" state, holes accumulate in the silicon channel. However, by applying a negative voltage to the storage gate line except when the memory cell connected to the storage gate line is being written with "0" data, the holes remain near the storage gate in the silicon channel. On the other hand, since a negative voltage is never applied to the memory gate, even if electrons are present in the channel, they remain near the memory gate. Therefore, the opportunity for holes and electrons to meet in the channel is extremely low, reducing the probability of their recombination. Therefore, even if a memory cell is in the "1" state and holes accumulate in the silicon channel, the holes do not recombine with electrons for a long time, allowing the "1" state to be maintained for a long time. Furthermore, since the storage gate is not in contact with the source and drain diffusion layers and an insulating film pillar is sandwiched between the storage gate and both diffusion layers, even if a negative voltage is applied to the storage gate except when writing "0" data, no breakdown occurs in the silicon channel layer near the storage gate and no electron-hole pairs are generated. Therefore, holes are unlikely to increase in a memory cell in which "0" data has been written, and the "0" state can be maintained for a long time. This allows for a longer data retention time.

[0013] Figure 1-1 is a perspective view showing the configuration of the memory cell array according to the first embodiment. Figure 1-2 is a cross-sectional view taken along the line AA of Figure 1-1. Figure 1-3 is a cross-sectional view taken along the line BB of Figure 1-1. Figure 2-1 is a top view of Figure 1-1, with one memory cell indicated by the area enclosed by the dashed line. Figure 2-2 is an equivalent circuit diagram of Figure 2-1. Figure 2-3 is a top view of eight memory cells arranged side by side. Figure 2-4 is its equivalent circuit diagram. Figure 3-1 is a perspective view showing the connection between the memory cell array and the peripheral core circuitry that drives the cell array, and Figure 3-2 is a cross-sectional view taken along the line AA of Figure 3-1. Figure 4-1 shows the operation of the memory cell, and Figure 4-2 shows the state of the memory cell corresponding to Figure 4-1. Figure 5-1 is a top view of a memory cell showing how to write a "0," and Figure 5-2 is a timing chart for writing a "0." Figure 6-1 is a top view of a memory cell showing how to write a "1," and Figure 6-2 is a timing chart for writing a "1." FIG. 7-1 is a diagram showing the configuration of the cell array and the voltage of each node when writing "0." FIG. 7-2 is a diagram showing the configuration of the cell array and the voltage of each node when writing "1." FIG. 7-3 is a diagram and table showing the sizes of components of a memory cell, indicating the configuration of the cell array and the voltage of each node when reading data. A diagram for explaining a method for manufacturing a semiconductor memory device according to the first embodiment. A diagram for explaining a method for manufacturing a semiconductor memory device according to the first embodiment. FIG. 9-3a is a diagram for explaining a method for manufacturing a semiconductor memory device according to the first embodiment, and FIG. 9-3b is a diagram for explaining a method for manufacturing a semiconductor memory device according to the first embodiment. A diagram for explaining a method for manufacturing a semiconductor memory device according to the first embodiment. A diagram for explaining a method for manufacturing a semiconductor memory device according to the first embodiment. A diagram for explaining a method for manufacturing a semiconductor memory device according to the first embodiment. A diagram for explaining a method for manufacturing a semiconductor memory device according to the first embodiment. A diagram for explaining a method for manufacturing a semiconductor memory device according to the first embodiment. A diagram for explaining a method for manufacturing a semiconductor memory device according to the first embodiment. A diagram for explaining a method for manufacturing a semiconductor memory device according to the first embodiment. A diagram for explaining a method for manufacturing a semiconductor memory device according to the first embodiment. A diagram for explaining a method for manufacturing a semiconductor memory device according to the first embodiment.10-1 is a perspective view showing a configuration of a memory cell array according to a second embodiment. FIG. 10-2 is a cross-sectional view taken along line AA of FIG. 10-1. FIG. 10-3 is a top view of FIG. 10-1, showing a region of one memory cell surrounded by a dashed line. , and Figure 10-4 is its equivalent circuit diagram. Figure 10-5 is a top view of eight memory cells lined up. Figure 10-6 is its equivalent circuit diagram. Figure 10-7 is a perspective view showing the connection between the memory cell array and the peripheral core circuit section that drives the cell array. Figure 10-8 is a cross-sectional view taken along the line A-A in Figure 10-7. Figure 10-9 is a diagram showing the configuration of the cell array and the voltages of each node when writing "0". Figure 10-10 is a diagram for explaining a method for manufacturing a semiconductor memory device according to the second embodiment. Figure 10-11 is a diagram for explaining a method for manufacturing a semiconductor memory device according to the second embodiment. Figure 10-12 is a diagram for explaining a method for manufacturing a semiconductor memory device according to the third embodiment. Figure 10-13 is a diagram for explaining a method for manufacturing a semiconductor memory device according to the third embodiment.FIG. 12-1 is a diagram for explaining a method for writing a "1" to a memory cell of a conventional example; FIG. 12-2 is a diagram for explaining the state of a memory cell of a conventional example after writing a "1" to the memory cell of a conventional example; FIG. 12-3 is a diagram for explaining a write operation of a "0" to the memory cell of a conventional example; FIG. 12-4 is a diagram for explaining the voltage-current characteristics of a memory cell of a conventional example; FIG. 13-1 is a diagram for explaining the "0" state of a memory cell of a conventional example; FIG. 13-2 is a diagram for explaining the "1" state of a memory cell of a conventional example; and FIG. 13-3 is a diagram for explaining a read operation of a conventional example. FIG. 14-1 is a diagram showing the voltages applied to two memory cells during a write operation of a "0" to the memory cell of a conventional example; and FIG. 14-2 is a diagram showing operational problems of the memory cell of the conventional example.

[0014] The structure, driving method and manufacturing method of a semiconductor memory device according to the present invention will be described below with reference to the drawings.

[0015] First, the structure of a semiconductor memory device according to the present invention will be described with reference to the drawings. Figures 1, 2, and 3 show the structure of a memory cell according to the present invention and its equivalent circuit diagram. As shown in Figure 1-1, an insulating film 209 and a silicon layer 203 are sequentially stacked on a substrate. While Figure 1 shows a two-layer stack as an example, three or more layers are also possible. A memory gate 201 (MG) and a storage gate 200 (SG) are vertically arranged, penetrating from the top silicon layer 203 to the bottom silicon layer 203, and each gate is covered with a gate insulating film 202. An insulating film 210 is arranged on both ends of the storage gate, and the insulating film 210 extends vertically from the top silicon layer 203 to the bottom silicon layer 203. Diffusion layers 204 and 205 containing N-type or P-type impurities are arranged on both ends of the silicon layer 203. Although the silicon layer 203 does not contain impurities, N-type or P-type impurities are partially thermally diffused from the diffusion layer near the diffusion layer. A MOS transistor is formed by a memory gate 201, a silicon layer 203, and diffusion layers 204 and 205. The silicon layer 203 forms the channel portion, the diffusion layer 204 forms the drain of the MOS transistor, and the diffusion layer 205 forms the source. Low-resistance bit lines 206 and 207 are arranged adjacent to the diffusion layer 204. The top-layer bit line 206 and the bottom-layer bit line 207 are electrically independent. A low-resistance common source line 208 is arranged adjacent to the diffusion layer 205. A common potential is applied to the multiple source lines 208. On the other hand, the silicon layer 203 is in contact with the storage gate 200 via a gate insulating film 202. The memory gate is in contact with the diffusion layers 204 and 205 via the gate insulating film 202, but the storage gate is not in contact. 1-2 is a cross-sectional view taken along the line A-A in FIG. 1-1, showing a shape in which the memory gate 201, storage gate 200, and gate insulating film 202 vertically penetrate partway through the lowest insulating film layer 209. FIG. 1-3 is a cross-sectional view taken along the line B-B in FIG. 1-1, showing a shape in which the storage gate 200, gate insulating film 202, and insulating film 210 vertically penetrate partway through the lowest insulating film layer 209. The arrangement of the source diffusion layer 205 and common source line 208, and the drain diffusion layer 204 and bit lines 206 and 207 is also shown.

[0016] Figure 2-1 is a plan view. Two memory cells are arranged with the storage gate 200 as the axis of inversion symmetry, and the rectangular area indicated by the dashed line corresponds to one memory cell. In other words, two memory cells share one storage gate 200. Furthermore, by vertically stacking the silicon layer 203, source diffusion layer 205, and drain diffusion layer 204 in an n-layer configuration, the number of memory cells can be increased by n times the number of cells in the plan view. Note that Figure 2-1 is a diagram of the top silicon layer, and the bit line is 206. For the bottom silicon layer, the bit line is 207. Figure 2-2 shows the equivalent circuit of one memory cell. The memory cell has four terminals and two gates: a memory gate 201 and a storage gate 200. The channel potential is determined by the voltages of the two gates, the bit line 206 connected to the drain 204, and the common source line 208 connected to the source 205.

[0017] Figure 2-3 shows the array structure in which two pairs of memory cells on the top layer shown in Figure 2-1 are arranged side-by-side, resulting in a total of eight memory cells. Figure 2-4 is an equivalent circuit diagram, but the common source line 208 is shared by all eight memory cells. The two bit lines 206 are independent of each other, and the memory gates are connected to metal wiring, word lines 212 (WL). The two word lines 212 are also independent. The storage gate 200 is connected to a storage gate line 213 (SGL). Each storage gate line 213 is also independent of each other. Figure 3-1 shows the connection of the word lines 212 and storage gate line 213 from the memory cell array to the row decoder circuit, and the connection of the bit lines (BL) 206 and 207 and the common source line (CSL) 208 from the memory cell array to the column decoder circuit. This example shows a three-layer stack of memory transistors. Figure 3-2 shows the AA cross section of Figure 3-1. The bit lines (BL) are independent of each other in three stacked layers, and individual voltages are applied to them by the column decoder.

[0018] Next, the source diffusion layer 205 and drain diffusion layer 204 are N-type silicon. Figure 4-1 shows the memory cell drain current (Icell) as a function of the voltage on the memory gate 201. For example, a constant negative voltage is applied to the storage gate 200, the source diffusion layer 205 is at 0 V, and a positive voltage is applied to the drain diffusion layer 204. Figure 4-1 shows two curves with different threshold voltages (Vt). The difference is due to the presence or absence of holes in the channel region 203. Curve (A) corresponds to the case where holes are present, and curve (B) corresponds to the case where holes are absent. Figure 4-2 shows a cross-sectional view of a memory cell with holes present. Because a negative voltage is applied to the storage gate 200, holes are present near the storage gate. However, the presence of holes increases the potential of the channel region 203 near the memory gate 201 compared to when holes are absent. Therefore, the voltage on the memory gate due to the formation of an inversion layer near the memory gate 201 is lower when holes are present than when holes are absent. In other words, the threshold voltage is lower when holes are present. This difference results in the difference between (A) and (B) in the I-V characteristics. Thus, the drain current (Icell) during readout differs depending on whether holes are present in the channel. Therefore, the difference in Icell when a certain positive voltage is applied to the memory gate is detected and used to represent data "1" or "0." Here, a cell with holes in the channel is called a "1" cell, and a cell without holes is called a "0" cell. Note that when the source and drain diffusion layers are P-type silicon, the threshold voltage changes depending on whether electrons are present in the silicon channel layer, and the difference between these threshold voltages is used as data. Therefore, the voltage applied to each node is reversed in sign from when the source and drain diffusion layers are P-type silicon. The same applies to readout and writing of data "1" and "0." Below, we will explain operation when the source and drain diffusion layers are N-type silicon. In explaining operation, the memory gate is referred to as MG and the storage gate as SG.

[0019] First, we will explain how to write a "0." Before writing "0" data, the memory cell is in a "1" state and there are holes in the channel 203. For example, apply 0V to CSL and BL, 0.5V to MG, and 1V to SG. Since the channel is made of intrinsic silicon without N-type or P-type impurities, the channel potential becomes higher than the source and drain potential, as shown in Figure 5-1, and holes migrate to the source or drain diffusion layer. The migrated holes recombine with electrons in the source or drain and disappear. Therefore, after writing "1," there are no holes in the channel, resulting in a neutral state with no charge. If the memory cell was in a "0" state before writing "0," writing "0" leaves no holes in the channel, and no state change occurs. Figure 5-2 shows the voltage timing diagram for MG, SG, and BL when writing "0." Note that CSL is always fixed at 0V during write and read operations.

[0020] Next, we will explain how to write data "1." This assumes that the memory cell is in the "0" state before writing "1" and there are no holes in the channel portion 203. For example, 1 V is applied to BL, 1.1 V to MG, -1 V to SG, and 0 V to CSL. As shown in Figure 6-1, the MG voltage is higher than the threshold voltage of the memory cell in the "0" state, so an inversion layer 215 is formed in the channel portion near MG, and electrons flow from the source to the drain. However, the potential at the drain end of the channel is high, causing depletion. This increases the lateral electric field, causing electron impact ionization and generating electron-hole pairs. The generated holes remain in the channel, and the state of the memory cell changes from "0" to "1." If the memory cell was in the "1" state before writing "1," the holes in the channel continue to exist, so there is no state change. Figure 6-2 shows the voltage timing diagram for MG, SG, and BL when writing "0."

[0021] Next, we will explain the read method. For example, apply 0.2V to BL, 1V to MG, -1V to SG, and fix CSL to 0V. As shown in Figure 4-1, there is a difference in the drain current between the "1" state and the "0" state, and this current difference is detected by the sense circuit in the column decoder.

[0022] Figure 7-1 shows the potentials applied to eight upper and eight lower memory cells when writing a "0." This figure shows an upper silicon layer (Layer 1) and a lower silicon layer (Layer 2), with eight memory cells arranged on each of the upper and lower silicon layers. Assuming the upper and lower layers are in the same location in a plan view, the MG and SG are shared, while the CSL is shared by the left and right memory cells and the upper and lower memory cells. The BLs connected to the upper memory cells (BL1,1 and BL2,1) and the BLs connected to the lower memory cells (BL1,2 and BL2,2) can take independent potentials. However, in Layer 1 and Layer 2, all memory cells connected to SG1 (encircled by the dashed lines) are simultaneously written to a "0." Memory cells not connected to SG1 are not written to a "0." A group of memory cells connected to a single SG line is referred to as a block. The voltages applied to each node when writing a "0" are shown in the table on the right. A positive voltage between 0.2V and 0.8V is applied to the memory gates (MG1, MG2) connected to the selected block, and a positive voltage between 0.5V and 1.5V is applied to the storage gate (SG1). BL and CSL are set to 0V. As a result, as shown in Figure 5-1, holes in the channel region move to the source diffusion layer (205) or drain diffusion layer (204). A negative voltage between -0.5V and -1.5V is applied to the storage gate (SG2) connected to the unselected block. As a result, holes in the channel region remain near the storage gate, and "0" is not written.

[0023] Figure 7-2 shows the potentials applied to eight memory cells on each side when writing a "1." A "1" is written to all memory cells connected to MG1 in Layer 1 and Layer 2, enclosed by dashed lines. A group of memory cells connected to a single MG line is called a page. A block consists of two pages. A voltage between 0.8V and 1.5V is applied to MG in the selected page. Whether a memory cell is written to a "1" is determined by the voltage applied to BL. The left cell connected to MG1 in Layer 1 and the right cell in Layer 2 are written to a "1," while the other cells are not. In this case, as shown in the table on the right, a voltage between 0.8V and 1.5V is applied to BL1,1 and BL2,2, and 0V is applied to BL2,1, BL1,2, and CSL. As shown in Figure 6-1, applying a positive voltage to BL and a voltage above the memory cell's threshold to MG causes impact ionization of electrons near the drain, generating electron-hole pairs. The generated holes remain in the channel, and the state of the memory cell changes from "0" to "1." Note that 0V is applied to the unselected memory gates (MG2-MG4). A voltage between -0.5V and -1.5V is applied to all storage gates (SG1 and SG2). The "0" and "1" write operations were explained using Figures 7-1 and 7-2, but to rewrite the data in a memory cell of a certain page, the cell data of the block containing that page is temporarily stored in the latch circuit in the column decoder, and then a "0" is written first. Next, the data stored in the latch circuit or new data is written sequentially to two pages in the block.

[0024] Figure 7-3 shows the voltages applied to eight memory cells on each side during data read. All memory cells in one page connected to MG1, enclosed by dashed lines in Layer 1 and Layer 2, are read simultaneously. Within the selected page, MG1 is applied with a voltage between 0.6V and 1.3V. All BLs connected to Layer 1 and Layer 2 (BL1,1, BL2,1, BL1,2, and BL2,2) are applied with a voltage between 0.2V and 0.6V. All storage gates SG (SG1 and SG2) are fixed at a voltage between -0.5V and -1.5V. When a memory cell is in a "1" or "0" state, there is a difference in the current flowing between the CSL and BL, which is detected by the sense amplifier circuit in the column decoder. When a block is in standby mode (not in write or read mode), a voltage between -0.5V and -1.5V is applied to SG, and the WL, BL, and CSL are all set to 0V. The write and read voltages also depend on the work functions of the memory gate and storage gate. The values ​​shown in Figure 7 are for a work function of approximately 5.2 eV. For example, if the work function is lowered, the voltages applied to the MG and SG must be lowered accordingly.

[0025] Figure 8 shows the gate length and gate insulating film thickness of the memory cell. MG is the length of the memory gate, L SG is the length of the storage gate, L Diff is the length of the drain diffusion layer 204 and the source diffusion layer 205 to the outer end of the insulating film 210, and L Si is the length of the channel region 203, and L OX indicates the length from the channel end to the inner end of the insulating film 210. Channel is the width of the channel region 203, and t Storage is the width from the end of the gate insulating film 202 to the end of the insulating film 210, and t Insulator indicates the width of the insulating film 209, and W indicates the width of the silicon 203. MG is 40 to 90 nanometers, L SG is 10 to 25 nanometers, L Diff is 10 to 30 nanometers, L Si is 36 to 80 nanometers, L OX is 10 to 20 nanometers, tChannel is 20 to 40 nanometers, Storage is 10 to 20 nanometers, W and t Insulator The gate insulating film 202 is preferably made of silicon oxide or hafnium oxide (HfO2), but the physical thickness of the gate insulating film (t Gate-Ox ) is preferably 3 to 7 nanometers when using HfO2.

[0026] t Channel / t Storage We compare Icell under three conditions: 10 nanometers / 5 nanometers, 30 nanometers / 15 nanometers, and 60 nanometers / 30 nanometers. The read conditions are a voltage between -0.5V and -1.5V applied to SG, 1V to MG, and 0.2V to BL. The difference between Icell ("1") and Icell ("0") immediately after writing is approximately 0.01 μA, 0.15 μA, and 0.12 μA for 10 / 5 nanometers, 30 / 15 nanometers, and 60 / 30 nanometers, respectively. In other words, the data difference in Icell is small at 10 / 5 nanometers, making reading difficult. On the other hand, the difference in Icell is large at 15 / 30 nanometers and 30 / 60 nanometers, making data readable. Since a negative voltage is applied to SG, in the case of 10 / 5 nanometers, even if 1V is applied to MG, a sufficient inversion layer is not formed in the silicon channel layer near MG, and Icell ("1") is small. However, if a higher voltage is applied to SG, the holes do not remain near SG, but diffuse to the vicinity of MG in the channel, and if readout is repeated in this state, recombination of electrons and holes occurs, reducing the number of holes. This reduces the number of times that readout is possible. Therefore, t Channel / t Storage The size of the channel needs to be larger than 10 / 5 nanometers. Also, if the SG voltage is increased during standby, the recombination of electrons and holes becomes easier in the memory cell in the "1" state, and the number of holes in the channel decreases. Therefore, Icell ("1") decreases as the standby time passes. This phenomenon is called t Channel / t Storageoccurs in the same way under all three conditions. However, if the applied voltage to SG is reduced to -0.5V or less, the change in the standby time of Icell ("1") decreases. This is because holes are localized only near SG during the standby time, reducing the probability of recombining with electrons. Therefore, to improve data retention characteristics, it is desirable to apply a negative voltage of -0.5V or less to SG.

[0027] On the other hand, Icell("0") increases with increasing standby time. This is due to weak junction breakdown in the silicon channel near the source and drain diffusion layers, generating electron-hole pairs. The generated holes gradually accumulate in the silicon channel, causing Icell("0") to increase. However, the rate at which Icell("0") increases does not depend much on the SG voltage. Even when a negative voltage between -0.5V and -1.5V is applied to the SG, there is little change in Icell("0") from the time "0" was written until the standby time reached approximately 3 seconds at 85°C. This is because the SG is not in direct contact with the source and drain diffusion layers, but rather a 10-nanometer or thick insulating film 210 is sandwiched between the diffusion layers and the SG. Because the insulating film 210 is located between the SG and the diffusion layers, the electric field in the silicon near the SG is small, even when a negative voltage is applied to the SG, reducing the generation of electron-hole pairs. Therefore, the time dependency of Icell ("0") during standby is reduced compared to the conventional example, and a significant improvement in data retention characteristics is observed. Channel / t Storage There is not much difference between 15 / 30 nanometers and 30 / 60 nanometers. On the other hand, from the viewpoint of reducing cell size, Channel Therefore, in order to gain a read margin, the difference between Icell ("1") and Icell ("0") after writing data should be increased, and the waiting time should be increased. Channel is 18 to 55 nanometers, t Storage It is desirable to set the thickness to around 8 to 31 nanometers.

[0028] A manufacturing method for a memory device according to the first embodiment will be described using Figures 9-1 to 10-28. As shown in Figure 9-1, an insulating film layer 2 and a silicon layer 3 are sequentially stacked on a substrate 1. Note that the substrate 1 may be made of silicon. Here, a two-layer stack of a silicon layer 3 and an insulating film layer 2 is shown. An insulating film layer 4 is further deposited on the top silicon layer 3. The silicon layer 3 may contain no impurities. Methods for forming the silicon layer 3 on the insulating film 2 include depositing an amorphous or polycrystalline silicon film and then crystallizing the silicon by annealing in a later process.

[0029] Next, as shown in Figure 9-2, the insulating film layer 2, silicon layer 3, and insulating film layer 4 are divided into multiple strips. Figure 9-3a shows the next step, which is a cross-sectional view taken along the A-A line along the short side of the rectangle in Figure 9-2. Multiple silicon layers 3 are exposed in the spaces 6 between adjacent stacked films, and high-concentration N-type or P-type impurities are implanted into the exposed silicon layers 3. Note that while Figure 9-3a shows the bottom insulating film layer 2 being completely removed by etching the sections 6, partial removal is also possible. There are three methods for implanting high-concentration N-type or P-type impurities. One method is to fill the spaces between the stacked films with a silicon layer containing high-concentration N-type or P-type impurities and allow solid-phase diffusion, followed by removal of the silicon layer containing high-concentration phosphorus. The second method is to ion-implant N-type or P-type impurities through the spaces 6. The ion implantation is performed at an oblique angle so that the impurities are implanted into the silicon layers 3. 9-3b, the third method is to partially remove the silicon layer 3 from the space 6 between the laminated films to create a void 5-1 in the silicon layer 3, and then deposit a silicon layer containing a high concentration of N-type or P-type impurities to fill the space 6 between the laminated films.Then, reactive ion etching is used to remove the silicon layer containing a high concentration of N-type or P-type impurities in the space 6 between the laminated films, but at the same time, the silicon layer containing a high concentration of N-type or P-type impurities is left in the void 5-1.

[0030] Next, as shown in the plan view of Figure 9-4, the insulating film layer 4, the stacked silicon layer 3, and the insulating film layer 2 are etched at locations 7 and 8, down to the middle of the bottom insulating film layer 2. Alternatively, the substrate 1 is exposed. While both methods are possible, Figure 9-4 and the subsequent figures illustrate the case of etch-down to the middle of the bottom insulating film layer 2. Figure 9-5 shows a cross-sectional view of Figure 9-4 taken along B-B. Figure 9-6 shows a plan view of Figure 9-5, excluding the insulating film layer 4. Figure 9-7 shows a cross-sectional view of Figure 9-4 taken along A-A. Note that while Figure 9-7 shows the bottom insulating film 2 at space 6 as completely etched, the subsequent figures assume it is partially left. Next, gate insulating film 9 and then gate material 10 are deposited, and then they are polished to expose the top of the insulating film layer 4. Figure 9-8 shows the process up to this point. Figure 9-9 shows a cross-sectional view of Figure 9-8 taken along B-B.

[0031] Next, mask material 11 is deposited, and Figure 9-10 shows a plan view of the mask material after it has been patterned. Here, the areas where gate material 10 is embedded and not covered by mask material 11 are designated 12 and 13. Figure 9-11 shows the B-B cross section of Figure 9-10. Next, gate material 10 is etched using mask material 11 and insulating film 4 as etching-resistant materials. Gate insulating film 9 may also be etched at the same time as gate material 10, but is not etched here. Figure 9-12 shows a plan view after mask material 11 has been removed after etching. Figure 9-13 shows the A-A cross section of Figure 9-12. In Figure 9-13, the gate etching areas are designated 15 and 16.

[0032] Next, an insulating film is deposited, and the surface is polished to expose the insulating film 4. This is shown in Figure 9-14, a plan view. 17 and 18 are the remaining portions of this insulating film. Figure 9-15 is a cross-sectional view taken along the line A-A in Figure 9-14. Next, both the remaining portion of the insulating film at 18 in Figure 9-14 and the gate insulating film 9 are etched to expose the bottom insulating film 4. Figure 9-16 is a plan view after the bottom insulating film 4 has been exposed. Figure 9-17 shows the cross-sectional view taken along the line A-A in Figure 9-16. Next, in the region 19 where the diffusion layer 5 is exposed in Figure 9-17, the diffusion layer 5 is partially etched. Figure 9-18 shows the shape after partial etching. Next, a metal material 21 is deposited, and the surface of the insulating film 4 is exposed by flat polishing, resulting in the shape shown in Figure 9-19.

[0033] Next, using the insulating film 4 as an etching-resistant material, reactive ion etching is used to remove the metal material 21 at location 22. During this process, the metal portion covered by the insulating film 4 and insulating film 2 is not etched, resulting in the shape shown in Figure 9-20. In Figure 9-20, 23 represents the metal wiring. Next, insulating film 24 is deposited, and then the surface of insulating film 4 is exposed by flat polishing. As shown in the plan view of Figure 9-21, insulating film 24 remains only at location 22 in Figure 9-20. Note that gate material 10 (200) corresponds to the storage gate 200 in Figure 1-1. Gate material 10 (201) corresponds to the memory gate 201 in Figure 1-1. The A-A cross section of Figure 9-21 corresponds to the shape shown in Figure 9-22. The plan view viewed from the CC plane results in the shape shown in Figure 9-23. The B-B cross section of 9-23 results in the shape shown in Figure 9-24.

[0034] Next, an interlayer insulating film 25 is deposited, and then an opening is made in the interlayer insulating film 25 at the contact hole 26 to expose the gate 10. Figure 9-26 shows a plan view of the contact hole 26. Note that the interlayer insulating film 25 is not shown in Figure 9-25 to show that it is located over the contact hole 26 and both gates 200 and 201. Next, as shown in the plan view of Figure 9-26, a metal material is deposited, and then the metal material is patterned to form gate wiring 27 and 28. Figure 9-27 shows a cross-sectional view taken along the line A-A of Figure 9-26. The gate wiring 27 extends up to the contact hole 26 and connects to the storage gate 200. As shown in Figure 9-25, the gate wiring 27 is connected to the storage gate 200, and the gate wiring 28 is connected to the memory gate 201. Next, as shown in Figure 9-28, an interlayer insulating film 29 is deposited on the gate wiring 27 and 28, completing the memory cell array fabrication process.

[0035] Other modifications of the present invention are shown using Figures 10-1 to 10-11. In the first embodiment, the SG was shared by two memory cells, but a configuration in which each memory cell has its own individual SG is also possible. Figure 10-1 shows the structure of a memory cell of the present invention. The only difference from the first embodiment is that each memory cell has its own individual SG, and the rest is the same. Figure 10-2 shows the A-A cross section of Figure 10-1. Two adjacent SGs are separated by an insulating film 216. The B-B cross section of Figure 10-1 is the same as Figure 1-3.

[0036] Figure 10-3 is a plan view, in which two memory cells are arranged upside down, and the rectangular area indicated by the dashed line corresponds to one memory cell. Figure 10-4 shows the equivalent circuit of one memory cell, which is the same as that of the first embodiment. Figure 10-5 shows the array structure in which two sets of memory cells shown in Figure 10-1 are arranged side by side, resulting in a total of eight memory cells. Figure 10-6 is the equivalent circuit diagram, in which the common source line 208 is shared by the eight memory cells.

[0037] Figure 10-7 shows how the word lines 212 and storage gate lines 213 are connected from the memory cell array to the row decoder circuit, and how the bit lines (BL) 206 and 207 and common source line (CSL) 208 are connected from the memory cell array to the column decoder circuit. This shows a case where three memory transistor groups are stacked. Figure 10-8 shows the AA cross section of Figure 10-7.

[0038] Figure 10-9 shows the potentials applied to eight memory cells in each of the two upper and lower layers when writing "0." Here, too, the upper silicon layer (Layer 1) and the lower silicon layer (Layer 2) are assumed to be in the same location in a plan view, with MG and SG shared. CSL is shared by the left and right and upper and lower memory cells. All memory cells connected to SG1, enclosed by the dashed lines in Layer 1 and Layer 2, are simultaneously written to "0." Memory cells not connected to SG1 are not written to "0." A group of memory cells connected to a single SG line is called a block here, and the number of memory cells connected to one block is the same as the number of memory cells in one page connected to one MG. The voltages applied to each node are shown in the table on the right and are the same as those in the first embodiment.

[0039] In the manufacturing process of the second embodiment, only those differences from the manufacturing process of the first embodiment are listed. Figure 10-10 corresponds to the manufacturing process of the first embodiment in Figures 9-10, but a region 13-2 is provided to divide the gate material 10, which will later become the SG, into two. Figure 10-10 is a cross-sectional view taken along line B-B in Figure 10-10, and corresponds to the manufacturing process of Figures 9-11 of the first embodiment. The subsequent processes are the same as the manufacturing process of the first embodiment.

[0040] 11-1 to 11-7 show other embodiments of the present invention. In the first embodiment, the manufacturing process from FIG. 9-1 onward in which an insulating film and a silicon layer are stacked on a substrate is shown, but in the third embodiment, a method of stacking an insulating film and a silicon layer on a substrate is shown.

[0041] In FIG. 11-1, a silicon germanium layer 101 and a silicon layer 102 are sequentially stacked on a silicon substrate 100. Furthermore, an insulating film 103 is deposited on the top silicon layer, and a mask material 104 is deposited on top of that. Next, as shown in FIG. 11-2, the mask material 104 is patterned into multiple parallel strips. Using the mask material as a mask, the insulating film 103 and the stacked silicon germanium layer 101 and silicon layer 102 are etched, exposing the silicon substrate 100 at location 105. Next, a buffer film 106 is deposited, and the buffer film 106 is polished by surface polishing to expose the surface of the mask material 104, resulting in the shape shown in FIG. 11-3. Next, only the even-numbered buffer layers from the left are etched to expose the silicon substrate surface, resulting in the shape shown in FIG. 11-4. Location 107 in FIG. 11-4 has been etched. Next, the silicon germanium layer 101 is etched from the gap 107, resulting in the shape shown in FIG. 11-5, which is the A-A cross-sectional view of FIG. 11-4. Here, the silicon germanium layer at the location 108 has been removed. Next, an insulating film 109 is deposited from the gap 107. Next, the insulating film at the location 107 is etched using the mask material 104 as a mask, exposing the surface of the silicon substrate 100, resulting in the shape shown in FIG. 11-6. Next, the buffer layer at the location 106 is selectively etched, resulting in the shape shown in FIG. 11-7. After this, the mask material 104 is removed, resulting in the same shape as that shown in FIG. 9-2 of the first embodiment 1. Alternatively, although not shown, both sides of each strip-shaped laminated film are sandwiched by buffer layers, and a mask material and the laminated film thereunder are patterned in the center of each strip-shaped laminated film, and the silicon substrate is exposed where the mask material and the laminated film are patterned. The silicon germanium compound layer is selectively removed from the etched portions, and then an insulating film is embedded in the gaps created by removing the silicon germanium compound layer from the spaces between the laminated strips. Furthermore, the insulating film deposited in areas other than the gaps in the laminated strips is removed by reactive ion etching, and then the remaining buffer layer is removed, thereby completing a plurality of strip-shaped laminated films of insulating films and silicon films on the silicon substrate. Thereafter, the source and drain diffusion layers, gate insulating films, memory gates, storage gates, source lines, bit lines, word lines, and storage gate lines are sequentially formed in this laminated film, thereby manufacturing a memory cell array.

[0042] REFERENCE SIGNS LIST 1 Substrate 2 Insulating film 3 Intrinsic silicon semiconductor 4 Top insulating film 5 N-type or P-type silicon layer 6 Etched portion of first stacked silicon layer and insulating film layer 7 Etched portion of second stacked silicon layer and insulating film layer 8 Etched portion of third stacked silicon layer and insulating film layer 9 Gate insulating film 10 Gate material 11 Gate material etching mask material 12 First gate material etching region 13 Second gate material etching region 14 First gate material removal region 15 Second gate material removal region 16 Third gate material removal region 17 First insulating film remaining region 18 Second insulating film remaining region 19 Insulating film etching region 20 N-type or P-type silicon layer partially etched region 21 Metal layer formation 22 Metal layer removal region 23 Metal wiring 24 Insulating film formation region 25 Interlayer insulating film 26 Contact region 27 Storage gate wiring 28 Word line wiring 29 Interlayer insulating film 100 Silicon substrate 101 Silicon germanium compound film 102 Intrinsic silicon film 103 Top insulating film 104 Mask material 105 Stacked film etching portion 106 Buffer film 107 Buffer film removal portion 108 Silicon germanium compound film removal portion 109 Insulating film deposition portion 200 Storage gate 201 Memory gate 202 Gate insulating film 203 Channel region 204 Drain diffusion layer 205 Source diffusion layer 206 Upper bit line 207 Lower bit line 208 Common source line 209 First insulating film 210 Second insulating film 211 Substrate 212 Word line (WL) 213 Storage gate line (SGL) 300 SOI substrate 301 SiO2 layer 302 Floating body 303 Source N + Layer 304 Drain N + Layer 305: Gate conductive layer 306: Holes 307: Inversion layer 309: Gate insulating film 310: Memory cell 310-1: Memory cell in "1" state 310-2: Memory cell in "0" state

Claims

1. Two or more MOS transistors that are insulated from a substrate and arranged horizontally are stacked in multiple layers. An insulating film is laid between each transistor layer to provide insulation. Each MOS transistor forms one memory cell. Each memory cell includes one silicon channel layer, a source diffusion layer and a drain diffusion layer made of a pair of N-type or P-type silicon that sandwich the silicon channel layer. The silicon channel layer, the source diffusion layer, and the drain diffusion layer have substantially the same thickness and no step difference. The gate insulating film and the gate conductor layer form a vertical pillar so as to be shared by each stacked MOS transistor layer, penetrate from the uppermost MOS transistor layer to the lowermost MOS transistor, and the gate conductor layer is in contact with the side surface of the silicon channel layer of each layer with the gate insulating film layer interposed therebetween. The threshold value of the MOS transistor can be changed depending on whether or not a certain charge is accumulated in each silicon channel layer, and data is read by detecting the value of the threshold value. A semiconductor memory device characterized by this.

2. The source diffusion layer of each layer is connected to a source line, while the drain diffusion layer is connected to a bit line. The pair of source lines and bit lines of each layer extend in parallel. The bit lines stacked in multiple layers are insulated from each other. The source lines and bit lines are connected to the source diffusion layers and drain diffusion layers of a plurality of memory cell groups. The source lines and bit lines are connected to a column decoder that controls the bit lines and source lines of each layer at the memory cell array end. The semiconductor memory device according to claim 1, characterized by this.

3. Two different gate conductor layers of the vertical pillar sandwich two side surfaces of the silicon channel layer of the MOS transistor where the source diffusion layer and the drain diffusion layer are not arranged. An interlayer insulating film is provided on the uppermost MOS transistor. The gate conductor layers of the two different vertical pillars extend to the upper surface of the interlayer insulating film and are respectively connected to two different gate wiring layers. The two gate wiring layers extend in parallel in a direction forming an angle of 60 to 90 degrees with the bit line. The two gate wiring layers are connected to the gates of a plurality of memory cell groups and are connected to a row decoder that controls the voltage of the gate wiring at the memory cell array end. The semiconductor memory device according to claim 2, characterized by this.

4. The silicon channel layer of the MOS transistor laminated in multiple layers is sandwiched between the two gate conductor layers. One of the gate conductor layers, the memory gate, extends up to the ends of the source diffusion layer and the drain diffusion layer with the gate insulating film therebetween. The other gate conductor layer, the storage gate, is characterized in that its gate length is shorter and it does not extend up to the ends of the source diffusion layer and the drain diffusion layer. The semiconductor memory device according to claim 3.

5. The storage gate is characterized in that two vertical columnar insulating films different from the gate insulating film are separately arranged between the gate and the source diffusion layer and between the gate and the drain diffusion layer, so that the storage gate is not in direct contact with the source diffusion layer and the drain diffusion layer with the gate insulating film therebetween. The semiconductor memory device according to claim 4.

6. The length from the end of the columnar insulating film different from the gate insulating film near the storage gate to the end of the silicon channel layer in contact with the source diffusion layer or the drain diffusion layer is in the range of 10 to 20 nanometers. The semiconductor memory device according to claim 5.

7. In each layer of the MOS transistor layer, a plurality of memory cells are arranged in a row with a pair of source lines and bit lines therebetween. Two adjacent memory cells share one storage gate and have a memory cell structure with the storage gate as the axis of inversion symmetry. The memory gate is arranged at both ends of a pair of memory cells, and another pair of memory cells is arranged further inside. A vertical columnar insulating film is sandwiched between the adjacent memory gates and they are insulated from each other. The semiconductor memory device according to claim 5.

8. In each layer of the MOS transistor layer, a plurality of memory cells are arranged in a row with a pair of source lines and bit lines therebetween. Two adjacent memory cells have two different storage gates and have a memory cell structure with the columnar insulating film between the two storage gates as the axis of inversion symmetry. The memory gate is arranged at both ends of a pair of memory cells, and another pair of memory cells is arranged further inside. A columnar insulating film is sandwiched between the adjacent memory gates and they are insulated from each other. The semiconductor memory device according to claim 5.

9. The ratio of the width of the silicon channel layer sandwiched between the memory gate and the storage gate to the width between the columnar insulating film, which is different from the gate insulating film described in claim 5, and the memory gate is between 1.8 to 1 and 2.2 to 1, and the respective widths are in the range of 18 to 55 nanometers for the former and 8 to 31 nanometers for the latter. The semiconductor memory device according to claim 5, characterized in that.

10. When the source and drain diffusion layers are N-type silicon, "0" data is written simultaneously to all memory cells connected to a certain storage gate. During the writing operation of "0" data, a certain positive voltage is applied to the storage gate connected to the selected memory cell, a certain positive voltage lower than the storage gate is applied to the memory gate, and a voltage lower than the storage gate is applied to the bit line and the source line, thereby removing holes from the silicon channel layer. When the source and drain diffusion layers are P-type silicon, electrons are removed from the silicon channel layer by applying voltages with the positive and negative of the voltages in the N-type case reversed to the bit line, the memory gate, and the storage gate. The semiconductor memory device according to claim 4, characterized in that.

11. When the source and drain diffusion layers are N-type silicon, "0" data is written simultaneously to all memory cells connected to a certain storage gate. During the writing operation of "0" data, a certain voltage between 0.5 V and 1.5 V is applied to the storage gate connected to the selected memory cell, a certain voltage between 0.2 V and 0.8 V is applied to the memory gate, and 0 V is applied to the bit line and the source line, thereby removing holes from the silicon channel layer. When the source and drain diffusion layers are P-type silicon, electrons are removed from the silicon channel layer by applying voltages with the positive and negative of the voltages in the N-type case reversed to the bit line, the memory gate, and the storage gate. The semiconductor memory device according to claim 4, characterized in that.

12. When the source and drain diffusion layers are made of N-type silicon, "1" data is written into a memory cell connected to a certain memory gate. During the operation of writing "1" data, a certain positive voltage is applied to the selected memory gate, a certain negative voltage is applied to the storage gate, a certain positive voltage is applied to the bit line connected to the memory cell for writing "1" data, 0V is applied to the bit line connected to the memory cell that does not write "1", and 0V is applied to the source line, so that holes are accumulated in the silicon channel layer only in the "1" writing cell. When the source and drain diffusion layers are made of P-type silicon, by applying voltages with the positive and negative reversed from those in the N-type case to the bit line, the memory gate, and the storage gate, electrons are accumulated in the silicon channel layer. The semiconductor memory device according to claim 4, characterized in that.

13. When the source and drain diffusion layers are made of N-type silicon, "1" data is written into a memory cell connected to a certain memory gate. During the operation of writing "1" data, a certain voltage between 0.8V and 1.5V is applied to the selected memory gate, a certain voltage between -0.5V and -1.5V is applied to the storage gate, a certain voltage between 0.8V and 1.5V is applied to the bit line connected to the memory cell for writing "1" data, 0V is applied to the bit line connected to the memory cell that does not write "1", and 0V is applied to the source line, so that holes are accumulated in the silicon channel layer only in the "1" writing cell. When the source and drain diffusion layers are made of P-type silicon, by applying voltages with the positive and negative reversed from those in the N-type case to the bit line, the memory gate, and the storage gate, electrons are accumulated in the silicon channel layer. The semiconductor memory device according to claim 4, characterized in that.

14. When the source and drain diffusion layers are made of N-type silicon, when reading data from a memory cell connected to a certain memory gate, a certain positive voltage is applied to that memory gate, a certain negative voltage is applied to the storage gate paired with the memory gate, a certain positive voltage is applied to the bit line connected to the memory cell from which data is read, the bit line connected to the memory cell from which data is not read is set to 0V, 0V is applied to the source line, and the current flowing from the source line to the bit line of the memory cell from which data is read is detected. However, since the threshold value is lower in the "1" state than in the "0" state, more current flows, so the current difference is detected by a sense amplifier circuit in the column decoder to which the bit line is connected, and "0" and "1" data are read. When the source and drain diffusion layers are made of P-type silicon, by applying voltages with the positive and negative of the voltages in the N-type case reversed to the bit line, memory gate, and storage gate, the current flowing from the source line to the bit line is detected. However, since the threshold value is higher in the "1" state than in the "0" state, more current flows, so the current difference is detected by a sense amplifier circuit in the column decoder to which the bit line is connected, and "0" and "1" data are read. The semiconductor memory device according to claim 4, characterized by the above.

15. When the source and drain diffusion layers are made of N-type silicon, when reading data of a memory cell connected to a certain memory gate, a certain voltage between 0.6 V and 1.3 V is applied to the memory gate, a certain voltage between -0.5 V and -1.5 V is applied to the storage gate paired with the memory gate, a certain voltage between 0.2 V and 0.6 V is applied to the bit line connected to the memory cell from which data is read, the bit line connected to the memory cell from which data is not read is set to 0 V, 0 V is applied to the source line, and the current flowing from the source line to the bit line of the memory cell from which data is read is detected. Since the threshold value is lower in the "1" state than in the "0" state, more current flows, so the "0" and "1" data are read by detecting the current difference in the sense amplifier circuit in the column decoder to which the bit line is connected. When the source and drain diffusion layers are made of P-type silicon, by applying voltages with the positive and negative of the voltages in the N-type case reversed to the bit line, memory gate, and storage gate, the current flowing from the source line to the bit line is detected. Since the threshold value is higher in the "1" state than in the "0" state, more current flows, so the "0" and "1" data are read by detecting the current difference in the sense amplifier circuit in the column decoder to which the bit line is connected. The semiconductor memory device according to claim 4, characterized in that.

16. When rewriting the data of a certain memory cell, first write "0" to all the memory cells connected to the storage gate connected to the memory cell, and then selectively write "1" data to the memory cells connected to the memory cell. The semiconductor memory device according to claim 12, characterized in that.

17. When the source and drain diffusion layers are made of N-type silicon, when writing and reading the "0" to "1" data to / from a memory cell connected to a certain memory gate, apply 0 V to the memory gate connected to the non-selected memory cell group where data writing and reading are not performed, and apply a certain negative voltage to the storage gate. When the source and drain diffusion layers are made of P-type silicon, apply voltages with the positive and negative of the voltages in the N-type case reversed to the bit line, memory gate, and storage gate. The semiconductor memory device according to claim 16, characterized in that.

18. When the source and drain diffusion layers are made of N-type silicon, when writing and reading the "0" to "1" data to a memory cell connected to a certain memory gate, a voltage of 0 V is applied to the memory gate connected to a non-selected memory cell group that does not perform data writing and reading, and a voltage between -0.5 V and -1.5 V is applied to the storage gate. When the source and drain diffusion layers are made of P-type silicon, a voltage with the positive and negative of the voltage in the N-type case reversed is applied to the bit line, the memory gate, and the storage gate. The semiconductor memory device according to claim 16, characterized in that.

19. When the source and drain diffusion layers are made of N-type silicon, during the standby period when data writing and reading are not performed, a certain negative voltage is applied to the storage gate, and 0 V is applied to the memory gate, the bit line, and the source line. When the source and drain diffusion layers are made of P-type silicon, a voltage with the positive and negative of the voltage in the N-type case reversed is applied to the bit line, the memory gate, and the storage gate. The semiconductor memory device according to claim 16, characterized in that.

20. If the memory cell is left unwritten for a long time after data writing, the amount of charge accumulated in the silicon channel of the memory cell changes. Therefore, the data of the memory cell is read within a certain period of time and rewritten. The semiconductor memory device according to claim 16, characterized in that.

21. A method of manufacturing a semiconductor memory device according to claim 1, comprising the steps of: sequentially repeating a plurality of times the steps of depositing a silicon germanium compound layer on a silicon substrate and then depositing an intrinsic silicon semiconductor layer containing no N-type and P-type impurities; depositing an insulating film on the stacked silicon germanium compound layer and silicon layer; then depositing a mask material having etching resistance to the insulating film, silicon layer, and silicon germanium compound layer; then patterning the mask material and the underlying stacked film into a plurality of strip shapes, with the silicon substrate being exposed at the locations where the mask material and the stacked film are etched; then depositing a buffer film and exposing the surface of the mask material on the upper part of the stacked film by surface polishing to form a strip-shaped stacked film and a buffer layer embedded in the space thereof; then removing every other buffer layer embedded in the space of each strip-shaped stacked film, selectively removing the silicon germanium compound layer from the space between the stacked strips where the embedded buffer film has been removed; then embedding a certain insulating film in the void from which the silicon germanium compound layer has been removed from the space between the stacked strips, and removing the insulating film deposited outside the void portion of the stacked strip portion by reactive ion etching; and then removing the remaining buffer layer to form a stacked film of a plurality of strip-shaped insulating films and silicon films on the silicon substrate, and then sequentially forming the source, drain diffusion layer, gate insulating film, memory gate, storage gate, source line, bit line, word line, and storage gate line on this stacked film to manufacture a memory cell array.

22. A silicon germanium compound layer is deposited on a silicon substrate, and then a pure silicon semiconductor layer containing no N-type and P-type impurities is deposited sequentially a plurality of times. After that, an insulating film is deposited on the stacked silicon germanium compound layer and silicon layer. Next, a mask material having etching resistance to the insulating film, silicon layer, and silicon germanium compound layer is deposited. Then, the mask material and the underlying stacked film are patterned into a plurality of strip shapes. At the locations where the mask material and the stacked film are etched, the silicon substrate is exposed. Next, after depositing a buffer film, the surface of the mask material on the upper part of the stacked film is exposed by surface polishing to form a strip-shaped stacked film and a buffer layer embedded in the space therebetween. Then, at the central part of each strip-shaped stacked film sandwiched by the buffer layer on both sides, the mask material and the underlying stacked film are patterned. At the locations where the mask material and the stacked film are etched, the silicon substrate is exposed, and the silicon germanium compound layer is selectively removed from the etched portion. Next, a certain insulating film is embedded in the void from which the silicon germanium compound layer has been removed in the space between the stacked strips. Further, the insulating film deposited outside the void portion of the stacked strip portion is removed by reactive ion etching. Then, by removing the remaining buffer layer, a stacked film of a plurality of strip-shaped insulating films and silicon films is formed on the silicon substrate. After that, a memory cell array is manufactured by sequentially forming the source, drain diffusion layer, gate insulating film, memory gate, storage gate, source line, bit line, word line, and storage gate line on this stacked film. The method for manufacturing a semiconductor memory device according to claim 1, characterized in that.

23. A laminated film in which a plurality of the insulating film layers and the silicon layers are sequentially laminated on a substrate and an insulating film is deposited on the uppermost layer is patterned into the strip shape in which a plurality of them are arranged side by side. A silicon layer containing acceptor or donor impurities of source and drain diffusion layers is formed at an end portion of each silicon layer from a space in a short side direction between adjacent strips. Next, in order to form the gate insulating film and the gate conductor layer in a vertical column shape in the laminated film, patterning is performed from the upper surface of the laminated film. In an etched portion of the laminated film, at least the lowermost silicon film layer is removed. Next, the gate insulating film is first deposited on side surfaces and the bottom of the etched portion of the laminated film, and then the gate conductor layer is deposited. Next, the gate conductor layer and the gate insulating film are sequentially polished planar to expose the surface of the insulating film at the uppermost portion of the laminated film. Next, the gate conductor layer is patterned from the upper surface to form a memory gate and a storage gate. Next, an insulating film is filled in an etched portion of the gate conductor layer to insulate each memory gate and storage gate individually. A method of manufacturing a semiconductor memory device according to claim 21 or 22, characterized in that.

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