Electronic device and method for processing lag of image transmission, and non-transitory computer-readable storage medium

Abstract

An electronic device is described. The electronic device may comprise: at least one processor including a processing circuit; and a display including a display driving circuit and a display panel. The display driving circuit can receive a first portion of an image to be displayed on a first horizontal line of an active area of the display panel from the at least one processor, receive a pulse signal transmitted from the at least one processor in order to synchronize the time in the at least one processor for display on the display panel with the time in the display driving circuit for display on the display panel after the first portion of the image is received, and identify whether a horizontal synchronization signal (HSS) packet for a second portion of the image to be displayed on a second horizontal line of the active area after the first horizontal line is received from the at least one processor within a reference time interval from the time at which the pulse signal was received.

Description

Electronic device, method, and non-transitory computer-readable storage medium for processing a rack of image transmission

[0001] The following descriptions relate to electronic devices, methods, and non-transitory computer-readable storage media for handling lag in image transmission.

[0002] An electronic device may include a display and a processor. The display may be used to display an image generated (or acquired) by the processor. For example, an image may be transmitted from the processor to the display for displaying the image.

[0003] The above information may be provided as background art to aid in understanding the present disclosure. No claim or determination is made as to whether any of the above is applicable as prior art related to the present disclosure.

[0004] An electronic device is described. The electronic device may include at least one processor including a processing circuit. The electronic device may include a display including a display driving circuit and a display panel. The display driving circuit may be configured to receive, from the at least one processor, a first portion of an image to be displayed on a first horizontal line of an active area of ​​the display panel. The display driving circuit may be configured to receive, after the first portion of the image is received, a pulse signal transmitted from the at least one processor to synchronize a time within the at least one processor for display on the display panel with a time within the display driving circuit for display on the display panel. The display driving circuit may be configured to identify whether a horizontal synchronization signal (HSS) packet for a second portion of the image to be displayed on a second horizontal line of the active area following the first horizontal line is received from the at least one processor within a reference time interval from a time at which the pulse signal is received. The display driving circuit may be configured to perform a scan for display on the second horizontal line based on the HSS packets received within the reference time interval. The display driving circuit may be configured to postpone the scan based on the HSS packets not received within the reference time interval.

[0005] A method is described. The method can be executed in an electronic device comprising a display including a display driver circuit and a display panel, and at least one processor. The method can include an operation in which the display driver circuit receives, from the at least one processor, a first portion of an image to be displayed on a first horizontal line of an active area of ​​the display panel. The method can include an operation in which the display driver circuit, after receiving the first portion of the image, receives a pulse signal transmitted from the at least one processor to synchronize a time within the at least one processor for display on the display panel with a time within the display driver circuit for display on the display panel. The method can include an operation in which the display driver circuit identifies whether a horizontal synchronization signal (HSS) packet for a second portion of the image to be displayed on a second horizontal line of the active area subsequent to the first horizontal line is received from the at least one processor within a reference time interval from a time at which the pulse signal is received. The method may include an operation in which the display driving circuit performs a scan for display on the second horizontal line based on the HSS packet received within the reference time interval. The method may include an operation in which the scan is postponed based on the HSS packet not received within the reference time interval.

[0006] A non-transitory computer-readable storage medium is described. The non-transitory computer-readable storage medium may store one or more programs. The one or more programs may include instructions that, when executed by an electronic device including a display including a display driving circuit and a display panel and at least one processor, cause the electronic device to receive from the at least one processor a first portion of an image to be displayed on a first horizontal line of an active area of ​​the display panel. The one or more programs may include instructions that, when executed by the electronic device, cause the electronic device to receive a pulse signal transmitted from the at least one processor to synchronize a time within the at least one processor for display on the display panel with a time within the display driving circuit for display on the display panel after the first portion of the image has been received. The one or more programs may include instructions that, when executed by the electronic device, cause the electronic device to identify whether a horizontal synchronization signal (HSS) packet for a second portion of the image to be displayed on a second horizontal line of the active area following the first horizontal line is received from the at least one processor within a reference time interval from a time at which the pulse signal is received. The one or more programs may include instructions that, when executed by the electronic device, cause the electronic device to perform a scan for display on the second horizontal line based on the HSS packet received within the reference time interval.The one or more programs may include instructions that, when executed by the electronic device, cause the electronic device to postpone the scan based on the HSS packet not received within the reference time interval.

[0007] An electronic device is described. The electronic device may include a display including a display driving circuit and a display panel. The electronic device may include at least one processor including a processing circuit. The electronic device may include a memory including one or more storage media and storing instructions. The instructions, when individually or collectively executed by the at least one processor, may cause the electronic device to transmit a first portion of an image to be displayed on a first horizontal line of an active area of ​​the display panel to the display driving circuit. The instructions, when individually or collectively executed by the at least one processor, may cause the electronic device to recognize that, after transmitting the first portion of the image, it is not ready to transmit a second portion of the image to the display driving circuit to be displayed on a second horizontal line of the active area subsequent to the first horizontal line. The instructions, when individually or collectively executed by the at least one processor, may cause the electronic device, in response to the recognition, to cease transmitting a pulse signal to the display driver circuitry to synchronize a time within the at least one processor for display on the display panel with a time within the display driver circuitry for display on the display panel. The instructions, when individually or collectively executed by the at least one processor, may cause the electronic device, based on recognizing that transmission of the second portion of the image to the display driver circuitry is ready, to resume transmitting the pulse signal and, in response to the resumed transmission of the pulse signal, to transmit the second portion of the image to the display driver circuitry.

[0008] A method is described. The method can be executed in an electronic device comprising a display including a display driving circuit and a display panel, and at least one processor. The method can include transmitting a first portion of an image to be displayed on a first horizontal line of an active area of ​​the display panel to the display driving circuit. The method can include recognizing, after transmitting the first portion of the image, that it is not ready to transmit a second portion of the image to the display driving circuit to be displayed on a second horizontal line of the active area subsequent to the first horizontal line. The method can include, in response to the recognition, stopping transmitting a pulse signal to the display driving circuit to synchronize a time within the at least one processor for display on the display panel with a time within the display driving circuit for display on the display panel. The method may include resuming transmission of the pulse signal based on recognizing that transmission of the second portion of the image to the display driving circuit is ready, and transmitting the second portion of the image to the display driving circuit in accordance with the resumed transmission of the pulse signal.

[0009] A non-transitory computer-readable storage medium is described. The non-transitory computer-readable storage medium may store one or more programs. The one or more programs may include instructions that, when executed by an electronic device including a display including a display driving circuit and a display panel and at least one processor, cause the electronic device to transmit a first portion of an image to be displayed on a first horizontal line of an active area of ​​the display panel to the display driving circuit. The one or more programs may include instructions that, when executed by the electronic device, cause the electronic device to recognize that, after transmitting the first portion of the image, it is not ready to transmit a second portion of the image to the display driving circuit, to be displayed on a second horizontal line of the active area subsequent to the first horizontal line. The one or more programs may include instructions that, when executed by the electronic device, cause the electronic device, in response to the recognition, to cease transmitting a pulse signal to the display driver circuitry to synchronize a time within the at least one processor for display on the display panel with a time within the display driver circuitry for display on the display panel. The one or more programs may include instructions that, when executed by the electronic device, cause the electronic device, based on recognizing that transmission of the second portion of the image to the display driver circuitry is ready, to resume transmitting the pulse signal and, in response to the resumed transmission of the pulse signal, to transmit the second portion of the image to the display driver circuitry.

[0010] An electronic device is described. The electronic device may include a processor assembly comprising at least one first processor including a processing circuit and a second processor including a processing circuit. The electronic device may include a display including a display driving circuit and a display panel. The electronic device may include a memory including one or more storage media and storing instructions. The instructions, when executed by the processor assembly, may cause the electronic device to generate multiple images for an image to be displayed on the display panel using the at least one first processor. The instructions, when executed by the processor assembly, may cause the electronic device to identify a load of the second processor using the at least one first processor. The instructions, when executed by the processor assembly, may cause the electronic device to provide the multiple images to the second processor using the at least one first processor based on the load being less than a threshold load, generate an image in which the multiple images are synthesized using the second processor, and transmit the image generated using the second processor to the display driving circuit using the second processor. The instructions, when executed by the processor assembly, may cause the electronic device to generate the image in which the multiple images are synthesized using the at least one first processor, provide the image generated using the at least one first processor to the second processor using the at least one first processor, and transmit the image to the display driving circuit using the second processor.

[0011] A method is described. The method can be executed in an electronic device having a processor assembly including at least one first processor including a processing circuit and a second processor including a processing circuit, and a display including a display driver circuit and a display panel. The method can include generating multiple images for an image to be displayed on the display panel using the at least one first processor. The method can include identifying a load of the second processor using the at least one first processor. The method can include providing the multiple images to the second processor using the at least one first processor based on the load being less than a threshold load, generating an image in which the multiple images are synthesized using the second processor, and transmitting the image generated using the second processor to the display driver circuit using the second processor. The method may include generating the image synthesized from the multiple images using the at least one first processor based on the load being greater than the threshold load, providing the image generated using the at least one first processor to the second processor using the at least one first processor, and transmitting the image to the display driving circuit using the second processor.

[0012] A non-transitory computer-readable storage medium is described. The non-transitory computer-readable storage medium may store one or more programs. The one or more programs may include instructions that, when executed by an electronic device having a processor assembly including at least one first processor including a processing circuit and a second processor including a processing circuit, and a display including a display driver circuit and a display panel, cause the electronic device to generate multiple images for an image to be displayed on the display panel using the at least one first processor. The one or more programs may include instructions that, when executed by the electronic device, cause the electronic device to identify a load of the second processor using the at least one first processor. The one or more programs may include instructions that, when executed by the electronic device, cause the electronic device to provide the multiple images to the second processor using the at least one first processor, generate the image in which the multiple images are synthesized using the second processor, and transmit the image generated using the second processor to the display driving circuit using the second processor, based on the load being less than a threshold load.The one or more programs may include instructions that, when executed by the electronic device, cause the electronic device to generate the image in which the multiple images are synthesized using the at least one first processor based on the load being greater than the threshold load, provide the image generated using the at least one first processor to the second processor using the at least one first processor, and transmit the image to the display driving circuit using the second processor.

[0013] Figure 1 is a simplified block diagram of an exemplary electronic device.

[0014] Figure 2 illustrates an exemplary method for handling lag in image transmission using a pulse signal and a horizontal synchronization signal (HSS) packet.

[0015] FIG. 3 illustrates an exemplary method for adaptively synthesizing multiple images for an image to be displayed on a display panel to reduce lag in image transmission.

[0016] Figure 4 illustrates an exemplary method for handling lag in image transmission using retransmission requests.

[0017] Figure 5 illustrates an exemplary method for handling lag in image transmission using GRAM (graphic random access memory).

[0018] FIG. 6 is a block diagram of an electronic device within a network environment according to various embodiments.

[0019] FIG. 7 is a block diagram of a display module according to various embodiments.

[0020] An electronic device may include a display and at least one processor. The display may be used to display an image generated (or acquired) by the at least one processor. For example, an image may be transmitted from the processor to the display for displaying the image.

[0021] For example, the at least one processor may process not only the first task for image transmission but also second tasks using available resources. For example, the at least one processor may process the second tasks while processing the first task. For example, the at least one processor may allocate first resources among the resources for the first task and second resources among the resources for the second tasks to process the first task and the second tasks simultaneously. As a non-limiting example, the amount of the first resources may be reduced due to a priority of at least some of the second tasks being higher than a priority of the first task. For example, a lag in the image transmission may occur due to a reduction in the amount of the first resources. As a non-limiting example, the lag in the image transmission may occur due to an underrun of the at least one processor. As a non-limiting example, the lag in the image transmission may be caused by an underrun of a display processing unit (DPU) (e.g., including a processing circuit) within the at least one processor due to a shortage of the first resources allocated for the image transmission.

[0022] As a non-limiting example, the lag in the image transmission may reduce the visual quality of the image displayed on the display. For example, since the lag in the image transmission reduces the visual quality, first operations (or functions or features) for handling the lag in the image transmission and / or second operations for reducing the occurrence of the lag in the image transmission may be executed (or performed) within the electronic device. Components of the electronic device that are available for executing the first operations and / or the second operations are exemplified within the description of FIG. 1.

[0023] Figure 1 is a simplified block diagram of an exemplary electronic device.

[0024] Referring to FIG. 1, the electronic device (100) may be one of various forms of electronic devices, such as a laptop, smartphones having various form factors (e.g., bar-type smartphones, foldable-type smartphones, or slideable (or rollable) type smartphones), tablets, cellular phones, and other similar computing devices. The components, their relationships, and their functions illustrated in FIG. 1 are merely exemplary and do not limit the implementations described or claimed in this document. The electronic device (100) may be referred to as a mobile device, a user device, a multi-function device, a portable device, or a server.

[0025] The electronic device (100) may include at least one processor (110), a memory (120), and a display (130). The components (e.g., at least one processor (110), a memory (120), and a display (130)) are merely exemplary. For example, the electronic device (100) may include other components (e.g., a power management integrated circuitry (PMIC) or a rechargeable battery). For example, some components may be omitted from the electronic device (100). For example, some components may be integrated into a single component.

[0026] At least one processor (110) may be implemented as one or more integrated circuitry (IC) chips and may perform various data processing operations. At least one processor (110) may include at least one electrical circuit and may individually or collectively perform distributed processing of instructions (or programs, data, etc.) stored in a memory (120). At least one processor (110) may include a processor assembly including one or more processing circuits. At least one processor (110) may include any processing circuit operative to control the performance and operations of one or more components (e.g., the memory (120) and / or the display (130)) of the electronic device (100). For example, at least one processor (110) (e.g., an application processor (AP)) may be implemented as a system on chip (SoC) (e.g., a single chip or a single chipset). For example, at least one processor (110) may be implemented with multiple cores (or multiple core circuits), multiple chips, or multiple chip sets. For example, at least one processor (110) may include one or more processing circuits configured to individually and / or collectively perform various functions of the present disclosure. As a non-limiting example, at least one processor (110) may include a first processor (e.g., including a processing circuit) included in a first chip and a second processor (e.g., including a processing circuit) included in a second chip different from the first chip.

[0027] For example, at least one processor (110) may include a central processing unit (CPU) (111) (e.g., including processing circuitry) and a display processing unit (DPU) (112) (e.g., including processing circuitry). The components of the at least one processor (110) (e.g., the CPU (111) and the DPU (112)) are merely exemplary. For example, the at least one processor (110) may further include other components (e.g., a memory controller (or memory control circuit) for the memory (120), a storage controller (or storage control circuit) for the memory (120), and a graphics processing unit (GPU) (e.g., including processing circuitry)). For example, some of the components of the at least one processor (110) (e.g., the DPU (112) and the GPU) may be omitted from the at least one processor (110).

[0028] At least one processor (110) may cause other components of the electronic device (100) to perform various operations by executing instructions stored in the memory (120). For example, the CPU (111) (or central processing circuit (111)) may be configured to control other components (e.g., DPU (112)) of the at least one processor (110) based on the execution of instructions stored in the memory (120). For example, the DPU (112) (or display processing circuit (112)) may be configured to process an image obtained (or transmitted) from the CPU (111) into a format suitable for the display (130).

[0029] For example, at least one processor (110) may include at least a portion of the processor (620) of FIG. 6 or may correspond to at least a portion of the processor (620) of FIG. 6.

[0030] The memory (120) may include one or more storage media (or one or more storage devices). For example, the memory (120) may include a memory assembly including one or more storage media. For example, the one or more storage media may include a hard drive, flash memory, permanent memory such as read-only memory (ROM), semi-permanent memory such as random access memory (RAM), any other suitable type of storage (or storage assembly), or any combination thereof. The memory (120) may include a cache memory, which is one or more different types of memory used to temporarily store data for a function or feature of the electronic device (100). As a non-limiting example, the cache memory may be included within the processor (110).

[0031] The memory (120) may be fixedly embedded within the electronic device (100) or incorporated into one or more suitably types of components (e.g., a subscriber identity module (SIM) card and / or a secure digital (SD) card) that can be repeatedly inserted into and removed from the electronic device (100).

[0032] For example, the memory (120) may store one or more software applications, such as an operating system (or system software application), a firmware software application, a driver software application, a plug-in (e.g., add-in, add-on, and / or applet) software application, and / or any other suitable software applications. For example, the one or more software applications may include instructions executable by at least one processor (110). For example, the memory (120) may store instructions callable by an application programming interface (API). For example, the memory (120) may store instructions within a library.

[0033] For example, the memory (120) may store a first program (191) included in a hardware abstraction layer (HAL) to control the display (130) and a second program (192) included in a framework layer to control the display (130). For example, the first program (191) may include instructions for executing (or performing) at least some of the operations to be exemplified below. For example, the second program (192) may include instructions for executing (or performing) at least another part of the operations to be exemplified below. As a non-limiting example, the first program (191) and the second program (192) may be executable by the CPU (111) among the CPU (111) and the DPU (112).

[0034] For example, the memory (120) may store one or more third-party programs (193) that generate at least a portion of the images displayed on the display panel (132) and a user interface (UI) library (194) that is used to generate at least a portion of the images that are different from the at least a portion of the images generated by the one or more third-party programs (193). For example, the one or more third-party programs (193) may include a software application for gaming. As a non-limiting example, the one or more third-party programs (193) may generate the at least a portion of the images without using the UI library (194). For example, the UI library (194) may be referred to as a UI toolkit or a user experience (UX) toolkit. For example, the UI library (194) may be used to set visual objects and / or movements of the visual objects within a user interface provided by other programs (not shown) that are distinct from the one or more third-party programs. One or more third programs (193) and the UI library (194) may determine a frame interval. For example, the frame interval may be determined, defined, and / or obtained to execute image transmission from at least one processor (110) to the display driving circuit (131) at a time (or timing) determined by at least one processor (110) (e.g., CPU (111)) of at least one processor (110) and the display (130). The frame interval may represent the shortest time interval between times (or timings) (e.g., start times) and (e.g., end times) at which images are respectively generated using the second program (192). For example, the frame interval may represent the shortest time interval between image transmissions from the second program (192) to the first program (191).For example, the frame interval may represent the shortest time interval between image transmissions from at least one processor (110) to the display driver circuit (131) that are executed to (renew) display an image on the display panel (132). For example, the frame interval may be represented by the number of one or more emission periods that are available to provide time for transmitting an image. For example, the frame interval may represent the shortest time interval between image transmissions from at least one processor (110) to the display driver circuit (131) that are executed (or will be executed) to change an image displayed on the display panel (132). For example, because the frame interval represents the shortest time interval, the ability of the at least one processor (110) to execute image transmissions at each start time of an emission period for each of the pixels within the display panel (132) may be limited due to the frame interval. As a non-limiting example, one or more third programs (193) may be executable by the CPU (111) among the CPU (111) and the DPU (112). As a non-limiting example, the UI library (194) may be utilized by the CPU (111).

[0035] For example, the memory (120) may include at least a portion of the memory (630) of FIG. 6 or may correspond to at least a portion of the memory (630) of FIG. 6.

[0036] The display (130) can be used to display an image. The display (130) can include a display driving circuit (131) and a display panel (132) for displaying an image.

[0037] The display driving circuit (131) can receive an image from at least one processor (110) (or DPU (112)) through image transmission from at least one processor (110) (or DPU (112)) to the display driving circuit (131). The image can be transmitted from at least one processor (110) (or DPU (112)) to the display driving circuit (131) via an interface (140). For example, the interface (140) (e.g., including at least one circuit) can be usable for a first mode (e.g., a video mode of MIPI (mobile industry processor interface) DSI (display serial interface)), a second mode (e.g., a video hybrid mode of MIPI DSI), and / or a third mode (e.g., an adaptive refresh panel (ARP) of MIPI DSI), which will be exemplified below. For example, the interface (140) may operate according to the first mode, the second mode, and / or the third mode. As a non-limiting example, the interface (140) may include (or support) MIPI (mobile industry processor interface).

[0038] The display driving circuit (131) can display the image on the display panel (132) by scanning the image. For example, the display driving circuit (131) can display the image on the display panel (132) by applying (or providing) a gate voltage and a source voltage to the display panel (132) through the scan.

[0039] The display driving circuit (131) may include a graphic random access memory (GRAM) for the second mode. For example, the GRAM may be used to (at least temporarily) store an image received from at least one processor (110).

[0040] For example, the display driver circuit (131) may include at least a part of the display driver IC (730) of FIG. 7 or may correspond to at least a part of the display driver IC (730) of FIG. 7.

[0041] The display panel (132) can display an image under the control of the display driving circuit (131). For example, the display panel (132) can include sub-pixels. For example, each of the sub-pixels can include a driving transistor and a light-emitting element. For example, the display panel (132) can display an image according to a gate voltage and a source voltage from the display driving circuit (131).

[0042] Although not illustrated in FIG. 1, another interface distinct from the interface (140) may be included within the electronic device (100) to connect the display (130) (or the display driving circuit (131)) to at least one processor (110) (or DPU (112)). For example, the other interface may be used for a pulse signal that is (periodically) transmitted from the at least one processor (110) to the display driving circuit (131). The pulse signal will be exemplified within the description of FIG. 2.

[0043] As a non-limiting example, a lag in the transmission of an image from at least one processor (110) to the display driver circuit (131) may occur due to an underrun of at least one processor (110). For example, the lag in the transmission of the image may occur while the transmission of the image is in progress. For example, the display driver circuit (131) may be configured to handle the lag in the transmission of the image. For example, the display driver circuit (131) may handle the lag in the transmission of the image by performing a scan for display on a horizontal line of an active area (or displaying area) of the display panel (132) or postponing the scan using a horizontal synchronization signal (HSS) packet transmitted from at least one processor (110) to the display driver circuit (131) for the portion of the image to be displayed on the horizontal line before the portion of the image is transmitted from the at least one processor (110) to the display driver circuit (131). For example, the display driving circuit (131) can process the lag of the image by performing the scan or postponing the scan using the HSS packet and the pulse signal transmitted to the display driving circuit (131) from at least one processor (110). This operation is exemplified in the description of FIG. 2.

[0044] Figure 2 illustrates an exemplary method for handling lag in image transmission using a pulse signal and a horizontal synchronization signal (HSS) packet.

[0045] Referring to FIG. 2, at least one processor (110) may (periodically) transmit a pulse signal (200) to the display driving circuit (131). For example, the pulse signal (200) may be transmitted to the display driving circuit (131) to synchronize at least a portion of the operations of the display (130) with at least a portion of the operations of the at least one processor (110). For example, the pulse signal (200) may be transmitted to the display driving circuit (131) to synchronize a time within the at least one processor (110) for display on the display panel (132) with a time within the display driving circuit (131) for display on the display panel (132). As a non-limiting example, the pulse signal (200) may be referred to as an external synchronization signal because it is transmitted from outside the display (130) (e.g., from at least one processor (110)) to synchronize the display (130).

[0046] For example, the transmission path of the pulse signal (200) may be different from the transmission path of the image transmission. For example, the image transmission may be performed through the interface (140), and the transmission of the pulse signal (200) may be performed through the other interface.

[0047] For example, the transmission period of the pulse signal (200) may correspond to the period of a synchronization signal for at least one processor (110) used or identified for display on the display panel (132). As a non-limiting example, the transmission period may correspond to the period of a horizontal synchronization signal (HSS) for at least one processor (110) used for display on the display panel (132) (e.g., the period of the HSS packet).

[0048] As a non-limiting example, the waveform of the pulse signal (200) may be changed to indicate the period of another synchronization signal for at least one processor (110), which is distinct from the synchronization signal indicated by the transmission period and used or identified for display on the display panel (132). As a non-limiting example, the waveform may be changed according to the period of a vertical synchronization signal for at least one processor (110) and / or the period of an emission synchronization signal (e.g., indicating the timing of the emission period (or the timing of the emission signal)) for at least one processor (110). For example, the waveform of the pulse signal (200) transmitted at a start time of the horizontal synchronization signal for at least one processor (110) corresponding to a start time (or start timing) of the vertical synchronization signal for at least one processor (110) may be a second waveform different from a first waveform, which is a waveform of the pulse signal transmitted at a start time of the horizontal synchronization signal for at least one processor (110) that does not correspond to (or is different from) the start time of the vertical synchronization signal for at least one processor (110).

[0049] The display driving circuit (131) can display the image on the display panel (132) by scanning the image received from at least one processor (110) (or DPU (112)) through the image transmission. For example, the image can be displayed on the active area of ​​the display panel (132). For example, the active area can include horizontal lines (or partial areas of the active area corresponding to the horizontal lines). For example, the image can include portions of the image to be displayed on each of the horizontal lines (or the partial areas). For example, the portions of the image can correspond to each of the horizontal lines.For example, performing a scan of the image received from at least one processor (110) includes performing a first scan for displaying on a first horizontal line (e.g., corresponding to the first portion of the image) among the horizontal lines using a first portion of the image received from at least one processor (110) among the portions of the image, performing a second scan for displaying on a second horizontal line (e.g., the second horizontal line is a horizontal line following the first horizontal line and corresponding to the second portion of the image) among the horizontal lines using a second portion of the image received from at least one processor (110) among the portions of the image, … , performing an N-1 scan for displaying on an N-1 horizontal line (e.g., corresponding to the N-1-th portion of the image) among the horizontal lines using an N-1-th portion of the image (N is any natural number) received from at least one processor (110) among the portions of the image, and performing an N-th scan for displaying on an N-th horizontal line (e.g., corresponding to the N-1-th portion of the image) among the horizontal lines using an N-th portion of the image received from at least one processor (110) among the portions of the image.

[0050] For example, the display driving circuit (131) may receive a pulse signal (200) from at least one processor (110). For example, the display driving circuit (131), in response to the reception of the pulse signal (200), may identify (or confirm) (or monitor) whether an HSS packet for a K-th portion of the image (e.g., K is greater than or equal to 1 and less than N) is received from at least one processor (110) within a reference time period from a K-th time at which the pulse signal (200) is received. For example, the display driving circuit (131), based on the HSS packet for the K-th portion of the image received within the reference time period from the K-th time, may perform a K-th scan for display on the K-th horizontal line among the horizontal lines using the K-th portion of the image received from the at least one processor (110) after (or immediately after) the HSS packet for the K-th portion of the image is received. For example, the display driving circuit (131) can defer performing the K-th scan based on the HSS packet for the K-th portion of the image that is not received within the reference time interval from the K-th time. For example, the display driving circuit (131) can, after deferring the K-th scan, receive a pulse signal (200) received from at least one processor (110). For example, the display driving circuit (131) can, in response to the reception of the pulse signal (200), identify whether the HSS packet for the K-th portion of the image is received from at least one processor (110) within the reference time interval from the K+1-th time at which the pulse signal (200) is received.For example, the display driving circuit (131) can perform the K-th scan using the K-th portion of the image received from at least one processor (110) after (or immediately after) receiving the HSS packet for the K-th portion of the image based on the HSS packet for the K-th portion of the image received within the reference time interval from the K+1-th time. For example, the K-th scan postponed according to the HSS packet for the K-th portion of the image not received within the reference time interval from the K-th time can be performed according to the HSS packet for the K-th portion of the image received within the reference time interval from the K+1-th time. For example, the display driving circuit (131) can (again) postpone the K-th scan based on the HSS packet for the K-th portion of the image not received within the reference time interval from the K+1-th time.

[0051] As a non-limiting example, the display driving circuit (131) may receive a pulse signal (200) from at least one processor (110) at a first time (230-1). For example, the display driving circuit (131) may identify whether an HSS packet (210-1) for a first portion (220-1) of an image is received from at least one processor (110) within a reference time interval (240) from the first time (230-1). For example, the display driving circuit (131) may perform a scan for display on a first horizontal line among the horizontal lines of the active area using the first portion (220-1) of the image that is received after the HSS packet (210-1) is received, based on the HSS packet (210-1) received within the reference time interval (240) from the first time (230-1).

[0052] For example, the display driving circuit (131) can receive a pulse signal (200) from at least one processor (110) at a second time (230-2). For example, the display driving circuit (131) can identify whether an HSS packet (210-2) for a second portion (220-2) of the image is received from at least one processor (110) within a reference time interval (240) from the second time (230-2). For example, the display driving circuit (131) can perform a scan for displaying on a second horizontal line (e.g., next to the first horizontal line) among the horizontal lines of the active area by using the second portion (220-2) of the image that is received after the HSS packet (210-2) is received, based on the HSS packet (210-2) received within the reference time interval (240) from the second time (230-2). As a non-limiting example, the display driving circuit (131) may perform the scan for the display on the second horizontal line by performing a count for the second horizontal line based on an HSS packet (210-2) received within a reference time interval (240) from a second time (230-2) (or by counting the second horizontal line based on an HSS packet (210-2) received within a reference time interval (240) from a second time (230-2)).

[0053] For example, the display driving circuit (131) can receive a pulse signal (200) from at least one processor (110) at a third time (230-3). For example, the display driving circuit (131) can identify whether an HSS packet (210-3) for a third portion (220-3) of the image is received from at least one processor (110) within a reference time interval (240) from the third time (230-3). For example, the display driving circuit (131) can perform a scan for displaying on a third horizontal line (e.g., next to the second horizontal line) among the horizontal lines of the active area by using the third portion (220-3) of the image that is received after the HSS packet (210-3) is received, based on the HSS packet (210-3) received within the reference time interval (240) from the third time (230-3). As a non-limiting example, the display driving circuit (131) may perform the scan for the display on the third horizontal line by performing a count for the third horizontal line based on an HSS packet (210-3) received within a reference time interval (240) from a third time (230-3) (or by counting the third horizontal line based on an HSS packet (210-3) received within a reference time interval (240) from a third time (230-3)).

[0054] For example, the display driving circuit (131) can receive a pulse signal (200) from at least one processor (110) at a fourth time (230-4). For example, the display driving circuit (131) can identify whether an HSS packet (210-4) for a fourth portion (220-4) of the image is received from at least one processor (110) within a reference time interval (240) from the fourth time (230-4). For example, the display driving circuit (131) can perform a scan for displaying on a fourth horizontal line (e.g., next to the third horizontal line) among the horizontal lines of the active area by using the fourth portion (220-4) of the image that is received after the HSS packet (210-4) is received, based on the HSS packet (210-4) received within the reference time interval (240) from the fourth time (230-4). As a non-limiting example, the display driving circuit (131) can perform the scan for the display on the fourth horizontal line by performing a count for the fourth horizontal line based on an HSS packet (210-4) received within a reference time interval (240) from a fourth time (230-4) (or by counting the fourth horizontal line based on an HSS packet (210-4) received within a reference time interval (240) from a fourth time (230-4)).

[0055] For example, the display driving circuit (131) may receive a pulse signal (200) from at least one processor (110) at a fifth time (230-5). For example, the display driving circuit (131) may identify whether, within a reference time interval (240) from the fifth time (230-5), an HSS packet (210-5) for a fifth portion (220-5) of the image is received from at least one processor (110). As a non-limiting example, an underrun of at least one processor (110) may occur after the fourth portion (220-4) of the image is transmitted from at least one processor (110) to the display driving circuit (131). For example, a lag in image transmission from at least one processor (110) to the display driving circuit (131) may occur due to the underrun of at least one processor (110). For example, the HSS packet (210-5) may not be transmitted from at least one processor (110) to the display driving circuit (131) within a reference time interval (240) from the fifth time (230-5), depending on the lag of the image transmission. For example, the display driving circuit (131) may postpone a scan for display on a fifth horizontal line (e.g., next to the fourth horizontal line) among the horizontal lines, based on an HSS packet (210-5) that is not received within the reference time interval (240) from the fifth time (230-5). As a non-limiting example, the display driving circuit (131) may postpone the scan for the display on the fifth horizontal line by refraining from counting the fifth horizontal line based on an HSS packet (210-5) not received within a reference time interval (240) from the fifth time (230-5) (or by not counting the fifth horizontal line based on an HSS packet (210-5) not received within a reference time interval (240) from the fifth time (230-5)).

[0056] Although FIG. 5 illustrates an example in which an HSS packet (210-5) is not transmitted due to an underrun of at least one processor (110), this is merely exemplary. The underrun of at least one processor (110) may also occur before the fifth portion (220-5) of the image is transmitted based on transmitting the HSS packet (210-5). As a non-limiting example, the display driver circuit (131) may postpone the scan for the display on the fifth horizontal line by refraining from counting the fifth horizontal line based on the fifth portion (220-5) of the image not being received after receiving the HSS packet (210-5) (or by not counting the fifth horizontal line based on the HSS packet (210-5) not being received within the reference time interval (240) from the fifth time (230-5)).

[0057] For example, the display driving circuit (131) may receive a pulse signal (200) from at least one processor (110) at a sixth time (230-6). For example, the display driving circuit (131) may identify whether, within a reference time interval (240) from the sixth time (230-6), an HSS packet (210-5) for a fifth portion (220-5) of the image is received from at least one processor (110). As a non-limiting example, the underrun of at least one processor (110) caused after transmitting the fourth portion (220-4) of the image may be maintained. For example, the lag in the image transmission may be maintained due to the underrun of at least one processor (110) maintained after transmitting the fourth portion (220-4) of the image. For example, the HSS packet (210-5) may not be transmitted from at least one processor (110) to the display driving circuit (131) within a reference time interval (240) from the sixth time (230-6), depending on the lag of the image transmission. For example, the display driving circuit (131) may postpone the scan for the display on the fifth horizontal line based on the HSS packet (210-5) not being received within the reference time interval (240) from the sixth time (230-6). As a non-limiting example, the display driving circuit (131) may postpone the scan for the display on the fifth horizontal line by refraining from counting for the fifth horizontal line based on an HSS packet (210-5) not received within a reference time interval (240) from the sixth time (230-6) (or by not counting the fifth horizontal line based on an HSS packet (210-5) not received within a reference time interval (240) from the sixth time (230-6)).

[0058] For example, the display driving circuit (131) may receive a pulse signal (200) from at least one processor (110) at a seventh time (230-7). For example, the display driving circuit (131) may identify whether to receive an HSS packet (210-5) for a fifth portion (220-5) of the image from at least one processor (110) within a reference time interval (240) from the seventh time (230-7). As a non-limiting example, the underrun of the at least one processor (110) that occurred after transmitting the fourth portion (220-4) of the image may be released. For example, the at least one processor (110) may transmit the HSS packet (210-5) within the reference time interval (240) from the seventh time (230-7) according to the release of the underrun of the at least one processor (110). For example, the display driving circuit (131) can perform the scan for the display on the fifth horizontal line of the active area by using the fifth portion (220-5) of the image received after the HSS packet (210-5) is received, based on the HSS packet (210-5) received within the reference time interval (240) from the seventh time (230-7). As a non-limiting example, the display driving circuit (131) can perform the scan for the display on the fifth horizontal line by performing a count for the fifth horizontal line based on the HSS packet (210-5) received within the reference time interval (240) from the seventh time (230-7) (or by counting the fifth horizontal line based on the HSS packet (210-5) received within the reference time interval (240) from the seventh time (230-7)).

[0059] For example, the display driving circuit (131) may postpone a scan (e.g., the scan for the display on the fifth horizontal line) performed using a portion of the image (e.g., the fifth portion (220-5) of the image) transmitted together with the HSS packet based on an HSS packet (e.g., the HSS packet (210-5)) that is not received within a reference time interval (240) from a time (e.g., a fifth time (230-5)) at which the pulse signal (200) is received. For example, the display driving circuit (131) may postpone the scan until the HSS packet (e.g., the HSS packet (210-5)) is received from at least one processor (110) within a reference time interval (240) from another time (e.g., a seventh time (230-7)) at which the pulse signal (200) is received.

[0060] For example, the display driving circuit (131) may receive a pulse signal (200) from at least one processor (110) at an eighth time (230-8). For example, the display driving circuit (131) may identify whether an HSS packet (210-6) for a sixth portion (220-6) of the image is received from at least one processor (110) within a reference time interval (240) from the eighth time (230-8). For example, the display driving circuit (131) may perform a scan for displaying on a sixth horizontal line (e.g., next to the fifth horizontal line) among the horizontal lines of the active area by using the sixth portion (220-6) of the image that is received after the HSS packet (210-6) is received, based on the HSS packet (210-6) received within the reference time interval (240) from the eighth time (230-8). As a non-limiting example, the display driving circuit (131) can perform the scan for the display on the sixth horizontal line by performing a count for the sixth horizontal line based on an HSS packet (210-6) received within a reference time interval (240) from the eighth time (230-8) (or by counting the sixth horizontal line based on an HSS packet (210-6) received within a reference time interval (240) from the eighth time (230-8)).

[0061] For example, the time length of the active portion of the vertical synchronization signal targeted for display of the image before the underrun of at least one processor (110) is caused may correspond to the time interval (260). For example, the at least one processor (110) may extend the time length of the active portion of the vertical synchronization signal to compensate for the lag of the image transmission caused by the underrun of the at least one processor (110). For example, the at least one processor (110) may transmit the HSS packet (210-K) for the Kth portion (220-K) of the image (K is a natural number greater than or equal to 7) to the display driving circuit (131) at a time (261) corresponding to the end time of the time interval (260) due to the underrun of the at least one processor (110).

[0062] For example, the display driving circuit (131) can receive a pulse signal (200) from at least one processor (110) at an M-th time (230-M) (M is a natural number greater than K). For example, the display driving circuit (131) can identify whether an HSS packet (210-K) for a K-th portion (220-K) of the image is received from at least one processor (110) within a reference time interval (240) from the M-th time (230-M). For example, the display driving circuit (131) can perform a scan for display on the K-th horizontal line among the horizontal lines of the active area by using the K-th portion (220-K) of the image that is received after the HSS packet (210-K) is received, based on the HSS packet (210-K) received within the reference time interval (240) from the M-th time (230-M). As a non-limiting example, the display driving circuit (131) can perform the scan for the display on the K-th horizontal line by performing a count for the K-th horizontal line based on an HSS packet (210-K) received within a reference time interval (240) from the M-th time (230-M) (or by counting the K-th horizontal line based on an HSS packet (210-K) received within a reference time interval (240) from the M-th time (230-M)).

[0063] For example, at least one processor (110) may transmit, to the display driver circuit (131), a vertical synchronization signal (VSS) packet (272) for another image following the image (e.g., which may be at least partially different from the image or may be identical to the image) based on completing the transmission of the image to the display driver circuit (131) through the image transmission. For example, the time length of the active period of the vertical synchronization signal for the image, which is represented by the VSS packet (271) for the image and the VSS packet (272) for the image, may correspond to a time interval (270). For example, at least one processor (110) may extend the time length of the active period of the vertical synchronization signal according to the underrun of the at least one processor (110). For example, the extended time length may correspond to a time interval (270) that is longer than the time interval (260).

[0064] As a non-limiting example, at least one processor (110) may change the width of the pulse signal (200) to indicate a start time (or start timing) of the vertical synchronization signal. For example, at least one processor (110) may set the width of the pulse signal (200-1) transmitted to indicate a time at which the VSS packet (271) is transmitted and the width of the pulse signal (200-2) transmitted to indicate a time at which the VSS packet (272) is transmitted to a second width (282). As a non-limiting example, the second width (282) may be different from the first width (281), which is the width of the pulse signal (200) transmitted at a time at which the VSS packet (e.g., the VSS packet (271) and the VSS packet (272)) is not transmitted. As a non-limiting example, the second width (282) may be wider than the first width (281). For example, the time for changing the width of the pulse signal (200) can be adjusted by at least one processor (110) according to postponing the scan that is executed due to the lag of the image transmission. For example, at least one processor (110) can maintain the width of the pulse signal (200) transmitted to be a first width (281) to indicate a time (261) corresponding to the end time of the time interval (260), such as a state (283). For example, at least one processor (110) can change the width of the pulse signal (200-2) transmitted to be a first width (281) to a second width (282) to indicate the time at which the VSS packet (272) is transmitted. For example, the time for performing the change from the first width (281) to the second width (282) can be changed from the time (261).

[0065] As a non-limiting example, at least one processor (110) may stop transmitting the pulse signal (200) to the display driving circuit (131) based on (or in response to) recognizing that the display driving circuit (131) is not ready to transmit a portion of an image (e.g., a fifth portion (220-5) of the image) to be displayed on a horizontal line (e.g., the fifth horizontal line) of the active area of ​​the display panel (132). For example, the at least one processor (110) may stop transmitting the pulse signal (200) to the display driving circuit (131) in response to the underrun of the at least one processor (110). However, the present invention is not limited thereto. For example, at least one processor (110) may transmit, in response to the underrun of the at least one processor (110), a pulse signal (200) having a third width different from the first width (281) and the second width (282) to the display driving circuit (131). For example, the third width may indicate the underrun of the at least one processor (110). As a non-limiting example, the pulse signal (200) having the third width may be transmitted at a transmission time (or transmission timing) of an HSS packet after (or immediately after) the underrun of the at least one processor (110). As a non-limiting example, the pulse signal (200) having the third width may be transmitted at a transmission time of a VSS (vertical synchronization signal) packet after (or immediately after) the underrun of the at least one processor (110). As a non-limiting example, a pulse signal (200) having the third width may be transmitted to avoid counting for the fifth horizontal line.

[0066] For example, at least one processor (110) may, in response to recognizing that the fifth portion (220-5) of the image is not ready to be transmitted to the display driving circuit (131), cease transmitting the pulse signal (200) to the display driving circuit (131), as in state (284). For example, at least one processor (110) may, in response to recognizing that the fifth portion (220-5) of the image is ready to be transmitted to the display driving circuit (131), resume transmitting the pulse signal (200), as in state (285). For example, at least one processor (110) may transmit the fifth portion (220-5) of the image to the display driving circuit (131) in response to the resumed transmitting of the pulse signal (200). For example, at least one processor (110) can transmit an HSS packet (210-5) to the display driving circuit (131) within a reference time interval (240) from a seventh time (230-7) at which the pulse signal (200) is transmitted to the display driving circuit (131) in response to the resumed transmission of the pulse signal (200), and can transmit a fifth portion (220-5) of the image to the display driving circuit (131) in response to transmitting the HSS packet (210-5).

[0067] For example, the display driver circuit (131) may postpone the scan for the display on the fifth horizontal line based on not receiving the pulse signal (200) from at least one processor (110). As a non-limiting example, the display driver circuit (131) may postpone the scan by refraining from counting for the fifth horizontal line based on not receiving the pulse signal (200) from at least one processor (110). For example, the display driver circuit (131) may postpone the scan until an HSS packet (e.g., an HSS packet (210-5)) is received from at least one processor (110) within a reference time interval (240) from a seventh time (230-7) at which the pulse signal (200) is received from at least one processor (110) according to the resumed transmission.

[0068] For example, the display driving circuit (131) can perform the scan based on the HSS packet (210-5) received within the reference time interval (240) from the seventh time (230-7) at which the pulse signal (200) was received from at least one processor (110) according to the resumed transmission. For example, the display driving circuit (131) can perform the scan by performing a count for the fifth horizontal line based on the HSS packet (210-5) received within the reference time interval (240) from the seventh time (230-7) at which the pulse signal (200) was received from at least one processor (110) according to the resumed transmission.

[0069] As described above, the electronic device (100) can handle the lag of image transmission from at least one processor (110) to the display driving circuit (131) by determining whether to perform a scan for display on a horizontal line of the active area of ​​the display panel (132) using the pulse signal (200) and the HSS packet.

[0070] Referring back to FIG. 1, as a non-limiting example, the lag in the image transmission may be caused by an underrun of the DPU (112). For example, at least one processor (110) may reduce the lag in the image transmission by executing a portion of the operations executed using the DPU (112) using at least one component (e.g., the CPU (111) and / or the GPU) of at least one processor (110) other than the DPU (112). Such an operation is exemplified in the description of FIG. 3.

[0071] FIG. 3 illustrates an exemplary method for adaptively synthesizing multiple images for an image to be displayed on a display panel to reduce lag in image transmission.

[0072] Referring to FIG. 3, at least one first processor (311) may include the CPU (111) exemplified in the description of FIG. 1 and / or the GPU exemplified in the description of FIG. 1. The second processor (312) may include the DPU (112) exemplified in the description of FIG. 1. As a non-limiting example, at least one first processor (311) and the second processor (312) may be included in a processor assembly.

[0073] For example, at least one first processor (311) may generate (or obtain) multiple images (301) for an image (302) to be displayed on a display panel (132). For example, the multiple images (301) may be used for multiple layers of an image (302) that overlap each other.

[0074] For example, at least one first processor (311) can identify (or estimate) (or determine) (or monitor) (or verify) (or recognize) the load of the second processor (312). For example, at least one first processor (311) can identify the load of the second processor (312) to reduce the occurrence of underruns of the second processor (312). As a non-limiting example, identifying the load can be executed using the first program (191) illustrated in the description of FIG. 1.

[0075] For example, at least one first processor (311) may compare the load with a threshold load. For example, the comparison between the load and the threshold load may be performed to determine whether to transmit the multiple images (301) to the second processor (312). For example, the load being greater than the threshold load may indicate a relatively high probability of an underrun of the second processor (312), and the load being less than the threshold load (or the load being less than or equal to the threshold load) may indicate a relatively low probability of an underrun of the second processor (312). As a non-limiting example, the comparison between the load and the threshold load may be performed using the first program (191).

[0076] For example, at least one first processor (311) may perform (331) providing multiple images (301) to a second processor (312) based on the load being less than the threshold load. As a non-limiting example, at least one first processor (311) may perform (331) providing multiple images (301) to the second processor (312) by storing the multiple images (301) in a memory (120) (e.g., a dynamic random access memory (DRAM)) in response to the load being less than the threshold load. For example, the second processor (312) may generate an image (302) in which the multiple images (301) are synthesized based on obtaining the multiple images (301) from the memory (120). For example, the image (302) may be generated using the multiple images (301), such as in the state (321). For example, the second processor (312) can perform (333) transmitting the image (302) to the display driving circuit (131).

[0077] For example, at least one first processor (311) can generate an image (302) in which multiple images (301) are synthesized based on the load being greater than the threshold load. For example, the image (302) can be generated using the multiple images (301), such as in the state (322). For example, at least one first processor (311) can perform the synthesis of the multiple images (301) instead of the second processor (312) based on the load being greater than the threshold load. For example, at least one first processor (311) can provide the image (302) in which the multiple images (301) are synthesized to the second processor (312) (332). As a non-limiting example, at least one first processor (311) may perform (332) providing an image (302) to a second processor (312) by storing the image (302) synthesized from multiple images (301) in the memory (120). For example, the second processor (312) may perform (334) transmitting the image (302) to the display driving circuit (131) based on obtaining the image (302) from the memory (120).

[0078] As a non-limiting example, at least one first processor (311) may change the speed of a clock for a second processor (312) from a first speed to a second speed higher than the first speed based on the load being greater than the threshold load, and provide (331) the multiple images (301) to the second processor (312). For example, the second processor (312) may acquire the multiple images (301) according to the second speed, generate an image (302) in which the multiple images (301) are synthesized, and transmit (333) the image (302) to the display driving circuit (131).

[0079] As a non-limiting example, at least one first processor (311) may reduce the speed of the interface (140) based on the load being greater than the threshold load. For example, at least one first processor (311) may reduce the occurrence of underruns of the second processor (312) by reducing the speed of the interface (140) to increase the bandwidth for one horizontal line based on the load being greater than the threshold load.

[0080] As described above, the electronic device (100) can reduce the occurrence of underruns of the second processor (312) by monitoring the load of the second processor (312) (e.g., DPU (112)). The occurrence of lag in the image transmission to the display driving circuit (131) can be reduced by reducing the occurrence of underruns of the second processor (312).

[0081] Referring back to FIG. 1, as a non-limiting example, the DPU (112) (or the display driving circuit (131)) can identify (or monitor) (or detect) (or confirm) the occurrence of a lag in the image transmission (or the occurrence of an underrun of the DPU (112)). For example, the DPU (112) (or the display driving circuit (131)) can, based on (or in response to) the occurrence of the lag in the image transmission, transmit to the CPU (111) (or the DPU (112)) a request for retransmission (or repeated transmission) of an image associated with the lag in the image transmission. For example, the electronic device (100) can process the lag in the image transmission through the request. This operation is exemplified within the description of FIG. 4.

[0082] Figure 4 illustrates an exemplary method for handling lag in image transmission using retransmission requests.

[0083] Referring to FIG. 4, the DPU (112) may transmit an image A to be displayed on the display panel (132) to the display driver circuit (131) as indicated by an arrow (450) through image transmission from at least one processor (110) (or DPU (112)) to the display driver circuit (131). As a non-limiting example, unlike a portion (411) of the image A that is transmitted to the display driver circuit (131), another portion (412) (or the remaining portion (412)) of the image A may not be transmitted to the display driver circuit (131). For example, the other portion (412) of the image A may not be transmitted to the display driver circuit (131) within the time interval of the vertical synchronization signal targeted for the image A due to an underrun of the DPU (112). For example, a lag in the image transmission for the image A may be caused by the underrun of the DPU (112).

[0084] For example, the DPU (112) (or the display driving circuit (131)) (or a tiny core within the CPU (111)) (e.g., used to detect an underrun of the DPU (112) and used for a state for a lower power state of the CPU (111)) can detect (or identify) (or recognize) (or monitor) (or confirm) the underrun (or the lag in the image transmission) of the DPU (112), as indicated by the state (441). For example, the DPU (112) (or the display driving circuit (131)) can, in response to the detection, transmit a request (400) for repeated transmission of image A to the CPU (111) (or to at least one processor (110)).

[0085] For example, the DPU (112) may perform the repeated transmission of image A acquired from the CPU (111) (or memory (120)) in response to a request (400), as indicated by arrow (431). For example, the tiny core may cause the DPU (112) to perform the repeated transmission of image A in response to a request (400) caused in response to the detection. As a non-limiting example, at least a portion of one or more cores within the CPU (111) distinct from the tiny core may be maintained in a sleep or idle state, unlike the tiny core utilized for the repeated transmission of image A.

[0086] As a non-limiting example, while the above repeated transmission of image A is performed (or while the repeated display of image A is performed on the display panel (132)), an image B following image A may be generated.

[0087] For example, the DPU (112) may transmit an image B to be displayed on the display panel (132) as indicated by an arrow (451) through the image transmission to the display driver circuit (131). As a non-limiting example, unlike a portion (413) of the image B that is transmitted to the display driver circuit (131), another portion (414) (or the remaining portion (414)) of the image B may not be transmitted to the display driver circuit (131). For example, the other portion (414) of the image B may not be transmitted to the display driver circuit (131) within the time interval of the vertical synchronization signal targeted for the image B due to an underrun of the DPU (112). For example, a lag in the image transmission for the image B may be caused by the underrun of the DPU (112).

[0088] For example, the DPU (112) (or the display driving circuit (131)) may detect the underrun (or the lag in the image transmission) of the DPU (112), as indicated by the state (442). For example, in response to the detection, the DPU (112) (or the display driving circuit (131)) may transmit a request (400) for repeated transmission of image B to the CPU (111) (or at least one processor (110)).

[0089] For example, while transmission of image B (or abnormal transmission of image B) is performed (or while display of image B (abnormal display of image B) is performed on the display panel (132)), image C following image B can be generated.

[0090] For example, the time interval (460) may be available for displaying image C generated while the repeated display of image B and the transmission of image B are being performed according to the request (400). For example, since the repeated display of image B is for another part (414) of image B that is not transmitted to the display driving circuit (131), the priority of the display of image C may be higher than the priority of the repeated display of image B. For example, since an abnormal display caused on the display panel (132) due to another part (414) of image B that is not transmitted to the display driving circuit (131) is compensated for according to the display of image C, the display of image C among the repeated display of image B according to the request (400) and the repeated display of image C may be performed within the time interval (460).

[0091] For example, the DPU (112) may transmit image C to be displayed on the display panel (132) to the display driving circuit (131), as indicated by arrow (452). For example, the DPU (112) may refrain from repeated transmission of image B for the repeated display of image B within a time interval (460), as indicated by arrow (432).

[0092] Although FIG. 4 illustrates an example in which the repeated transmission of image A is executed in response to the underrun of the DPU (112), this is merely exemplary. For example, the repeated transmission of image A may be replaced by the transmission of a pre-stored image (e.g., a black image). For example, the DPU (112) (or the display driver circuit (131)) (or the tiny core) may detect (or identify) (or recognize) (or monitor) (or confirm) the underrun (or the lag in the image transmission) of the DPU (112), as indicated by the state (441). For example, the DPU (112) may, in response to the detection, perform the transmission of the pre-stored image. For example, the tiny core may, in response to the detection, cause the DPU (112) to perform the transmission of the pre-stored image. As a non-limiting example, at least some of the one or more cores within the CPU (111) distinct from the tiny core may be maintained in a sleep or idle state, unlike the tiny core used for the repeated transmission of image A.

[0093] As described above, the electronic device (100) can handle the lag in the image transmission to the display driving circuit (131) by using a request (400) that causes repeated transmission of the image.

[0094] Referring back to FIG. 1, as a non-limiting example, the display driver circuit (131) may include the GRAM for the second mode. For example, the display driver circuit (131) may process the lag of the image transmission using the GRAM. This operation is exemplified in the description of FIG. 5.

[0095] Figure 5 illustrates an exemplary method for handling lag in image transmission using GRAM (graphic random access memory).

[0096] Referring to FIG. 5, the active area of ​​the display panel (132) may include the horizontal lines (or the sub-areas of the active area corresponding to the horizontal lines). For example, the image may include portions of the image to be displayed on each of the horizontal lines (or the sub-areas). For example, the portions of the image may be sequentially transmitted to the display driving circuit (131) through image transmission from at least one processor (110) to the display driving circuit (131).

[0097] For example, the display driving circuit (131) can postpone scanning of the portions of the image sequentially received from at least one processor (110) within a reference time interval from a start time of the image transmission for displaying the image. For example, the display driving circuit (131) can store the portions of the image sequentially received from at least one processor (110) within the reference time interval in the GRAM. For example, the display driving circuit (131) can start (or initiate) scanning for displaying the image on the display panel (132) on a condition that the reference time interval elapses.

[0098] For example, the display driving circuit (131) may postpone sequentially scanning the portions of the image received from at least one processor (110) until the reference time interval has elapsed and store the portions of the image received from at least one processor (110) in the GRAM. For example, the display driving circuit (131) may sequentially scan the portions of the image stored in the GRAM based on identifying that the reference time interval has elapsed.

[0099] For example, the display driving circuit (131) can sequentially receive the first part (500-1) of the image, the second part (500-2) of the image, the third part (500-3) of the image, the fourth part (500-4) of the image, ..., and the Kth part (500-K) of the image from at least one processor (110) through the image transmission. For example, the display driving circuit (131) can sequentially store the first part (500-1) of the image to the Kth part (500-K) of the image, which are sequentially received from at least one processor (110), in the GRAM, as indicated by the state (510).

[0100] For example, the display driving circuit (131) may scan the first portion (500-1) of the image within the GRAM, as indicated by arrow (511), based on the elapsed time of the reference time interval from the start time of reception of the first portion (500-1) of the image. The first portion (500-1) of the image may be removed (or discarded) from the GRAM according to the scanning of the first portion (500-1) of the image.

[0101] For example, the display driving circuit (131) can store the K+1-th portion (500-(K+1)) of the image received from at least one processor (110) in the GRAM. For example, the state of the GRAM can be changed from state (510) to state (520) by removing the first portion (500-1) of the image from the GRAM and storing the K+1-th portion (500-(K+1)) of the image in the GRAM.

[0102] For example, the display driving circuit (131) can scan the second portion (500-2) of the image within the GRAM, as indicated by arrow (521). The second portion (500-2) of the image can be removed from the GRAM according to the scanning of the second portion (500-2) of the image.

[0103] For example, after the K+1-th portion (500-(K+1)) of the image is transmitted to the display driving circuit (131) via the image transmission, an underrun of at least one processor (110) may occur. For example, a lag in the image transmission may be caused by the underrun of at least one processor (110). For example, the transmission of the K+2-th portion (500-(K+2)) of the image may not be executed at a target time due to the underrun of at least one processor (110).

[0104] For example, the state of the GRAM may change from state (520) to state (530) upon transmission of the second portion (500-2) of the image removed from the GRAM and the K+2 portion (500-(K+2)) of the image that was not executed by the underrun of at least one processor (110).

[0105] For example, the display driving circuit (131) can scan the third portion (500-3) of the image within the GRAM, as indicated by arrow (531). The third portion (500-3) of the image can be removed from the GRAM according to the scanning of the third portion (500-3) of the image.

[0106] For example, the underrun of at least one processor (110) may be maintained. For example, the transmission of the K+2-th portion (500-(K+2)) of the image may not be executed at the target time due to the underrun of at least one processor (110).

[0107] For example, the state of the GRAM may change from state (530) to state (540) upon transmission of a third portion (500-3) of the image removed from the GRAM and a K+2-th portion (500-(K+2)) of the image that was not executed by the underrun of at least one processor (110).

[0108] For example, the display driving circuit (131) can scan the fourth portion (500-4) of the image within the GRAM, as indicated by arrow (541). The fourth portion (500-4) of the image can be removed from the GRAM according to the scanning of the fourth portion (500-4) of the image.

[0109] For example, the underrun of at least one processor (110) can be released. For example, the display driving circuit (131) can store the K+2-th part (500-(K+2)) of the image received from at least one processor (110) in the GRAM. For example, the state of the GRAM can be changed from state (540) to state (550) by removing the fourth part (500-4) of the image from the GRAM and storing the K+2-th part (500-(K+2)) of the image in the GRAM.

[0110] As described above, the electronic device (100) can maintain the quality of an image displayed on the display panel (132) despite the underrun of at least one processor (110) by performing a delayed scan of the display driving circuit (131) using the GRAM.

[0111] The above exemplified operations can be executed by the electronic device (601) exemplified in the description below.

[0112] FIG. 6 is a block diagram of an electronic device (601) within a network environment (600) according to various embodiments. Referring to FIG. 6, in the network environment (600), the electronic device (601) may communicate with the electronic device (602) via a first network (698) (e.g., a short-range wireless communication network), or may communicate with at least one of the electronic device (604) or the server (608) via a second network (699) (e.g., a long-range wireless communication network). In one embodiment, the electronic device (601) may communicate with the electronic device (604) via the server (608). According to one embodiment, the electronic device (601) may include a processor (620), a memory (630), an input module (650), an audio output module (655), a display module (660), an audio module (670), a sensor module (676), an interface (677), a connection terminal (678), a haptic module (679), a camera module (680), a power management module (688), a battery (689), a communication module (690), a subscriber identification module (696), or an antenna module (697). In some embodiments, the electronic device (601) may omit at least one of these components (e.g., the connection terminal (678)), or may have one or more other components added. In some embodiments, some of these components (e.g., the sensor module (676), the camera module (680), or the antenna module (697)) may be integrated into one component (e.g., the display module (660)).

[0113] The processor (620) may, for example, execute software (e.g., a program (640)) to control at least one other component (e.g., a hardware or software component) of the electronic device (601) connected to the processor (620) and perform various data processing or operations. According to one embodiment, as at least a part of the data processing or operations, the processor (620) may store commands or data received from other components (e.g., a sensor module (676) or a communication module (690)) in a volatile memory (632), process the commands or data stored in the volatile memory (632), and store result data in a non-volatile memory (634). According to one embodiment, the processor (620) may include a main processor (621) (e.g., a central processing unit or an application processor) or an auxiliary processor (623) (e.g., a graphics processing unit, a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor) that can operate independently or together with the main processor (621). For example, when the electronic device (601) includes the main processor (621) and the auxiliary processor (623), the auxiliary processor (623) may be configured to use less power than the main processor (621) or to be specialized for a given function. The auxiliary processor (623) may be implemented separately from the main processor (621) or as a part thereof.

[0114] The auxiliary processor (623) may control at least a portion of functions or states associated with at least one component (e.g., a display module (660), a sensor module (676), or a communication module (690)) of the electronic device (601), for example, on behalf of the main processor (621) while the main processor (621) is in an inactive (e.g., sleep) state, or together with the main processor (621) while the main processor (621) is in an active (e.g., application execution) state. In one embodiment, the auxiliary processor (623) (e.g., an image signal processor or a communication processor) may be implemented as a part of another functionally related component (e.g., a camera module (680) or a communication module (690)). In one embodiment, the auxiliary processor (623) (e.g., a neural network processing unit) may include a hardware structure specialized for processing artificial intelligence models. The artificial intelligence models may be generated through machine learning. This learning can be performed, for example, on the electronic device (601) itself where the artificial intelligence model is executed, or can be performed through a separate server (e.g., server (608)). The learning algorithm can include, for example, supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning, but is not limited to the examples described above. The artificial intelligence model can include multiple artificial neural network layers.The artificial neural network may be one of a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q-network, or a combination of two or more of the above, but is not limited to the examples described above. In addition to, or alternatively to, a hardware structure, an artificial intelligence model may include a software structure.

[0115] The memory (630) can store various data used by at least one component (e.g., the processor (620) or the sensor module (676)) of the electronic device (601). The data can include, for example, software (e.g., the program (640)) and input data or output data for commands related thereto. The memory (630) can include a volatile memory (632) or a non-volatile memory (634).

[0116] The program (640) may be stored as software in the memory (630) and may include, for example, an operating system (642), middleware (644), or an application (646).

[0117] The input module (650) can receive commands or data to be used in a component of the electronic device (601) (e.g., a processor (620)) from an external source (e.g., a user) of the electronic device (601). The input module (650) can include, for example, a microphone, a mouse, a keyboard, a key (e.g., a button), or a digital pen (e.g., a stylus pen).

[0118] The audio output module (655) can output audio signals to the outside of the electronic device (601). The audio output module (655) can include, for example, a speaker or a receiver. The speaker can be used for general purposes, such as multimedia playback or recording playback. The receiver can be used to receive incoming calls. In one embodiment, the receiver can be implemented separately from the speaker or as part of the speaker.

[0119] The display module (660) can visually provide information to an external party (e.g., a user) of the electronic device (601). The display module (660) may include, for example, a display, a holographic device, or a projector and a control circuit for controlling the device. In one embodiment, the display module (660) may include a touch sensor configured to detect a touch, or a pressure sensor configured to measure the intensity of a force generated by the touch.

[0120] The audio module (670) can convert sound into an electrical signal, or vice versa, convert an electrical signal into sound. According to one embodiment, the audio module (670) can acquire sound through the input module (650), output sound through the sound output module (655), or an external electronic device (e.g., electronic device (602)) (e.g., speaker or headphone) directly or wirelessly connected to the electronic device (601).

[0121] The sensor module (676) can detect the operating status (e.g., power or temperature) of the electronic device (601) or the external environmental status (e.g., user status) and generate an electrical signal or data value corresponding to the detected status. According to one embodiment, the sensor module (676) can include, for example, a gesture sensor, a gyro sensor, a barometric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0122] The interface (677) may support one or more designated protocols that may be used to directly or wirelessly connect the electronic device (601) with an external electronic device (e.g., the electronic device (602)). In one embodiment, the interface (677) may include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface.

[0123] The connection terminal (678) may include a connector through which the electronic device (601) may be physically connected to an external electronic device (e.g., the electronic device (602)). In one embodiment, the connection terminal (678) may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0124] The haptic module (679) can convert electrical signals into mechanical stimuli (e.g., vibration or movement) or electrical stimuli that a user can perceive through tactile or kinesthetic sensations. According to one embodiment, the haptic module (679) can include, for example, a motor, a piezoelectric element, or an electrical stimulation device.

[0125] The camera module (680) can capture still images and videos. According to one embodiment, the camera module (680) may include one or more lenses, image sensors, image signal processors, or flashes.

[0126] The power management module (688) can manage the power supplied to the electronic device (601). According to one embodiment, the power management module (688) can be implemented as, for example, at least a part of a power management integrated circuit (PMIC).

[0127] A battery (689) may power at least one component of the electronic device (601). In one embodiment, the battery (689) may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0128] The communication module (690) may support the establishment of a direct (e.g., wired) communication channel or a wireless communication channel between the electronic device (601) and an external electronic device (e.g., electronic device (602), electronic device (604), or server (608)), and the performance of communication through the established communication channel. The communication module (690) may operate independently from the processor (620) (e.g., application processor) and may include one or more communication processors that support direct (e.g., wired) communication or wireless communication. According to one embodiment, the communication module (690) may include a wireless communication module (692) (e.g., a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module (694) (e.g., a local area network (LAN) communication module, or a power line communication module). Any of these communication modules may communicate with an external electronic device (604) via a first network (698) (e.g., a short-range communication network such as Bluetooth, wireless fidelity (WiFi) direct, or infrared data association (IrDA)) or a second network (699) (e.g., a long-range communication network such as a legacy cellular network, a 5G network, a next-generation communication network, the Internet, or a computer network (e.g., a LAN or WAN)). These various types of communication modules may be integrated into a single component (e.g., a single chip) or implemented as multiple separate components (e.g., multiple chips). The wireless communication module (692) may use subscriber information (e.g., an international mobile subscriber identity (IMSI)) stored in the subscriber identification module (696) to verify or authenticate the electronic device (601) within a communication network such as the first network (698) or the second network (699).

[0129] The wireless communication module (692) can support 5G networks and next-generation communication technologies following the 4G network, such as NR access technology (new radio access technology). The NR access technology can support high-speed transmission of high-capacity data (eMBB (enhanced mobile broadband)), minimization of terminal power and connection of multiple terminals (mMTC (massive machine type communications)), or high reliability and low latency (URLLC (ultra-reliable and low-latency communications)). The wireless communication module (692) can support, for example, a high-frequency band (e.g., mmWave band) to achieve a high data transmission rate. The wireless communication module (692) may support various technologies for securing performance in a high-frequency band, such as beamforming, massive multiple-input and multiple-output (MIMO), full dimensional MIMO (FD-MIMO), array antenna, analog beam-forming, or large scale antenna. The wireless communication module (692) may support various requirements specified in the electronic device (601), an external electronic device (e.g., the electronic device (604)), or a network system (e.g., the second network (699)). According to one embodiment, the wireless communication module (692) may support a peak data rate (e.g., 20 Gbps or more) for eMBB realization, a loss coverage (e.g., 164 dB or less) for mMTC realization, or a U-plane latency (e.g., 0.5 ms or less for downlink (DL) and uplink (UL), or 1 ms or less for round trip) for URLLC realization.

[0130] The antenna module (697) can transmit or receive signals or power to or from an external device (e.g., an external electronic device). In one embodiment, the antenna module (697) may include an antenna including a radiator formed of a conductor or a conductive pattern formed on a substrate (e.g., a PCB). In one embodiment, the antenna module (697) may include a plurality of antennas (e.g., an array antenna). In this case, at least one antenna suitable for a communication method used in a communication network, such as the first network (698) or the second network (699), may be selected from the plurality of antennas, for example, by the communication module (690). A signal or power may be transmitted or received between the communication module (690) and the external electronic device via the at least one selected antenna. In some embodiments, in addition to the radiator, another component (e.g., a radio frequency integrated circuit (RFIC)) may be additionally formed as a part of the antenna module (697).

[0131] According to various embodiments, the antenna module (697) may form a mmWave antenna module. In one embodiment, the mmWave antenna module may include a printed circuit board, an RFIC disposed on or adjacent a first side (e.g., a bottom side) of the printed circuit board and capable of supporting a designated high-frequency band (e.g., a mmWave band), and a plurality of antennas (e.g., an array antenna) disposed on or adjacent a second side (e.g., a top side or a side side) of the printed circuit board and capable of transmitting or receiving signals in the designated high-frequency band.

[0132] At least some of the above components can be interconnected and exchange signals (e.g., commands or data) with each other via a communication method between peripheral devices (e.g., a bus, GPIO (general purpose input and output), SPI (serial peripheral interface), or MIPI (mobile industry processor interface)).

[0133] According to one embodiment, commands or data may be transmitted or received between the electronic device (601) and an external electronic device (604) via a server (608) connected to a second network (699). Each of the external electronic devices (602 or 604) may be the same or a different type of device as the electronic device (601). According to one embodiment, all or part of the operations executed in the electronic device (601) may be executed in one or more of the external electronic devices (602, 604, or 608). For example, when the electronic device (601) is to perform a certain function or service automatically or in response to a request from a user or another device, the electronic device (601) may, instead of or in addition to executing the function or service itself, request one or more external electronic devices to perform the function or at least part of the service. One or more external electronic devices that receive the request may execute at least a portion of the requested function or service, or an additional function or service related to the request, and transmit the result of the execution to the electronic device (601). The electronic device (601) may process the result as is or additionally and provide it as at least a portion of a response to the request. For this purpose, cloud computing, distributed computing, mobile edge computing (MEC), or client-server computing technology may be used, for example. The electronic device (601) may provide an ultra-low latency service by using distributed computing or mobile edge computing, for example. In one embodiment, the external electronic device (604) may include an Internet of Things (IoT) device. The server (608) may be an intelligent server utilizing machine learning and / or a neural network. According to one embodiment, the external electronic device (604) or the server (608) may be included in the second network (699).The electronic device (601) can be applied to intelligent services (e.g., smart home, smart city, smart car, or healthcare) based on 5G communication technology and IoT-related technology.

[0134] FIG. 7 is a block diagram (700) of a display module (660) according to various embodiments. Referring to FIG. 7, the display module (660) may include a display (710) and a display driver IC (DDI) (730) for controlling the display (710). The DDI (730) may include an interface module (731), a memory (733) (e.g., a buffer memory), an image processing module (735), or a mapping module (737). The DDI (730) may receive image information including, for example, image data or an image control signal corresponding to a command for controlling the image data, from another component of the electronic device (601) through the interface module (731). For example, according to one embodiment, image information may be received from a processor (620) (e.g., a main processor (621) (e.g., an application processor) or an auxiliary processor (623) (e.g., a graphics processing unit) that operates independently of the function of the main processor (621). The DDI (730) may communicate with a touch circuit (750) or a sensor module (676) through the interface module (731). In addition, the DDI (730) may store at least a part of the received image information in the memory (733), for example, in units of frames. The image processing module (735) may, for example, perform preprocessing or postprocessing (e.g., resolution, brightness, or size adjustment) on at least a part of the image data based at least on the characteristics of the image data or the characteristics of the display (710). The mapping module (737) may generate a voltage value or a current value corresponding to the image data that has been preprocessed or postprocessed through the image processing module (735). According to one embodiment, the voltage The generation of the values ​​or current values ​​may be performed at least in part based on properties of the pixels of the display (710), for example, the arrangement of the pixels (RGB stripe or pentile structure), or the size of each of the sub-pixels.At least some pixels of the display (710) may be driven based at least in part on, for example, the voltage value or current value, so that visual information (e.g., text, an image, or an icon) corresponding to the image data may be displayed through the display (710).

[0135] According to one embodiment, the display module (660) may further include a touch circuit (750). The touch circuit (750) may include a touch sensor (751) and a touch sensor IC (753) for controlling the same. The touch sensor IC (753) may control the touch sensor (751) to detect, for example, a touch input or a hovering input for a specific location of the display (710). For example, the touch sensor IC (753) may detect a touch input or a hovering input by measuring a change in a signal (e.g., voltage, light quantity, resistance, or charge quantity) for a specific location of the display (710). The touch sensor IC (753) may provide information (e.g., location, area, pressure, or time) regarding the detected touch input or hovering input to the processor (620). According to one embodiment, at least a portion of the touch circuit (750) (e.g., touch sensor IC (753)) may be included as part of the display driver IC (730), or as part of the display (710), or as part of another component (e.g., auxiliary processor (623)) disposed external to the display module (660).

[0136] According to one embodiment, the display module (660) may further include at least one sensor (e.g., a fingerprint sensor, an iris sensor, a pressure sensor, or an illuminance sensor) of the sensor module (676), or a control circuit therefor. In this case, the at least one sensor or the control circuit therefor may be embedded in a part of the display module (660) (e.g., the display (710) or the DDI (730)) or a part of the touch circuit (750). For example, if the sensor module (676) embedded in the display module (660) includes a biometric sensor (e.g., a fingerprint sensor), the biometric sensor may obtain biometric information (e.g., a fingerprint image) associated with a touch input through a part of the display (710). As another example, if the sensor module (676) embedded in the display module (660) includes a pressure sensor, the pressure sensor may obtain pressure information associated with a touch input through a part or the entire area of ​​the display (710). According to one embodiment, the touch sensor (751) or sensor module (676) may be positioned between pixels of a pixel layer of the display (710), or above or below the pixel layer.

[0137] The technical problems to be achieved in the present disclosure are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by a person having ordinary knowledge in the technical field to which the present disclosure pertains.

[0138] As described above, an electronic device (e.g., electronic device (100)) may include at least one processor (e.g., at least one processor (110)) including a processing circuit, and a display (e.g., display (130)) including a display driving circuit (e.g., display driving circuit (131)) and a display panel (e.g., display panel (132)). The display driving circuit may be configured to receive a first portion of an image to be displayed on a first horizontal line of an active area of ​​the display panel from the at least one processor, and, after the first portion of the image is received, receive a pulse signal transmitted from the at least one processor to synchronize a time within the at least one processor for display on the display panel with a time within the display driving circuit for display on the display panel, identify whether a horizontal synchronization signal (HSS) packet for a second portion of the image to be displayed on a second horizontal line of the active area following the first horizontal line is received from the at least one processor within a reference time interval from a time at which the pulse signal is received, and perform a scan for display on the second horizontal line based on the HSS packet received within the reference time interval, and postpone the scan based on the HSS packet not received within the reference time interval.

[0139] The display driving circuit may be configured to postpone the scan until the HSS packet is received from the at least one processor within the reference time interval from another time at which the pulse signal is received.

[0140] The display driving circuit may be configured to perform the scan by performing a count for the second horizontal line based on the HSS packets received within the reference time interval, and to postpone the scan by refraining from the count based on the HSS packets not received within the reference time interval.

[0141] The display driving circuit may be configured to perform the scan using the second portion of the image received from the at least one processor after the HSS packet is received within the reference time interval.

[0142] The electronic device may include a first interface (e.g., interface (140)) connecting the at least one processor to the display driving circuit and a second interface connecting the at least one processor to the display driving circuit and being separate from the first interface. The first interface may be used for receiving the first portion of the image, receiving the second portion of the image, and receiving the HSS packet, and the second interface may be used for receiving the pulse signal.

[0143] When the HSS packet is received within the reference time interval, the time length of the active portion of the vertical synchronization signal for displaying the image may be shorter than the time length when the HSS packet is not received within the reference time interval.

[0144] The at least one processor may include a central processing unit (CPU) including a processing circuit (e.g., CPU (111)) and a display processing unit (DPU) including a processing circuit (e.g., DPU (112)). The HSS packet not received within the reference time interval may be caused by an underrun of the DPU.

[0145] The time for changing the width of the pulse signal to indicate the start timing of a vertical synchronization signal for an image to be displayed next to the image may be adjusted by the at least one processor according to delaying the scan.

[0146] The first portion of the image, the HSS packet, and the second portion of the image may be transmitted from the at least one processor to the display driving circuit according to a video mode of a mobile industry processor interface (MIPI) display serial interface (DSI).

[0147] The first portion of the image, the HSS packet, and the second portion of the image may be transmitted from the at least one processor to the display driving circuit according to a video hybrid mode of a mobile industry processor interface (MIPI) display serial interface (DSI).

[0148] The first portion of the image, the HSS packet, and the second portion of the image may be transmitted from the at least one processor to the display driving circuit according to an adaptive refresh panel (ARP) of a mobile industry processor interface (MIPI) display serial interface (DSI).

[0149] As described above, an electronic device (e.g., electronic device (100)) may include a display (e.g., display (130)) including a display driving circuit (e.g., display driving circuit (131)) and a display panel (e.g., display panel (132)) and at least one processor (e.g., at least one processor (110)) including a processing circuit. The at least one processor may be individually or collectively configured to transmit a first portion of an image to be displayed on a first horizontal line of an active area of ​​the display panel to the display driving circuit, and to recognize that, after transmitting the first portion of the image, it is not ready to transmit a second portion of the image to the display driving circuit to be displayed on a second horizontal line of the active area subsequent to the first horizontal line, and in response to the recognition, to stop transmitting a pulse signal to the display driving circuit to synchronize a time within the at least one processor for display on the display panel with a time within the display driving circuit for display on the display panel, and to resume transmitting the pulse signal based on recognizing that it is ready to transmit the second portion of the image to the display driving circuit, and to transmit the second portion of the image to the display driving circuit in response to the resumed transmission of the pulse signal.

[0150] The display driving circuit may be configured to postpone scanning for display on the second horizontal line based on failure to receive the pulse signal from the at least one processor.

[0151] The display driving circuit may be configured to postpone the scan until the HSS packet is received from the at least one processor within a reference time interval from the time the pulse signal is received from the at least one processor according to the resumed transmission.

[0152] The display driving circuit may be configured to postpone the scan by refraining from counting for the second horizontal line based on failure to receive the pulse signal from the at least one processor.

[0153] The at least one processor may be individually or collectively configured to, based on recognizing that the second portion of the image is ready to be transmitted to the display driving circuit, resume the transmission of the pulse signal and transmit the HSS packet to the display driving circuit within a reference time interval from the time the pulse signal was transmitted to the display driving circuit in response to the resumed transmission of the pulse signal, and in response to transmitting the HSS packet, transmit the second portion of the image to the display driving circuit.

[0154] The at least one processor may include a central processing unit (CPU) including a processing circuit (e.g., CPU (111)) and a display processing unit (DPU) including a processing circuit (e.g., DPU (112)). The failure to transmit the second portion of the image to the display driving circuit may be caused by an underrun of the DPU.

[0155] As described above, an electronic device (e.g., electronic device (100)) may include a processor assembly including at least one first processor (e.g., at least one first processor (311)) including a processing circuit and a second processor (e.g., second processor (312)) including a processing circuit, and a display (e.g., display (130)) including a display driving circuit (e.g., display driving circuit (131)) and a display panel (e.g., display panel (132)). The at least one first processor may be configured to generate multiple images for an image to be displayed on the display panel and identify a load of the second processor. The at least one first processor may be configured to provide the multiple images to the second processor based on the load being less than a threshold load. The second processor may be configured to generate the image in which the multiple images are synthesized and transmit the image generated by the second processor to the display driving circuit. The at least one processor may be configured to generate the image synthesized from the multiple images based on the load being greater than the threshold load and provide the image generated by the at least one first processor to the second processor. The second processor may be configured to transmit the image to the display driving circuit.

[0156] The at least one first processor may be configured to identify, using the at least one first processor, whether the load is greater than the threshold load.

[0157] The electronic device may include a memory (e.g., memory (120)). The memory may store a program included in a hardware abstraction layer (HAL) for controlling the display. The program may include instructions executable by the at least one first processor to identify the load and determine whether the load is greater than the threshold load.

[0158] The effects that can be obtained from the present disclosure are not limited to the effects mentioned above, and other effects that are not mentioned will be clearly understood by a person having ordinary skill in the art to which the present disclosure pertains.

[0159] The devices described above may be implemented as hardware components, software components, and / or a combination of hardware components and software components. For example, the devices and components described in the embodiments may be implemented using one or more general-purpose computers or special-purpose computers, such as a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a programmable logic unit (PLU), a microprocessor, or any other device capable of executing instructions and responding to them. A processing device (or processing circuit) may execute an operating system (OS) and one or more software applications running on the operating system. In addition, the processing device may access, store, manipulate, process, and generate data in response to the execution of the software. For ease of understanding, the processing device is sometimes described as being used alone; however, one of ordinary skill in the art will recognize that the processing device may include multiple processing elements and / or multiple types of processing elements. For example, a processing unit may include multiple processors, or a processor and a controller. Other processing configurations, such as parallel processors, are also possible.

[0160] Software may include a computer program, code, instructions, or a combination of one or more of these, which may configure a processing device to perform a desired operation or may independently or collectively command the processing device. The software and / or data may be embodied in any type of machine, component, physical device, computer storage medium, or device for interpretation by the processing device or for providing instructions or data to the processing device. The software may also be distributed over networked computer systems and stored or executed in a distributed manner. The software and data may be stored on one or more computer-readable recording media.

[0161] According to one embodiment, the method may be implemented in the form of program instructions that can be executed by various computer means and recorded on a computer-readable medium. The medium may continuously store a computer-executable program or temporarily store it for execution or download. Furthermore, the medium may be a variety of recording or storage means in the form of a single or multiple hardware devices combined. It is not limited to media directly connected to a computer system, but may also be distributed across a network.

[0162] Electronic devices according to the various embodiments disclosed in this document may take various forms. Electronic devices may include, for example, portable communication devices (e.g., smartphones), computer devices, portable multimedia devices, portable medical devices, cameras, wearable devices, or home appliances. Electronic devices according to the embodiments of this document are not limited to the aforementioned devices.

[0163] The various embodiments of this document and the terminology used therein are not intended to limit the technical features described in this document to specific embodiments, but should be understood to include various modifications, equivalents, or substitutes of the embodiments. In connection with the description of the drawings, similar reference numerals may be used for similar or related components. The singular form of a noun corresponding to an item may include one or more of the items, unless the context clearly indicates otherwise. In this document, each of the phrases "A or B", "at least one of A and B", "at least one of A or B", "A, B, or C", "at least one of A, B, and C", and "at least one of A, B, or C" can include any one of the items listed together in the corresponding phrase among those phrases, or all possible combinations thereof. Terms such as "first," "second," or "first" or "second" may be used merely to distinguish one component from another, and do not limit the components in any other respect (e.g., importance or order). When a component (e.g., a first component) is referred to as "coupled" or "connected" to another (e.g., a second component), with or without the terms "functionally" or "communicatively," it means that the component can be connected to the other component directly (e.g., wired), wirelessly, or through a third component.

[0164] The term "module" used in various embodiments of this document may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with terms such as logic, logic block, component, or circuit. A module may be an integral component, or a minimum unit or part of such a component that performs one or more functions. For example, according to one embodiment, a module may be implemented in the form of an application-specific integrated circuit (ASIC).

[0165] Various embodiments of the present document may be implemented as software (e.g., a program (640)) including one or more instructions stored in a storage medium (e.g., an internal memory (636) or an external memory (638)) readable by a machine (e.g., an electronic device (601)). For example, a processor (e.g., a processor (620)) of the machine (e.g., an electronic device (601)) may call at least one instruction among the one or more instructions stored from the storage medium and execute it. This enables the machine to operate to perform at least one function according to the at least one called instruction. The one or more instructions may include code generated by a compiler or code executable by an interpreter. The machine-readable storage medium may be provided in the form of a non-transitory storage medium. Here, 'non-transitory' simply means that the storage medium is a tangible device and does not contain signals (e.g., electromagnetic waves), and the term does not distinguish between cases where data is stored semi-permanently or temporarily on the storage medium.

[0166] According to one embodiment, the method according to various embodiments disclosed in this document may be provided as included in a computer program product. The computer program product may be traded as a commodity between a seller and a buyer. The computer program product may be distributed in the form of a machine-readable storage medium (e.g., compact disc read-only memory (CD-ROM)), or may be distributed online (e.g., downloaded or uploaded) via an application store (e.g., Play Store™) or directly between two user devices (e.g., smart phones). In the case of online distribution, at least a portion of the computer program product may be temporarily stored or temporarily generated in a machine-readable storage medium, such as the memory of a manufacturer's server, an application store's server, or an intermediary server.

[0167] According to various embodiments, each component (e.g., a module or a program) of the above-described components may include one or more entities, and some of the entities may be separated and placed in other components. According to various embodiments, one or more components or operations of the aforementioned components may be omitted, or one or more other components or operations may be added. Alternatively or additionally, a plurality of components (e.g., a module or a program) may be integrated into a single component. In such a case, the integrated component may perform one or more functions of each of the plurality of components identically or similarly to those performed by the corresponding component among the plurality of components prior to the integration. According to various embodiments, the operations performed by a module, program, or other component may be executed sequentially, in parallel, iteratively, or heuristically, or one or more of the operations may be executed in a different order, omitted, or one or more other operations may be added.

Claims

1. In electronic devices, At least one processor comprising a processing circuit; and A display comprising a display driving circuit and a display panel, The above display driving circuit, Receiving a first portion of an image to be displayed on a first horizontal line of an active area of the display panel from the at least one processor, After the first portion of the image is received, a pulse signal transmitted from the at least one processor is received to synchronize the time within the at least one processor for display on the display panel and the time within the display driving circuit for display on the display panel, Identifying whether a horizontal synchronization signal (HSS) packet for a second portion of the image to be displayed on a second horizontal line of the active area following the first horizontal line is received from the at least one processor within a reference time interval from the time the pulse signal is received, Based on the HSS packets received within the above reference time interval, a scan is performed for display on the second horizontal line, configured to postpone the scan based on the HSS packets not received within the above reference time interval, Electronic devices.

2. In claim 1, the display driving circuit, configured to postpone the scan until the HSS packet is received from the at least one processor within the reference time interval from another time at which the pulse signal is received. Electronic devices.

3. In claim 1, the display driving circuit, The scan is performed by performing a count for the second horizontal line based on the HSS packet received within the above reference time interval, configured to postpone the scan by refraining from the count based on the HSS packets not received within the above reference time interval, Electronic devices.

4. In claim 1, the display driving circuit, configured to perform the scan using the second portion of the image received from the at least one processor after the HSS packet is received within the reference time interval; Electronic devices.

5. In claim 1, a first interface connecting said at least one processor to said display driving circuit; and further comprising a second interface, said second interface connecting said at least one processor to said display driving circuit, and separated from said first interface; The above first interface is, Used for receiving the first part of the image, receiving the second part of the image, and receiving the HSS packet, The above second interface is, Used for receiving the above pulse signal, Electronic devices.

6. In claim 1, when the HSS packet is received within the reference time interval, the time length of the active part of the vertical synchronization signal for displaying the image is If the above HSS packet is not received within the above reference time period, shorter than the above time length, Electronic devices.

7. In claim 1, the at least one processor, a central processing unit (CPU) including a processing circuit; and Includes a DPU (display processing unit) including a processing circuit, The HSS packets that are not received within the above reference time interval, Caused by underrun of the above DPU, Electronic devices.

8. In claim 1, the time for changing the width of the pulse signal to indicate the start timing of the vertical synchronization signal for the image to be displayed next to the image is, As the above scan is postponed, it is adjusted by the at least one processor, Electronic devices.

9. In claim 1, the first part of the image, the HSS packet, and the second part of the image, Transmitted from the at least one processor to the display driving circuit according to the video mode of MIPI (mobile industry processor interface) DSI (display serial interface), Electronic devices.

10. In claim 1, the first part of the image, the HSS packet, and the second part of the image, Transmitted from the at least one processor to the display driving circuit according to the video hybrid mode of MIPI (mobile industry processor interface) DSI (display serial interface), Electronic devices.

11. In claim 1, the first part of the image, the HSS packet, and the second part of the image, Transmitted from the at least one processor to the display driving circuit according to the adaptive refresh panel (ARP) of the MIPI (mobile industry processor interface) DSI (display serial interface), Electronic devices.

12. A method for executing in an electronic device including at least one processor and a display including a display driving circuit and a display panel, An operation in which the display driving circuit receives, from the at least one processor, a first portion of an image to be displayed on a first horizontal line of an active area of the display panel; An operation in which the display driving circuit receives a pulse signal transmitted from the at least one processor to synchronize a time within the at least one processor for display on the display panel and a time within the display driving circuit for display on the display panel after the first portion of the image is received, An operation for the display driving circuit to identify whether a horizontal synchronization signal (HSS) packet for a second portion of the image to be displayed on a second horizontal line of the active area following the first horizontal line is received from the at least one processor within a reference time interval from the time at which the pulse signal is received; An operation in which the display driving circuit performs a scan for display on the second horizontal line based on the HSS packet received within the above reference time interval, and An operation in which the display driving circuit postpones the scan based on the HSS packet not received within the above reference time interval, method.

13. In claim 12, the operation of delaying the scan comprises: An operation in which the display driving circuit postpones the scan until the HSS packet is received from the at least one processor within the reference time interval from another time at which the pulse signal is received. method.

14. In claim 12, the operation of delaying the scan is: An operation performed by the display circuit to perform the scan by performing a count for the second horizontal line based on the HSS packet received within the reference time interval, An operation in which the display circuit delays the scan by refraining from counting based on the HSS packets not received within the reference time interval, method.

15. In claim 12, the operation of performing the scan comprises: An operation in which the display driving circuit performs the scan using the second portion of the image received from the at least one processor after the HSS packet is received within the reference time interval. method.

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