Method and device for decoding channel code in communication and broadcasting system

Abstract

The present disclosure relates to a 5G or 6G communication system for supporting higher data transmission rates than a 4G communication system, such as LTE. A method for decoding a channel code by a reception device in a communication system according to an embodiment of the present invention comprises the steps of: generating a first input sequence on the basis of bits that are received from a transmission device and encoded with a channel code; determining, on the basis of the structure of the channel code, a search range of, in the first input sequence, at least one element to be changed in order to generate a plurality of second input sequences; determining at least one element to be changed in order to generate the one or more second input sequences on the basis of the search range; generating the one or more second input sequences by changing the at least one element; and determining a final decoding result by decoding each of the one or more second input sequences.

Description

Method and device for decoding channel codes in communication and broadcasting systems

[0001] The present disclosure relates generally to communication or broadcasting systems, and more particularly to a method and apparatus for decrypting data in a communication or broadcasting system using channel codes.

[0002] Looking back at the evolution of communication and broadcasting systems over the generations, technologies have primarily been developed for human-facing services such as voice, multimedia, and data. In particular, with the commercialization of 5G (5th-generation) communication systems, an explosive increase in connected devices is expected to be connected to communication networks. Examples of networked objects include vehicles, robots, drones, home appliances, displays, smart sensors installed in various infrastructures, construction equipment, and factory equipment. Mobile devices are also expected to evolve into diverse form factors, such as augmented reality glasses, virtual reality headsets, and holographic devices. In the 6th-generation (6G) era, efforts are being made to develop improved 6G communication systems to connect hundreds of billions of devices and objects and provide diverse services. For this reason, 6G communication systems are often referred to as "beyond 5G."

[0003] The 6G communication system, expected to be realized around 2030, will have a maximum transmission speed of terabit (i.e., 1,000 gigabits per second) and a wireless latency of 100 microseconds (μsec). This means that compared to 5G, the transmission speed in a 6G communication system will be 50 times faster, while the wireless latency will be reduced to one-tenth.

[0004] To achieve these high data rates and ultra-low latency, 6G communication systems are being considered for implementation in terahertz bands (e.g., from 95 gigahertz (GHz) to 3 terahertz (THz). Compared to the millimeter wave (mmWave) band introduced in 5G, the terahertz band is expected to experience more severe path loss and atmospheric absorption, making it more crucial to ensure signal reach, or coverage, in this band. Key technologies to ensure coverage include radio frequency (RF) components, antennas, new waveforms that offer better coverage than orthogonal frequency division multiplexing (OFDM), beamforming, and multiple antenna transmission technologies such as massive multiple-input and multiple-output (MIMO), full-dimensional MIMO (FD-MIMO), array antennas, and large-scale antennas. In addition, new technologies such as metamaterial-based lenses and antennas, high-dimensional spatial multiplexing using orbital angular momentum (OAM), and reconfigurable intelligent surfaces (RIS) are being discussed to improve the coverage of terahertz band signals.

[0005] In addition, in order to improve frequency efficiency and system network, 6G communication systems are developing full duplex technology that utilizes the same frequency resources for uplink and downlink at the same time; network technology that integrates satellites and high-altitude platform stations (HAPS); network structure innovation technology that supports mobile base stations and enables optimization and automation of network operation; dynamic spectrum sharing technology through collision avoidance based on spectrum usage prediction; AI-based communication technology that utilizes artificial intelligence (AI) from the design stage and internalizes end-to-end AI support functions to realize system optimization; and next-generation distributed computing technology that realizes services with complexity that exceeds the limits of terminal computing capabilities by utilizing ultra-high-performance communication and computing resources (mobile edge computing (MEC), cloud, etc.). In addition, efforts are being made to further strengthen connectivity between devices, further optimize networks, promote softwareization of network entities, and increase openness in communications through the design of new protocols to be used in 6G communication systems, the implementation of hardware-based security environments, the development of mechanisms for the safe use of data, and the development of technologies for maintaining privacy.

[0006] Research and development of these 6G communication systems are expected to enable a new level of hyper-connected experience (the next hyper-connected experience) through the hyper-connectivity of 6G communication systems, which encompass not only connections between things but also connections between people and things. Specifically, 6G communication systems are expected to enable services such as truly immersive extended reality (Truly Immersive XR), high-fidelity mobile holograms, and digital replicas. Furthermore, services such as remote surgery, industrial automation, and emergency response, which are provided through 6G communication systems through enhanced security and reliability, will find application in diverse fields such as industry, medicine, automobiles, and home appliances.

[0007] Meanwhile, when transmitting and receiving data between a transmitter and a receiver in a typical communication and broadcasting system, link performance can be significantly degraded by various forms of noise, fading, and inter-symbol interference (ISI) present in the communication channel. Therefore, to implement high-speed digital communication or broadcasting systems that require high data throughput and reliability, such as next-generation mobile communications, digital broadcasting, and portable Internet, it is necessary to develop channel coding and decoding technologies that overcome noise, fading, and inter-symbol interference.

[0008] The present disclosure relates generally to communication or broadcasting systems, and more particularly to a method and apparatus for decrypting data in a communication or broadcasting system using channel codes.

[0009] The present disclosure aims to improve the decoding performance of channel codes, such as turbo codes and low-density parity-check codes (LDPC codes), which gradually update a posterior probability, a posteriori log-likelihood ratio (AP-LLR), etc. of codeword bits through iterative processing in a communication or broadcasting system. Theoretically, channel codes have low error-correction performance when the code dimension (the number of information bits to be encoded, the encoder input length) and the code length (the number of codeword bits obtained by encoding, the encoder output length) are short. Specifically, even at the same code rate (the ratio of the code dimension to the code length), the error-correction performance when the code dimension and length are short is lower than that when the code dimension and length are long. In addition, turbo codes and LDPC codes are characterized by a greater degradation in performance when the code dimension and length are short.

[0010] The present disclosure proposes a decoding method and device for improving low error-correction performance that occurs when the dimension and length of a channel code, such as a turbo code or an LDPC code, are short.

[0011] According to one embodiment of the present disclosure, a decoding method for a channel code of a receiving device in a communication system includes: generating a first input sequence based on bits encoded with a channel code received from a transmitting device; determining, based on a structure of the channel code, a search range of at least one element to be changed in the first input sequence to generate a plurality of second input sequences; determining, based on the search range, at least one element to be changed in order to generate the at least one second input sequence; generating the at least one second input sequence by changing the at least one element; and performing decoding on each of the at least one second input sequence to determine a final decoding result.

[0012] According to one embodiment of the present disclosure, a receiving device for performing decoding of a channel code in a communication system comprises: a transceiver; and at least one processor; wherein the at least one processor is configured to generate a first input sequence based on bits encoded with a channel code received from a transmitting device, determine a search range of at least one element to be changed in order to generate a plurality of second input sequences in the first input sequence based on a structure of the channel code, determine at least one element to be changed in order to generate the at least one second input sequence based on the search range, generate the at least one second input sequence by changing the at least one element, and perform decoding on each of the at least one second input sequence to determine a final decoding result.

[0013] A decoding device and method according to an embodiment of the present disclosure can significantly improve decoding performance by generating at least two modified decoder input sequences based on an original decoder input sequence, performing decoding based on each of them, and then collating the results.

[0014] The decoding device and method according to the embodiment of the present disclosure can reduce complexity by adjusting the search range when determining an element to be changed in an original decoder input sequence.

[0015] The decoding device and method according to the embodiment of the present disclosure can improve the error-correction performance of channel decoding.

[0016] In particular, the decoding device and method according to various embodiments of the present disclosure can improve error-correction performance by determining elements to be changed in the original decoder input sequence based on the decoder output sequence obtained after one decoding.

[0017] The effects that can be obtained from the present disclosure are not limited to the effects mentioned above, and other effects that are not mentioned can be clearly understood by a person having ordinary skill in the art to which the present disclosure belongs from the description below.

[0018] FIG. 1 illustrates a communication system according to one embodiment of the present disclosure.

[0019] FIG. 2 illustrates an example of a configuration of a transmitting device and a receiving device performing communication in a communication system according to one embodiment of the present disclosure.

[0020] Figure 3 illustrates an example of a parity check matrix of an LDPC (low-density parity-check) code.

[0021] Figure 4 illustrates a binary graph corresponding to the parity check matrix of Figure 3.

[0022] FIG. 5 is a block diagram of a transmitting device that performs channel encoding and a series of operations according to one embodiment of the present disclosure.

[0023] FIG. 6 is a block diagram illustrating a receiving device that performs channel decoding and a series of operations according to one embodiment of the present invention.

[0024] Figure 7 illustrates a procedure of ensemble decoding in which a receiving device selects a location of an LLR with low reliability in an intrinsic LLR (log likelihood ratio) sequence and generates a modified candidate LLR sequence based on the location to perform decoding.

[0025] Figure 8 illustrates an example of a block diagram showing the sequence of operations of ensemble decoding.

[0026] Figure 9 illustrates that the search range for the receiver to find the position of the LLR whose value is to be changed in the intrinsic LLR sequence is the entire range excluding the non-punctured bit positions.

[0027] FIG. 10 illustrates a search range in which a receiving device searches for a position of an LLR whose value is to be changed in an intrinsic LLR sequence according to one embodiment of the present disclosure.

[0028] FIG. 11 is a diagram illustrating an example of a search range for finding a position of an LLR to change a given value in an intrinsic LLR sequence including a systematic puncture bit according to one embodiment of the present disclosure.

[0029] FIG. 12 is a diagram illustrating an example of a search range for finding a location of an LLR to change a given value in an intrinsic LLR sequence that does not include a systematic puncture bit according to one embodiment of the present disclosure.

[0030] FIG. 13 is a diagram for explaining the effect of achieving low complexity when determining a search range in a 5G NR (new radio) LDPC code system according to one embodiment of the present disclosure.

[0031] FIG. 14 is a diagram for explaining the effect of achieving error-correction performance when determining a search range in a 5G NR LDPC code system according to one embodiment of the present disclosure.

[0032] FIG. 15 illustrates a procedure for performing ensemble decoding based on an AP-LLR sequence obtained by decoding an intrinsic LLR sequence as input according to one embodiment of the present invention.

[0033] FIG. 16 illustrates an example of a search range for determining the position of an LLR whose value is to be changed based on an AP-LLR sequence according to one embodiment of the present invention.

[0034] Figure 17 shows an example of the performance of limiting the position of the LLR to be changed according to the post-LLR sequence.

[0035] FIG. 18 is a flowchart showing an ensemble decoding operation of a channel code performed by a receiving device according to one embodiment of the present invention.

[0036] FIG. 19 is a flowchart showing an operation when a transmitter is a base station and a receiving device is a terminal according to one embodiment of the present invention.

[0037] Figure 20 is a block diagram for ensemble decoding using signal expansion.

[0038] Figure 21 is a block diagram for ensemble decoding using signal expansion.

[0039] Figure 22 shows examples of ensemble decoding using signal expansion.

[0040] Figure 23 shows examples of ensemble decoding using signal expansion.

[0041] Figure 24 shows examples of ensemble decoding using signal expansion.

[0042] Figure 25 shows examples of ensemble decoding using signal expansion.

[0043] Hereinafter, embodiments of the present invention will be described in detail with the attached drawings.

[0044] In describing the embodiments, descriptions of technical details that are well known in the technical field to which the present invention pertains and are not directly related to the present invention will be omitted. This is to avoid obscuring the gist of the present invention by omitting unnecessary explanations and to convey the gist more clearly.

[0045] For the same reason, some components in the attached drawings are highlighted, omitted, or schematically depicted. Furthermore, the dimensions of each component do not entirely reflect its actual size. Identical or corresponding components in each drawing are assigned the same reference numbers.

[0046] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various different forms. These embodiments are provided only to complete the disclosure of the present invention and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

[0047] At this time, it will be understood that each block of the processing flowchart drawings and combinations of the flowchart drawings can be performed by computer program instructions. These computer program instructions can be installed in a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing equipment, so that the instructions executed by the computer or the processor of the other programmable data processing equipment create a means for performing the functions described in the flowchart block(s). These computer program instructions can also be stored in a computer-available or computer-readable memory that can be directed to a computer or other programmable data processing equipment to implement the functions in a specific manner, so that the instructions stored in the computer-available or computer-readable memory can also produce a manufactured item that includes an instruction means for performing the functions described in the flowchart block(s). Since the computer program instructions may be installed on a computer or other programmable data processing device, a series of operational steps may be performed on the computer or other programmable data processing device to create a computer-executable process, and the instructions that cause the computer or other programmable data processing device to perform the steps for performing the functions described in the flowchart block(s) may also provide steps for performing the functions described in the flowchart block(s).

[0048] Additionally, each block may represent a module, segment, or portion of code that contains one or more executable instructions for performing a specific logical function(s). It should also be noted that in some alternative implementation examples, the functions described in the blocks may occur out of order. For example, two blocks depicted in succession may actually be executed substantially concurrently, or the blocks may sometimes be executed in reverse order, depending on their respective functions.

[0049] Here, the term '~ unit' used in the present embodiment means a software or hardware component such as an FPGA or ASIC, and the '~ unit' performs certain roles. However, the '~ unit' is not limited to software or hardware. The '~ unit' may be configured to be on an addressable storage medium and may be configured to play one or more processors. Accordingly, as an example, the '~ unit' includes components such as software components, object-oriented software components, class components, and task components, processes, functions, properties, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables. The functions provided within the components and '~ units' may be combined into a smaller number of components and '~ units' or further separated into additional components and '~ units'. Additionally, components and '~parts' may be implemented to regenerate one or more CPUs within a device or secure multimedia card.

[0050] Hereinafter, various embodiments will be described in detail with reference to the attached drawings. At this time, it should be noted that the same components in the attached drawings are represented by the same reference numerals as much as possible. In addition, it should be noted that the attached drawings of the present invention are provided to help understand the present invention, and the present invention is not limited to the form or arrangement illustrated in the drawings. In addition, detailed descriptions of well-known functions and configurations that may obscure the gist of the present invention will be omitted. It should be noted that in the following description, only the parts necessary for understanding the operation according to various embodiments of the present invention will be described, and the description of other parts will be omitted so as not to distract from the gist of the present invention.

[0051] FIG. 1 illustrates a communication system according to one embodiment of the present disclosure.

[0052] FIG. 1 illustrates a transmitter (110) and a receiver (120) as part of devices or nodes that utilize a wireless channel in a communication system. FIG. 1 illustrates one transmitter (110) and one receiver (120), but may include multiple transmitters or multiple receivers. In addition, for convenience of explanation, in the present disclosure, the transmitter (110) and the receiver (120) are described as separate entities, but the functions of the transmitter (110) and the receiver (120) may be interchanged. For example, in the case of an uplink in a cellular communication system, the transmitter (110) may be a terminal, and the receiver (120) may be a base station. In the case of a downlink, the transmitter (110) may be a base station, and the receiver (120) may be a terminal.

[0053] In one embodiment, the transmitter (110) may generate a codeword by encoding information bits based on a turbo code, and the receiver (120) may decode a signal of the received codeword based on the turbo code. For example, the receiver (120) may use a turbo decoding method according to an embodiment of the present disclosure, and may check with a concatenated CRC code to determine whether the decoding result is normal. The transmitter (110) and the receiver (120) perform encoding and decoding using a structure of a turbo code known to each other (trellis, linear feedback shift register, etc.). For example, the structure of the turbo code may include a trellis, linear feedback shift register, etc. defined in the 3GPP (3rd generation partnership project) LTE (long-term evolution) standard.

[0054] In one embodiment, the transmitter (110) may generate a codeword by encoding information bits based on an LDPC (low-density parity-check) code, and the receiver (120) may decode a signal of the received codeword based on the LDPC code. For example, the receiver (120) may use an LDPC decoding method according to an embodiment of the present disclosure and may perform a syndrome check to determine whether the decoding result is normal. The transmitter (110) and the receiver (120) perform LDPC encoding and decoding using a parity check matrix known to each other. For example, the parity check matrix may include a parity check matrix defined in the 3GPP NR standard.

[0055] FIG. 2 illustrates an example of a configuration of a device performing communication in a communication system according to one embodiment of the present disclosure.

[0056] The configuration illustrated in Fig. 2 is for a transmitter (200) and a receiver (240), and can be understood as the configuration of the transmitter (110) and receiver (120) illustrated in Fig. 1, respectively. Terms such as "...unit" and "...unit" used hereinafter mean a unit that processes at least one function or operation, and this can be implemented by hardware, software, or a combination of hardware and software.

[0057] Referring to FIG. 2, the transmitting device (200) may include a transceiver (210), a storage unit (230), and a control unit (220).

[0058] According to FIG. 2, the transmitting device (200) includes a transceiver (210), a control unit (220), and a storage unit (230). The transmitting device (200) may be, for example, a terminal or a base station. However, the components of the transmitting device (200) are not limited to the examples described above, and for example, the transmitting device (200) may include more or fewer components than the presented components. In addition, the transceiver (210), the control unit (220), and the storage unit (230) may be implemented in the form of a single chip.

[0059] The transceiver (210) can perform functions for transmitting and receiving signals via a wireless channel. For example, the transceiver (210) can perform a conversion function between a baseband signal and a bit stream according to the physical layer specifications of the system. For example, when transmitting data, the transceiver (210) can generate complex symbols by encoding and modulating a transmission bit stream. In addition, when receiving data, the transceiver (210) can restore a reception bit stream by demodulating and decoding a baseband signal. In addition, the transceiver (210) can up-convert a baseband signal into an RF (radio frequency) band signal and transmit it through an antenna, and down-convert an RF band signal received through the antenna into a baseband signal.

[0060] To this end, the transceiver (210) may include a transmitting filter, a receiving filter, an amplifier, a mixer, an oscillator, a digital to analog convertor (DAC), an analog to digital convertor (ADC), etc. In addition, the transceiver (210) may include a plurality of transmitting and receiving paths. Furthermore, the transceiver (210) may include at least one antenna array composed of a plurality of antenna elements. In terms of hardware, the communication unit (210) may be composed of a digital unit and an analog unit, and the analog unit may be composed of a plurality of sub-units according to operating power, operating frequency, etc. In addition, the communication unit 210 may include a decoding unit to perform decoding according to various embodiments of the present disclosure.

[0061] The transceiver (210) transmits and receives signals as described above. Accordingly, the transceiver (210) may be referred to as a "transmitter," a "receiver," or a "communicator." Furthermore, in the following description, the term "transmission and reception" performed via a wireless channel is used to mean that the transceiver (210) performs the processing described above. Furthermore, if the device of FIG. 2 is a base station, the transceiver (210) may further include a backhaul communication unit for communicating with other network entities connected via a backhaul network.

[0062] The transceiver (210) can transmit and receive signals with the transmitter (240). Here, the signals can include control information and data. To this end, the transceiver (210) can be configured with an RF transmitter that up-converts and amplifies the frequency of a transmitted signal, and an RF receiver that low-noise amplifies and frequency-converts a received signal. However, this is only one embodiment of the transceiver (210), and the components of the transceiver (210) are not limited to the RF transmitter and the RF receiver. In addition, the transceiver (210) can receive a signal through a wireless channel, output it to the control unit (220), and transmit the signal output from the control unit (220) through the wireless channel. In addition, the transceiver (210) can separately include an RF transceiver for a first communication technology and an RF transceiver for a second communication technology, or can perform physical layer processing according to the first communication technology and the second communication technology with a single transceiver.

[0063] The storage unit (230) can store programs and data required for the operation of the transmitting device (200). In addition, the storage unit (230) can store control information or data included in signals transmitted and received by the transmitting device (200). The storage unit (230) can be configured as a storage medium or a combination of storage media, such as a ROM, a RAM, a hard disk, a CD-ROM, and a DVD. In addition, there can be a plurality of storage units (230).

[0064] The storage unit (230) can store data such as basic programs, application programs, and setting information for the operation of the transmitter (110). The storage unit (230) can be composed of volatile memory, non-volatile memory, or a combination of volatile memory and non-volatile memory. In addition, the storage unit (230) can provide stored data upon request from the control unit (220).

[0065] The control unit (220) can control the overall operations of the device. For example, the control unit (220) can transmit and receive signals through the transceiver unit (210). In addition, the control unit (220) can record or read data in the storage unit (230). For this purpose, the control unit (220) may include at least one processor or microprocessor, or may be a part of a processor. According to various embodiments, the control unit (220) can control the device to perform operations according to various embodiments described below.

[0066] According to FIG. 2, the receiving device (240) includes a transceiver (250), a control unit (260), and a storage unit (280). The receiving device (240) may be, for example, a terminal or a base station. However, the components of the receiving device (240) are not limited to the examples described above, and for example, the receiving device (240) may include more or fewer components than the presented components. In addition, the transceiver (250), the control unit (260), and the storage unit (280) may be implemented in the form of a single chip.

[0067] The transceiver (250) can perform functions for transmitting and receiving signals via a wireless channel. For example, the transceiver (250) can perform a conversion function between a baseband signal and a bit stream according to the physical layer specifications of the system. For example, when transmitting data, the transceiver (250) can generate complex symbols by encoding and modulating a transmission bit stream. In addition, when receiving data, the transceiver (250) can restore a reception bit stream by demodulating and decoding a baseband signal. In addition, the transceiver (250) can upconvert a baseband signal to an RF band signal and transmit it through an antenna, and downconvert an RF band signal received through the antenna to a baseband signal.

[0068] To this end, the transceiver (250) may include a transmitting filter, a receiving filter, an amplifier, a mixer, an oscillator, a DAC, an ADC, etc. In addition, the transceiver (250) may include a plurality of transmitting and receiving paths. Furthermore, the transceiver (250) may include at least one antenna array composed of a plurality of antenna elements. In terms of hardware, the transceiver (250) may be composed of a digital unit and an analog unit, and the analog unit may be composed of a plurality of sub-units according to operating power, operating frequency, etc. In addition, the transceiver (250) may include a decoding unit to perform decoding according to various embodiments of the present disclosure.

[0069] The transceiver (250) transmits and receives signals as described above. Accordingly, the transceiver (250) may be referred to as a "transmitter" or a "receiver." Furthermore, in the following description, the term "transmission and reception" performed via a wireless channel is used to mean that the transceiver (250) performs the processing described above. Furthermore, if the device of FIG. 2 is a base station, the transceiver (250) may further include a backhaul communication unit for communicating with other network entities connected via a backhaul network.

[0070] The transceiver (250) can transmit and receive signals with the receiving device (200). Here, the signals can include control information and data. To this end, the transceiver (250) can be configured with an RF transmitter that up-converts and amplifies the frequency of a transmitted signal, and an RF receiver that low-noise amplifies and frequency-converts the received signal. However, this is only one embodiment of the transceiver (250), and the components of the transceiver (250) are not limited to the RF transmitter and the RF receiver. In addition, the transceiver (250) can receive a signal through a wireless channel, output it to the control unit (260), and transmit the signal output from the control unit (260) through the wireless channel. In addition, the transceiver (250) can separately include an RF transceiver for a first communication technology and an RF transceiver for a second communication technology, or can perform physical layer processing according to the first communication technology and the second communication technology with a single transceiver.

[0071] The storage unit (280) can store programs and data required for the operation of the receiving device (240). In addition, the storage unit (280) can store control information or data included in signals transmitted and received by the receiving device (240). The storage unit (280) can be configured as a storage medium or a combination of storage media, such as a ROM, a RAM, a hard disk, a CD-ROM, and a DVD. In addition, there can be a plurality of storage units (280).

[0072] The storage unit (280) can store data such as basic programs, application programs, and setting information for the operation of the receiver (120). The storage unit (280) can be composed of volatile memory, non-volatile memory, or a combination of volatile and non-volatile memory. In addition, the storage unit (280) can provide stored data upon request from the control unit (260).

[0073] The control unit (260) can control the overall operations of the device. For example, the control unit (260) can transmit and receive signals through the transceiver unit (280). In addition, the control unit (260) can record or read data in the storage unit (280). To this end, the control unit (260) may include at least one processor or microprocessor, or may be a part of a processor. According to various embodiments, the control unit (260) can control the device to perform operations according to various embodiments described below.

[0074] The at least one processor may control generating a first input sequence based on bits encoded with a channel code received from a transmitting device. The at least one processor may determine a search range of at least one element to be changed in the first input sequence to generate a plurality of second input sequences based on a structure of the channel code. In one embodiment, the length of the search range is a length of the encoded bits (E) and a length of the parent code (N=N). b Z) may be shorter than the smaller one.

[0075] In one embodiment, the receiving device determining the search range of the at least one element may include performing decoding on the first input sequence, identifying a first output sequence generated or updated based on the decoding, and determining the search range of the at least one element based on the first output sequence. In one embodiment, the search range of the at least one element may be predetermined. In one embodiment, the receiving device determining the search range of the at least one element based on the first output sequence may, when the first output sequence is updated, determine the search range of the at least one element based on one of the positions of updated elements in the first output sequence, the positions of updated information bits in the first output sequence, and the positions of updated cinematic puncture bits in the first output sequence.

[0076] In one embodiment, the search range may be determined based on information bits, perforated bits within the information bits, and shortened bits within the information bits. In one embodiment, the length of the search range may be a value (K-2Z-F) obtained by subtracting the length of the perforated bits within the information bits (2Z) and the length of the shortened bits within the information bits (F) from the length of the cinematic portion (K).

[0077] The at least one processor may determine at least one element used to generate the at least one second input sequence based on the search range. In one embodiment, when the first input sequence is an LLR sequence, the receiving device determining the at least one element used to generate the at least one second input sequence may include determining at least one of a predetermined number of n elements having a low reliability value.

[0078] The at least one processor may generate the at least one second input sequence by modifying the at least one element. In one embodiment, the receiving device generates the at least one second input sequence by modifying the at least one of the n determined elements in the first input sequence. n It may include generating a plurality of second input sequences of the dog.

[0079] The at least one processor may perform decoding on each of the at least one second input sequence to determine a final decoding result.

[0080] In one embodiment, the receiving device can receive information necessary for the decoding from the transmitting device, and the first input sequence can be decoded based on the information necessary for the decoding. In one embodiment, when the receiving device is a terminal and the transmitting device is a base station, the information necessary for the decoding can be transmitted via an upper layer message.

[0081] This disclosure describes various embodiments using terminology used in certain communication standards (e.g., 3GPP). However, these are merely illustrative examples. The various embodiments of this disclosure can be easily modified and applied to other communication and broadcasting systems.

[0082] Furthermore, in the detailed description of the present invention, commonly used mathematical symbols are used to avoid ambiguity. These mathematical symbols will be clearly understandable to those skilled in the art to which the present disclosure pertains. Representative examples of commonly known mathematical symbols used in the present disclosure include the following:

[0083] - Calligraphic characters (e.g., ) is used to refer to a set.

[0084] - Unless otherwise stated throughout this disclosure, it is assumed that the index of the first element of a set, sequence, or vector starts from 0 (zero-based numbering).

[0085] - A set of indexed elements About, is a set of indices of elements . For example, About am.

[0086] - Two sets and About, is a set A set for It represents the relative complement of .

[0087] - Group and any number About, Is to all elements of A set consisting of values ​​that have been added It represents.

[0088] - sign , , are used to refer to the set of natural numbers, the set of integers, and the set of real numbers, respectively.

[0089] - represents a binary field.

[0090] - non-negative integer About, Silver from 0 A series of Represents a set of integers of a dog. That is, am.

[0091] - Boldface lowercase (e.g., ) is used to indicate a vector, and boldface capital letters (e.g., ) is used to indicate a matrix. In the case of vectors, unless otherwise stated, it indicates a column vector.

[0092] - Vector and matrix About and represents each transpose.

[0093] - matrix and two non-negative integers , About, is a matrix of th row, Represents the element of the th column.

[0094] - matrix and the set of two non-negative integers , About, is a matrix Gather in Rows and sets specified by elements of Represents a submatrix consisting of columns specified by elements of .

[0095] In communication systems, error detection codes and error correcting codes (ECC) are utilized to help receivers overcome errors that may occur in the communication channel. The error correction codes used in communication between transmitters and receivers are generally referred to as channel coding or forward error correction (FEC). The transmitter encodes the information vector it wishes to transmit, generates a codeword vector, and transmits it. The receiver then performs a series of processing on the received signal and decodes it to estimate the information vector.

[0096] A variety of channel coding techniques are used in communications and broadcasting systems. Current methods include convolutional codes, turbo codes, low-density parity-check coding (LDPC) codes, and polar codes. Turbo and LDPC codes are channel coding techniques that perform iterative decoding. They excel particularly at long-length encodings, and are therefore widely used in various communications and broadcasting systems.

[0097] Turbo coding was the first channel coding technique to demonstrate performance approaching channel capacity using a decoding algorithm with realistic complexity. Turbo coding systems perform decoding by repeatedly exchanging messages between two component decoders, a process known as turbo processing. This decoding method demonstrates exceptional performance, particularly when processing long information and codeword vectors. Due to these advantages, it has been adopted and is being used to process information in the data channels of 3GPP's 4th generation (4G) Long-Term Evolution (LTE).

[0098] LDPC codes are also a channel coding technique known to achieve performance approaching channel capacity with a decoding algorithm of realistic complexity. In particular, the decoding method, called belief-propagation (BP), is well-suited for parallelizing each detailed operation, which is advantageous for achieving high throughput. Due to these advantages, LDPC codes are used in various communication and broadcasting systems, such as IEEE 802.11n / ac / ax Wi-Fi, DVB-T2 / C2 / S2, and ATSC 3.0. Recently, they have also been adopted for the 3GPP New Radio (NR) system, a 5G mobile communication system.

[0099] Turbo codes and low-density parity-check (LDPC) codes are error-correction codes that exhibit performance approaching channel capacity. Due to their superior performance and ease of implementation, turbo and LDPC codes are used in various communications and broadcasting systems. For example, turbo codes have been adopted and used in the 3GPP's 4G LTE mobile communication system standard, and LDPC codes have been adopted and used in the 3GPP's 5G NR mobile communication system standard.

[0100] Hereinafter, embodiments of the present disclosure are described based on a communication or broadcasting system using LDPC codes. However, these are merely examples to avoid redundant descriptions of different channel coding techniques and to simplify the explanation. The various embodiments described can be easily modified and applied to communication and broadcasting systems using other channel coding techniques, including turbo codes.

[0101] First, we describe the characteristics of LDPC codes as channel coding. LDPC codes are linear codes, and each LDPC code is typically defined by a parity-check matrix. The number of input bits to be encoded using LDPC codes is , and the number of output bits of the encoded result is It is written as . In terms of coding theory, the number of input bits of encoding is called the code dimension, and is the number of output bits of the encoding. is called the code length. One of the important characteristics of the channel code is the code rate. It is defined as the sign length minus the sign dimension. is called the number of parity bits or the number of redundant bits.

[0102] Sign dimension and the sign length LDPC codes with a parity-check matrix is defined by the parity check matrix All valid codeword vectors generated by LDPC codes defined as satisfies the relationship of the following mathematical expression 1.

[0103] [Mathematical Formula 1]

[0104]

[0105] In mathematical expression 1 Silver length is the zero vector of . According to mathematical expression 1, the parity check matrix A codeword vector generated by encoding with an LDPC code defined by is a parity check matrix is the nullspace for . of The row vector corresponding to the th row It is written as, of th row, The element of the th column Let's write it as . The encoding and decoding of LDPC codes are based on the above parity check matrix It is performed based on .

[0106] Parity check matrix The general operation of LDPC codes defined by is described in detail using drawings. LDPC decoding is performed using a parity check matrix It can be understood as a so-called belief-propagation (BP) process that repeatedly exchanges messages on a bipartite graph corresponding to .

[0107] Figure 3 shows an example of a parity check matrix of an LDPC (low-density parity-check) code.

[0108] Figure 3 shows the number of rows And the number of columns is Parity check matrix of binary LDPC code An example is shown. The number of 1s in a parity check matrix is ​​called density, and this density determines the computational complexity of encoding and decoding. The density of a typical parity check matrix of an LDPC code is the total size of the parity check matrix. The contrast is very low, and this characteristic is what makes this class of codes called low-density parity check codes. However, the parity check matrix in Fig. 3 is very small. class As an example of an LDPC code having a relatively high density, it should be noted that a conventionally designed LDPC code has a larger number of bits than the example in Fig. 3. class , and the density of the parity check matrix is ​​much lower.

[0109] Figure 4 shows a binary graph corresponding to the parity check matrix of Figure 3.

[0110] Figure 4 is the parity check matrix of Figure 3. A bipartite graph formed when considering a binary adjacency matrix represents a bipartite graph is a set of variable nodes ( ), a set of check nodes ( ), and a set of edges connecting the elements of the two sets. It consists of. By the usual expression of graph theory. Is th variable node and th inspection node indicates that they are connected. Conversely, Is th variable node and th inspection node indicates that the parity check matrix is ​​not connected. About, th row, Element of the th column If the value is 1 and, If the value is 0 am.

[0111] Variable nodes are encoded word output vectors corresponds to each bit of , th variable node have the same index th code word bit corresponds to the parity check matrix. Each row and codeword vector It represents a linear equation represented by the inner product on the binary field of . Specifically, th inspection node Is represents the corresponding linear equation. This linear equation is On the bipartite graph given by The result of performing a modulo-2 sum (or bitwise XOR) of the bit values ​​corresponding to all variable nodes connected to the th test node is 0. The belief-propagation (BP) decoding of LDPC codes can be understood as an iterative message exchange process utilizing the relationship between variable nodes and test nodes on this graph.

[0112] LDPC codes are used in various communication and broadcasting systems, and are designed and used to satisfy requirements given according to the characteristics of the system.

[0113] For example, one of the required characteristics of channel codes for communication systems is code length flexibility. In a communication system, the number of information bits to be transmitted can vary with each transmission depending on the message to be transmitted. When transmitting multimedia information such as video, the number of information bits may be large. Conversely, when transmitting text messages, the number of information bits may be small. Furthermore, in a communication system, the amount of communication resources, such as time and frequency, available for the transmission of specific information may vary with each transmission for various reasons. For example, the total amount of available communication resources may vary, or the amount of communication resources allocated to transmit a given piece of information from the total available communication resources may vary. Since the number of bits to be transmitted varies with each transmission, the channel code used in a communication system must be designed to flexibly handle encoding and decoding in situations where the number of input and output bits of the coder change.

[0114] Another required characteristic of channel codes for communication systems is rate flexibility. In communication systems, especially mobile communication systems, the channel quality between the transmitter and receiver constantly changes. For example, if the receiver physically moves, the distance between the transmitter and receiver may change, resulting in channel conditions such as path loss and multipath fading. When the channel quality is good, the transmitter can increase the code rate (i.e., reduce the number of parity bits) to achieve error-free encoding / decoding by efficiently utilizing communication resources. Conversely, when the channel quality is poor, the transmitter can decrease the code rate (i.e., increase the number of parity bits) to increase the probability of overcoming the poor channel quality. Therefore, channel codes used in communication systems must be designed to flexibly change the code rate according to the situation.

[0115] LDPC codes for practical communication and broadcasting systems are designed to have the above-mentioned required characteristics (flexible code length adjustment, flexible code rate adjustment). For example, LDPC codes that satisfy the above-mentioned required characteristics are designed and used in 3GPP NR mobile communication systems.

[0116] FIG. 5 is a block diagram of a transmitting device (500) according to an embodiment of the present disclosure. Referring to FIG. 5, the transmitting device (500) may include a segmentation unit (510), an outer encoding unit (520), a zero addition unit (530), an LDPC encoding unit (540), a code rate adjustment unit (550), an interleaving unit (560), a combining unit (570), and a modulation unit (580) to transmit an input bit sequence by LDPC encoding and modulating it. Examples of modulation methods include BPSK (binary phase shift keying), -BPSK, QPSK (quadrature phase shift keying), 16-QAM (quadrature amplitude modulation), 64-QAM, 256-QAM, 1024QAM, etc., and any other modulation technique is possible. The components illustrated in FIG. 5 are components that perform encoding and modulation on the input bit sequence, and this is only an example, and in some cases, some of the components illustrated in FIG. 5 may be omitted or changed, and other components may be added.

[0117] The transmitter (500) determines code parameters to be used for the LDPC code based on given scheduling parameters, such as the number of input bits, the number of final output bits, and the code rate, which is the relationship between them, for encoding and modulation. The code parameters may include a parity check matrix of the LDPC code to be used and information thereon, information for segmentation, information for code rate adjustment (shortening, puncturing, repetition, etc.), information for bit interleaving, information for modulation, etc.

[0118] The information bits that the transmitting device (500) intends to transmit may be referred to as a transport block (TB). Accordingly, the number of bits in a transport block may be referred to as a transport block size (TBS). The transport block may be a result obtained by encoding with an external concatenation code, such as a cyclic redundancy check (CRC) code.

[0119] In a typical communication system, the number of bits to be transmitted, i.e., TBS (or the sum of the number of parity bits generated by the TBS and the externally concatenated code), varies depending on the situation. TBS is the parity check matrix determined above. If the TBS is greater than the maximum number of input bits that can be encoded (or the number of input bits is greater than a preset value), the transport block can be divided into two or more code blocks (CB), i.e., segmented (510). Each segmented code block is input to one LDPC encoder. If the TBS is less than or equal to the maximum number of input bits (or the number of input bits is less than or equal to a preset value), segmentation is not performed. The number of code blocks determined or calculated by the above process It is called Index About The second block of code It is expressed as, here indicates the length of the corresponding code block.

[0120] Each segmented code block can be encoded with a concatenated outer code (520). The outer code may include, for example, CRC encoding, and the outer code is not restricted to a special coding technique. Whether to perform outer encoding and the type of outer code may be determined differently depending on whether segmentation is performed. The outer encoding may be used to assist the LDPC decoding operation performed by the receiver to improve performance. The outer encoding may be used to verify and examine the validity of the LDPC decoding result performed by the receiver. th code block The outer codeword obtained by encoding the vector It is written as, represents its length ( ). If external encoding is not performed . Even if no external encoding is performed for consistency. The result substituted into is called an external codeword. The bit sequence generated in this way is input to the LDPC encoder.

[0121] The outer codewords for each code block are independently LDPC encoded. Therefore, understanding how a code block is processed allows for understanding the overall processing of the transmitter. Therefore, the LDPC encoding process for a single code block is described below. For simplicity, subscripts indicating the index of the code block are used. , excluding (dropping) the code block , the external codeword which is the result of external encoding I decided to write it like this.

[0122] The above externally encoded length External codeword of is the sign dimension is encoded with an LDPC code. The LDPC code used for encoding has a code dimension The length of the house can be chosen to be as close as possible to, but greater than, or equal to, the length of the external codeword. A sign dimension If it is smaller than, A number of filler bits can be added to the encoded input bit sequence. If the length of the external codeword is and sign dimension If is equal, the number of filler bits is This is done. Filler bits are external codewords in various ways. can be added to, for example At the end of An appending method that adds filler bits may be used. This filler bit adding method is not limited to a specific method. The filler bits may be determined to have any fixed value, and are generally determined to have a fixed bit value of 0. Therefore, the process of adding the filler bits may be referred to as Zero Filling, Zero Padding, or Zero Appending (530). Since the filler bits have no value as actual information, they may be excluded from the final transmission. The process of excluding the filler bits from the final transmission can be understood as shortening, one of the code modification methods that reduces the code length and code dimension by the same amount. Encoder input vector is the external code word Perform operations such as Zero Filling and the code dimension of the LDPC code to be used for encoding. This shows the result of adjusting the length to that amount. The above filler bit is also called a shortened bit, and the term shortened bit is used below.

[0123] Input length After matching, LDPC encoding is performed (540). LDPC encoding is performed using a parity check matrix determined by the scheduling parameters, code parameters, etc. It is performed based on. Specifically, LDPC encoding is performed based on the encoding input vector given through the above series of processes. The length satisfying mathematical expression 1 based on mother codeword vector is the process of generating a parity check matrix. In other words, encoding is a parity check matrix. Encoding input vector based on A mother code vector satisfying mathematical expression 1 that is mapped to It is a process of obtaining. If the bit sequence of the input code block is directly displayed in the mother code bit sequence, it is called a systematic code, otherwise it is called a non-systematic code.

[0124] Length as output of LDPC encoding The mother tongue vector of is generated, and this mother code is transformed to fit the transmission environment and transmission resources through a rate matching process (550). The length of the coded bit sequence to be finally transmitted for the corresponding code block is called the rate-matching size. , which is a parameter determined by scheduling such as transmission environment and transmission resources. At this time, The size of the code rate adjustment of the th code block is It is written as , and here, we are dealing with a series of encoding processes of one code block, so for the sake of brevity of expression, subscripts are used. Except for It should be noted that the code rate adjustment process is described as follows. The mother tongue vector of length from codeword vector It can be understood as a process of generating a codeword vector. to the Mobuho vector To distinguish it more clearly, it is also called a transmitted codeword vector.

[0125] The above code rate adjustment process can be implemented in various ways. For example, it can be systematically performed through simple rules using a circular buffer. The size of the circular buffer to be used He said, is the length of the parentheses It may be different from the usual Is It is determined by a value less than or equal to . For example, in the 3GPP NR LDPC encoding system, if there are no special restrictions, cast ( is determined by the lifting size (a positive integer between 2 and 384) described later. Length Circular buffer of Then, each bit of the circular buffer is a mother code as shown in the following mathematical expression 2. is determined by the bits.

[0126] [Equation 2]

[0127]

[0128] Circular buffer as in the above mathematical expression 2 When configuring, the mother tongue The first of The bits of the dog are not stored or recorded in the circular buffer and are therefore excluded from transmission. 3GPP NR LDPC codes are systematic codes with length First in the Mobuho language The bits represent the encoded input bit sequence (i.e., the information bit sequence) as it is. Therefore, in the 3GPP NR LDPC encoding system, among the information bits, Systematic puncturing, or information puncturing, occurs when bits are punctured at a fixed rate. In this way, fewer information bits are transmitted, but more parity bits generated during the encoding process can be transmitted.

[0129] The code rate adjustment unit is a circular buffer configured as above. A pre-determined starting point From ( sequentially) ), and cycles through (the end of the buffer) When you reach the first point of the buffer, (Go to) Read on Select the bit of the dog. The point from which to start reading the circular buffer. can be determined by considering using Hybrid Automatic Repeat reQuest (HARQ). Also, in the circular buffer When selecting the bit of the dog, (530) added in the process The dog's short bits are not selected. If the code rate adjustment bits are Among the code word bits excluding the shortened bits recorded in the circular buffer, Puncture occurs, excluding the dog from transmission. If In this case, a repetition occurs in which all or part of the code word bits recorded in the circular buffer are transmitted more than twice.

[0130] Length generated by the above code rate adjustment The bit sequence can be transmitted through a bit interleaved coded modulation (BICM) technique, and interleaving of the rate-adjusted bit sequence can be performed to appropriately map bits to modulation symbols (560).

[0131] If the above transmission block is segmented into two or more code blocks, concatenation may be performed to combine the outputs of the above series of encoding processes for each code block into one (570). Here, the encoding results of each code block may be simply sequentially concatenated, or the encoding results of the code blocks may be mixed and concatenated according to a predetermined pattern.

[0132] After all bit-level operations are performed, a baseband signal to be transmitted is generated through modulation (580). During the modulation process, various additional operations may be performed to enable the receiving device, which will be described later, to effectively demodulate and restore the signal. The baseband signal may be transmitted on a carrier wave of the band to be used for transmission. Through the above series of operations, the bits of the transmission block may be encoded and modulated before being transmitted.

[0133] Meanwhile, although functional configurations for LDPC encoding are described in FIG. 5, in some cases, the transmitting device (500) may further include configurations for controlling the operation of the transmitting device.

[0134] According to one embodiment, the transmitter (500) may additionally include a transceiver. The transceiver performs functions for transmitting and receiving signals via a wireless channel. For example, the transceiver performs baseband signal and bit-to-bit conversion functions according to the physical layer specifications of the system. For example, when transmitting data, the transceiver generates complex symbols by encoding and modulating a transmission bit stream. Furthermore, when receiving data, the transceiver restores a reception bit stream by demodulating and decoding a baseband signal. Furthermore, the transceiver upconverts a baseband signal into an RF band signal and transmits it through an antenna, and downconverts an RF band signal received through the antenna into a baseband signal. According to various embodiments, the transmitter (500) may transmit an LDPC encoded signal to a reception device (600) described below.

[0135] To this end, the transceiver may include a transmit filter, a receive filter, an amplifier, a mixer, an oscillator, a DAC, an ADC, etc. In addition, the transceiver may include a plurality of transmit and receive paths. Furthermore, the transceiver may include at least one antenna array composed of a plurality of antenna elements. In terms of hardware, the communication unit may be composed of a digital unit and an analog unit, and the analog unit may be composed of a plurality of sub-units according to operating power, operating frequency, etc.

[0136] FIG. 6 is a block diagram illustrating a receiving device that performs channel decoding and a series of operations according to one embodiment of the present invention.

[0137] Referring to FIG. 6, the receiving device (600) may include a demodulation unit (610), a decomposition unit (620), a deinterleaving unit (630), a code rate detuning unit (640), an HARQ combining unit (650), an LDPC decoding unit (660), a zero removal unit (670), an external decoding unit (680), and a desegmentation unit (690) to estimate accurate information bits from a received signal.

[0138] The receiving device (600), like the transmitting device (500), checks or determines various parameters necessary for the receiving operation based on scheduling information, code parameters, etc. The following series of processes performed by the receiver are performed based on the various parameters checked and determined in this manner.

[0139] The operation of the demodulator (610) may include several processes depending on the case. For example, the demodulator (610) may be subdivided into a process of obtaining a channel estimation result based on the received signal, and a soft demapping process of determining values ​​(e.g., log-likelihood ratio (LLR) or a corresponding value, etc.) required for FEC (forward error control) decoding corresponding to the codeword bits from the demodulated signal or symbol based on the channel estimation result. In this case, the operation within each demodulator may be subdivided and expressed as each channel measurement block, soft demapping block, etc. Of course, more diverse subdivisions are possible depending on the structure of the system.

[0140] From now on, the operation is described assuming a receiving device (500) that calculates and processes LLR values ​​for codeword bits. However, the metric value processed by the receiving device is not limited to LLR, and any corresponding value may be used.

[0141] If the signal transmitted from the transmitting device (500) is composed of two or more code blocks, the receiving device (600) performs inverse concatenation, which is the reverse process of the concatenation (570) performed by the transmitting device, to distinguish the LLR for each code block (620). If the number of code blocks is one, inverse concatenation is not performed. Through this process, the receiving device (600) obtains the LLR sequence for each code block. The LLR sequence length for the th code block is the code rate adjustment size In the following, a series of decoding processes performed by the receiving device (600) for one code block is described, and for the sake of simplicity of expression, the code rate adjustment size is subscripted. Except for It is written as follows.

[0142] If the transmitting device (500) performs interleaving (560), the receiving device (600) performs deinterleaving (630), which is the reverse process. This process is a process of changing the order of the LLR sequence of the code block based on a set pattern, and the sequence length is unchanged. The LLR sequence obtained by performing de-concatenation and deinterleaving in this way is I decided to write it like this.

[0143] Next, the receiving device (600) performs rate dematching as the reverse process of rate adjustment (550) to obtain an LLR sequence or its corresponding value for a codeword that the LDPC decoder can process (640). That is, the rate dematching unit obtains an LLR sequence determined by the previous process. LLR sequence for the mother tongue based on Creates. th LLR is a Mobuho bit It is about.

[0144] For example, when rate adjustment using a circular buffer is performed in a 3GPP NR LDPC encoding system, rate inverse adjustment can be performed through the following process to generate an LLR sequence for the mother codeword.

[0145] 1) LLR sequence for mother tongue Initializes all values ​​to 0.

[0146] 2) Code rate inverse adjustment LLR sequence Position index for Set to the buffer start position is a scheduling parameter that allows the transmitter and receiver to confirm each other through a series of processes. Also, the input LLR sequence Position index for Set to .

[0147] 3) Perform one of the following actions depending on the processing of the mother code bits determined by the encoding process performed by the transmitter: Determines the value of .

[0148] - If from the transmitter If it is shortened (shortened bits with value 0), is determined as the LLR value, or its equivalent, which represents the probability of bit value 0 being the maximum. And Increment by , Leave it as is.

[0149] - if If it is not a shortened bit, It is decided by. That is, to the existing value of accumulates. If the decoder performs fixed-point operations, appropriate saturation or clipping operations can be performed to prevent overflow. And as, Increment by .

[0150] 4) Code rate inverse adjustment LLR sequence Index for go When this happens (reaching the end), and set it to . And the process of 3) above is repeated. This iterative operation is performed on the input LLR sequence. All LLRs of the code rate inverse LLR sequence Until it is reflected in, that is, go It is performed until it becomes .

[0151] LLR sequence for circular buffer through the above code rate adjustment process As a result of the above series of processes, the LLR of the shortened bit position is determined as the LLR value indicating the maximum probability of bit value 0, or its corresponding value. Since no value is accumulated in the LLR of the punctured bit position, the initial value remains 0, which indicates that the probability of bit 0 and bit 1 is the same at 0.5 and is not biased toward either one.

[0152] Systematic perforation according to the decoder operation of the above embodiment Length including LLR of the dog The code rate inverse adjustment LLR sequence can be generated. In this case, the code rate adjustment process can be modified and performed as follows.

[0153] 1) LLR sequence for mother tongue Initializes all values ​​to 0.

[0154] 2) Code rate inverse adjustment LLR sequence Position index for Set to the buffer start position is a scheduling parameter that allows the transmitter and receiver to confirm each other through a series of processes. Also, the input LLR sequence Position index for Set to .

[0155] 3) One of the following operations is performed according to the processing of the mother code bit determined by the encoding process performed in the transmitting device (500). Determines the value of .

[0156] - If from the transmitter If it is shortened (shortened bits with value 0), is determined as the LLR value, or an equivalent value, which indicates the probability of bit value 0 being the maximum. And Increment by , Leave it as is.

[0157] - if If it is not a shortened bit, It is decided by. That is, To the existing value of accumulates. If the decoder performs fixed-point operations, appropriate saturation or clipping operations can be performed to prevent overflow. And as, Increment by .

[0158] 4) Code rate inverse adjustment LLR sequence Index for go When this happens (reaching the end), and set it to . And the process of 3) above is repeated. This iterative operation is performed on the input LLR sequence. All LLRs of the code rate inverse LLR sequence Until it is reflected in, that is, go It is performed until it becomes .

[0159] In the following, we explain the subsequent operations assuming that the rate-adjusted LLR sequence is generated so as not to include LLRs for systematic puncturing bits. That is, the rate-adjusted LLR sequence is Assuming that it is obtained by . If we consider the systematic perforation bit, the length of in front of Consider the LLR prepending with a value of 0. Therefore, choosing one assumption for the sake of simplicity in the above explanation does not make a difference to the final decoding result.

[0160] In mobile communication systems, HARQ operations can be performed to ensure data integrity and efficiently utilize overall communication transmission resources. In this case, the receiving device transmits the HARQ LLR sequence for each code block. It operates using separate memory, etc. In addition, the receiving device and Based on this, soft combining for HARQ is performed as follows (650).

[0161] - If this transmission is the first transmission, Is is determined by. That is, all About, The substitution is performed. The code rate inverse adjustment LLR sequence The elements of are not updated separately.

[0162] - If this transmission is a retransmission (second transmission) or a subsequent transmission, class The elements at each position are added to each other. That is, the element-wise addition of the two vectors is performed. Specifically, all About, In the manner of is updated. can be updated to take into account various types of memory operations, usually go is updated (i.e. all About, ) can be rewritten to the corresponding memory.

[0163] If there is no HARQ operation, the above process can be omitted.

[0164] The LDPC decoder generates the LLR sequence through a series of processes as described above. is input and decrypted (660). As described above, the input LLR sequence is It may be a sequence containing LLRs for the systematic puncturing bits of the dog. In this case, the LDPC decoder uses the sign parameter (sign dimension , sign length , code rate adjustment size , code rate And the input LLR sequence according to the size, etc. of the various parameters and parity check matrix calculated based on this Modify or Decoding can be performed using only a portion of the parity check matrix. Specifically, when a puncture occurs in the parent code due to a high transmission code rate, the receiver can reduce the decoding complexity and processing time by not using the portion of the parity check matrix corresponding to the punctured bits for decoding according to conditions.

[0165] LDPC decoding is a process of performing belief propagation (BP) based on the LLR for the codeword bits. In the BP decoding process, a message passing operation is performed to iteratively update a posteriori LLR (AP-LLR) for the codeword bits, and the maximum number of such iterative decodings is determined based on requirements for decoding performance, time, etc. Typically, a syndrome check is performed every time the iterative decoding process is performed once or a certain number of times. This is an estimated bit sequence obtained by making a hard decision based on the updated AP-LLR. Whether is the null space for the parity check matrix, i.e., based on mathematical expression 1, which is the condition of the LDPC code. It is a process to check whether the syndrome test satisfies the estimated bit sequence. It should be noted that only some of them may be considered, and in this case, the above syndrome test formula may also be modified. The estimated bit sequence decoded through the syndrome test It verifies the validity of the decryption and determines whether to terminate the decryption early based on the validity.

[0166] As explained above, when the bits of the mother code are punctured, the LDPC decoder uses a parity check matrix to reduce the decoding complexity and processing time. A sub parity-check matrix (sub-PCM) consisting of submatrices Decoding can be performed using the sub-parity check matrix. In this case, the above series of BP decoding processes can be modified to fit the modified parity check matrix. The decryption operation using is not mandatory, but can be used to reduce complexity in general.

[0167] The estimated bit sequence for the code block obtained after LDPC decoding may include shortened bits without a fixed amount of information due to zero filling (530) performed by the transmitter. Therefore, zero removal (670) may be performed to exclude shortened bits from the estimated bit sequence as a reverse process of the zero filling performed by the transmitter (500).

[0168] When external encoding (520) is performed on the above code block, the bit sequence obtained as a result of LDPC decoding can be decoded based on the external encoding (680). Typically, error detection codes such as CRC codes are often concatenated, and in this case, the validity of the bit sequence obtained by LDPC decoding is additionally checked.

[0169] If a transmission block is composed of multiple code blocks, inverse segmentation can be performed (690), which concatenates the results of each code block to derive a final result. This process can be understood as the reverse process of segmentation (510) performed in the transmitting device (400).

[0170] The components illustrated in the above drawing 6 are components that perform functions corresponding to the components illustrated in the drawing 6, and this is only an example, and some of them may be omitted or changed depending on the case, and other components may be added.

[0171] One embodiment of the present disclosure relates to an LDPC decoding operation (660) among a series of processes performed by the receiver. As described above, the LDPC decoding operation is performed by decoding an LLR sequence It is performed based on. The initial LLR sequence used in the decoding operation is also called intrinsic LLR. This is to distinguish it from a posteriori LLR (AP-LLR), which is updated by iterative belief propagation during the decoding process. Typically, intrinsic LLR values ​​can be obtained through the demodulation process and can be used as input values ​​for the channel decoder.

[0172] LLR represents an estimate of the value of the corresponding codeword bit and the confidence or reliability of that estimate. Specifically, in one embodiment, the codeword bit LLR for is the corresponding symbol observed by the receiver Based on this, it can be defined as in the following mathematical formula 3.

[0173] [Equation 3]

[0174]

[0175] According to the definition in mathematical expression 3, LLR is the code word bit Observed symbols for the values ​​of It is the logarithm of the probability, that is, the likelihood ratio.

[0176] Code word bit in mathematical expression 3 Likelihood for value 0 is the codeword bit If it is greater than the likelihood for value 1, LLR has a positive value greater than 0. Conversely, the code word bit in Equation 3 Likelihood for value 1 is the codeword bit If it is greater than the likelihood for value 0, LLR has a negative value less than 0. Therefore, the sign of LLR indicates the more likely value among the values ​​that the corresponding code word bit can have.

[0177] In one embodiment, LLR may be defined differently from the above. For example, the numerator and denominator may be swapped in the fractional value taking the log of Equation 3. Such LL is defined as Equation 3 by only swapping the signs of the LLR (i.e., changing + to - and - to +). Although the present disclosure describes the operation of the invention by considering the LLR defined as Equation 3, the invention may be applied without any difference if the sign is swapped even if the LLR is defined differently.

[0178] Code word bit in mathematical expression 3 Likelihood and codeword bits for value 0 If the difference in likelihood for value 1 is large, LLR absolute value of becomes very large. As an extreme example, The likelihood for value 0 is 1 and the code word bit If the likelihood for value 1 is significantly different from 0, LLR has a positive infinite value. As an extreme example of the opposite, The likelihood for value 0 is 0 and the code word bit If the likelihood for value 1 is significantly different from 1, LLR has a negative infinite value. However, Likelihood and codeword bits for value 0 If the likelihood for value 1 is the same as 0.5 and there is no difference, then LLR has a value of 0. Therefore, the absolute value of LLR can be interpreted as indicating the confidence or reliability of the estimate of the values ​​that the codeword bits can have.

[0179] The process of setting the LLR values ​​for the shortened codeword bits and the punctured codeword bits in the code rate de-tuning unit (640) of the receiving device is based on the reliability expressed as the absolute value of the LLR. Although the receiving device does not receive the shortened bits, it can clearly know that the value is 0. Therefore, the LLR value for the shortened bits is set to a positive infinite value, which means that the bit value is 0 and that the certainty or reliability for it is high. In an actual implementation, it can be set to any positive number that the data type used can express. On the other hand, since the receiving device cannot know any information about the punctured bits, the LLR value for the shortened bits is determined to be 0, which means that the probability of the two values ​​that the codeword bits can have is equal to 0.5.

[0180] Intrinsic LLR sequence The absolute value of each element can be interpreted as a measure of how much the receiver's observation of each codeword bit is corrupted by noise. For example, codeword bit LLR for Absolute value of If is large, it indicates that the corresponding codeword bit has not been damaged during the series of end-to-end transmission processes (including all related processes at the transmitter and receiver). On the other hand, the codeword bit LLR for Absolute value of If it is close to zero, it indicates that the corresponding codeword bit has been corrupted during the end-to-end transmission process (including all related processes at the transmitter and receiver).

[0181] The LDPC decoding operation (660) is performed through repeated belief propagation based on the intrinsic LLR sequence as described above. An example of belief propagation decoding of an LDPC code is described below. The structure and architecture of the decoder, the algorithm used, etc. may be configured in various ways, and the scope of application of the embodiments of the present invention is not limited to a specific implementation method described below. Embodiments of the present invention may be applied to various decoding architectures and algorithms, and such application methods will be clearly understood by those skilled in the art to which the present disclosure pertains.

[0182] The decoder uses the intrinsic LLR sequence , and based on this, the AP-LLR sequence is transmitted through a trust-propagation process. Update the Intrinsic LLR sequence go AP-LLR sequence, regardless of whether it includes LLR for the dog's systematically perforated bits. Is It should be noted that the initial AP-LLR sequence for the systematically perforated bits of the dog is included. is the intrinsic LLR sequence is set to . In one embodiment, the intrinsic LLR sequence If the LLR for the systematically perforated bits is not included (i.e., ), early AP-LLR can be set as shown in the following mathematical expression 4.

[0183] [Equation 4]

[0184]

[0185] In one embodiment, the intrinsic LLR sequence If it contains LLR for systematically perforated bits (i.e., ), early AP-LLR can be set as shown in the following mathematical expression 5.

[0186] [Equation 5]

[0187]

[0188] As described above, the LDPC decoder considers the punctured bits and generates a sub-parity-check matrix (sub-PCM). If , the code length actually considered above is the code length of the mother code. Note that it may be smaller than . Whether or not a subparity check matrix is ​​used is not related to the detailed operation of the decoder, so below we will describe the parity check matrix Describe the decryption operation assuming that .

[0189] The AP-LLR sequence set as above is updated at each iteration by the iterative belief-propagation operation of LDPC decoding. This process can be understood as a message passing operation between a variable node (hereinafter VN) and a check node (hereinafter CN) on a bipartite graph corresponding to a parity check matrix (or sub-parity check matrix).

[0190] First, the message to be transmitted from the VN to the CN is determined based on the intrinsic LLR sequence or the AP-LLR sequence determined based on the intrinsic LLR sequence. VN is neighboring A message from V to C (variable-to-check message, hereinafter referred to as V2C message) At the beginning of the decryption operation, the V2C message is determined as shown in the mathematical expression 6 below.

[0191] [Equation 6]

[0192]

[0193] In the above mathematical formula 6 is VN is the set of all neighboring CNs, Is Represents a set of indices of CNs belonging to .

[0194] Each CN calculates the message to be forwarded to its neighboring VN based on the V2C message received from the neighboring VN. This neighbor VN A message from CN to VN (check-to-variable message, hereinafter referred to as C2V message) The C2V message can be calculated as shown in the mathematical expression 7 below.

[0195] [Equation 7]

[0196]

[0197] In the above mathematical formula 7 is CN is the set of all neighboring VNs, Is It represents the set of indices of VN belonging to CN as in mathematical formula 7. The neighboring VN C2V message delivered to is VN It is calculated based on V2C messages received from all other neighboring VNs except .

[0198] The C2V message calculation by the above mathematical expression 7 can be approximated and transformed in various ways. In one embodiment, the C2V message calculation as in the above mathematical expression 7 can be calculated as in the following mathematical expression 8 using the so-called min-sum approximation method.

[0199] [Equation 8]

[0200]

[0201] In the above mathematical formula 8 is the sign of the entered value is a function that outputs . And in the above mathematical expression 8, is a normalization value whose value is greater than 0, is an offset value greater than or equal to 0. The C2V message calculation by the above mathematical expression 8 is widely used because it is simpler in operation and easier to implement than the C2V message calculation by the mathematical expression 7, and it approximates the result well.

[0202] When CNs compute C2V messages for neighboring VNs, each VN updates its AP-LLR and V2C messages based on the intrinsic LLR and the C2V messages received from neighboring CNs. First, VN AP-LLR of can be calculated as shown in mathematical formula 9 below.

[0203] [Equation 9]

[0204]

[0205] And VN This neighboring CN The V2C message transmitted can be calculated as shown in the mathematical expression 10 below.

[0206] [Equation 10]

[0207]

[0208] The V2C message calculated as in the above mathematical expression 10 is the AP-LLR calculated in mathematical expression 9. It can be simply calculated using the following mathematical formula 11.

[0209] [Equation 11]

[0210]

[0211] Estimation for each codeword bit can be performed based on the updated AP-LLR as in the above mathematical expression 9. Updated AP-LLR Based on the code word bit Estimation for can be obtained through a hard decision process as shown in the following mathematical expression 12.

[0212] [Equation 12]

[0213]

[0214] The hard decision as in Equation 12 above is based on the definition of LLR in Equation 3. If the definition of LLR is different, the hard decision of Equation 12 can be modified accordingly. If the decoder of the LDPC code is implemented in a fixed-point representation, AP-LLR This can be exactly 0. In this case, the hard decision process of the above mathematical expression 12 is estimated can be determined by a pre-determined rule. In one embodiment, AP-LLR If this is 0, then the estimate can be determined by fixing it to one of the values ​​0 or 1. In one embodiment, AP-LLR If this is 0, then the estimate It can be determined by randomly selecting one of the values ​​0 or 1.

[0215] If we obtain an estimate of all codeword bits as above, the estimated codeword vector is valid in terms of a given LDPC code, i.e., Check whether it satisfies this condition. This process is called syndrome check. If the estimated codeword vector Ga syndrome test If satisfies , the estimated codeword vector is valid in terms of the LDPC code used, even if the decoding is not performed as many times as the preset maximum number of iterative decodings. can be obtained as a result and decryption can be terminated early. If the estimated codeword vector Ga syndrome test If it is not satisfied, the above series of C2V message calculation, P-LLR update, V2C message calculation, hard decision, etc. are repeated within the preset maximum number of iterated decodings. If the syndrome check formula is not satisfied within the preset maximum number of iterated decodings, Estimated codeword vector satisfying If it is not found, it is considered a decryption failure and the decryption process can be terminated.

[0216] Syndrome screening performs a syndrome check on all elements of the estimated codeword vector. However, from the perspective of the receiver, what is of interest are the information bits contained in the estimated codeword vector, so instead of using the entire estimated codeword vector, only some of the syndrome check formulas can be utilized to determine the validity of the decoding result.

[0217] As in the above series of message exchanges, the initial intrinsic LLR values ​​are exchanged with neighboring nodes due to the structure of the bipartite graph and are used to update the AP-LLR. If the absolute value of the intrinsic LLR value is small, it does not significantly affect the reliable propagation decoding operation. In other words, low-confidence LLR values ​​generated by channel-interfered or corrupted observations do not affect decoding.

[0218] Based on the characteristics of this confidence-propagation process, LDPC decoders can improve their performance by handling low-confidence LLRs (i.e., LLRs with small absolute values) in a specific way. Specifically, LDPC decoders can experiment with all guesses for bits that are judged to be low-confidence and select one of them. For example, LDPC decoders can select bits that are judged to be low-confidence. The location of the dog can be confirmed. The reliability of the bit can be determined or evaluated based on various criteria, for example, the reliability of the bit can be determined or evaluated based on the absolute value of the LLR generated by receiving a signal from the channel. And the LDPC decoder can be determined or evaluated based on the absolute value of the LLR generated by receiving a signal from the channel. All possible bit patterns for a bit of a dog After creating a dog and reflecting it in LLR, each dog can be decoded and the results can be combined to confirm the final result. For example, Then, all possible bit patterns are Like this A dog is given, one of which is for the exact bit transmitted by the transmitter. The way to reflect each bit pattern in the LLR is to assign the LLR of the maximum absolute value corresponding to the bit value to the position of each bit. Based on Equation 3, the LLR of the maximum absolute value for bit 0 is It can be any positive number, and in actual implementations it can be any positive number to consider the representable LLR range and avoid various numerical problems.

[0219] Based on Equation 3, the LLR of the maximum absolute value for bit 1 is It can be arbitrarily negative in actual implementations to consider the expressible LLR range and avoid various numerical problems. Generated as above Each modified candidate LLR sequence is decoded. The decoding operation, which performs iterative message exchanges such as trusted-propagation decoding, affects the LLR of each bit in updating the AP-LLR of other bits. Therefore, the above Among the candidate LLR sequences modified by the transmitter, the sequence containing the exact bits transmitted by the transmitter has a positive effect on the improvement of other bits through iterative reliable-propagation decoding, thereby increasing the probability of successful decoding. The success of the decoding can be confirmed by the LDPC code and related functions, and in one embodiment, it can be confirmed by a syndrome check performed by the decoder of the LDPC code and decoding of the externally concatenated CRC code.

[0220] The above series of processes reflects all possible guesses about low-confidence bits into the decoder input, and then expects that repeated belief-propagation decoding will succeed for inputs that reflect accurate guesses. This opportunistic decoding operation is called by various names, such as ensemble decoding, quasi maximum-likelihood (quasi-ML, QML) decoding, afterburner decoding, and saturate decoding. In this disclosure, these techniques will be collectively referred to as ensemble decoding.

[0221] Figure 7 illustrates a procedure of ensemble decoding in which a receiving device selects a location of an LLR with low reliability in an intrinsic LLR (log likelihood ratio) sequence and generates a modified candidate LLR sequence based on the location to perform decoding.

[0222] Figure 7 conceptually illustrates the process of an ensemble decoding technique that estimates a low-reliability LLR in all possible ways as described above and then trust-propagates the result to verify the validity of the result.

[0223] The ensemble decoding operation is performed on the intrinsic LLR sequences whose absolute values ​​are low (or judged to be low) in whole or in part. It starts with the process of finding the location of the dog. This process may involve sorting the absolute values ​​of the entire or partial range in the LLR sequence. For example, in the intrinsic LLR sequence, the number of LLRs within the range where the value will change (in short, the search range) If so, in this search range To find the LLR with the lowest absolute value of the dog A comparison operation can be performed on the values ​​of the LLR with a low absolute value. Once the location of the dog is found, the LLR value of that location is transformed into a preset positive and negative number. A modified candidate LLR sequence is generated. The above-described positive and negative numbers can generally be determined as the maximum positive and minimum negative numbers used in the LLR representation in the decoder, but this is not necessarily the case and can be determined as any positive or negative number in the representation range. For example, as shown in Fig. 7 If 3, then 8 variant candidate LLR sequences, which are all possible combinations, can be generated.

[0224] The candidate LLR sequences modified as described above can be independently decoded. As discussed above, LDPC decoding is performed through a trust-propagation process based on intrinsic LLR sequences. Since the modified candidate LLR sequences are generated with all possible combinations of codeword bits, one of them corresponds to the correct codeword bit. Therefore, the modified candidate LLR sequence, whose LLR absolute value is changed to the maximum or highest value for the correct codeword bit, transmits the correct message to other codewords through the iterative message exchange decoding operation, thereby increasing the probability of successful decoding. Therefore, After performing each decoding based on the modified candidate LLR sequence for the dog, a syndrome check, a check using the concatenated CRC code, etc. are performed. If the decoding is successfully completed, the estimate obtained by the decoding can be regarded as the result of the final successful decoding. In this way, the ensemble decoding method and device perform multiple decodings based on multiple modified candidate LLR sequences and collate the results, thereby increasing the probability of successful decoding and improving error-correction performance.

[0225] Figure 8 illustrates an example of a block diagram showing the sequence of operations of ensemble decoding.

[0226] Referring to Fig. 8, for the intrinsic LLR sequence (801), an LLR selection process (810) is performed to find a position to change the value of the LLR. In general, the LLR selection process (810) sorts the absolute values ​​of the LLR to determine a predetermined It involves finding a position with a lower value than the dog. Once the LLR position is found, the maximum for all combinations for this position is An LLR modification process (820) is performed to generate a modified candidate LLR sequence. The decoder decodes (830) each modified candidate LLR sequence and collates the results to obtain the final result (802).

[0227] The above maximum If at least one decryption based on the modified candidate LLR sequence succeeds, that result is the final output. Although unlikely, if two or more decryptions succeed, the final output is obtained according to a predetermined rule. If none of the decryptions succeeds, the decryption is declared a failure.

[0228] Below, we present a method for improving an ensemble decoding method and device based on various embodiments. The ensemble decoding method determines the location of an LLR to be changed by aligning elements of an intrinsic LLR sequence. The present disclosure proposes a method for improving the following problems or areas of improvement in the ensemble decoding method.

[0229] - The ensemble decoding method and device identify the location of the LLR whose value is to be changed based on the intrinsic LLR sequence, but this may not guarantee improvement in the final decoding result.

[0230] - The ensemble decoding method and device perform an operation that compares the absolute values ​​of all LLRs to determine the location of the LLR whose value will be changed. This operation, which is not performed in general decoding, causes additional complexity and delay.

[0231] Embodiments of the present disclosure propose a method for improving the problems of the above ensemble decoding method and device based on the structure and characteristics of LDPC codes. Various embodiments of the present invention are proposed below.

[0232] An ensemble decoding method and device according to one embodiment of the present invention is characterized in that, when determining an LLR position for which a value is to be changed based on a determined intrinsic LLR sequence, the search range of the LLR to be changed is limited to information bits (or information bits and shortened bits), or to some area that is determined to be helpful for trust-propagation decoding.

[0233] Figures 9 and 10 are diagrams illustrating the range of LLRs whose values ​​are to be changed.

[0234] Figure 9 illustrates that the search range for the receiver to find the position of the LLR whose value is to be changed in the determined intrinsic LLR sequence is the entire range excluding the bit position to be punctured.

[0235] In Fig. 9, the entire range (910) excluding the bit positions punctured in the intrinsic LLR is considered as the search range. Therefore, the number of LLRs within the search range is the minimum number of bits transmitted through the channel (i.e., the code rate-adjustment bit length). It can be. Since the LLR for the short bit is set to a large value corresponding to bit 0, including the LLR for the short bit in the search range may not make a difference in the final result. Therefore, for ease of implementation, Including LLR for the dog's short bits A position having an LLR can be found by considering a continuous range of bits as a search range. If there are no punctured bits, the number of LLRs in the search range is the maximum excluding the systematic punctured bit positions. It can be a dog.

[0236] FIG. 10 illustrates a search range for a receiving device to find a position of an LLR whose value is to be changed in a determined intrinsic LLR sequence according to one embodiment of the present disclosure.

[0237] Fig. 10 illustrates that the search range for the LLR to change the value can be limited to a portion by considering the characteristics of the bits, the configuration of the sign, etc. In one embodiment, the remaining information bits excluding the systematic puncturing bits and the shortened bits can be considered as the search range for the LLR to change the value. Accordingly, the receiving device can determine the predetermined value within this range. You can choose the LLR position of the dog. In this case, the number of bits within the search range to find the LLR whose value will change is In the entire systematic part of the dog Systematic perforation bits for dogs Except for the dog's short bits According to this embodiment, the search range for finding an LLR whose value can be changed regardless of the code rate of the LDPC code (i.e., regardless of the number of parity bits) is as shown in Fig. 10. It is fixed as a dog, and this value is The method according to the above embodiment can be implemented and realized with lower complexity and delay because it finds the LLR to change the value in a smaller search range than the method illustrated in FIG. 9.

[0238] The reason why the information bit range excluding the puncturing and shortening bits in the embodiment of the present invention is determined as the search range of the LLR whose value is to be changed is because a general LDPC code is designed to prioritize improving the information bits over the parity bits. For example, the 3GPP NR LDPC code is designed with the goal of error correction and recovery for the information bits, and accordingly, it is designed so that the VNs corresponding to the information bits receive messages from more neighboring CNs. That is, the LDPC code is designed so that the VNs corresponding to the information bits have a high degree. If the absolute value of the information bit LLR corresponding to a VN having a high degree is large, it can have a more positive effect on other bits in the repetitive message exchange by reliable propagation. The embodiment of the present invention determines the search range so as to change the LLR value of the information bit corresponding to a VN having a high degree.

[0239] FIG. 11 is a diagram illustrating an example of a search range for finding a position of an LLR to change a given value in an intrinsic LLR sequence including a systematic puncture bit according to one embodiment of the present disclosure.

[0240] Figure 11 shows the intrinsic LLR sequence. When the LLR for the systematic puncture bits of the dog is included, the search range of the LLR whose value can be changed by the above embodiment of the present disclosure is specifically shown. The index of the systematic puncture bits is from In this case, the index of the search range determined by the embodiment of the present invention is It could be.

[0241] FIG. 12 is a diagram illustrating an example of a search range for finding a location of an LLR that changes a given value in an intrinsic LLR sequence that does not include a systematic puncture bit according to one embodiment of the present disclosure.

[0242] Fig. 12 specifically illustrates the search range of LLRs whose values ​​can be changed by the embodiment of the present invention when the intrinsic LLR sequence does not include an LLR for a systematic puncture bit. Since the systematic puncture bit does not exist, the index of the search range determined by the embodiment of the present invention in this case is It can be. For the convenience of implementation, the search range is It can be determined to include a short bit of the dog, in which case the index of the search range determined by the embodiment of the present invention is It could be.

[0243] FIG. 13 is a diagram for explaining the effect of achieving low complexity when determining a search range in a 5G NR (new radio) LDPC code system according to one embodiment of the present disclosure.

[0244] Figure 13 shows the code dimension in the 5G NR LDPC code system. If is 256, The computational complexity of the method (Method 1) for determining the search range of the entire LLR shown in Fig. 9 to find the LLR to change the value of the dog and the method (Method 2) of the embodiment of the present disclosure shown in Fig. 10 is shown. Here, both Method 1 and Method 2 determine the search range in the order of the smallest absolute value. Check the location of the dog LLR. For example, the size of the search range If so, then to find the LLR with the smallest absolute value, Comparison operations may be required. To find the next smallest LLR of absolute value, we need to compare the remaining elements except for the LLR of the smallest absolute value found previously. A comparison operation may be required. In summary, if the above method is used, the size The LLR position with the smallest absolute value in the search range The total number of comparison operations performed to find a dog is It could be.

[0245] The X-axis in Figure 13 represents the code rate. A lower code rate generates more parity bits, resulting in a code rate-adjusted length As the code rate increases, fewer parity bits are generated, resulting in a code rate-adjusted length The Y-axis of Fig. 13 is the position of the LLR with the smallest absolute value in the search range of each method as described above. Represents the total number of comparison operations performed to find a dog.

[0246] In Fig. 13, the first curve (1301) is the total number of comparison operations performed by the method 1, and the curve (1302) is the total number of comparison operations performed by the method 2. As can be confirmed through a comparison of the curves (1301) and (1302), the method of limiting the search range for finding the LLR with the smallest absolute value among the LLR sequences illustrated in Fig. 10 corresponding to the method 2 reduces the complexity by performing a smaller number of comparison operations than the method 1. In addition, the method 2 always performs the same number of comparison operations regardless of the code rate.

[0247] FIG. 14 is a diagram for explaining the effect of achieving error-correction performance when determining a search range in a 5G NR LDPC code system according to one embodiment of the present disclosure.

[0248] FIG. 14 illustrates an evaluation of the error-correction performance of a method (method 1) for determining a search range for the entire LLR illustrated in FIG. 9 according to a code dimension and a code rate in a 5G NR LDPC code system and a method (method 2) of the embodiment of the present disclosure illustrated in FIG. 10.

[0249] In Figure 14, the X-axis is the sign dimension , and the Y-axis represents the signal-to-noise ratio (SNR) at which BLER 1% is achieved through a block error rate (BLER) evaluation experiment for each sign parameter. (dB) value was checked.

[0250] All individual points in Fig. 14 are verified through experiments to obtain a BLER curve. The value of the Y-axis is BLER 1%. A smaller value indicates better error-correction performance, as it means that the same BLER can be achieved with less energy.

[0251] A diagram evaluating error-correction performance, such as in Fig. 14, is useful for effectively representing experiments for various code parameters (code dimension, code rate), and is also used in the present disclosure when explaining the effects of other embodiments later.

[0252] Fig. 14 includes experimental results for various code rates, and each curve represents an experiment for code parameters with the same code rate. The ensemble decoding method by the method (method 1) for determining the search range for the entire LLR illustrated in Fig. 9 and the method (method 2) of the embodiment of the present disclosure illustrated in Fig. 10 is performed in the intrinsic LLR sequence. Find the LLR position with the lowest absolute value and change the value of LLR at that position to all possible patterns. Decoding is attempted by generating a modified candidate LLR sequence. Methods 1 and 2 differ in that they set different search ranges for finding LLR positions where values ​​will be changed. For reference, the results of normal decoding (normal BP) without ensemble decoding are also shown.

[0253] As illustrated in FIG. 14, the method considering a limited search range according to the above embodiment of the present disclosure can achieve almost the same error-correction performance as the method considering the entire LLR sequence as the search range. Accordingly, as confirmed through FIGS. 13 and 14, the method considering a limited search range according to the above embodiment of the present disclosure can achieve the same error-correction performance with a smaller number of operations compared to the method considering the entire LLR sequence as the search range.

[0254] Below, a method is described for determining the position of the LLR whose value is to be changed based on the AP-LLR obtained after one decoding based on the intrinsic LLR sequence.

[0255] An ensemble decoding method and device according to an embodiment of the present disclosure determines the positions of LLRs to be changed based on the AP-LLR sequence finally obtained when decoding fails after attempting decoding based on an intrinsic LLR sequence. This operation can perform pre-compensation by identifying the position of the LLR that ultimately failed to converge and thus caused decoding to fail when performing decoding based on the intrinsic LLR sequence. In the above embodiment, decoding performance can be improved by changing the LLR that ultimately contributes to the decoding failure.

[0256] FIG. 15 illustrates a procedure for determining the positions of LLRs whose values ​​are to be changed based on an AP-LLR sequence obtained by decoding an intrinsic LLR sequence as input according to one embodiment of the present invention, changing the values ​​of the intrinsic LLR sequence based on these positions, and performing ensemble decoding based on this.

[0257] Fig. 15 is a block diagram illustrating the process of the above embodiment. First, the receiving device can perform general decoding (1510) on the determined intrinsic LLR sequence (1501). If the decoding is successful, the receiving device can obtain the estimate obtained from the decoder as the final result (1503). If the decoding fails, the receiving device can perform an LLR selection (1520) process for determining the LLR position to change the value based on the AP-LLR (1502) updated by the iterative trust-propagation decoding. The method for determining the LLR position to change the value based on the AP-LLR can be implemented through various specific operations, and the present invention is not limited to any specific method. In one embodiment, the predetermined LLR to change the value is selected. The position of the LLR of the dog can be determined based on the absolute value of each element of the AP-LLR sequence, for example, the one with the smallest absolute value. The position of the dog can be determined. Once the position of the LLR to change the value is determined, the receiving device changes the value of the corresponding position in the intrinsic LLR sequence to the maximum. A modified candidate LLR sequence can be generated (1530).

[0258] According to the embodiment illustrated in FIG. 15, the receiving device can select the position of the LLR whose value is to be changed based on the updated AP-LLR sequence after performing repeated trust-propagation as many times as the preset maximum number of iterated decodings. Furthermore, according to the embodiment of the present disclosure, the position of the LLR whose value is to be changed is determined based on the AP-LLR sequence, but the modified candidate LLR sequence is generated by changing the corresponding position element of the intrinsic LLR sequence.

[0259] In the process of determining the position of the LLR whose value is to be changed based on the AP-LLR sequence by the receiving device, the search range of the AP-LLR sequence may include an LLR (value 0) for a punctured bit in the intrinsic LLR sequence used as the search target, which need not be considered as the position of the LLR whose value is to be changed, and thus may not be included in the search range. According to an embodiment of the present disclosure, the operation of selecting the LLR position to be changed is based on the AP-LLR sequence obtained after decoding, and the AP-LLR for the punctured bit can be updated by an iterative trust-propagation operation. Therefore, unlike the LLR position selection method based on the intrinsic LLR sequence, in the method according to the embodiment of the present disclosure, the punctured bit can also be considered as a position where the value of the LLR can be changed. In the embodiment of the present disclosure, the punctured bits considered as positions where the value can be changed may include systematic punctured bits (information bits) and general punctured bits (parity bits).

[0260] FIG. 16 illustrates an example of a search range for determining the position of an LLR whose value is to be changed based on an AP-LLR sequence according to one embodiment of the present invention.

[0261] The AP-LLR sequence can be broadly divided into a systematic portion (the portion containing the information bits) and a parity portion. The systematic portion can be further divided into a systematic puncturing portion, a shortening portion, and a remainder portion. The parity portion can be divided into a portion where the LLR is updated through iterative decoding and a portion where it is not.

[0262] As described above, the LLR for some or all of the punctured bits can be updated through repeated, reliable-propagation decoding operations. In particular, since the systematically punctured portion is for information bits, restoration of this portion is essential, and therefore the AP-LLR for this portion is necessarily updated.

[0263] According to one embodiment of the present disclosure, the position of the LLR whose value is to be changed can be determined by taking the entire range of LLRs in which the AP-LLR is updated as a search range, as illustrated in 1610 of FIG. 16. This search range may include systematic puncturing bits, remaining systematic bits, parity bits in which the AP-LLR is updated, and shortened bits. In this case, the AP-LLR for the shortened bits generally does not affect the determination of the position of the LLR to be changed. Therefore, in one embodiment of the present invention, the receiving device considers the entire range in which the LLR is updated as a search range in the process of finding the position of the LLR whose value is to be changed from the AP-LLR sequence, and the search range may or may not include the shortened bits.

[0264] According to one embodiment of the present disclosure, as illustrated in 1620 of FIG. 16, the position of the LLR whose value is to be changed can be determined by using the LLR of the systematic range in which the AP-LLR is updated as a search range. The search range may include systematic puncturing bits, the remaining systematic bits, and shortened bits. In this case, the AP-LLR for the shortened bit generally does not affect the determination of the position of the LLR to be changed. Therefore, as illustrated in 1620, the receiving device considers the systematic range in which the LLR is updated as the search range in the process of finding the position of the LLR whose value is to be changed from the AP-LLR sequence, and the search range may or may not include the shortened bit.

[0265] According to one embodiment of the present disclosure, as illustrated in 1630 of FIG. 16, the position of the LLR whose value is to be changed can be determined by using the LLR for the systematic puncturing bits for which the AP-LLR is updated as a search range. This search range may include all or part of the systematic puncturing bits. For example, the 3GPP NR LDPC code is designed so that the systematic puncturing bits are effectively restored, and thus, the VNs corresponding to the systematic puncturing bits are designed to receive messages from more neighboring CNs. That is, the LDPC code is designed so that the VNs corresponding to the systematic puncturing bits have a high degree. If the absolute value of the information bit LLR corresponding to the VN having a high degree is large, it can have a more positive effect on other bits in the repeated message exchange by trust-propagation, thereby increasing the probability of successful decoding. Accordingly, based on this basis, the search range is determined to change the LLR value of the information bit corresponding to the VN having a high degree, as in 1630 of Fig. 16.

[0266] Fig. 17 illustrates an example of the performance of restricting the positions of LLRs to be changed according to the post-LLR sequence. Fig. 17 shows the results of evaluating the error-correction performance of a conventional method (e.g., method 1) and a method (e.g., method 3) that uses restrictions on the positions of LLRs to be changed using AP-LLR according to embodiments of the present disclosure, depending on the code dimension and code rate in a 5G NR LDPC code system.

[0267] Referring to Figure 17, the graph (1700) represents the error correction performance by code dimension. The horizontal axis of the graph (1700) represents the code dimension. , and the vertical axis of the graph (1700) represents the signal-to-noise ratio (SNR) to achieve the required BLER (block error rate) of 1%. (dB) value. The graph (1700) includes experimental results for various code dimensions. For example, the graph (1700) may include error-correction performance of general decoding other than ensemble decoding, error-correction performance of ensemble decoding according to the first example (1610) of the third method, error-correction performance of ensemble decoding according to the second example (1620) of the third method, and error-correction performance of ensemble decoding according to the third example (1630) of the third method. Each curve represents an experiment for a code parameter having the same code rate. In the ensemble decoding method according to the third method, the decoder may search in each search range of the AP-LLR sequence. Find the LLR position with the lowest absolute value and change the value of LLR at that position to all possible patterns. Decoding is attempted by generating a modified candidate LLR sequence. Graph (1700) also includes the result of normal decoding (normal BP) without applying ensemble decoding.

[0268] As illustrated in FIG. 17, it can be confirmed that almost similar error-correction performance is achieved for various code dimensions and code rates even though the search ranges are set differently according to examples of the third method (e.g., the first example (1610), the second example (1620), and the third example (1630)). Since the search range of the third example (1630) is the narrowest, ensemble decoding according to the third example (1630) may be advantageous for implementation in terms of providing the same and / or similar performance with low complexity.

[0269] Although the above figure 17 shows the results for the method (the third method) of performing ensemble decoding based on the AP-LLR sequence, the method of performing ensemble decoding based on the intrinsic LLR sequence also generally provides better performance than the conventional method.

[0270] In the ensemble decoding method according to the above two methods (e.g., ensemble decoding according to the second method and ensemble decoding according to the third method), the decoder decodes the intrinsic LLR sequence and the AP-LLR sequence, respectively. Find the LLR position with the lowest absolute value and change the value of LLR at that position to all possible patterns. Decoding is attempted by generating a modified candidate LLR sequence. In the method based on the intrinsic LLR sequence (the second method), the non-punctured systematic bits can be determined as the search region. In the method based on the AP-LLR sequence (the third method), the systematic punctured bits can be determined as the search region. In both methods, as described above, the LLR value of the bit index of the changed region in the intrinsic LLR sequence is replaced with the candidate value. In the case where the number of bit indices of the changed region is three ( ) can form a total of 8 candidate patterns, and in the case of 4 ( ) can form a total of 16 candidate patterns. Based on the intrinsic LLR sequence, as 8 or 16 candidate patterns are applied to the change area, the decoder can generate 8 or 16 candidate input sequences. The decoder can obtain a final decoding result by performing decoding on each candidate input sequence of at least some of the candidate input sequences.

[0271] Typically, determining the change area based on AP-LLR often outperforms determining the change area based on intrinsic LLR. However, determining the location of the LLR to be changed based on AP-LLR (method 3) is performed additionally after completing a single decoding operation based on intrinsic LLR, so its complexity and delay may be relatively higher than those of the intrinsic LLR-based method (method 2). Therefore, either method can be effectively selected depending on the conditions, environment, and requirements of the LDPC code system.

[0272] FIG. 18 is a flowchart showing an ensemble decoding operation of a channel code performed by a receiving device according to one embodiment of the present invention.

[0273] In step 1810, the receiving device may generate a first input sequence based on a signal (or bit) encoded with a channel code received from the transmitting device. In step 1820, the receiving device may determine a search range of one element to be changed in order to generate a plurality of second input sequences in the first input sequence based on the structure of the channel code. In one embodiment, the receiving device may determine a search range of at least one element to be changed in order to generate a plurality of second input sequences in the first input sequence based on the structure of the channel code. In one embodiment, the length of the search range may be shorter than the length (E) of the encoded and transmitted bit. In one embodiment, the length of the search range is a length of the encoded and transmitted bit and a length of the parent code (N=N). b Z) may be shorter than the smaller one.

[0274] In one embodiment, the receiving device determining the search range of the at least one element may include performing decoding on the first input sequence, identifying a first output sequence generated or updated based on the decoding, and determining the search range of the at least one element based on the first output sequence. In one embodiment, the receiving device may determine the search range of the at least one element based on the first output sequence, if the first output sequence is updated, based on one of the positions of updated elements in the first output sequence, the positions of updated information bits in the first output sequence, and the positions of updated cinematic puncture bits in the first output sequence. In one embodiment, the search range of the at least one element may be determined in advance.

[0275] In one embodiment, the search range may be determined based on information bits, perforated bits within the information bits, and shortened bits within the information bits. In one embodiment, the length of the search range may be a value (K-2Z-F) obtained by subtracting the length of the perforated bits within the information bits (2Z) and the length of the shortened bits within the information bits (F) from the length of the cinematic portion (K).

[0276] In step 1830, the receiving device may determine at least one element to be modified to generate the at least one second input sequence based on the search range. In one embodiment, the receiving device may determine at least one element to be modified to generate the at least one second input sequence based on the search range. In one embodiment, when the first input sequence is an LLR sequence, the receiving device determining at least one element used to generate the at least one second input sequence may include determining at least one of a predetermined n elements having a low reliability value.

[0277] In step 1840, the receiving device may generate the at least one second input sequence by changing the at least one element. In one embodiment, the receiving device generates the at least one second input sequence by changing the at least one of the n determined elements in the first input sequence. n It may include generating a plurality of second input sequences of the dog.

[0278] At step 1850, the receiving device can perform decoding on each of the at least one second input sequence to determine a final decoding result.

[0279] In one embodiment, the receiving device can receive information necessary for the decoding from the transmitting device, and the first input sequence can be decoded based on the information necessary for the decoding. In one embodiment, when the receiving device is a terminal and the transmitting device is a base station, the information necessary for the decoding can be transmitted via an upper layer message.

[0280] FIG. 19 is a flowchart showing a decoding-related setting operation based on capability information of a terminal when a transmitting device is a base station and a receiving device is a terminal according to one embodiment of the present invention.

[0281] FIG. 19 is a case where the transmitting device (200) illustrated in FIG. 2 is a base station (1902) and the receiving device (240) is a terminal (1901).

[0282] At step 1910, the base station (1902) may request UE capability information from the terminal (1901).

[0283] In step 1920, the terminal (1901) may transmit UE capability information to the base station (1902). However, if the base station has already received the UE capability of the terminal, the step of the base station requesting the UE capability from the terminal and receiving the UE capability information may be omitted.

[0284] In step 1930, the base station (1902) may transmit an RRC connection reconfiguration message to the terminal (1901) including decoding-related configuration information or predetermined decoding-related configuration information considering the UE capability information. However, the RRC connection reconfiguration message is an example for transmitting the decoding-related configuration information, and a message transmitted by the base station to the terminal (e.g., a message transmitted from a higher layer) may correspond to this and is not limited to the RRC connection reconfiguration message.

[0285] In one embodiment, the decoding-related configuration information may include code parameters used during encoding. The code parameters may include a parity check matrix of the LDPC code to be used and information thereon, information for segmentation, information for code rate adjustment (shortening, puncturing, repetition, etc.), information for bit interleaving, information for modulation, etc. In one embodiment, the decoding-related configuration information may include scheduling information. In one embodiment, the decoding-related configuration information may include an LLR or a value corresponding thereto.

[0286] In step 1940, the terminal (1901) can make decryption-related settings based on the information included in the RRC connection reconfiguration message.

[0287] At step 1950, the terminal (1901) may transmit an RRC connection reconfiguration complete message to the base station (1902).

[0288] The terminal (1901) that has completed the decryption-related settings as described above can then receive an encoded signal from the base station (1902) and perform decryption based on the decryption-related settings.

[0289] Figures 20 and 21 are block diagrams for ensemble decoding using signal expansion.

[0290] A span decoding method and device according to one embodiment of the present disclosure performs decoding by adding a virtual LLR value to a punctured bit position of an intrinsic LLR sequence. That is, the present embodiment performs decoding at a changed position in an area separated by the same distance due to a virtual signal from a received signal. In this case, the range to which a signal is added can be selected to include bits punctured in the systematic (e.g., information bits) or bits punctured in the parity. This method (hereinafter, the fourth method) ultimately provides the effect of lowering the code rate as the parity bit of a given signal is virtually expanded, which means improved decoding performance compared to the existing method.

[0291] Referring to Fig. 20, a general decoding (1810) is performed on an intrinsic LLR sequence (2001). If the decoding (1810) is successful, the estimate obtained from the decoder is obtained as the final result (2002). Although not shown in Fig. 20, if the decoding (1810) fails, the intrinsic LLR sequence (2001) can be used for virtual extension (1820). The decoder can virtually add LLR values ​​at the punctured bit positions of a given signal. In this case, the positions where the values ​​are changed are predetermined by reflecting the structural characteristics of the code, rather than using the intrinsic LLR value of the given signal and the values ​​calculated by the decoding.

[0292] Referring to FIG. 21, unlike FIG. 20, the decoder may perform virtual expansion (1820) directly from an LLR sequence (e.g., an intrinsic LLR sequence (2101)) without performing general decoding. The decoder may virtually add an LLR value to at least one of the punctured bits of the LLR sequence (e.g., an intrinsic LLR sequence (2101)). The decoder according to embodiments of the present disclosure may utilize at least one of the method according to FIG. 20 or the method according to FIG. 21.

[0293] The method for determining where to add a virtual LLR in a perforated bit (hereinafter, the fourth method) can be implemented through various operations, and the operation of the decoder of the present disclosure is not limited to any specific method. For example, a predetermined location to add a value The location of the LLR of the dog can be determined sequentially within the punched bit sequence, i.e., the smallest in the punched parity bit index. The position of the dog can be determined. Once the puncture bit positions of the LLR to which the value is to be added are determined, the decoder can perform ensemble decoding (1830). The decoder adds the value to the intrinsic LLR sequence (2101) to obtain the maximum It is possible to generate a modified candidate LLR sequence of a dog.

[0294] A decoder according to an embodiment of the fourth method can select a position to add an LLR value based on the positions of puncture bits of an LLR sequence (e.g., an intrinsic LLR sequence (2001 or 2101)) determined from a received signal. The fourth method may be understood as finding a position to additionally generate a candidate pattern for ensemble decoding in addition to the determined LLR sequence, rather than limiting a position to change an LLR value for ensemble decoding within the LLR sequence.

[0295] As shown in Fig. 8, in the first conventional method, LLR selection (810) is performed to find a position to change the value of the LLR for the intrinsic LLR sequence (801). For example, the absolute value of the LLR is generally sorted to determine a pre-determined A process of finding a position with a lower value than the dog is used. On the other hand, the decoder according to the fourth method does not go through this search process, and the position where the LLR value is to be changed is determined according to the configuration of the code. For example, in the 3GPP NR system, the decoder can consider the search range of the LLR to change the values ​​of the systematic puncture bits and the general puncture bits. The decoder can determine the search range based on the predetermined value. The LLR positions of the bits can be selected. In this case, the specific positions for changing the values ​​within the search range can be determined by considering the structure and implementation of the code. For example, the 3GPP NR LDPC code was designed to support various code rates by sequentially expanding single-order parity bits in consideration of ease of operation. The LDPC code can obtain the effect of lowering the code rate than the given signal as the parity is expanded by sequentially adding virtual signals from low indices in the punctured parity part. In addition, in the case of systematic puncturing bits, it is designed to improve decoding performance by puncturing some of the VNs with high orders. If a value with a large absolute value of the bit LLR is added to this part, it can have a greater impact on other bits in the repetitive message exchange by reliable propagation.

[0296] In embodiments of the present disclosure, by adding a virtual signal to the parity punctured bit, the code extension can be applied preferentially over the systematic punctured bit. The systematic punctured bit can be determined as a change area for changing the LLR value after the parity punctured bit is changed. For example, the number of additionally punctured bits If the size of the change area is smaller than q (e.g., the number of bits corresponding to the change area), Bits of a plurality of LLR sequences (e.g., intrinsic LLR sequence (2001), intrinsic LLR sequence (2101)) may be selected as part of the change region. In the embodiment of the present disclosure, since the process of selecting a location to change a value using intrinsic or AP LLR is omitted, the implementation and realization process is simplified, thereby reducing implementation complexity and delay due to decoding.

[0297] Figures 22 to 25 illustrate examples of ensemble decoding using signal expansion. Figures 22 to 25 illustrate areas where LLR values ​​will change according to the fourth method.

[0298] Referring to Figure 22, the intrinsic LLR sequence is the entire N b can have length Z. The entire N b The length of Z can correspond to the sign length N. N b can be determined according to the base graph for the LDPC code. For example, the code length can be 66Z or 50Z depending on the base graph. The Z can correspond to the lifting size for the LDPC code. Fig. 22 shows an intrinsic LLR sequence. LLR and punched parity bits for the dog's systematic punched bits If the LLR of the dog is included, the value can be changed. The LLR positions of the dogs are specifically illustrated. The index 0 of the bits of the intrinsic LLR sequence may start from the punctured systematic puncture bit. According to an embodiment of the present disclosure, the LLR positions whose values ​​can be changed may be determined from the punctured parity bit portion based on rate matching, and when q, which is the number of LLR positions whose values ​​can be changed, is greater than p, which is the number of parity bits, a portion of the systematic puncture bits may be determined as the positions of the LLRs whose values ​​can be changed. For example, the change area ( ) is obtained through mathematical equation 13 below.

[0299] [Equation 13]

[0300]

[0301] represents the bit index of the i-th position within the change area. N b Z can correspond to the code length N. Z can correspond to the lifting size for LDPC. E represents the number of bits according to the code rate adjustment (e.g., the number of bits transmitted over a wireless channel), and F represents the number of bits shortened according to zero filling (e.g., zero filling (530)). q represents the size of the change region.

[0302] Referring to Figure 23, the intrinsic LLR sequence is the entire N b can have length Z. The entire N b The length of Z can correspond to the sign length N. N bcan be determined according to the base graph for the LDPC code. For example, the code length can be 66Z or 50Z depending on the base graph. The Z can correspond to the lifting size for the LDPC code. Fig. 23 shows a case where the intrinsic LLR sequence includes LLRs for systematic puncturing bits but does not include all punctured parity bits (i.e., includes some parity bits), and the value can be changed. The LLR positions of the dogs are specifically shown. Unlike Fig. 22, the parity bits When grouped by dog, groups that do not include even one bit of LLR value can be excluded from the selection area for implementation and delay time improvement. According to an embodiment of the present disclosure, the LLR position where the value can be changed can be determined from the punctured parity bit portion based on the rate match, and the parity bits When grouped by dog, groups that do not include even one bit of the LLR value can be excluded. If q, the number of LLR positions where the value can be changed, is greater than the number of parity bits that are not excluded, some of the systematic puncturing bits can be determined as the positions of the LLR where the value can be changed. Specifically, mathematical expression 14 can represent the LLR change area determined by the embodiment.

[0303] [Equation 14]

[0304]

[0305] represents the bit index of the i-th position within the change area. N bZ can correspond to the code length N. Z can correspond to the lifting size for LDPC. E represents the number of bits according to the code rate adjustment (e.g., the number of bits transmitted over a wireless channel), and F represents the number of bits shortened according to zero filling (e.g., zero filling (530)). q represents the size of the change region.

[0306] In Figs. 24 and 25, the search range of the LLR whose value can be changed is specifically illustrated when the intrinsic LLR sequence does not include an LLR for a systematic puncture bit. Fig. 24 has the same operation of the parity part as Fig. 22, but since the intrinsic LLR sequence does not include a systematic puncture bit, the change range of the LLR can be determined according to mathematical expression 15.

[0307] [Equation 15]

[0308]

[0309] represents the bit index of the i-th position within the change area. N b Z can correspond to the code length N. Z can correspond to the lifting size for LDPC. E represents the number of bits according to the code rate adjustment (e.g., the number of bits transmitted over a wireless channel), and F represents the number of bits shortened according to zero filling (e.g., zero filling (530)). q represents the size of the change region.

[0310] FIG. 25 is a case where the systematic puncture bits and the entire punctured parity bits are not included (i.e., the system puncture bits are not included and some parity bits are included), and the LLR change range can be determined according to Equation 16.

[0311] [Equation 16]

[0312]

[0313] represents the bit index of the i-th position within the change area. N b Z can correspond to the code length N. Z can correspond to the lifting size for LDPC. E represents the number of bits according to the code rate adjustment (e.g., the number of bits transmitted over a wireless channel), and F represents the number of bits shortened according to zero filling (e.g., zero filling (530)). q represents the size of the change region.

[0314] In Figs. 24 and 25, the LLR search range is presented starting from the first bit of the unperforated systematic bit for the sake of implementation convenience, but it can be applied in a variety of ways. For example, considering the weight distribution of the parity check matrix of the 5G LDPC code, the LLR search range is not the first bit of the systematic bit, but The th bit can be determined as the starting point of the search range, and the bit index can be determined in the following mathematical expression 17.

[0315] [Equation 17]

[0316]

[0317] or

[0318]

[0319] Additionally, the search range can be determined in advance based on the weight (or degree) distribution of the parity check matrix. For example, among the basic matrices of LDPC codes defined in TS 38.212, the 3GPP 5G standard specification, The weights of the 0th and 1st columns are the highest at 30 and 28, and the weights of the 2nd, 3rd, 4th, and 5th columns are arranged in the order of 7, 11, 9, and 4, respectively. If the column with a relatively high weight of 11 is set as the starting point of the search range, can be set as follows. Similarly, among the basic matrices of LDPC codes defined in TS 38.212 document, The weights of the 0th and 1st columns are the highest at 22 and 23, and the weights of the 2nd, 3rd, 4th, and 5th columns are arranged in the order of 10, 5, 5, and 14, respectively. If the column with a relatively high weight of 14 is set as the starting point of the search range, It can be set as follows. In the above mathematical expression 17, is a value defined by considering the bit-unit index, but if the index is expressed in Z-bit block units, The value can also be expressed as an integer value in units of Z-bit blocks. In other words, when the LLR search range is determined by shifting it by kZ bits, It can be expressed as , but considering the Z-bit block unit It can also be defined as follows. As a specific example, , Values ​​such as these are considered in Z-bit block units. , It may be decided as follows.

[0320] The method of determining the search range by considering the weight distribution in the basic matrix or parity check matrix can be similarly applied to the methods of Figs. 10 to 12. For example, in the case of the method of Fig. 10, the search range for finding the LLR is The index of the search range for finding LLR in the case of the method of Fig. 11 is fixed as a dog. It can be, and in the case of the method of Fig. 12, the index of the search range for finding LLR is or It can be expressed as follows. In the case of Fig. 12, the weight is selected considering If bits are always excluded from the search range, the index of the search range for finding LLR is or It can also be expressed as follows.

[0321] The receiving device of the present disclosure receives a signal encoded and transmitted with a channel code used, generates an original decoder input sequence (or vector, array, etc.) such as a log-likelihood ratio (LLR) sequence from the signal, generates at least one modified decoder input sequence by changing at least one element in the original decoder input sequence, performs decoding based on each of the at least one modified decoder input sequence, and determines a final decoding result based on results obtained from the decoding performed on each of the at least one modified decoder input sequence, wherein at least one element to be changed in the original decoder input sequence can be determined within a limited range determined based on the structure and characteristics of the channel code used.

[0322] In addition, the receiving device of the present disclosure may receive a signal encoded and transmitted with a channel code, generate an original decoder input sequence (or vector, array, etc.) such as a log-likelihood ratio (LLR) sequence from the signal, perform decoding based on the original decoder input sequence, obtain a decoder output sequence generated by the decoder when decoding based on the original decoder input sequence fails, determine a position at which a value of at least one element is to be changed based on the decoder output sequence, change at least one of the elements of the original decoder input sequence based on the position of the element at which the value is to be changed to generate at least one or more modified decoder input sequences, perform decoding based on each of the at least one or more modified decoder input sequences, and determine a final decoding result based on results obtained from the decoding performed on each of the at least one or more modified decoder input sequences.

[0323] The present disclosure can be applied to intelligent services (e.g., smart homes, smart buildings, smart cities, smart cars or connected cars, healthcare, digital education, retail, security and safety-related services, etc.) based on 5G communication technology and IoT-related technology. The present disclosure provides an apparatus and method for efficiently decoding bits, symbols, signals, etc. encoded with channel codes such as low-density parity-check (LDPC) codes and turbo codes and transmitted through a channel in a communication or broadcasting system. In addition, the present disclosure provides an apparatus and method for efficiently realizing and implementing ensemble decoding, which determines a final result by decoding two or more modified LLR sequences generated by changing the value of at least one element in a log-likelihood ratio (LLR) sequence input to a decoder. Specifically, the ensemble decoding method and device according to an embodiment of the present invention are characterized in that they determine at least one element whose value is to be changed based on a limited range in consideration of the structure and characteristics of the code being used. In addition, the ensemble decoding method and device according to the embodiment of the present invention are characterized in that they attempt decoding based on a decoder input LLR sequence and determine at least one element whose value is to be changed based on a decoder output LLR sequence obtained thereby.

[0324] The methods according to the embodiments described in the claims or specification of the present disclosure may be implemented in the form of hardware, software, or a combination of hardware and software. If implemented in software, a computer-readable storage medium storing one or more programs (software modules) may be provided. The one or more programs stored in the computer-readable storage medium are configured for execution by one or more processors within an electronic device. The one or more programs include instructions that cause the electronic device to execute the methods according to the embodiments described in the claims or specification of the present disclosure.

[0325] These programs (software modules, software) may be stored in random access memory, non-volatile memory including flash memory, read only memory (ROM), electrically erasable programmable read only memory (EEPROM), magnetic disc storage device, compact disc ROM (CD-ROM), digital versatile discs (DVDs) or other forms of optical storage device, magnetic cassette. Or, they may be stored in a memory configured as a combination of some or all of these. In addition, each configuration memory may be included in multiple numbers.

[0326] Additionally, the program may be stored in an attachable storage device that is accessible via a communication network such as the Internet, an intranet, a local area network (LAN), a wide local area network (WLAN), a storage area network (SAN), or a combination thereof. Such a storage device may be connected to a device performing an embodiment of the present disclosure via an external port. Additionally, a separate storage device on the communication network may be connected to a device performing an embodiment of the present disclosure.

[0327] In the specific embodiments of the present disclosure described above, components included in the invention are expressed in the singular or plural form, depending on the specific embodiment presented. However, the singular or plural expressions are selected to suit the presented situation for convenience of explanation, and the present disclosure is not limited to singular or plural components. Components expressed in the plural form may be composed of singular elements, or components expressed in the singular form may be composed of plural elements.

[0328] While the detailed description of this disclosure has described specific embodiments, it should be understood that various modifications are possible without departing from the scope of this disclosure. Therefore, the scope of this disclosure should not be limited to the described embodiments, but should be defined not only by the scope of the claims described below, but also by equivalents thereof.

Claims

1. In a method for decoding a channel code of a receiving device in a communication system, A step of generating a first input sequence based on bits encoded with a channel code received from a transmitting device; In the first input sequence, a step of determining a search range of at least one element to be changed to generate a plurality of second input sequences based on the structure of the channel code; A step of determining at least one element to be changed to generate at least one second input sequence based on the search range; generating at least one second input sequence by changing at least one element; and A method characterized by comprising the step of performing decoding for each of the at least one second input sequence to determine a final decoding result.

2. In the first paragraph, the step of determining the search range of at least one element is: A step of performing decoding on the first input sequence; A step of identifying a first output sequence generated or updated based on the above decryption; and A step of determining a search range of at least one element based on the first output sequence, The length of the above search range is the length of the encoded bit (E) and the length of the parent code (N=N b Z) is shorter than the smaller one, A method characterized in that the search range of at least one element is predetermined.

3. In paragraph 1, A method characterized in that the above search range is determined based on information bits, perforated bits within information bits, and shortened bits within information bits.

4. In paragraph 1, A method characterized in that the length of the above search range is a value obtained by subtracting the length of the punctured bits (2Z) within the information bits and the length of the shortened bits (F) within the information bits from the length of the cinematic portion (K) (K-2Z-F).

5. In the second paragraph, the step of determining the search range of the at least one element based on the first output sequence is: A method characterized in that it comprises the step of determining a search range of at least one element based on one of the positions of updated elements in the first output sequence, the positions of updated information bits in the first output sequence, and the positions of updated cinematic perforation bits in the first output sequence, when the first output sequence is updated.

6. In paragraph 1, Further comprising a step of receiving information necessary for the decoding from the transmitting device, The above first input sequence is decrypted based on the information required for the decryption, A method characterized in that when the receiving device is a terminal and the transmitting device is a base station, the information required for decoding is transmitted through an upper layer message.

7. In the first paragraph, if the first input sequence is an LLR sequence, The step of determining at least one element used to generate the at least one second input sequence comprises the step of determining at least one element of a predetermined number n having a low confidence value, The step of generating at least one second input sequence comprises changing at least one of the n determined elements in the first input sequence to 2 n A method characterized in that it comprises the step of generating a plurality of second input sequences of the dog.

8. In a receiving device that performs decoding of a channel code in a communication system, Transmitter and receiver; and At least one processor; comprising: Generating a first input sequence based on bits encoded with a channel code received from a transmitting device, In the first input sequence, a search range of at least one element to be changed to generate a plurality of second input sequences is determined based on the structure of the channel code, determining at least one element used to generate at least one second input sequence based on the above search range; Generating at least one second input sequence by changing at least one element, and A receiving device characterized in that it performs decoding for each of the at least one second input sequence to determine a final decoding result.

9. In the 8th paragraph, the at least one processor, Perform decoding on the first input sequence, Identifying a first output sequence generated or updated based on the above decryption, and Determine the search range of at least one element based on the first output sequence, The length of the above search range is shorter than the length of the encoded bits (E), A receiving device, characterized in that the search range of at least one element is predetermined.

10. In paragraph 8, A receiving device characterized in that the above search range is determined based on information bits, perforated bits within information bits, and shortened bits within information bits.

11. In paragraph 8, A receiving device characterized in that the length of the above search range is a value (K-2Z-F) obtained by subtracting the length of the punctured bits (2Z) within the information bits and the length of the shortened bits (F) within the information bits from the length of the cinematic portion (K).

12. In the 9th paragraph, the at least one processor, A receiving device characterized in that, when the first output sequence is updated, the search range of the at least one element is determined based on one of the positions of updated elements in the first output sequence, the positions of updated information bits in the first output sequence, and the positions of updated cinematic perforation bits in the first output sequence.

13. In the 8th paragraph, the at least one processor, Receive information required for decoding from the above transmitting device, The above first input sequence is decoded based on the information required for the decoding, A receiving device characterized in that, when the receiving device is a terminal and the transmitting device is a base station, the information required for decoding is transmitted through an upper layer message.

14. A receiving device according to claim 8, characterized in that, when the first input sequence is an LLR sequence, the at least one processor determines at least one element of a predetermined number of n having a low reliability value.

15. In paragraph 14, the at least one processor, By changing at least one of the n elements determined in the first input sequence, 2 n A receiving device characterized by comprising generating a plurality of second input sequences of the dog.

Images