Display substrate, display panel, and display device

Abstract

A display substrate (100), a display panel (200), and a display device (1000). The display substrate (100) comprises: a base substrate (1); and a first semiconductor layer (3), a second conductive layer (4), a third conductive layer (6), a second semiconductor layer (7) and a fourth conductive layer (8) which are sequentially arranged away from the base substrate (1). The display substrate (100) further comprises a plurality of pixel circuits. Each pixel circuit comprises a data writing transistor (T1) and a driving transistor (T3). The data writing transistor (T1) comprises an active layer (ACT 1), a control electrode (G1) and a second electrode (S1), wherein the active layer (ACT1) of the data writing transistor (T1) is located in the first semiconductor layer (3), the control electrode (G1) is located in the second conductive layer (4), and the second electrode (S1) is located in the third conductive layer (6). The driving transistor (T3) comprises an active layer (ACT 3), a control electrode (G3), a first electrode (D3), and a second electrode (S3), wherein the active layer (ACT3) of the driving transistor (T3) is located in the second semiconductor layer (7), the portion of the second electrode (S1) of the data writing transistor (T1) overlapping the active layer (ACT3) of the driving transistor (T3) is the control electrode (G3) of the driving transistor (T3), and the first electrode (D3) and the second electrode (S3) of the driving transistor (T3) are both located in the fourth conductive layer (8) and are separately in direct contact with the active layer (ACT3) of the driving transistor (T3).

Description

Display substrate, display panel, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and particularly to a display substrate, a display panel, and a display device. Background Art

[0002] In recent years, with the rise of the metaverse, virtual reality (VR) displays, as a key enabler of the metaverse, have garnered widespread attention. As a near-eye display, VR displays place higher demands on the pixel density of display devices to achieve higher clarity, better display effects, and a more immersive experience. However, the higher the pixel density of a display panel, the smaller the pixel size, which in turn reduces the wiring space.

[0003] How to rationally arrange devices and signal lines in a limited space and improve the space utilization of display products is one of the important research topics for R&D personnel.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art.

[0005] Summary of the Invention

[0006] In one aspect, a display substrate is provided, wherein the display substrate includes: a base substrate; a plurality of pixel units arranged on the base substrate, the plurality of pixel units being arranged in an array along a first direction and a second direction on the base substrate; a plurality of pixel circuits, the plurality of pixel circuits being used to drive the plurality of pixel units; the display substrate also includes a first semiconductor layer arranged on the base substrate; a second conductive layer arranged on a side of the first semiconductor layer away from the base substrate; a third conductive layer arranged on a side of the second conductive layer away from the base substrate; a second semiconductor layer arranged on a side of the third conductive layer away from the base substrate; and a fourth conductive layer directly arranged on a side of the second semiconductor layer away from the base substrate; the pixel circuit includes a data writing transistor and a driving transistor, wherein the data writing transistor includes an active layer, a control electrode and a second electrode, and the data writing transistor The active layer is located in the first semiconductor layer, and the control electrode of the data writing transistor is located in the second conductive layer; the second electrode of the data writing transistor is located in the third conductive layer; the second electrode of the data writing transistor is electrically connected to the active layer of the data writing transistor through a second via; the driving transistor includes an active layer, a control electrode, a first electrode and a second electrode, the active layer of the driving transistor is located in the second semiconductor layer, the orthographic projection of the second electrode of the data writing transistor on the substrate is at least partially overlapped with the orthographic projection of the active layer of the driving transistor on the substrate, and the part where the second electrode of the data writing transistor overlaps with the active layer of the driving transistor is the control electrode of the driving transistor; the first electrode and the second electrode of the driving transistor are both located in the fourth conductive layer, and the first electrode and the second electrode of the driving transistor are directly in contact with the active layer of the driving transistor respectively.

[0007] According to some exemplary embodiments, the pixel circuit also includes a first scanning signal line extending along a first direction, and the first scanning signal line is located in the second conductive layer; the active layer of the data writing transistor includes a channel region and a second pole region, and the channel region of the data writing transistor extends along the second direction; the positive projection of the channel region of the data writing transistor on the substrate at least partially overlaps with the positive projection of the first scanning signal line on the substrate, and the part where the first scanning signal line overlaps with the channel region of the data writing transistor is the control electrode of the data writing transistor; the second pole of the data writing transistor is electrically connected to the second pole region of the data writing transistor through a third via.

[0008] According to some exemplary embodiments, the display substrate further includes a first conductive layer arranged on a side of the first semiconductor layer close to the base substrate; the pixel circuit further includes a data signal line extending along a second direction, and the data signal line is located in the first conductive layer; the data write transistor further includes a first electrode, and the active layer of the data write transistor further includes a first electrode region, wherein the first electrode of the data write transistor is electrically connected to the data signal line and the first electrode region of the data write transistor through a second via.

[0009] According to some exemplary embodiments, the pixel circuit further includes a voltage signal line extending along the first direction, the voltage signal line is located in the fourth conductive layer, and the first electrode of the driving transistor is electrically connected to the voltage signal line.

[0010] According to some exemplary embodiments, the display substrate further includes a fifth conductive layer disposed on a side of the fourth conductive layer away from the base substrate; the pixel circuit further includes a sensing transistor, a sensing signal line and a second scanning signal line, wherein the sensing signal line is located in the fifth conductive layer and extends along the second direction; the second scanning signal line is located in the third conductive layer and extends along the first direction; the sensing transistor includes an active layer, a control electrode and a second electrode, the active layer of the sensing transistor is located in the second semiconductor layer, the positive projection of the active layer of the sensing transistor on the base substrate at least partially overlaps with the positive projection of the second scanning signal line on the base substrate, and the portion where the second scanning signal line overlaps with the active layer of the sensing transistor is the control electrode of the sensing transistor; the second electrode of the sensing transistor is electrically connected to the sensing signal line through a first via.

[0011] According to some exemplary embodiments, the sensing transistor further includes a first electrode; the pixel circuit further includes a first conductive connection portion located in the fourth conductive layer, the first conductive connection portion including a first part and a second part, wherein the first part is the second electrode of the driving transistor; the second part is the first electrode of the sensing transistor.

[0012] According to some exemplary embodiments, the first portion has a first width in a first direction, the second portion has a second width in the first direction, and the first width is greater than the second width.

[0013] According to some exemplary embodiments, the display substrate further includes a fourth insulating layer arranged between the fourth conductive layer and the fifth conductive layer; a fifth insulating layer arranged on the side of the fifth conductive layer away from the base substrate; a sixth conductive layer arranged on the side of the fifth insulating layer away from the base substrate; a planarization layer arranged on the side of the sixth conductive layer away from the base substrate; a first electrode layer arranged on the side of the planarization layer away from the base substrate; the pixel unit includes a light-emitting element, the light-emitting element includes a first electrode, and the first electrode of the light-emitting element is located in the first electrode layer; the second pole of the driving transistor is electrically connected to the first conductive transition portion through a fourth via hole, the first conductive transition portion is electrically connected to the second conductive transition portion through a fifth via hole, and the second conductive transition portion is electrically connected to the first electrode of the light-emitting element, wherein the first conductive transition portion is located in the fifth conductive layer, and the second conductive transition portion is located in the sixth conductive layer.

[0014] According to some exemplary embodiments, the orthographic projection of the first conductive transition portion on the base substrate at least partially overlaps with the orthographic projection of the active layer of the driving transistor on the base substrate; and / or the orthographic projection of the second conductive transition portion on the base substrate at least partially overlaps with the orthographic projection of the active layer of the driving transistor on the base substrate.

[0015] According to some exemplary embodiments, the orthographic projection of the first conductive transition portion on the base substrate at least partially overlaps with the orthographic projection of the first part of the first conductive connection portion on the base substrate; and / or the orthographic projection of the second conductive transition portion on the base substrate at least partially overlaps with the orthographic projection of the first conductive transition portion on the base substrate.

[0016] According to some exemplary embodiments, the multiple pixel units include multiple columns of sub-pixels located in the jth column, j+1th column, j+2th column and j+3th column, respectively, wherein j is greater than or equal to 1, and the pixel circuit of the sub-pixel in the jth column and the pixel circuit of the sub-pixel in the j+1th column share a sensing signal line; and the pixel circuit of the sub-pixel in the j+2th column and the pixel circuit of the sub-pixel in the j+3th column share a sensing signal line.

[0017] According to some exemplary embodiments, the multiple pixel units include multiple rows of sub-pixels respectively located in the i-th row and the i+1-th row, and multiple columns of sub-pixels respectively located in the j-th column and the j+1-th column, wherein i is greater than or equal to 1, and j is greater than or equal to 1, wherein the second electrode of the sensing transistor in the pixel circuit of the i-th row and j-th column sub-pixel is electrically connected to the sensing signal line through the first via and the second conductive connection portion; the second electrode of the sensing transistor in the pixel circuit of the i-th row and j+1-th column sub-pixel is electrically connected to the sensing signal line through the first via and the second conductive connection portion; the second electrode of the sensing transistor in the pixel circuit of the i+1-th row and j+1-th column sub-pixel is electrically connected to the sensing signal line through the first via and the second conductive connection portion; and the second electrode of the sensing transistor in the pixel circuit of the i+1-th row and j+1-th column sub-pixel is electrically connected to the sensing signal line through the first via and the second conductive connection portion.

[0018] According to some exemplary embodiments, the display substrate further includes a fourth insulating layer arranged between the fourth conductive layer and the fifth conductive layer; a fifth insulating layer arranged on the side of the fifth conductive layer away from the base substrate; a sixth conductive layer arranged on the side of the fifth insulating layer away from the base substrate; a planarization layer arranged on the side of the sixth conductive layer away from the base substrate; a first electrode layer arranged on the side of the planarization layer away from the base substrate; the pixel unit includes a light-emitting element, the light-emitting element includes a first electrode, and the first electrode of the light-emitting element is located in the first electrode layer; the second pole of the driving transistor is electrically connected to the third conductive transition portion through a sixth via hole, and the third conductive transition portion is electrically connected to the first electrode of the light-emitting element, wherein the third conductive transition portion is located in the sixth conductive layer, and the sixth via hole passes through the fourth insulating layer and the fifth insulating layer.

[0019] According to some exemplary embodiments, the display substrate further includes a fourth insulating layer arranged between the fourth conductive layer and the fifth conductive layer; a planarization layer arranged on the side of the fifth conductive layer away from the base substrate; a first electrode layer arranged on the side of the planarization layer away from the base substrate; the pixel unit includes a light-emitting element, the light-emitting element includes a first electrode, and the first electrode of the light-emitting element is located in the first electrode layer; the second pole of the driving transistor is electrically connected to the first conductive transition portion through a fourth via hole, and the first conductive transition portion is electrically connected to the first electrode of the light-emitting element through an eighth via hole, wherein the first conductive transition portion is located in the fifth conductive layer, the fourth via hole penetrates the fourth insulating layer, and the eighth via hole penetrates the planarization layer.

[0020] According to some exemplary embodiments, the display substrate further includes a first conductive layer arranged on a side of the first semiconductor layer close to the base substrate, the pixel circuit further includes a data signal line extending along a second direction, and the data signal line is located in the first conductive layer; the control electrode of the data write transistor includes a first sub-control electrode and a second sub-control electrode, the first sub-control electrode is located in the second conductive layer, and the second sub-control electrode is located in the first conductive layer.

[0021] According to some exemplary embodiments, the display substrate further includes a first conductive layer arranged on a side of the first semiconductor layer close to the base substrate; a seventh conductive layer arranged on a side of the first conductive layer close to the base substrate; the pixel circuit further includes a data signal line extending along a second direction, and the data signal line is located in the first conductive layer; the control electrode of the data write transistor includes a first sub-control electrode and a second sub-control electrode, the first sub-control electrode is located in the second conductive layer, and the second sub-control electrode is located in the seventh conductive layer.

[0022] According to some exemplary embodiments, the display substrate further includes an eighth conductive layer disposed on a side of the first semiconductor layer close to the base substrate; a first conductive layer disposed on a side of the eighth conductive layer close to the base substrate; the pixel circuit further includes a data signal line extending along a second direction, the data signal line being located in the first conductive layer; the control electrode of the data write transistor includes a first sub-control electrode and a second sub-control electrode, the first sub-control electrode being located in the second conductive layer, and the second sub-control electrode being located in the eighth conductive layer.

[0023] According to some exemplary embodiments, the display substrate further includes a fifth conductive layer disposed on a side of the fourth conductive layer away from the base substrate; the pixel circuit further includes a sensing transistor, a sensing signal line, and a second scanning signal line, wherein the sensing signal line is located in the fifth conductive layer and extends along the second direction; the second scanning signal line is located in the second conductive layer and extends along the first direction; the sensing transistor includes an active layer, a control electrode, a first electrode, and a second electrode; the active layer of the sensing transistor is located in the first semiconductor layer; the orthographic projection of the active layer of the sensing transistor on the base substrate at least partially overlaps with the orthographic projection of the second scanning signal line on the base substrate; the portion where the second scanning signal line overlaps with the active layer of the sensing transistor is the control electrode of the sensing transistor; the first electrode and the second electrode of the sensing transistor are both located in the fourth conductive layer, and the first electrode of the sensing transistor and the second electrode of the driving transistor share a third conductive connection portion; the second electrode of the sensing transistor is electrically connected to the sensing signal line through a first via and a fifth conductive transition portion, and the fifth conductive transition portion is located in the fifth conductive layer.

[0024] According to some exemplary embodiments, the display substrate further includes a first insulating layer disposed between the first semiconductor layer and the second conductive layer; a second insulating layer disposed between the second conductive layer and the third conductive layer; and a third insulating layer disposed between the third conductive layer and the second semiconductor layer; at least a portion of the first electrode of the sensing transistor is located in a ninth via hole, and at least a portion of the second electrode of the sensing transistor is located in a tenth via hole, wherein either the ninth via hole or the tenth via hole passes through the first insulating layer, the second insulating layer, and the third insulating layer.

[0025] According to some exemplary embodiments, the display substrate further includes a fifth conductive layer disposed on a side of the fourth conductive layer away from the base substrate; the pixel circuit further includes a sensing transistor, a sensing signal line and a second scanning signal line, wherein the sensing signal line is located in the fifth conductive layer and extends along the second direction; the second scanning signal line is located in the second conductive layer and extends along the first direction; the sensing transistor includes an active layer, a control electrode, a first electrode and a second electrode; the active layer of the sensing transistor is located in the first semiconductor layer; the positive projection of the active layer of the sensing transistor on the base substrate at least partially overlaps with the positive projection of the second scanning signal line on the base substrate; the portion where the second scanning signal line overlaps with the active layer of the sensing transistor is the control electrode of the sensing transistor; the first electrode and the second electrode of the sensing transistor are both located in the fifth conductive layer, the first electrode of the sensing transistor is electrically connected to the second electrode of the driving transistor via a first conductive transition portion; the second electrode of the sensing transistor is electrically connected to the sensing signal line.

[0026] According to some exemplary embodiments, the display substrate further includes a first insulating layer disposed between the first semiconductor layer and the second conductive layer; a second insulating layer disposed between the second conductive layer and the third conductive layer; a third insulating layer disposed between the third conductive layer and the second semiconductor layer; and a fourth insulating layer disposed between the fourth conductive layer and the fifth conductive layer; at least a portion of the first electrode of the sensing transistor is located in an eleventh via, and at least a portion of the second electrode of the sensing transistor is located in a twelfth via, wherein any one of the eleventh via and the twelfth via passes through the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer.

[0027] In another aspect, a display panel is provided, comprising the display substrate as described in any one of the above items.

[0028] In yet another aspect, a display device is provided, comprising the display substrate as described in any one of the above items or the display panel as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above contents and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0030] FIG1 is a schematic plan view of a display substrate according to an embodiment of the present disclosure;

[0031] FIG2 is an equivalent circuit diagram of a pixel circuit of a single sub-pixel of the display substrate in FIG1 ;

[0032] 3A is a schematic diagram illustrating a planar structure of a first conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure; FIG3B is a schematic diagram illustrating a planar structure of a first semiconductor layer of a pixel circuit according to an exemplary embodiment of the present disclosure; FIG3C is a schematic diagram illustrating a planar structure of a second conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure; FIG3D is a schematic diagram illustrating a planar structure of a second insulating layer and a plurality of vias according to an exemplary embodiment of the present disclosure; FIG3E is a schematic diagram illustrating a planar structure of a third conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure; FIG3F is a schematic diagram illustrating a planar structure of a second semiconductor layer of a pixel circuit according to an exemplary embodiment of the present disclosure; FIG3G is a schematic diagram illustrating a planar structure of a fourth conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure; FIG3H is a schematic diagram illustrating a planar structure of a fourth insulating layer and a plurality of vias of a pixel circuit according to an exemplary embodiment of the present disclosure; FIG3I is a schematic diagram illustrating a planar structure of a fifth conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure; FIG3J is a schematic diagram illustrating a planar structure of a fifth insulating layer and a plurality of vias of a pixel circuit according to an exemplary embodiment of the present disclosure; and FIG3K is a schematic diagram illustrating a planar structure of a sixth conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure;

[0033] 4 is a schematic diagram illustrating a planar structure of a combination of a first conductive layer, a first semiconductor layer, a second conductive layer, a third conductive layer, a second semiconductor layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure;

[0034] FIG5 is a partial enlarged view of the dotted-line area A1 in FIG4 ;

[0035] FIG6 is a partial cross-sectional schematic diagram showing a pixel circuit according to an exemplary embodiment of the present disclosure, taken along line BB′ in FIG4 ;

[0036] FIG7 is a partial cross-sectional schematic diagram of a pixel circuit according to some other exemplary embodiments of the present disclosure, taken along line BB′ in FIG4 ;

[0037] FIG8 is a partial cross-sectional schematic diagram of a pixel circuit according to some other exemplary embodiments of the present disclosure, taken along line BB′ in FIG4 ;

[0038] FIG9 is a partial cross-sectional schematic diagram of a pixel circuit according to some other exemplary embodiments of the present disclosure, taken along line BB′ in FIG4 ;

[0039] FIG10 is a partial cross-sectional schematic diagram of a pixel circuit according to some other exemplary embodiments of the present disclosure, taken along line BB′ in FIG4 ;

[0040] FIG11 is a partial cross-sectional schematic diagram of a pixel circuit according to some other exemplary embodiments of the present disclosure, taken along line BB′ in FIG4 ;

[0041] FIG12 is a partial cross-sectional schematic diagram of a pixel circuit according to some other exemplary embodiments of the present disclosure, taken along line BB′ in FIG4 ;

[0042] FIG13 is a partial cross-sectional schematic diagram of a pixel circuit according to some other exemplary embodiments of the present disclosure, taken along line BB′ in FIG4 ;

[0043] FIG14 is a schematic structural diagram of a display panel according to some embodiments of the present disclosure;

[0044] FIG15 is a schematic structural diagram of a display device according to some embodiments of the present disclosure.

[0045] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present invention, the sizes of layers, structures or regions may be enlarged or reduced, that is, these drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0046] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0047] It should be noted that in the drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0048] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meanings understood by those of ordinary skill in the art. The terms "first," "second," and similar terms used in this disclosure do not denote any order, quantity, or importance, but are simply used to distinguish different components. The terms "include," "comprising," and similar words mean that the element or object preceding the word encompasses the elements or objects listed after the word, and their equivalents, without excluding other elements or objects.

[0049] Unless otherwise specified, directional terms such as "upper," "lower," "left," "right," "inner," and "outer" are used herein to indicate positions or relationships based on the figures shown. These terms are intended solely to facilitate the description of the present disclosure and are not intended to indicate or imply that the devices, components, or parts referred to must have, be constructed, or operate in a specific orientation. It should be understood that when the absolute positions of the objects being described change, the relative positions they represent may also change accordingly. Therefore, these directional terms should not be construed as limiting the present disclosure.

[0050] It should be noted that, in this article, the term "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer used to form a specific pattern, and then patterning the film layer using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous. In other words, multiple elements, components, structures, and / or parts located in the "same layer" are composed of the same material and are formed through the same patterning process. Typically, multiple elements, components, structures, and / or parts located in the "same layer" have approximately the same thickness.

[0051] Those skilled in the art should understand that, in this article, unless otherwise specified, the expression "height" or "thickness" refers to the dimension of the surface of each film layer arranged perpendicular to the display substrate, that is, the dimension along the light emitting direction of the display substrate, or the dimension along the normal direction of the display device.

[0052] In this document, the directional expressions "first direction" and "second direction" are used to describe different directions along a pixel unit, such as the longitudinal and transverse directions of a pixel unit, or the row and column directions of a sub-pixel arrangement. It should be understood that such expressions are merely exemplary descriptions and are not intended to limit the present disclosure.

[0053] The transistors used in all embodiments of the present disclosure may be thin film transistors (TFTs), field effect transistors (MOSs), or other devices with the same characteristics, and the embodiments of the present disclosure are not limited thereto.

[0054] For example, the transistor may be a TFT. The TFT may be manufactured using an a-Si process, an oxide semiconductor process, a low-temperature polysilicon (LTPS) process, or a high-temperature polysilicon (HTPS) process. The embodiments of the present disclosure are not limited thereto.

[0055] The embodiments of the present disclosure do not limit the type of transistor. The transistor can be an N-type transistor or a P-type transistor, an enhancement-type transistor or a depletion-type transistor. In the embodiments of the present disclosure, the present application is exemplarily described by taking all transistors as N-type transistors as an example. The N-type transistor is turned on (opened) under the action of a high-level voltage signal and is turned off (shut off) under the action of a low-level voltage signal; in the embodiments of the present disclosure, "operating voltage" refers to the voltage that can control the conduction of the N-type transistor, that is, the high-level voltage; "cut-off voltage" refers to the voltage that can control the cut-off of the N-type transistor, that is, the low-level voltage.

[0056] In the embodiments of the present disclosure, the gate of a transistor is a control electrode. To distinguish the two electrodes of the transistor other than the gate, one of the electrodes is directly described as a first electrode and the other as a second electrode. In this case, the first electrode of the transistor can be one of the source and drain of the transistor, and the second electrode can be the other of the source and drain of the transistor. Since the source and drain of a transistor can be symmetrical in structure, their structures can be identical.

[0057] The capacitor in the embodiments of the present disclosure can be a capacitive device independently manufactured through a process, for example, by manufacturing a dedicated capacitor electrode. The individual capacitor electrodes (first plate and second plate) of the capacitor can be implemented by a metal layer, a semiconductor layer (e.g., doped polysilicon), etc. The capacitor can also be a parasitic capacitance between transistors, or implemented by the transistor itself and other devices or circuits, or by utilizing the parasitic capacitance between the circuits within the circuit itself.

[0058] Currently, the pixel density of LCD displays used for VR can reach 1500PPI (Pixels Per Inch). Organic Light Emitting Diode (OLED) display devices and inorganic light emitting diode display devices, such as sub-millimeter light emitting diode (Mini LED) display devices and micro light emitting diode (Micro LED) display devices, have better performance in terms of response time and brightness, but due to their driving principles, voltage compensation is usually required. Conventional methods include internal compensation circuits (such as 7T1C compensation circuits) and external compensation circuits (such as 3T1C compensation circuits). Due to the demand for high PPI, the size of a single pixel is constantly shrinking, and internal compensation solutions are difficult to meet the requirements due to the large number of components. The use of external compensation circuits can reduce the number of transistors, the number of traces, and the number of vias, which is beneficial to improving the pixel density of the display panel and improving the display effect of the display panel.

[0059] To facilitate understanding, some technical terms in this disclosure are explained.

[0060] TG structure transistor: a transistor using a top gate design.

[0061] BCE structure transistor: The layer where the source and drain electrodes in the transistor are located is in direct contact with the layer where the active layer in the transistor is located, without any other film layers or via structures in between, which is beneficial to reducing the number of vias in the pixel circuit.

[0062] Direct contact: The contact between two components does not go through vias.

[0063] Some embodiments of the present disclosure provide a display substrate, which includes: a base substrate; a plurality of pixel units arranged on the base substrate, the plurality of pixel units being arranged in an array along a first direction and a second direction on the base substrate; a plurality of pixel circuits, the plurality of pixel circuits being used to drive the plurality of pixel units; the display substrate also includes a first semiconductor layer arranged on the base substrate; a second conductive layer arranged on a side of the first semiconductor layer away from the base substrate; a third conductive layer arranged on a side of the second conductive layer away from the base substrate; a second semiconductor layer arranged on a side of the third conductive layer away from the base substrate; and a fourth conductive layer directly arranged on a side of the second semiconductor layer away from the base substrate; the pixel circuit includes a data writing transistor and a driving transistor, wherein the data writing transistor includes an active layer, a control electrode and a second electrode, and the data writing transistor The active layer of the transistor is located in the first semiconductor layer, and the control electrode of the data writing transistor is located in the second conductive layer; the second electrode of the data writing transistor is located in the third conductive layer; the second electrode of the data writing transistor is electrically connected to the active layer of the data writing transistor through a second via; the driving transistor includes an active layer, a control electrode, a first electrode, and a second electrode, the active layer of the driving transistor is located in the second semiconductor layer, the orthographic projection of the second electrode of the data writing transistor on the substrate substrate is at least partially overlapped with the orthographic projection of the active layer of the driving transistor on the substrate substrate, and the part where the second electrode of the data writing transistor overlaps with the active layer of the driving transistor is the control electrode of the driving transistor; the first electrode and the second electrode of the driving transistor are both located in the fourth conductive layer, and the first electrode and the second electrode of the driving transistor are directly in contact with the active layer of the driving transistor respectively.

[0064] On the one hand, the pixel circuit includes multiple transistors arranged in an upper and lower stack, among which the lower transistor adopts a TG structure design and the upper transistor adopts a BCE structure design. Since the source and drain metal and the active layer in the BCE structure transistor are directly overlapped, the area occupied by the via part can be saved; on the other hand, the source and drain electrodes of the lower TG structure transistor can be directly used as the gate of the upper BCE structure transistor, which not only reduces the connection vias but also realizes the overlapping placement of devices, which can optimize the area of ​​the devices and the connection holes, optimize the layout and wiring, and thus improve the pixel density of the display substrate.

[0065] FIG. 1 is a schematic plan view of a display substrate according to an embodiment of the present disclosure.

[0066] 1 , a display substrate according to an embodiment of the present disclosure may include a base substrate 1, and a plurality of pixel units PX disposed on the base substrate 1. The plurality of pixel units PX are arranged in an array along a first direction X and a second direction Y on the base substrate 1. The display substrate also includes a plurality of pixel circuits DX. The plurality of pixel circuits DX may be connected to the plurality of pixel units PX in a one-to-one correspondence, and the plurality of pixel circuits DX are configured to drive the plurality of pixel units PX, respectively.

[0067] The display substrate may include a display area AA and a non-display area NA. The display area AA may be an area where pixel cells PX displaying an image are located. The non-display area NA is an area where pixel cells PX are not located, that is, an area where no image is displayed. The non-display area NA corresponds to the bezel in the final display device, and the width of the bezel is determined based on the width of the non-display area NA.

[0068] The display area AA can have various shapes. For example, the display area AA can be provided in various shapes, such as a closed polygon (e.g., a rectangle) with straight sides, a circle or an ellipse with curved sides, or a semicircle or a semiellipse with both straight and curved sides. In the embodiment of the present disclosure, the display area AA is provided as a quadrilateral with straight sides. It should be understood that this is merely an exemplary embodiment of the present disclosure and is not intended to limit the present disclosure.

[0069] The non-display area NA may be provided on at least one side of the display area AA. In an embodiment of the present disclosure, the non-display area NA may surround the periphery of the display area AA. In an embodiment of the present disclosure, the non-display area NA may include a transverse portion extending in a first direction X and a longitudinal portion extending in a second direction Y.

[0070] The pixel unit PX is disposed in the display area AA and may include a light emitting device that emits red, green, blue, or white light.

[0071] The pixel units PX may be provided in a plurality and arranged in a matrix along rows extending in the first direction X and columns extending in the first direction Y. However, the embodiments of the present disclosure do not specifically limit the arrangement of the pixel units PX, and the pixel units PX may be arranged in various forms. For example, the pixel units PX may be arranged such that a direction inclined relative to the first direction X and the first direction Y becomes a column direction, and a direction intersecting the column direction becomes a row direction.

[0072] FIG. 2 is an equivalent circuit diagram of a pixel circuit of a single sub-pixel of the display substrate in FIG. 1 .

[0073] 2 , a pixel circuit may include multiple components such as a data writing transistor T1, a sensing transistor T2, a driving transistor T3, and a storage capacitor Cst. This pixel circuit may be referred to as a 3T1C structure.

[0074] It should be noted that the pixel circuit included in the display substrate according to the embodiment of the present disclosure is described here by taking the 3T1C structure as an example, but the pixel circuit included in the display substrate according to the embodiment of the present disclosure is not limited to the 3T1C structure.

[0075] It should be noted that each transistor may include an active layer, a control electrode (e.g., a gate), a first electrode (e.g., one of a source and a drain), and a second electrode (e.g., the other of the source and the drain). For example, the data write transistor T1 includes a gate G1 and an active layer ACT1; the sensing transistor T2 includes a gate G2 and an active layer ACT2; and the drive transistor T3 includes a gate G3 and an active layer ACT3. In the embodiments of the present disclosure, the active layers of the transistors may be located in different semiconductor layers, and the gates may be located in different conductive layers.

[0076] It should be noted that, in this document, the first electrode of a transistor may refer to one of a source and a drain of the transistor, and the second electrode of a transistor may refer to the other of the source and the drain of the transistor.

[0077] 2 , the gate of the data write transistor T1 is connected to the first scan signal line GL1, the first electrode of the data write transistor T1 is connected to the data signal line DL, and the second electrode of the data write transistor T1 is connected to the gate of the drive transistor T3. For example, the second electrode of the data write transistor T1 and the gate of the drive transistor T3 can both be electrically connected to the node G. The data write transistor T1 is used to control the writing of the voltage signal from the data signal line DL into the pixel circuit.

[0078] The gate of the driving transistor T3 is electrically connected to the node G. The first electrode of the driving transistor T3 is connected to the voltage signal line VDD. For example, the voltage signal line VDD can provide a high voltage level signal. The second electrode of the driving transistor T3 can be connected to the anode of the light-emitting element, so that a driving current can be generated according to the voltage signal to drive the light-emitting element L to emit light. For example, the light-emitting element L can be an organic light-emitting diode (OLED).

[0079] It should be noted that the pixel circuit disclosed herein can be used not only in OLED display devices, but also in Mini LED display devices or Micro LED display devices, and the present disclosure does not impose any special restrictions on this.

[0080] The two ends of the storage capacitor Cst are respectively connected to the gate and second electrode of the driving transistor T3, and are used to store the voltage signal input from the data signal line. For example, one end of the storage capacitor Cst is electrically connected to the node G, and the other end of the storage capacitor Cst is electrically connected to the node S. That is, one end of the storage capacitor Cst, the second electrode of the data writing transistor T1, and the gate of the driving transistor T3 are all electrically connected to the node G, and the other end of the storage capacitor Cst, the second electrode of the driving transistor T3, and the anode of the light-emitting element L are all electrically connected to the node S.

[0081] A gate of the sensing transistor T2 is connected to the second scan signal line GL2 , a first electrode of the sensing transistor T2 is electrically connected to the node S, and a second electrode of the sensing transistor T2 is connected to the sensing signal line SL.

[0082] The anode of the light emitting element L is electrically connected to the node S, and the cathode of the light emitting element L is electrically connected to the low voltage level signal VSS. The level signals VDD and VSS are both DC voltage signals for providing the necessary voltage to drive the light emitting element L to emit light.

[0083] The first scanning signal provided by the first scanning signal line GL1 and the second scanning signal provided by the second scanning signal line GL2 may be the same or different.

[0084] It should be understood that in the pixel circuit provided in the embodiments of the present disclosure, nodes such as node G, node S, and node D do not necessarily represent actual existing components. In some embodiments, these nodes represent the junction points of related couplings (i.e., electrical connections) in the equivalent circuit diagram of the pixel circuit. In other words, these nodes are nodes formed by the equivalent junction points of related electrical connections in the circuit diagram.

[0085] Figure 3A is a schematic diagram showing the planar structure of the first conductive layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 3B is a schematic diagram showing the planar structure of the first semiconductor layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 3C is a schematic diagram showing the planar structure of the second conductive layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 3D is a schematic diagram showing the planar structure of the second insulating layer and multiple vias according to an exemplary embodiment of the present disclosure; Figure 3E is a schematic diagram showing the planar structure of the third conductive layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 3F is a schematic diagram showing the planar structure of the second semiconductor layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 3G is a schematic diagram showing the planar structure of the fourth conductive layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 3H is a schematic diagram showing the planar structure of the pixel circuit according to an exemplary embodiment of the present disclosure FIG3 is a schematic diagram of a planar structure of a fourth insulating layer and a plurality of vias of a pixel circuit according to an exemplary embodiment of the present disclosure; FIG3I is a schematic diagram showing a planar structure of a fifth conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure; FIG3J is a schematic diagram showing a planar structure of a fifth insulating layer and a plurality of vias of a pixel circuit according to an exemplary embodiment of the present disclosure; FIG3K is a schematic diagram showing a planar structure of a sixth conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure; FIG4 is a schematic diagram showing a planar structure of a combination of a first conductive layer, a first semiconductor layer, a second conductive layer, a third conductive layer, a second semiconductor layer, a fourth conductive layer, a fifth conductive layer and a sixth conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure; FIG5 is a partial enlarged view of an area A1 of a dotted frame line in FIG4; FIG6 is a partial cross-sectional schematic diagram showing a pixel circuit according to an exemplary embodiment of the present disclosure taken along line BB' in FIG4.

[0086] For example, in some embodiments of the present disclosure, in combination with Figures 3A-6, the display substrate 100 may also include a first semiconductor layer 3 arranged on the base substrate 1; a second conductive layer 4 arranged on the side of the first semiconductor layer 3 away from the base substrate 1; a third conductive layer 6 arranged on the side of the second conductive layer 4 away from the base substrate 1; a second semiconductor layer 7 arranged on the side of the third conductive layer 6 away from the base substrate 1; and a fourth conductive layer 8 directly arranged on the side of the second semiconductor layer 7 away from the base substrate 1.

[0087] It should be noted that the fourth conductive layer 8 is directly disposed on the side of the second semiconductor layer 7 away from the base substrate 1 , which means that no other film layer is disposed between the fourth conductive layer 8 and the second semiconductor layer 7 .

[0088] Exemplarily, with reference to Figures 2, 3B-3G, 5 and 6, the pixel circuit includes a data write transistor T1 and a driving transistor T3, wherein the data write transistor T1 includes an active layer ACT1, a control electrode G1 and a second electrode S1, the active layer of the data write transistor T1 is located in the first semiconductor layer 3, and the control electrode G1 of the data write transistor T1 is located in the second conductive layer 4; the second electrode S1 of the data write transistor T1 is located in the third conductive layer 6; the second electrode S1 of the data write transistor T1 is electrically connected to the active layer ACT1 of the data write transistor T1 through a third via VH3.

[0089] The driving transistor T3 includes an active layer ACT3, a control electrode G3, a first electrode D3, and a second electrode S3. The active layer ACT3 of the driving transistor is located in the second semiconductor layer 7. The orthographic projection of the second electrode S1 of the data write transistor T1 on the base substrate 1 at least partially overlaps with the orthographic projection of the active layer ACT3 of the driving transistor T3 on the base substrate 1. The portion where the second electrode S1 of the data write transistor T1 overlaps with the active layer ACT3 of the driving transistor T3 is the control electrode G3 of the driving transistor T3. The first electrode D3 and the second electrode S3 of the driving transistor T3 are both located in the fourth conductive layer 8. The first electrode D3 and the second electrode S3 of the driving transistor T3 are respectively in direct contact with the active layer ACT3 of the driving transistor T3. For example, referring to Figure 6, the first electrode D3 of the driving transistor T3 is in direct contact with the active layer ACT3 of the driving transistor T3, without any other film layer in between, and the connection between the two does not require a via.

[0090] The data write transistor adopts a TG structure design, while the driver transistor adopts a BCE structure design. In the BCE driver transistor, the source and drain metal (e.g., the first electrode D3 and second electrode S3 of the driver transistor T3) are directly connected to the active layer ACT3, saving the area occupied by the vias. Furthermore, the second electrode S1 of the lower TG data write transistor T1 can directly serve as the gate G3 of the upper BCE driver transistor T3. In other words, the second electrode of the data write transistor T1 and the gate G3 of the driver transistor T3 can be the same conductive component, as shown in Figure 3E. This design not only reduces the number of connection vias but also enables overlapping device placement, optimizing the area of ​​the devices and connection vias, and optimizing the layout and wiring, thereby increasing the pixel density of the display substrate.

[0091] For example, in some embodiments of the present disclosure, with reference to Figures 3B-3D, 5, and 6, the pixel circuit further includes a first scan signal line GL1 extending along a first direction X, and the first scan signal line GL1 is located in the second conductive layer 4. The active layer ACT1 of the data write transistor T1 includes a channel region CH1 and a second electrode region 32, and the channel region CH1 of the data write transistor T1 extends along the second direction Y. The orthographic projection of the channel region CH1 of the data write transistor T1 on the base substrate 1 at least partially overlaps with the orthographic projection of the first scan signal line GL1 on the base substrate 1, and the overlapping portion of the first scan signal line GL1 and the channel region CH1 of the data write transistor T1 serves as the control electrode G1 of the data write transistor T1. The second electrode S1 of the data write transistor T1 is electrically connected to the second electrode region 32 of the data write transistor through a third via VH3.

[0092] For example, in some embodiments of the present disclosure, with reference to FIG3A-3D , FIG5 , and FIG6 , the display substrate 100 may further include a first conductive layer 2 disposed on a side of the first semiconductor layer 3 proximal to the base substrate 1. The pixel circuit may further include a data signal line DL extending along the second direction Y, the data signal line DL being located in the first conductive layer 2. The data write transistor T1 further includes a first electrode D1, and the active layer ACT1 of the data write transistor T1 further includes a first electrode region 31. The first electrode D1 of the data write transistor T1 is electrically connected to both the data signal line DL and the first electrode region 31 of the data write transistor T1 through a second via hole VH2.

[0093] The first conductive layer 2 can also be used as a light shielding layer for the pixel circuit. By arranging the data signal line DL in the light shielding layer, the wiring space can be fully utilized, which is beneficial to improving the resolution of the display substrate and achieving high-resolution display.

[0094] For example, in some embodiments of the present disclosure, in combination with FIG. 3G and FIG. 5 , the pixel circuit may further include a voltage signal line VDD extending along the first direction X, the voltage signal line VDD being located in the fourth conductive layer 8, and the first electrode D3 of the driving transistor T3 being electrically connected to the voltage signal line VDD.

[0095] For example, in some embodiments of the present disclosure, with reference to Figures 3E-3I, 5, and 6, the display substrate 100 may further include a fifth conductive layer 10 disposed on a side of the fourth conductive layer 8 away from the base substrate 1. The pixel circuit may further include a sensing transistor T2, a sensing signal line SL, and a second scanning signal line GL2. The sensing signal line SL is located in the fifth conductive layer 10 and extends along the second direction Y. The second scanning signal line GL2 is located in the third conductive layer 6 and extends along the first direction X. The sensing transistor T2 includes an active layer ACT2, a control electrode G2, and a second electrode S2. The active layer ACT2 of the sensing transistor is located in the second semiconductor layer 7. The orthographic projection of the active layer ACT2 of the sensing transistor T2 on the base substrate 1 at least partially overlaps with the orthographic projection of the second scanning signal line GL2 on the base substrate 1. The portion where the second scanning signal line GL2 overlaps with the active layer ACT2 of the sensing transistor T2 serves as the control electrode G2 of the sensing transistor T2. The second electrode S2 of the sensing transistor T2 is electrically connected to the sensing signal line SL via a first via VH1.

[0096] The first scan signal line GL1 and the second scan signal line GL2 may be located in different conductive layers. For example, the first scan signal line GL1 may be located in the second conductive layer 4, and the second scan signal line GL2 may be located in the third conductive layer 6. The first scan signal provided by the first scan signal line GL1 and the second scan signal provided by the second scan signal line GL2 may be the same or different.

[0097] For example, the sensing transistor T2 may further include a first electrode D2. The pixel circuit may further include a first conductive connection portion 81 located in the fourth conductive layer 8. The first conductive connection portion includes a first portion 811 and a second portion 812. The first portion 811 may be the second electrode S3 of the driving transistor T3, and the second portion 812 may be the first electrode D2 of the sensing transistor T2.

[0098] The first portion 811 has a first width d1 in the first direction X, and the second portion 812 has a second width d2 in the first direction X. The first width d1 is greater than the second width d2.

[0099] For example, in some embodiments of the present disclosure, in combination with Figures 3G-3K, Figure 5 and Figure 6, the display substrate 100 may also include a fourth insulating layer 9 arranged between the fourth conductive layer 8 and the fifth conductive layer 10; a fifth insulating layer 11 arranged on the side of the fifth conductive layer 10 away from the base substrate 1; a sixth conductive layer 12 arranged on the side of the fifth insulating layer 11 away from the base substrate 1; a planarization layer PLN arranged on the side of the sixth conductive layer 12 away from the base substrate 1; and a first electrode layer 13 arranged on the side of the planarization layer PLN away from the base substrate 1.

[0100] The pixel unit includes a light-emitting element, which includes a first electrode L1. The first electrode L1 of the light-emitting element is located in the first electrode layer 13. The second electrode S3 of the driving transistor T3 is electrically connected to the first conductive transition portion 101 through a fourth via VH4. The first conductive transition portion 101 is electrically connected to the second conductive transition portion 122 through a fifth via VH5. The second conductive transition portion 122 is electrically connected to the first electrode L1 of the light-emitting element. The first conductive transition portion 101 is located in the fifth conductive layer 10, and the second conductive transition portion 122 is located in the sixth conductive layer 12.

[0101] For example, the connection between the first electrode of the light-emitting element and the second electrode of the driving transistor requires a via in the planarization layer PLN. The via in the planarization layer PLN is relatively large, and the fifth conductive layer 10 also serves as the routing for the sensing signal line. This may result in insufficient wiring space in the fifth conductive layer. Adding the sixth conductive layer 12 above the fifth conductive layer 10 increases wiring space, facilitating the arrangement of signal routing, reducing crosstalk between signals, and improving display quality.

[0102] For example, in some embodiments of the present disclosure, in combination with Figures 3E, 3G, 3I and 6, the orthographic projection of the first conductive connection portion 81 on the substrate substrate at least partially overlaps with the orthographic projection of the control electrode G3 of the driving transistor on the substrate substrate; and / or, the orthographic projection of the first conductive transition portion 101 on the substrate substrate at least partially overlaps with the orthographic projection of the first part 811 of the first conductive connection portion 81 on the substrate substrate; and / or, the orthographic projection of the second conductive transition portion 122 on the substrate substrate at least partially overlaps with the orthographic projection of the first conductive transition portion 101 on the substrate substrate.

[0103] The pixel circuit may further include a storage capacitor Cst, which includes a first plate C1a and a second plate C1b, wherein the second plate C1b may include a first sub-plate C1b1 and a second sub-plate C1b2. The first plate C1a may be located in the third conductive layer 6. For example, the first plate C1a may include at least a portion of the control electrode G3 of the drive transistor. The first sub-plate C1b1 may be located in the fourth conductive layer 8. For example, the first sub-plate C1b1 may include at least a portion of the first conductive connection portion 81. The second sub-plate C1b2 may be located in the fifth conductive layer. For example, the second sub-plate C1b2 may include at least a portion of the first conductive transition portion 101.

[0104] The second plate of the storage capacitor includes a portion located in the fourth conductive layer (for example, the first sub-plate C1b1) and a portion located in the fifth conductive layer (for example, the second sub-plate C1b2), wherein the first sub-plate C1b1 and the second sub-plate C1b2 can be electrically connected through a via. By designing the second plate of the storage capacitor in two conductive layers, the capacity of the storage capacitor can be increased in a limited space, which is beneficial to improving the voltage storage capacity of the storage capacitor.

[0105] For example, continuing to refer to Figure 6, the orthographic projection of the first conductive transition portion 101 on the base substrate at least partially overlaps with the orthographic projection of the active layer ACT3 of the driving transistor on the base substrate; and / or, the orthographic projection of the second conductive transition portion 122 on the base substrate at least partially overlaps with the orthographic projection of the active layer ACT3 of the driving transistor on the base substrate.

[0106] The first conductive transition portion 101 and the second conductive transition portion 122 connected to the second electrode S3 of the driving transistor T3 can block at least a portion of incident light, reducing the influence of external light on the active layer ACT3 of the driving transistor T3, which is beneficial to improving the stability of the device.

[0107] For example, in some embodiments of the present disclosure, referring to FIG1 , a plurality of pixel units may include a plurality of columns of sub-pixels located respectively in the j-th column, the j+1-th column, the j+2-th column, and the j+3-th column, where j is greater than or equal to 1, and the pixel circuit of the sub-pixel in the j-th column and the pixel circuit of the sub-pixel in the j+1-th column may share a sensing signal line SL; the pixel circuit of the sub-pixel in the j+2-th column and the pixel circuit of the sub-pixel in the j+3-th column may share a sensing signal line SL.

[0108] The pixel circuit can adopt a bilaterally symmetrical design. The pixel circuits of two adjacent columns of pixel units can share a sensing signal line. This can reduce the number of sensing signal line traces and the number of vias connecting the corresponding sensing transistors to the sensing signal lines, which is conducive to optimizing the pixel circuit trace layout and improving the resolution of the display substrate.

[0109] For example, in some embodiments of the present disclosure, with reference to FIG3G to FIG3I, FIG4 and FIG6, a plurality of pixel units in a display substrate may include a plurality of rows of sub-pixels located in the i-th row and the i+1-th row, and a plurality of columns of sub-pixels located in the j-th column and the j+1-th column, respectively, wherein i is greater than or equal to 1, j is greater than or equal to 1, wherein the second electrode S2 of the sensing transistor T2 in the pixel circuit of the i-th row and j-th column sub-pixel is electrically connected to the sensing signal line SL through the first via hole VH1 and the second conductive connection portion 82; the i-th row and j+1 column sub-pixel is electrically connected to the sensing signal line SL through the first via hole VH1 and the second conductive connection portion 82; The second electrode S2 of the sensing transistor T2 in the pixel circuit of the pixel is electrically connected to the sensing signal line SL through the first via hole VH1 and the second conductive connection part 82; the second electrode S2 of the sensing transistor T2 in the pixel circuit of the sub-pixel in the i+1th row and j+1th column is electrically connected to the sensing signal line SL through the first via hole VH1 and the second conductive connection part 82; and the second electrode S2 of the sensing transistor T2 in the pixel circuit of the sub-pixel in the i+1th row and j+1th column is electrically connected to the sensing signal line SL through the first via hole VH1 and the second conductive connection part 82.

[0110] The pixel circuit can adopt a left-right and top-bottom symmetrical design. Two adjacent pixels on the left and right can share a sensing signal line and a via. Two adjacent pixels on the top and bottom can also share a sensing signal line and a via. In other words, four pixels can share a signal sensing line and a via, which is beneficial to reduce the number of vias, thereby saving wiring space and improving the resolution of the display substrate.

[0111] FIG. 7 is a partial cross-sectional schematic diagram of a pixel circuit according to some other exemplary embodiments of the present disclosure, taken along line BB′ in FIG. 4 .

[0112] For example, in some embodiments of the present disclosure, referring to FIG. 7 , the display substrate may further include a fourth insulating layer 9 disposed between the fourth conductive layer 8 and the fifth conductive layer 10; a fifth insulating layer 11 disposed on the side of the fifth conductive layer 10 away from the base substrate; a sixth conductive layer 12 disposed on the side of the fifth insulating layer 11 away from the base substrate; a planarization layer PLN disposed on the side of the sixth conductive layer 12 away from the base substrate; and a first electrode layer 13 disposed on the side of the planarization layer PLN away from the base substrate. The pixel unit may include a light-emitting element, the light-emitting element including a first electrode L1, and the first electrode L1 of the light-emitting element is located in the first electrode layer 13.

[0113] The second electrode S3 of the driving transistor T3 is electrically connected to the third conductive transition portion 123 through the sixth via VH6, and the third conductive transition portion 123 is electrically connected to the first electrode L1 of the light-emitting element, wherein the third conductive transition portion 123 is located in the sixth conductive layer 12, and the sixth via VH6 passes through the fourth insulating layer 9 and the fifth insulating layer 11.

[0114] The storage capacitor in the pixel circuit may include at least a portion of the layer where the gate G3 of the driving transistor T3 is located and at least a portion of the layer where the first conductive connection portion 81 is located. By optimizing the film thickness, for example, optimizing the thickness of the third conductive layer 6 or optimizing the thickness of the fourth conductive layer 8, it can be ensured that the storage capacitor in the pixel circuit meets the required voltage storage capacity.

[0115] FIG. 8 is a partial cross-sectional schematic diagram of a pixel circuit according to some other exemplary embodiments of the present disclosure, taken along line BB′ in FIG. 4 .

[0116] For example, in some embodiments of the present disclosure, referring to FIG. 8 , the display substrate may further include a fourth insulating layer 9 disposed between the fourth conductive layer 8 and the fifth conductive layer 10; a planarization layer PLN disposed on a side of the fifth conductive layer 10 away from the base substrate; and a first electrode layer 13 disposed on a side of the planarization layer PLN away from the base substrate. The pixel unit includes a light-emitting element, which includes a first electrode L1. The first electrode L1 of the light-emitting element is located in the first electrode layer 13.

[0117] The second electrode S3 of the driving transistor T3 is electrically connected to the first conductive transition portion 101 through the fourth via VH4, and the first conductive transition portion 101 is electrically connected to the first electrode L1 of the light-emitting element through the eighth via VH8, wherein the first conductive transition portion 101 is located in the fifth conductive layer 10, the fourth via VH4 penetrates the fourth insulating layer 9, and the eighth via VH8 penetrates the planarization layer PLN.

[0118] In some embodiments, the improved via precision of the PLN allows for simultaneous routing of sensing signal lines and routing the second electrode of the driver transistor upward within the fifth conductive layer. This design eliminates a conductive layer, such as the sixth conductive layer, simplifying the manufacturing process, saving costs, and improving display substrate production efficiency.

[0119] FIG. 9 is a partial cross-sectional schematic diagram of a pixel circuit according to some other exemplary embodiments of the present disclosure, taken along line BB′ in FIG. 4 .

[0120] For example, in some embodiments of the present disclosure, in combination with Figures 3A and 9, the display substrate may further include a first conductive layer 2 arranged on the side of the first semiconductor layer 3 close to the base substrate, and the pixel circuit may further include a data signal line DL extending along the second direction, and the data signal line DL is located in the first conductive layer 2.

[0121] The control electrode G1 of the data writing transistor T1 includes a first sub-control electrode G11 and a second sub-control electrode G12 . The first sub-control electrode G11 is located in the second conductive layer 4 , and the second sub-control electrode G12 is located in the first conductive layer 2 .

[0122] The lower transistors (e.g., data write transistors) use a dual-gate design, which improves their stability and contributes to the overall stability of the pixel circuit. The bottom gate of the lower transistors (e.g., the second sub-control electrode G12) can be located on the same layer as the data signal line, which helps reduce the number of patterning processes.

[0123] 10 is a partial cross-sectional schematic diagram of a pixel circuit according to some other exemplary embodiments of the present disclosure taken along line BB′ in FIG. 4 ; FIG. 11 is a partial cross-sectional schematic diagram of a pixel circuit according to some further exemplary embodiments of the present disclosure taken along line BB′ in FIG. 4 .

[0124] For example, in some embodiments of the present disclosure, with reference to FIG3A and FIG10 , the display substrate may further include a first conductive layer 2 disposed on a side of the first semiconductor layer 3 closer to the base substrate; and a seventh conductive layer 15 disposed on a side of the first conductive layer 2 closer to the base substrate. The pixel circuit may further include a data signal line DL extending along the second direction, the data signal line DL being located in the first conductive layer 2. The control electrode G1 of the data write transistor T1 includes a first sub-control electrode G11 and a second sub-control electrode G12, the first sub-control electrode G11 being located in the second conductive layer 4, and the second sub-control electrode G12 being located in the seventh conductive layer 15.

[0125] For example, in some embodiments of the present disclosure, with reference to FIG3A and FIG11 , the display substrate may further include an eighth conductive layer 16 disposed on a side of the first semiconductor layer 3 closer to the base substrate; and a first conductive layer 2 disposed on a side of the eighth conductive layer 16 closer to the base substrate. The pixel circuit may further include a data signal line DL extending along the second direction, the data signal line DL being located in the first conductive layer 2. The control electrode G1 of the data write transistor T1 includes a first sub-control electrode G11 and a second sub-control electrode G12, the first sub-control electrode G11 being located in the second conductive layer 4, and the second sub-control electrode G12 being located in the eighth conductive layer 16.

[0126] The lower transistor (e.g., data write transistor) adopts a dual-gate design, which can improve the stability of the lower transistor and help improve the overall stability of the pixel circuit. The bottom gate of the lower transistor (e.g., the second sub-control electrode G12) can be located on a different layer from the data signal line. For example, the layer where the second sub-control electrode G12 is located can be located on the side of the layer where the data signal line is located close to the base substrate; alternatively, the layer where the second sub-control electrode G12 is located can be located on the side of the layer where the data signal line is located away from the base substrate.

[0127] FIG. 12 is a partial cross-sectional schematic diagram of a pixel circuit according to some other exemplary embodiments of the present disclosure, taken along line BB′ in FIG. 4 .

[0128] For example, in some embodiments of the present disclosure, the pixel circuit may include a data write transistor T1, a sensing transistor T2, and a driving transistor T3. The data write transistor T1 and the sensing transistor T2 may be designed using a TG structure, and the driving transistor T3 may be designed using a BCE structure. For example, with reference to Figures 3E, 3I, 5, and 12, the display substrate may further include a fifth conductive layer 10 disposed on a side of the fourth conductive layer 8 away from the base substrate. The pixel circuit may further include a sensing signal line SL and a second scanning signal line GL2, wherein the sensing signal line SL is located in the fifth conductive layer 10 and extends along the second direction; the second scanning signal line GL2 is located in the second conductive layer 4 and extends along the first direction. The sensing transistor T2 includes an active layer ACT2, a control electrode G2, a first electrode D2 and a second electrode S2. The active layer ACT2 of the sensing transistor T2 is located in the first semiconductor layer 3. The positive projection of the active layer ACT2 of the sensing transistor T2 on the base substrate at least partially overlaps with the positive projection of the second scanning signal line GL2 on the base substrate. The part where the second scanning signal line GL2 overlaps with the active layer ACT2 of the sensing transistor T2 is the control electrode G2 of the sensing transistor T2; the first electrode D2 and the second electrode S2 of the sensing transistor T2 are both located in the fourth conductive layer 8.

[0129] For example, the first electrode D2 of the sensing transistor T2 and the second electrode S3 of the driving transistor T3 can share the third conductive connection portion 83. The second electrode S2 of the sensing transistor T2 is electrically connected to the sensing signal line SL through the first via VH1 and the fifth conductive transition portion 105. The fifth conductive transition portion 105 is located in the fifth conductive layer 10.

[0130] For example, the display substrate may further include a first insulating layer GI1 disposed between the first semiconductor layer 3 and the second conductive layer 4; a second insulating layer 5 disposed between the second conductive layer 4 and the third conductive layer 6; and a third insulating layer GI2 disposed between the third conductive layer 6 and the second semiconductor layer 7. At least a portion of the first electrode D2 of the sensing transistor T2 is located in the ninth via hole VH9, and at least a portion of the second electrode S2 of the sensing transistor T2 is located in the tenth via hole VH10. Both the ninth via hole VH9 and the tenth via hole VH10 penetrate through the first insulating layer GI1, the second insulating layer 5, and the third insulating layer GI2.

[0131] FIG. 13 is a partial cross-sectional schematic diagram of a pixel circuit according to some other exemplary embodiments of the present disclosure, taken along line BB′ in FIG. 4 .

[0132] For example, in some embodiments of the present disclosure, the pixel circuit may include a data write transistor T1, a sensing transistor T2, and a driving transistor T3. The data write transistor T1 and the sensing transistor T2 may be designed using a TG structure, and the driving transistor T3 may be designed using a BCE structure. For example, with reference to Figures 3E, 3I, 5, and 13, the display substrate may further include a fifth conductive layer 10 disposed on a side of the fourth conductive layer 8 away from the base substrate. The pixel circuit further includes a sensing signal line SL and a second scanning signal line GL2, wherein the sensing signal line SL is located in the fifth conductive layer 10 and extends along the second direction; the second scanning signal line GL2 is located in the second conductive layer 4 and extends along the first direction.

[0133] The sensing transistor T2 includes an active layer ACT2, a control electrode G2, a first electrode D2, and a second electrode S2. The active layer ACT2 of the sensing transistor T2 is located in the first semiconductor layer 3. The orthographic projection of the active layer ACT2 of the sensing transistor T2 on the substrate at least partially overlaps with the orthographic projection of the second scanning signal line GL2 on the substrate. The overlapping portion of the second scanning signal line GL2 and the active layer ACT2 of the sensing transistor T2 is the control electrode G2 of the sensing transistor T2; the first electrode D2 and the second electrode S2 of the sensing transistor T2 are both located in the fifth conductive layer 10, and the first electrode D2 of the sensing transistor T2 is electrically connected to the second electrode S3 of the driving transistor T3 through the first conductive transition portion 101; the second electrode S2 of the sensing transistor T2 is electrically connected to the sensing signal line SL.

[0134] For example, the display substrate may further include a first insulating layer GI1 disposed between the first semiconductor layer 3 and the second conductive layer 4; a second insulating layer 5 disposed between the second conductive layer 4 and the third conductive layer 6; a third insulating layer GI2 disposed between the third conductive layer 6 and the second semiconductor layer 7; and a fourth insulating layer 9 disposed between the fourth conductive layer 8 and the fifth conductive layer 10. At least a portion of the first electrode D2 of the sensing transistor T2 is located in the eleventh via hole VH11, and at least a portion of the second electrode S2 of the sensing transistor T2 is located in the twelfth via hole VH12. Both the eleventh via hole VH11 and the twelfth via hole VH12 penetrate through the first insulating layer GI1, the second insulating layer 5, the third insulating layer GI2, and the fourth insulating layer 9. The source and drain electrodes of the sensing transistor may be electrically connected via two deep via holes.

[0135] It should be noted that the above-mentioned embodiments can be used in combination unless they conflict. For example, the design in which the second electrode S3 of the driving transistor T3 is electrically connected to the third conductive transition portion 123 via the sixth via VH6 in the embodiment of FIG7 can be used in combination with the dual-gate design of the data writing transistor T1 in the embodiment of FIG9 . For another example, the dual-gate design of the data writing transistor T1 in the embodiment of FIG10 can be used in combination with the design in which the active layer ACT2 of the sensing transistor T2 is located in the first semiconductor layer in the embodiments of FIG12 or FIG13 .

[0136] FIG14 is a schematic structural diagram of a display panel according to some embodiments of the present disclosure.

[0137] Optionally, an embodiment of the present disclosure provides a display panel. Referring to FIG. 14 , the display panel 200 may include the display substrate 100 described above.

[0138] FIG15 is a schematic structural diagram of a display device according to some embodiments of the present disclosure.

[0139] Optionally, embodiments of the present disclosure further provide a display device. Referring to FIG. 25 , the display device 1000 may include the display substrate 100 or the display panel 200 described above. The display device may include, but is not limited to, electronic paper, mobile phones, tablet computers, monitors, laptop computers, digital photo frames, navigation systems, and any other product or component with a display function. It should be understood that this display device has the same beneficial effects as the display substrates provided in the aforementioned embodiments.

[0140] Although some embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the present general inventive concept, the scope of which is defined in the claims and their equivalents.

Claims

1. A display substrate, wherein: The display substrate comprises: substrate; A plurality of pixel units are provided on the base substrate, wherein the plurality of pixel units are arranged in an array along a first direction and a second direction on the base substrate; a plurality of pixel circuits, wherein the plurality of pixel circuits are used to drive the plurality of pixel units; The display substrate further includes a first semiconductor layer disposed on the base substrate; a second conductive layer disposed on a side of the first semiconductor layer away from the base substrate; a third conductive layer disposed on a side of the second conductive layer away from the base substrate; a second semiconductor layer disposed on a side of the third conductive layer away from the base substrate; and a fourth conductive layer directly disposed on a side of the second semiconductor layer away from the base substrate. The pixel circuit includes a data writing transistor and a driving transistor, wherein the data writing transistor includes an active layer, a control electrode, and a second electrode, the active layer of the data writing transistor is located in the first semiconductor layer, and the control electrode of the data writing transistor is located in the second conductive layer; the second electrode of the data writing transistor is located in the third conductive layer; and the second electrode of the data writing transistor is electrically connected to the active layer of the data writing transistor through a second via hole; The driving transistor includes an active layer, a control electrode, a first electrode, and a second electrode. The active layer of the driving transistor is located in the second semiconductor layer. The orthographic projection of the second electrode of the data writing transistor on the substrate at least partially overlaps with the orthographic projection of the active layer of the driving transistor on the substrate. The overlapping portion of the second electrode of the data writing transistor and the active layer of the driving transistor is the control electrode of the driving transistor. The first electrode and the second electrode of the driving transistor are both located in the fourth conductive layer, and the first electrode and the second electrode of the driving transistor are respectively in direct contact with the active layer of the driving transistor.

2. The display substrate according to claim 1, wherein The pixel circuit further includes a first scanning signal line extending along a first direction, wherein the first scanning signal line is located in the second conductive layer; The active layer of the data writing transistor includes a channel region and a second electrode region, and the channel region of the data writing transistor extends along the second direction; the orthographic projection of the channel region of the data writing transistor on the substrate at least partially overlaps with the orthographic projection of the first scanning signal line on the substrate, and the part where the first scanning signal line overlaps with the channel region of the data writing transistor is the control electrode of the data writing transistor; the second electrode of the data writing transistor is electrically connected to the second electrode region of the data writing transistor through a third via.

3. The display substrate according to claim 1 or 2, wherein: The display substrate further comprises a first conductive layer provided on a side of the first semiconductor layer close to the base substrate; The pixel circuit further includes a data signal line extending along the second direction, wherein the data signal line is located in the first conductive layer; The data writing transistor further includes a first electrode, and the active layer of the data writing transistor further includes a first electrode region. The first electrode of the data writing transistor is electrically connected to the data signal line and the first electrode region of the data writing transistor through a second via hole.

4. The display substrate according to any one of claims 1 to 3, wherein: The pixel circuit further includes a voltage signal line extending along a first direction, the voltage signal line is located in the fourth conductive layer, and the first electrode of the driving transistor is electrically connected to the voltage signal line.

5. The display substrate according to any one of claims 1 to 4, wherein: The display substrate further includes a fifth conductive layer provided on a side of the fourth conductive layer away from the base substrate; The pixel circuit further includes a sensing transistor, a sensing signal line and a second scanning signal line. Wherein, the sensing signal line is located in the fifth conductive layer and extends along the second direction; the second scanning signal line is located in the third conductive layer and extends along the first direction; The sensing transistor includes an active layer, a control electrode, and a second electrode. The active layer of the sensing transistor is located in the second semiconductor layer. The orthographic projection of the active layer of the sensing transistor on the base substrate at least partially overlaps with the orthographic projection of the second scanning signal line on the base substrate. The portion where the second scanning signal line overlaps with the active layer of the sensing transistor serves as the control electrode of the sensing transistor. The second electrode of the sensing transistor is electrically connected to the sensing signal line through a first via. The display substrate according to claim 5 , wherein: The sensing transistor further includes a first electrode; The pixel circuit further includes a first conductive connection portion located in the fourth conductive layer, the first conductive connection portion including a first portion and a second portion, wherein the first portion is the second electrode of the driving transistor; and the second portion is the first electrode of the sensing transistor.

7. The display substrate according to claim 6, wherein: The first portion has a first width in a first direction, the second portion has a second width in the first direction, and the first width is greater than the second width.

8. The display substrate according to any one of claims 1 to 4, wherein: The display substrate further includes a fourth insulating layer disposed between the fourth conductive layer and the fifth conductive layer; a fifth insulating layer disposed on a side of the fifth conductive layer away from the base substrate; and a sixth conductive layer disposed on a side of the fifth insulating layer away from the base substrate. a planarization layer disposed on a side of the sixth conductive layer away from the base substrate; A first electrode layer is provided on a side of the planarization layer away from the base substrate; The pixel unit includes a light-emitting element, the light-emitting element includes a first electrode, and the first electrode of the light-emitting element is located in the first electrode layer; The second electrode of the driving transistor is electrically connected to the first conductive transition portion through a fourth via, the first conductive transition portion is electrically connected to the second conductive transition portion through a fifth via, and the second conductive transition portion is electrically connected to the first electrode of the light-emitting element, wherein the first conductive transition portion is located in the fifth conductive layer, and the second conductive transition portion is located in the sixth conductive layer.

9. The display substrate according to claim 8, wherein: The orthographic projection of the first conductive transition portion on the base substrate at least partially overlaps with the orthographic projection of the active layer of the driving transistor on the base substrate; and / or, An orthographic projection of the second conductive transition portion on the base substrate at least partially overlaps with an orthographic projection of the active layer of the driving transistor on the base substrate.

10. The display substrate according to claim 8 or 9, wherein: The orthographic projection of the first conductive transition portion on the base substrate at least partially overlaps with the orthographic projection of the first portion of the first conductive connection portion on the base substrate; and / or, An orthographic projection of the second conductive transition portion on the base substrate at least partially overlaps with an orthographic projection of the first conductive transition portion on the base substrate.

11. The display substrate according to any one of claims 1 to 10, wherein: The plurality of pixel units include a plurality of columns of sub-pixels located in the jth column, the j+1th column, the j+2th column, and the j+3th column, wherein j is greater than or equal to 1, The pixel circuit of the j-th column sub-pixel and the pixel circuit of the j+1-th column sub-pixel share a sensing signal line; and The pixel circuit of the sub-pixel in the j+2 th column and the pixel circuit of the sub-pixel in the j+3 th column share a sensing signal line.

12. The display substrate according to any one of claims 1 to 11, wherein: The plurality of pixel units include a plurality of rows of sub-pixels located in the i-th row and the i+1-th row, and a plurality of columns of sub-pixels located in the j-th column and the j+1-th column, wherein i is greater than or equal to 1, j is greater than or equal to 1, and wherein, The second electrode of the sensing transistor in the pixel circuit of the sub-pixel in the i-th row and the j-th column is electrically connected to the sensing signal line through the first via hole and the second conductive connection portion; The second electrode of the sensing transistor in the pixel circuit of the sub-pixel in the i-th row and the j+1-th column is electrically connected to the sensing signal line through the first via hole and the second conductive connection portion; The second electrode of the sensing transistor in the pixel circuit of the sub-pixel in the i+1th row and the jth column is electrically connected to the sensing signal line through the first via hole and the second conductive connection portion; and The second electrode of the sensing transistor in the pixel circuit of the sub-pixel in the (i+1)th row and the (j+1)th column is electrically connected to the sensing signal line through the first via hole and the second conductive connection portion.

13. The display substrate according to any one of claims 1 to 7, 11 to 12, wherein: The display substrate further includes a fourth insulating layer disposed between the fourth conductive layer and the fifth conductive layer; a fifth insulating layer disposed on a side of the fifth conductive layer away from the base substrate; and a sixth conductive layer disposed on a side of the fifth insulating layer away from the base substrate. a planarization layer disposed on a side of the sixth conductive layer away from the base substrate; A first electrode layer is provided on a side of the planarization layer away from the base substrate; The pixel unit includes a light-emitting element, the light-emitting element includes a first electrode, and the first electrode of the light-emitting element is located in the first electrode layer; The second electrode of the driving transistor is electrically connected to the third conductive transition portion through a sixth via, and the third conductive transition portion is electrically connected to the first electrode of the light-emitting element, wherein the third conductive transition portion is located in the sixth conductive layer, and the sixth via hole passes through the fourth insulating layer and the fifth insulating layer.

14. The display substrate according to any one of claims 1 to 7, 11 to 12, wherein: The display substrate further includes a fourth insulating layer disposed between the fourth conductive layer and the fifth conductive layer; and a planarization layer disposed on a side of the fifth conductive layer away from the base substrate. A first electrode layer is provided on a side of the planarization layer away from the base substrate; The pixel unit includes a light-emitting element, the light-emitting element includes a first electrode, and the first electrode of the light-emitting element is located in the first electrode layer; The second electrode of the driving transistor is electrically connected to the first conductive transition portion through a fourth via, and the first conductive transition portion is electrically connected to the first electrode of the light-emitting element through an eighth via, wherein the first conductive transition portion is located in the fifth conductive layer, the fourth via penetrates the fourth insulating layer, and the eighth via penetrates the planarization layer.

15. The display substrate according to any one of claims 1 to 9, wherein: The display substrate further comprises a first conductive layer disposed on a side of the first semiconductor layer close to the base substrate, and the pixel circuit further comprises a data signal line extending along the second direction, wherein the data signal line is located in the first conductive layer; The control electrode of the data writing transistor includes a first sub-control electrode and a second sub-control electrode. The first sub-control electrode is located in the second conductive layer, and the second sub-control electrode is located in the first conductive layer.

16. The display substrate according to any one of claims 1 to 9, wherein: The display substrate further includes a first conductive layer disposed on a side of the first semiconductor layer close to the base substrate; and a seventh conductive layer disposed on a side of the first conductive layer close to the base substrate. The pixel circuit further includes a data signal line extending along the second direction, wherein the data signal line is located in the first conductive layer; The control electrode of the data writing transistor includes a first sub-control electrode and a second sub-control electrode. The first sub-control electrode is located in the second conductive layer, and the second sub-control electrode is located in the seventh conductive layer.

17. The display substrate according to any one of claims 1 to 9, wherein: The display substrate further includes an eighth conductive layer disposed on a side of the first semiconductor layer close to the base substrate; and a first conductive layer disposed on a side of the eighth conductive layer close to the base substrate. The pixel circuit further includes a data signal line extending along the second direction, wherein the data signal line is located in the first conductive layer; The control electrode of the data writing transistor includes a first sub-control electrode and a second sub-control electrode. The first sub-control electrode is located in the second conductive layer, and the second sub-control electrode is located in the eighth conductive layer.

18. The display substrate according to any one of claims 1 to 4 and 8 to 12, wherein: The display substrate further includes a fifth conductive layer provided on a side of the fourth conductive layer away from the base substrate; The pixel circuit further includes a sensing transistor, a sensing signal line and a second scanning signal line. The sensing signal line is located in the fifth conductive layer and extends along the second direction; the second scanning signal line is located in the second conductive layer and extends along the first direction. The sensing transistor includes an active layer, a control electrode, a first electrode, and a second electrode. The active layer of the sensing transistor is located in the first semiconductor layer. The orthographic projection of the active layer of the sensing transistor on the substrate at least partially overlaps with the orthographic projection of the second scanning signal line on the substrate. The overlapping portion of the second scanning signal line and the active layer of the sensing transistor is the control electrode of the sensing transistor. The first electrode and the second electrode of the sensing transistor are both located in the fourth conductive layer. The first electrode of the sensing transistor and the second electrode of the driving transistor share a third conductive connection portion. The second electrode of the sensing transistor is electrically connected to the sensing signal line through a first via and a fifth conductive transition portion. The fifth conductive transition portion is located in the fifth conductive layer.

19. The display substrate according to claim 18, wherein: The display substrate further includes a first insulating layer disposed between the first semiconductor layer and the second conductive layer; and a second insulating layer disposed between the second conductive layer and the third conductive layer. a third insulating layer disposed between the third conductive layer and the second semiconductor layer; At least a portion of the first electrode of the sensing transistor is located in the ninth via hole, and at least a portion of the second electrode of the sensing transistor is located in the tenth via hole, wherein: Any one of the ninth via hole and the tenth via hole passes through the first insulating layer, the second insulating layer and the third insulating layer.

20. The display substrate according to any one of claims 1 to 4 and 8 to 12, wherein: The display substrate further includes a fifth conductive layer provided on a side of the fourth conductive layer away from the base substrate; The pixel circuit further includes a sensing transistor, a sensing signal line and a second scanning signal line. The sensing signal line is located in the fifth conductive layer and extends along the second direction; the second scanning signal line is located in the second conductive layer and extends along the first direction. The sensing transistor includes an active layer, a control electrode, a first electrode, and a second electrode. The active layer of the sensing transistor is located in the first semiconductor layer. The orthographic projection of the active layer of the sensing transistor on the substrate at least partially overlaps with the orthographic projection of the second scanning signal line on the substrate. The second scanning signal line The portion overlapping with the active layer of the sensing transistor is the control electrode of the sensing transistor; the first electrode and the second electrode of the sensing transistor are both located in the fifth conductive layer, and the first electrode of the sensing transistor is electrically connected to the second electrode of the driving transistor through a first conductive transition portion; the second electrode of the sensing transistor is electrically connected to the sensing signal line.

21. The display substrate according to claim 20, wherein: The display substrate further includes a first insulating layer disposed between the first semiconductor layer and the second conductive layer; and a second insulating layer disposed between the second conductive layer and the third conductive layer. a third insulating layer disposed between the third conductive layer and the second semiconductor layer; a fourth insulating layer disposed between the fourth conductive layer and the fifth conductive layer; At least a portion of the first electrode of the sensing transistor is located in the eleventh via hole, and at least a portion of the second electrode of the sensing transistor is located in the twelfth via hole, wherein: Any one of the eleventh via hole and the twelfth via hole passes through the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer.

22. A display panel, wherein: The display panel includes the display substrate according to any one of claims 1 to 21.

23. A display device, wherein: The display device includes the display substrate according to any one of claims 1 to 21 or the display panel according to claim 22.

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