Mask layer structure, formation method therefor, and semiconductor structure formation method

Abstract

A mask layer structure, a formation method therefor, and a semiconductor structure formation method. The semiconductor structure formation method comprises: providing a substrate; forming a device layer on a surface of the substrate; forming an initial mask layer on a surface of the device layer; modifying the initial mask layer, forming on the device layer a mask layer and a modified layer on a surface of the mask layer, the density of the modified layer being greater than the density of the mask layer; performing patterning treatment on the modified layer and the mask layer; and, after the patterning treatment, etching the device layer using the mask layer and the modified layer on the surface of the mask layer as a mask, until a portion of the surface of the substrate is exposed, to form a via hole. The density of the modified layer is greater than the density of the mask layer, and the modified layer has more material in the same volume; during etching of the device layer, the etching rate of the modified layer is reduced, the loss of the modified layer in the transverse direction and the longitudinal direction during etching is reduced, and the key dimensions of the via hole obtained by means of etching do not increase due to mask loss, thereby improving the etching precision.

Description

Mask layer structure and forming method thereof and forming method of semiconductor structure

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on January 30, 2024, with application number 2024101316772 and invention name “Mask layer structure, formation method thereof and method for forming semiconductor structure”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a mask layer structure and a forming method thereof, and a forming method of a semiconductor structure. Background Art

[0003] With the development of three-dimensional NAND flash memory (3D NAND), the introduction of three-dimensional structures within 3D NAND flash memory has further increased the aspect ratio of these structures, placing higher demands on etching technology. The density of the carbon hard mask is positively correlated with its etch selectivity. To achieve higher aspect ratio etching requirements, a carbon hard mask with a higher selectivity is required as the carbon hard mask layer; in other words, a carbon hard mask with a higher film density is required.

[0004] However, current carbon hard masks still need further improvement.

[0005] Summary of the Invention

[0006] The technical problem solved by the present invention is to provide a mask layer structure and a forming method thereof and a forming method of a semiconductor structure, so as to increase the film density of the carbon hard mask layer and improve the morphology of the opening obtained by etching.

[0007] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a device layer on the surface of the substrate; forming an initial mask layer on the surface of the device layer; modifying the initial mask layer to form a mask layer and a modified layer on the surface of the mask layer on the device layer, wherein the density of the modified layer is greater than the density of the mask layer; patterning the modified layer and the mask layer; after the patterning, using the mask layer and the modified layer on the surface of the mask layer as masks, etching the device layer until a portion of the surface of the substrate is exposed to form a through hole.

[0008] Optionally, the device layer includes: a stack of several first dielectric layers and second dielectric layers; the thickness range of the device layer includes: 2μm to 10μm; the number of layers of the first dielectric layer ranges from: 30 layers to 200 layers; the number of layers of the second dielectric layer ranges from: 30 layers to 200 layers.

[0009] Optionally, it also includes: after etching the device layer, forming a channel in the through hole; after forming the channel, removing the first dielectric layer, and forming a gate layer between adjacent second dielectric layers; after forming the gate layer, removing the second dielectric layer, and performing source and drain doping on the channel exposed by the adjacent gate layer; after performing source and drain doping, forming a source and drain conductive layer between adjacent gate layers.

[0010] Optionally, the depth of the through hole ranges from 5 μm to 10 μm; the width of the through hole in a direction parallel to the substrate surface ranges from 50 nm to 150 nm; and the aspect ratio of the through hole ranges from 30 to 100.

[0011] Optionally, the inclination angle formed by the sidewall of the through hole and the substrate surface exposed at the bottom of the through hole is in the range of 85° to 95°.

[0012] Optionally, the modification process includes: an ion implantation process; the parameters of the ion implantation process include: the source gas of the ion implantation includes a carbon-containing gas, the energy range of the ion implantation is: 1KeV to 100KeV, and the depth range of the ion implantation is: The carbon-containing gas includes carbon dioxide.

[0013] Optionally, the material of the initial mask layer includes hydrogen-containing amorphous carbon; in the hydrogen-containing amorphous carbon, the atomic percentage concentration of hydrogen ranges from 10% to 15%.

[0014] Optionally, the initial mask layer formation process includes: a chemical vapor deposition process; the process parameters of the chemical vapor deposition process include: the reaction gas includes hydrocarbons, the gas flow range is: 1000sccm / s to 2000sccm / s, and the reaction temperature is greater than 500 degrees Celsius; the hydrocarbons include acetylene and propylene.

[0015] Optionally, the density of the modified layer is greater than the density of the mask layer by a percentage range of 10% to 20%; the thickness of the modified layer is in the range of: The thickness range of the mask layer is: The atomic percentage concentration range of hydrogen in the modified layer material is 2% to 7%.

[0016] Optionally, the method of graphical processing includes: forming an anti-reflective layer on the surface of the modified layer; forming a photoresist layer on the surface of the anti-reflective layer, the photoresist layer exposing a portion of the surface of the anti-reflective layer; using the photoresist layer as a mask, etching the modified layer and the mask layer until the surface of the device layer is exposed.

[0017] Correspondingly, the technical solution of the present invention also provides a method for forming a mask layer, including: providing a structure to be etched; forming an initial mask layer on the structure to be etched; modifying the initial mask layer to form a mask layer and a modified layer on the surface of the mask layer on the structure to be etched, wherein the density of the modified layer is greater than the density of the mask layer.

[0018] Optionally, the modification process includes: an ion implantation process; the parameters of the ion implantation process include: the source gas of the ion implantation includes a carbon-containing gas, the energy range of the ion implantation is: 1KeV to 100KeV, and the depth range of the ion implantation is: The carbon-containing gas includes carbon dioxide.

[0019] Optionally, the material of the initial mask layer includes hydrogen-containing amorphous carbon; in the hydrogen-containing amorphous carbon, the atomic percentage concentration of hydrogen ranges from 10% to 15%.

[0020] Optionally, the initial mask layer formation process includes: a chemical vapor deposition process; the process parameters of the chemical vapor deposition process include: the reaction gas includes hydrocarbons, the gas flow range is: 1000sccm / s to 2000sccm / s, and the reaction temperature is greater than 500 degrees Celsius; the hydrocarbons include acetylene and propylene.

[0021] Optionally, the density of the modified layer is greater than the density of the mask layer by a percentage range of 10% to 20%; the thickness of the modified layer is in the range of: The thickness range of the mask layer is: The atomic percentage concentration range of hydrogen in the modified layer material is 2% to 7%.

[0022] Correspondingly, the technical solution of the present invention also provides a mask layer structure, including: a structure to be etched; a mask layer located on the surface of the structure to be etched; and a modified layer located on the surface of the mask layer, wherein the density of the modified layer is greater than the density of the mask layer.

[0023] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0024] In the method for forming a mask layer according to the technical solution of the present invention, the initial mask layer is modified to form a mask layer and a modified layer located on the surface of the mask layer, so that the density of the modified layer is greater than that of the mask layer. Due to the increased density of the modified layer, more modified layer material is contained within the same volume, resulting in a reduced etch rate of the modified layer during etching using the mask layer and the modified layer as a mask. This also reduces the lateral and longitudinal loss of the modified layer during etching. As a result, in high-aspect-ratio etching, the critical dimensions of the etched opening are not increased due to mask loss, thereby improving etching precision.

[0025] In the method for forming a semiconductor structure of the technical solution of the present invention, the initial hard mask layer is modified to form a mask layer and a modified layer located on the surface of the mask layer. The density of the modified layer is greater than the density of the mask layer. Since the density of the modified layer increases, the modified layer material in the same volume increases, so that the etching rate of the modified layer is reduced during the etching of the device layer, and the lateral and longitudinal losses of the modified layer during the etching process are reduced. In etching with a high aspect ratio, the critical size of the etched through hole will not increase due to the loss of the mask, thereby reducing the taper of the through hole and improving the etching accuracy.

[0026] In the structure of the mask layer of the technical solution of the present invention, the density of the modified layer is greater than the density of the mask layer. As the density of the modified layer increases, the modified layer material in the same volume increases, which reduces the etching rate of the modified layer during the etching process, and reduces the lateral and longitudinal losses of the modified layer during the etching process. In etching with a high aspect ratio, the critical size of the etched opening will not increase due to the loss of the mask, thereby improving the etching accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] 1 to 6 are schematic cross-sectional views of a semiconductor structure forming process according to an embodiment of the present invention;

[0028] 7 to 9 are schematic cross-sectional views of the process of forming a mask layer according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] As described in the background art, the existing carbon hard mask needs further improvement.

[0030] In one embodiment, when a high aspect ratio opening is formed by etching using a carbon hard mask layer as a mask, the neck critical dimension of the obtained opening is large, the taper of the opening is large, and the morphology of the opening is poor.

[0031] In order to solve the above technical problems, the technical solution of the present invention proposes a mask layer structure, a method for forming the same, and a method for forming a semiconductor structure. The initial hard mask layer is modified to form a mask layer and a modified layer located on the surface of the mask layer. The density of the modified layer is greater than the density of the mask layer. Since the density of the modified layer increases, the modified layer material in the same volume increases, so that the etching rate of the modified layer decreases during the etching of the device layer, and the lateral and longitudinal losses of the modified layer during the etching process are reduced. In etching with a high aspect ratio, the critical size of the etched through hole will not increase due to the loss of the mask, thereby reducing the taper of the through hole and improving the etching accuracy.

[0032] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0033] 1 to 6 are schematic cross-sectional views of a semiconductor structure forming process according to an embodiment of the present invention.

[0034] Please refer to FIG. 1 , a substrate 100 is provided; and a device layer 101 is formed on a surface of the substrate 100 .

[0035] The substrate 100 may be made of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.

[0036] In this embodiment, the device layer 101 includes: a stack of several first dielectric layers 102 and second dielectric layers 103 , wherein the first dielectric layers 102 and the second dielectric layers 103 are used to form a NAND flash memory.

[0037] In other embodiments, the device layer can also be a single layer or multiple layers of other materials.

[0038] Specifically, in this embodiment, the thickness of the device layer 101 ranges from 2 μm to 10 μm; the number of layers of the first dielectric layer 102 ranges from 30 to 200 layers; and the number of layers of the second dielectric layer 103 ranges from 30 to 200 layers.

[0039] The material of the first dielectric layer 102 includes silicon oxide and silicon oxynitride.

[0040] The material of the second dielectric layer 103 includes amorphous carbon.

[0041] The first dielectric layer 102 provides a structural foundation for the subsequent formation of a gate layer.

[0042] The second dielectric layer 103 provides a structural basis for the subsequent formation of source and drain conductive layers.

[0043] The device layer 101 provides a structural basis for the subsequent formation of through holes 109 and channels.

[0044] Referring to FIG. 2 , an initial mask layer 104 is formed on the surface of the device layer 101 .

[0045] The material of the initial mask layer 104 includes hydrogen-containing amorphous carbon.

[0046] Specifically, in this embodiment, the atomic percentage concentration of hydrogen in the hydrogen-containing amorphous carbon is in the range of 10% to 15%.

[0047] The process of forming the initial mask layer 104 includes a chemical vapor deposition process.

[0048] The process parameters of the chemical vapor deposition process include: the reaction gas includes hydrocarbons, the gas flow rate range is: 1000sccm / s to 2000sccm / s, and the reaction temperature is greater than 500 degrees Celsius; the hydrocarbons include acetylene and propylene.

[0049] The thickness range of the initial mask layer 104 is:

[0050] The initial mask layer 104 provides a structural basis for the subsequent formation of the mask layer 105 and the modified layer 106 .

[0051] Subsequently, the initial mask layer 104 is modified to form a mask layer 105 and a modified layer 106 located on the surface of the mask layer 105. The density of the modified layer 106 is greater than that of the mask layer 105. As the density of the modified layer 106 increases, the material of the modified layer 106 in the same volume increases, so that the etching rate of the modified layer 106 decreases during the etching of the device layer 101, and the lateral and longitudinal losses of the modified layer 106 during the etching process are reduced. In etching with a high aspect ratio, the critical size of the etched through hole 109 will not increase due to the loss of the mask, thereby reducing the taper of the through hole 109 and improving the etching accuracy.

[0052] 3 , the initial mask layer 104 (as shown in FIG2 ) is modified to form a mask layer 105 and a modified layer 106 on the surface of the mask layer 105 on the device layer 101 . The density of the modified layer 106 is greater than that of the mask layer 105 .

[0053] The modification process includes: an ion implantation process; the parameters of the ion implantation process include: the source gas of the ion implantation includes a carbon-containing gas, the energy range of the ion implantation is: 1KeV to 100KeV, and the depth range of the ion implantation is: The carbon-containing gas includes carbon dioxide.

[0054] The density of the modified layer 106 is greater than the density of the mask layer 105 by a percentage range of 10% to 20%. The thickness of the modified layer 106 is in the range of: The thickness range of the mask layer 105 is: The atomic percentage concentration of hydrogen in the modified layer 106 material ranges from 2% to 7%.

[0055] The initial mask layer 104 (as shown in FIG2 ) is modified so that the density of the modified layer 106 is greater than that of the mask layer 105. As the density of the modified layer 106 increases, the material of the modified layer 106 in the same volume increases, so that the etching rate of the modified layer 106 decreases during the etching of the device layer 101, and the lateral and longitudinal losses of the modified layer 106 decrease during the etching process. In etching with a high aspect ratio, the critical dimension of the etched through hole 109 will not increase due to the loss of the mask, thereby reducing the taper of the through hole 109 and improving the etching accuracy.

[0056] After the initial mask layer 104 is modified, the modified layer 106 and the mask layer 105 are patterned. Please refer to FIG. 4 and FIG. 5 for details.

[0057] Referring to FIG. 4 , an anti-reflection layer 107 is formed on the surface of the modified layer 106 ; a photoresist layer 108 is formed on the surface of the anti-reflection layer 107 , and the photoresist layer 108 exposes a portion of the surface of the anti-reflection layer 107 .

[0058] The anti-reflection layer 107 is used to reduce light reflection during the photolithography process.

[0059] The photoresist layer 108 is used to define the dimensions of the mask layer 105 and the modified layer 106 to be formed subsequently along a direction parallel to the surface of the substrate 100 .

[0060] 5 , the modified layer 106 and the mask layer 105 are etched using the photoresist layer 108 (as shown in FIG. 4 ) as a mask until the surface of the device layer 101 is exposed.

[0061] The etching method includes: dry etching.

[0062] Specifically, in this embodiment, after etching the modified layer 106 and the mask layer 105 , the process further includes: removing the photoresist layer 108 .

[0063] The patterning process provides a structural basis for subsequent etching to form the through hole 109 .

[0064] 6 , after the patterning process, the device layer 101 is etched using the mask layer 105 and the modified layer 106 on the surface of the mask layer 105 as masks until a portion of the surface of the substrate 100 is exposed, thereby forming a through hole 109 .

[0065] The etching method includes: dry etching.

[0066] The depth of the through hole 109 ranges from 5 μm to 10 μm; the width of the through hole 109 along a direction parallel to the surface of the substrate 100 ranges from 50 nm to 150 nm; and the aspect ratio of the through hole 109 ranges from 30 to 100.

[0067] The tilt angle formed by the sidewall of the through hole 109 and the surface of the substrate 100 exposed at the bottom of the through hole 109 is in the range of 85° to 95°.

[0068] The density of the modified layer 106 is greater than the density of the mask layer 105. As the density of the modified layer 106 increases, the material of the modified layer 106 in the same volume increases, so that the etching rate of the modified layer 106 decreases during the etching of the device layer 101, and the lateral and longitudinal losses of the modified layer 106 during the etching process are reduced. In the etching with a high aspect ratio, the critical size of the etched through hole 109 will not increase due to the loss of the mask, thereby reducing the taper of the through hole 109 and improving the etching accuracy.

[0069] After etching the device layer 101, a channel (not shown) is formed in the through hole 109; after the channel is formed, the first dielectric layer 102 is removed, and a gate layer (not shown) is formed between adjacent second dielectric layers 103; after the gate layer is formed, the second dielectric layer 103 is removed, and source-drain doping is performed on the channel exposed by the adjacent gate layer; after the source-drain doping is performed, a source-drain conductive layer (not shown) is formed between adjacent gate layers.

[0070] Correspondingly, an embodiment of the present invention further provides a method for forming a mask layer, and please refer to FIG. 7 to FIG. 9 for details.

[0071] Referring to FIG. 7 , a structure 110 to be etched is provided.

[0072] Specifically, in this embodiment, the structure to be etched 110 includes a substrate (not shown) and a device layer (not shown) located on the surface of the substrate.

[0073] The material of the substrate includes silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0074] The thickness of the device layer ranges from 2 μm to 10 μm.

[0075] Referring to FIG. 8 , an initial mask layer 111 is formed on the structure to be etched 110 .

[0076] The material of the initial mask layer 111 includes hydrogen-containing amorphous carbon; the atomic percentage concentration of hydrogen in the hydrogen-containing amorphous carbon is in a range of 10% to 15%.

[0077] The initial mask layer 111 provides a structural foundation for the subsequent formation of the mask layer 112. The initial mask layer 111 is modified to form the mask layer 112 and the modified layer 113 located on the surface of the mask layer 112, so that the density of the modified layer 113 is greater than that of the mask layer 112. Due to the increased density of the modified layer 113, more material of the modified layer 113 is contained within the same volume, which reduces the etching rate of the modified layer 113 during the etching process using the mask layer 112 and the modified layer 113 as masks. The lateral and longitudinal loss of the modified layer 113 during the etching process is reduced. As a result, in high aspect ratio etching, the critical dimension of the etched opening is not increased due to mask loss, thereby improving etching accuracy.

[0078] 9 , the initial mask layer 111 (as shown in FIG8 ) is modified to form a mask layer 112 and a modified layer 113 on the surface of the mask layer 112 on the structure to be etched 110 , wherein the density of the modified layer 113 is greater than that of the mask layer 112 .

[0079] The modification process includes: an ion implantation process; the parameters of the ion implantation process include: the source gas of the ion implantation includes a carbon-containing gas, the energy range of the ion implantation is: 1KeV to 100KeV, and the depth range of the ion implantation is: The carbon-containing gas includes carbon dioxide.

[0080] The density of the modified layer 113 is greater than the density of the mask layer 112 by a percentage range of 10% to 20%. The thickness of the modified layer 113 is in the range of: The thickness range of the mask layer 112 is: The atomic percentage concentration of hydrogen in the modified layer 113 material is in the range of 2% to 7%.

[0081] The density of the modified layer 113 is greater than that of the mask layer 112. Due to the increased density of the modified layer 113, more material of the modified layer 113 is contained within the same volume, resulting in a reduced etching rate of the modified layer 113 during etching using the mask layer 112 and the modified layer 113 as masks. The lateral and longitudinal losses of the modified layer 113 during etching are also reduced. Consequently, in high aspect ratio etching, the critical dimensions of the etched openings are not increased due to mask loss, thereby improving etching accuracy.

[0082] Accordingly, an embodiment of the present invention further provides a mask layer structure, as shown in FIG9 . The mask layer structure includes: a structure to be etched 110 ; a mask layer 112 located on the surface of the structure to be etched 110 ; and a modified layer 113 located on the surface of the mask layer 112 , wherein the density of the modified layer 113 is greater than that of the mask layer 112 .

[0083] The structure of the mask layer includes: a structure to be etched 110 .

[0084] Specifically, in this embodiment, the structure to be etched 110 includes a substrate (not shown) and a device layer (not shown) located on the surface of the substrate.

[0085] The material of the substrate includes silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0086] The thickness of the device layer ranges from 2 μm to 10 μm.

[0087] The structure of the mask layer includes: a mask layer 112 located on the surface of the structure to be etched 110 .

[0088] The material of the mask layer 112 includes hydrogen-containing amorphous carbon; the atomic percentage concentration of hydrogen in the hydrogen-containing amorphous carbon is in a range of 10% to 15%.

[0089] The structure of the mask layer includes: a modified layer 113 located on the surface of the mask layer 112 , and the density of the modified layer 113 is greater than that of the mask layer 112 .

[0090] The atomic percentage concentration of hydrogen in the material of the modified layer 113 is in the range of 2% to 7%.

[0091] The density of the modified layer 113 is greater than the density of the mask layer 112. As the density of the modified layer 113 increases, the material of the modified layer 113 in the same volume increases, which reduces the etching rate of the modified layer 113 during the etching process, and reduces the lateral and longitudinal losses of the modified layer 113 during the etching process. In etching with a high aspect ratio, the critical size of the etched opening will not increase due to the loss of the mask, thereby improving the etching accuracy.

[0092] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a mask layer, characterized in that: include: providing a structure to be etched; forming an initial mask layer on the structure to be etched; The initial mask layer is modified to form a mask layer and a modified layer on the surface of the mask layer on the structure to be etched, wherein the density of the modified layer is greater than the density of the mask layer.

2. The method for forming a mask layer according to claim 1, wherein: The modification process includes: an ion implantation process; the parameters of the ion implantation process include: the source gas of the ion implantation includes a carbon-containing gas, the energy range of the ion implantation is: 1KeV to 100KeV, and the depth range of the ion implantation is: The carbon-containing gas includes carbon dioxide.

3. The method for forming a mask layer according to claim 1, wherein: The material of the initial mask layer includes hydrogen-containing amorphous carbon; in the hydrogen-containing amorphous carbon, the atomic percentage concentration of hydrogen ranges from 10% to 15%.

4. The method for forming a mask layer according to claim 3, wherein: The initial mask layer formation process includes: a chemical vapor deposition process; the process parameters of the chemical vapor deposition process include: the reaction gas includes hydrocarbons, the gas flow range is: 1000sccm / s to 2000sccm / s, and the reaction temperature is greater than 500 degrees Celsius; the hydrocarbons include acetylene and propylene.

5. The method for forming a mask layer according to claim 1, wherein: The density of the modified layer is greater than the density of the mask layer by a percentage range of 10% to 20%. The thickness of the modified layer is in the range of: The thickness range of the mask layer is: The atomic percentage concentration range of hydrogen in the modified layer material is 2% to 7%.

6. A mask layer structure, characterized in that: include: Structure to be etched; a mask layer located on the surface of the structure to be etched; A modified layer is located on the surface of the mask layer, and the density of the modified layer is greater than the density of the mask layer.

7. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a device layer on the surface of the substrate; forming an initial mask layer on the surface of the device layer; performing a modification treatment on the initial mask layer to form a mask layer and a modified layer on the surface of the mask layer on the device layer, wherein the density of the modified layer is greater than the density of the mask layer; performing patterning processing on the modified layer and the mask layer; After the patterning process, the mask layer and the modified layer on the surface of the mask layer are used as masks to etch the device layer until a portion of the surface of the substrate is exposed to form a through hole.

8. The method for forming a semiconductor structure according to claim 7, wherein: The device layer includes: a stack of several first dielectric layers and second dielectric layers; the thickness of the device layer ranges from 2 μm to 10 μm; the number of layers of the first dielectric layer ranges from 30 to 200 layers; the number of layers of the second dielectric layer ranges from 30 to 200 layers.

9. The method for forming a semiconductor structure according to claim 8, wherein: Also includes: After etching the device layer, a channel is formed in the through hole; after forming the channel, the first dielectric layer is removed, and a gate layer is formed between adjacent second dielectric layers; After forming the gate layer, the second dielectric layer is removed, and source and drain doping is performed on the exposed channel adjacent to the gate layer; after the source and drain doping is performed, a source and drain conductive layer is formed between the adjacent gate layers.

10. The method for forming a semiconductor structure according to claim 7, wherein: The depth of the through hole ranges from 5 μm to 10 μm; the width of the through hole in a direction parallel to the substrate surface ranges from 50 nm to 150 nm; and the aspect ratio of the through hole ranges from 30 to 100.

11. The method for forming a semiconductor structure according to claim 7, wherein: The inclination angle formed by the side wall of the through hole and the substrate surface exposed at the bottom of the through hole is in the range of 85° to 95°.

12. The method for forming a semiconductor structure according to claim 7, wherein: The modification process includes: an ion implantation process; the parameters of the ion implantation process include: the source gas of the ion implantation includes a carbon-containing gas, the energy range of the ion implantation is: 1KeV to 100KeV, and the depth range of the ion implantation is: The carbon-containing gas includes carbon dioxide.

13. The method for forming a semiconductor structure according to claim 7, wherein: The material of the initial mask layer includes hydrogen-containing amorphous carbon; in the hydrogen-containing amorphous carbon, the atomic percentage concentration of hydrogen ranges from 10% to 15%.

14. The method for forming a semiconductor structure according to claim 13, wherein: The initial mask layer formation process includes: a chemical vapor deposition process; the process parameters of the chemical vapor deposition process include: the reaction gas includes hydrocarbons, the gas flow range is: 1000sccm / s to 2000sccm / s, and the reaction temperature is greater than 500 degrees Celsius; the hydrocarbons include acetylene and propylene.

15. The method for forming a semiconductor structure according to claim 7, wherein: The density of the modified layer is greater than the density of the mask layer by a percentage range of 10% to 20%. The thickness of the modified layer is in the range of: The thickness range of the mask layer is: The atomic percentage concentration range of hydrogen in the modified layer material is 2% to 7%.

16. The method for forming a semiconductor structure according to claim 7, wherein: The graphical processing method includes: forming an anti-reflection layer on the surface of the modified layer; forming a photoresist layer on the surface of the anti-reflection layer, wherein the photoresist layer exposes part of the surface of the anti-reflection layer; using the photoresist layer as a mask, etching the modified layer and the mask layer until the surface of the device layer is exposed.

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