Display panel and luminance compensation method therefor, pixel array and display apparatus

Abstract

The present disclosure belongs to the technical field of display. Provided are a display panel and a luminance compensation method therefor, a pixel array, and a display apparatus, which can solve the problem of an image displayed by existing OLED display products being prone to a plurality of dark stripes, which results in a tripartite screen effect, thus affecting a display effect. The display panel in the present disclosure has a display area and a peripheral area at least arranged on one side of the display area, and the display panel comprises a plurality of rows of first pixel units and a plurality of rows of second pixel units, which are located within the display area, wherein the number of rows of second pixel units is less than the number of rows of first pixel units; and in the same display image frame, a first data voltage input into the first pixel units is less than a second data voltage input into the second pixel units.

Description

Display panel and brightness compensation method thereof, pixel array, and display device Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a display panel and a brightness compensation method thereof, a pixel array, and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) is a light-emitting device that uses organic solid-state semiconductors as light-emitting materials. It has broad application prospects due to its advantages such as simple preparation process, low cost, low power consumption, high luminous brightness, and wide operating temperature adaptability.

[0003] To switch between different refresh rates on OLED display products, frame skipping can be used to divide a frame into a refresh phase and multiple hold phases. However, due to the pixel structure of the display panel, current OLED display products are prone to displaying multiple dark lines, creating a three-part screen and affecting the display quality. Summary of the Invention

[0004] The present disclosure aims to solve at least one of the technical problems existing in the prior art, and provides a display panel and a brightness compensation method thereof, a pixel array, and a display device.

[0005] In a first aspect, an embodiment of the present disclosure provides a display panel having a display area and a peripheral area disposed at least on one side of the display area, wherein the display panel includes: a plurality of rows of first pixel units and a plurality of rows of second pixel units located in the display area; the number of rows of the second pixel units is smaller than the number of rows of the first pixel units;

[0006] In a same frame display image, a first data voltage input to the first pixel unit is smaller than a second data voltage input to the second pixel unit.

[0007] In some specific implementations, the first pixel unit includes: a first pixel driving circuit; the first pixel driving circuit includes: a first initialization transistor, a threshold compensation transistor, a driving transistor, a data writing transistor, a first light emission control transistor, a second light emission control transistor, a second initialization transistor, a third initialization transistor, a storage capacitor, and a light emitting device;

[0008] The control electrode of the driving transistor is connected to the first node, the first electrode is connected to the second node, and the second electrode is connected to the third node;

[0009] The control electrode of the data writing transistor is connected to the first scanning signal line, the first electrode is connected to the data signal line, and the second electrode is connected to the second node;

[0010] The control electrode of the threshold compensation transistor is connected to the second scanning signal line, the first electrode is connected to the third node, and the second electrode is connected to the first node;

[0011] One end of the storage capacitor is connected to the first node, and the other end is connected to the first power signal line;

[0012] The control electrode of the first light emitting control transistor is connected to the light emitting control signal line, the first electrode is connected to the first power signal line, and the second electrode is connected to the second node;

[0013] The control electrode of the second light emitting control transistor is connected to the light emitting control signal line, the first electrode is connected to the third node, and the second electrode is connected to the fourth node;

[0014] The control electrode of the first initialization transistor is connected to the first reset signal line, the first electrode is connected to the first initialization signal line, and the second electrode is connected to the third node;

[0015] The control electrode of the second initialization transistor is connected to the second reset signal line, the first electrode is connected to the second initialization signal line, and the second electrode is connected to the fourth node;

[0016] The control electrode of the third initialization transistor is connected to the second reset signal line, the first electrode is connected to the third initialization signal line, and the second electrode is connected to the second node;

[0017] The first electrode of the light emitting device is connected to the fourth node, and the second electrode is connected to the second power signal line.

[0018] In some specific implementations, the second pixel unit includes: a second pixel driving circuit; the second pixel driving circuit has the same structure as the first pixel driving circuit.

[0019] In some specific implementations, in the same frame of display image, the number of pulses of the light emitting control signal transmitted by the light emitting control signal line is the same as the number of pulses of the second reset signal transmitted by the second reset signal line.

[0020] In some specific implementations, during a refresh frame time, the first initialization transistor, the second initialization transistor, and the third initialization transistor are all turned on, and the first initialization signal, the second initialization signal, and the third initialization signal are written to the voltages of the third node, the fourth node, and the second node, respectively.

[0021] The data writing transistor and the threshold compensation transistor are both turned on to write a data voltage and a threshold voltage to the first node, and under the control of the first light emission control transistor and the second light emission control transistor, the driving transistor is used to drive the light emitting device to emit light;

[0022] During the holding frame time, the first initialization transistor, the second initialization transistor, and the third initialization transistor are all turned on, and the first initialization signal, the second initialization signal, and the third initialization signal are written to the voltages of the third node, the fourth node, and the second node, respectively;

[0023] The data writing transistor and the threshold compensation transistor are both turned off, and under the control of the first light emission control transistor and the second light emission control transistor, the driving transistor is used to drive the light emitting device to emit light.

[0024] In some specific implementations, the display panel further includes: a plurality of shift registers and gating circuits located in the peripheral area;

[0025] Each of the shift registers is connected to a row of the first pixel units or a row of the second pixel units through the gating circuit.

[0026] In a second aspect, an embodiment of the present disclosure provides a pixel array, comprising: a plurality of rows of first pixel units and a plurality of rows of second pixel units; the number of rows of the second pixel units is smaller than the number of rows of the first pixel units;

[0027] In a same frame display image, a first data voltage input to the first pixel unit is smaller than a second data voltage input to the second pixel unit.

[0028] In some specific implementations, the first pixel unit includes: a first pixel driving circuit; the first pixel driving circuit includes: a first initialization transistor, a threshold compensation transistor, a driving transistor, a data writing transistor, a first light emission control transistor, a second light emission control transistor, a second initialization transistor, a third initialization transistor, a storage capacitor, and a light emitting device;

[0029] The control electrode of the driving transistor is connected to the first node, the first electrode is connected to the second node, and the second electrode is connected to the third node;

[0030] The control electrode of the data writing transistor is connected to the first scanning signal line, the first electrode is connected to the data signal line, and the second electrode is connected to the second node;

[0031] The control electrode of the threshold compensation transistor is connected to the second scanning signal line, the first electrode is connected to the third node, and the second electrode is connected to the first node;

[0032] One end of the storage capacitor is connected to the first node, and the other end is connected to the first power signal line;

[0033] The control electrode of the first light emitting control transistor is connected to the light emitting control signal line, the first electrode is connected to the first power signal line, and the second electrode is connected to the second node;

[0034] The control electrode of the second light emitting control transistor is connected to the light emitting control signal line, the first electrode is connected to the third node, and the second electrode is connected to the fourth node;

[0035] The control electrode of the first initialization transistor is connected to the first reset signal line, the first electrode is connected to the first initialization signal line, and the second electrode is connected to the third node;

[0036] The control electrode of the second initialization transistor is connected to the second reset signal line, the first electrode is connected to the second initialization signal line, and the second electrode is connected to the fourth node;

[0037] The control electrode of the third initialization transistor is connected to the second reset signal line, the first electrode is connected to the third initialization signal line, and the second electrode is connected to the second node;

[0038] The first electrode of the light emitting device is connected to the fourth node, and the second electrode is connected to the second power signal line.

[0039] In some specific implementations, the second pixel unit includes: a second pixel driving circuit; the second pixel driving circuit has the same structure as the first pixel driving circuit.

[0040] In some specific implementations, in the same frame of display image, the number of pulses of the light emitting control signal transmitted by the light emitting control signal line is the same as the number of pulses of the second reset signal transmitted by the second reset signal line.

[0041] In some specific implementations, during a refresh frame time, the first initialization transistor, the second initialization transistor, and the third initialization transistor are all turned on, and the first initialization signal, the second initialization signal, and the third initialization signal are written to the voltages of the third node, the fourth node, and the second node, respectively.

[0042] The data writing transistor and the threshold compensation transistor are both turned on to write a data voltage and a threshold voltage to the first node, and under the control of the first light emission control transistor and the second light emission control transistor, the driving transistor is used to drive the light emitting device to emit light;

[0043] During the holding frame time, the first initialization transistor, the second initialization transistor, and the third initialization transistor are all turned on, and the first initialization signal, the second initialization signal, and the third initialization signal are written to the voltages of the third node, the fourth node, and the second node, respectively;

[0044] The data writing transistor and the threshold compensation transistor are both turned off, and under the control of the first light emission control transistor and the second light emission control transistor, the driving transistor is used to drive the light emitting device to emit light.

[0045] In a third aspect, an embodiment of the present disclosure provides a display device, wherein the display device includes the display panel provided as described above, or the pixel array provided as described above.

[0046] In a fourth aspect, an embodiment of the present disclosure provides a brightness compensation method for a display panel, wherein the brightness compensation method for a display panel includes:

[0047] According to the brightness of the pre-displayed display image, a first data voltage is input to the first pixel unit, and a second data voltage is input to the second pixel unit; the first data voltage is smaller than the second data voltage.

[0048] In some specific implementations, according to the brightness of the same pre-displayed display image, a first data voltage is input to the first pixel unit, and a second data voltage is input to the second pixel unit, and then the method further includes:

[0049] According to the brightness of different display images, the data voltage difference between the first data voltage and the second data voltage is fitted.

[0050] In some specific implementations, fitting the data voltage difference between the first data voltage and the second data voltage according to different brightness of the display screen includes:

[0051] Inputting a data voltage corresponding to a first display brightness value and a first grayscale value to the first pixel unit and the second pixel unit in the display panel to display a first display image;

[0052] Calculating a first display brightness difference between the first display image and the preset display image according to the first display image and the preset display image;

[0053] Calculating a first grayscale difference using a standard gamma curve according to the first display brightness difference;

[0054] Inputting a data voltage corresponding to a first display brightness value and a second grayscale value to the first pixel unit and the second pixel unit in the display panel to display a second display image;

[0055] Calculating a second display brightness difference between the second display image and the preset display image according to the second display image and the preset display image;

[0056] Calculating a second grayscale difference using a standard gamma curve according to the second display brightness difference;

[0057] A compensation value for each grayscale value is calculated according to the first grayscale difference and the second grayscale difference.

[0058] In some specific implementations, fitting the data voltage difference between the first data voltage and the second data voltage according to different brightness of the display screen further includes:

[0059] Inputting a data voltage corresponding to a second display brightness value and a first grayscale value to the first pixel unit and the second pixel unit in the display panel to display a third display image;

[0060] Calculating a third display brightness difference between the third display image and the preset display image according to the third display image and the preset display image;

[0061] Calculating a third grayscale difference using a standard gamma curve according to the third display brightness difference;

[0062] A compensation value for each grayscale value is calculated according to the first grayscale difference and the third grayscale difference. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] FIG1 is a schematic structural diagram of an exemplary display panel.

[0064] FIG. 2 is a schematic structural diagram of an exemplary pixel driving circuit in the display panel shown in FIG. 1 .

[0065] FIG3 is a timing diagram of the pixel driving circuit shown in FIG2 .

[0066] FIG4 is a schematic structural diagram of a display panel provided in an embodiment of the present disclosure.

[0067] FIG. 5 is a schematic structural diagram of a first pixel driving circuit in the display panel shown in FIG. 4 .

[0068] FIG6 is a timing diagram of the first pixel driving circuit shown in FIG5 .

[0069] FIG7 is a schematic flow chart of a brightness compensation method for a display panel provided in an embodiment of the present disclosure.

[0070] FIG8 is a schematic flow chart of a brightness compensation method provided in an embodiment of the present disclosure.

[0071] FIG9 is a flow chart of another brightness compensation method provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0072] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the present disclosure is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0073] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0074] It should be noted that the transistors used in the embodiments of the present disclosure can all be thin-film transistors or field-effect transistors or other devices with the same characteristics. In this embodiment, the coupling method of the drain and source of each transistor can be interchangeable. Therefore, the drain and source of each transistor in the embodiments of the present disclosure are actually the same. Here, only to distinguish the two poles of the transistor other than the control electrode (i.e., the gate), one of the poles is called the drain and the other pole is called the source. The thin-film transistor used in the shift register in the embodiments of the present disclosure can be a P-type transistor or an N-type transistor. Its control electrode can be the gate, the first pole can be the source, and the second pole can be the drain. For a P-type transistor, when a low-level signal is input to the gate, the source and drain are connected, and when a high-level signal is input to the gate, the source and drain are closed. For an N-type transistor, its working principle is the opposite, and its working principle will not be described in detail. The light-emitting device can specifically be a device such as an OLED, in which the first electrode can be an anode and the second electrode can be a cathode, and the light-emitting layer can emit light under the drive of the electric field of the anode and the cathode.

[0075] Figure 1 is a schematic structural diagram of an exemplary display panel. As shown in Figure 1, the display panel has a display area and a peripheral area arranged on at least one side of the display area; the display panel includes: a plurality of pixel units 101 arranged in an array in the display area, a plurality of shift registers 102 and a gating circuit 103 located in the peripheral area; each shift register 102 is connected to a row of pixel units 101 through the gating circuit 103.

[0076] The gating circuit 103 is connected to the gating signal line GE, and can adjust the refresh frequency of the display area of ​​the display panel by controlling the gating signal to control whether the output signal in the shift register 102 enters the pixel unit 101 in the display area within a certain period of time. For example, the refresh frequency of the display area of ​​the display panel can be 120Hz, which can maintain high-frequency refresh, and the refresh frequency of the display area of ​​the display panel can also be 40Hz, which can maintain low-frequency refresh, to achieve switching between high refresh frequency and low refresh frequency to save energy. It should be noted that a display cycle here can be specifically 1 second. At a high refresh frequency (120Hz), the display panel can display 120 frames of display images within 1 second, and at a low refresh frequency (40Hz), the display panel can display 40 frames of display images within 1 second. Among them, the refresh frequency can also be set as needed, and will not be listed one by one.

[0077] The pixel unit 101 is provided with a pixel driving circuit. The pixel driving circuit can adopt a 7T1C (7 thin-film transistors and 1 storage capacitor) or 8T1C (8 thin-film transistors and 1 storage capacitor) circuit structure. Because the 8T1C circuit structure has a third initial refresh signal for adjustment, it has better frequency switching performance and can avoid flicker. Therefore, the 8T1C circuit structure is generally used.

[0078] Figure 2 is a structural schematic diagram of an exemplary pixel driving circuit in the display panel shown in Figure 1. As shown in Figure 2, the pixel driving circuit includes: a first initialization transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second initialization transistor T7, a third initialization transistor T8, a storage capacitor Cst and a light-emitting device OLED.

[0079] The gate of the driving transistor T3 is connected to the first node N1, the source is connected to the second node N2, and the drain is connected to the third node N3. The gate of the data writing transistor T4 is connected to the first scan signal line Pgate, the source is connected to the data signal line Data, and the drain is connected to the second node N2. The gate of the threshold compensation transistor T2 is connected to the second scan signal line Ngate, the source is connected to the third node N3, and the drain is connected to the first node N1. One end of the storage capacitor Cst is connected to the first node N1, and the other end is connected to the first power signal line VDD. The gate of the first emission control transistor T5 is connected to the emission control signal line EM, the source is connected to the first power signal line VDD, and the drain is connected to the second node N2. The gate of the second emission control transistor T6 is connected to the emission control signal line EM, the source is connected to the third node N3, and the drain is connected to the fourth node N4. The gate of the first initialization transistor T1 is connected to the first reset signal line Preset1, the source is connected to the first initialization signal line Vinit1, and the drain is connected to the third node N3. The second initialization transistor T7 has a gate connected to the second reset signal line Preset2, a source connected to the second initialization signal line Vinit2, and a drain connected to the fourth node N4. The third initialization transistor T8 has a gate connected to the second reset signal line Preset2, a source connected to the third initialization signal line Vref, and a drain connected to the second node N2. The anode of the light-emitting device OLED is connected to the fourth node N4, and the cathode is connected to the second power signal line VSS.

[0080] The threshold compensation transistor T2 is an N-type transistor, for example, an N-type metal oxide thin film transistor. Metal oxide thin film transistors have low leakage current, thereby preventing leakage of the first node N1 through the threshold compensation transistor T2 during the light-emitting phase. Meanwhile, the first initialization transistor T1, the driving transistor T3, the data writing transistor T4, the first emission control transistor T5, the second emission control transistor T6, the second initialization transistor T7, and the third initialization transistor T8 are P-type transistors, for example, the first initialization transistor T1, the driving transistor T3, the data writing transistor T4, the first emission control transistor T5, the second emission control transistor T6, the second initialization transistor T7, and the third initialization transistor T8 are P-type low-temperature polysilicon thin film transistors. Low-temperature polysilicon thin film transistors have high carrier mobility, thereby facilitating the realization of display panels with high resolution, high response speed, high pixel density, and high aperture ratio. The first initialization signal line Vinit1, the second initialization signal line Vinit2, and the third initialization signal line Vref can output the same or different voltage signals depending on actual conditions.

[0081] FIG3 is a timing diagram of the pixel driving circuit shown in FIG2 . The working principle of the pixel driving circuit shown in FIG2 will be further described below in conjunction with FIG3 .

[0082] As shown in Figure 3, during the refresh frame time, the first reset signal line Preset1 outputs a low-level signal, the first initialization transistor T1 turns on, and the first initialization signal line Vinit1 inputs an initialization signal to the third node N3. The first scan signal line Pgate outputs a low-level signal, the second scan signal line Ngate outputs a high-level signal, the data write transistor T4 and the threshold compensation transistor T2 turn on, and the data signal line Data outputs a drive signal to write a voltage Vdata+Vth to the first node N1, where Vdata is the voltage of the drive signal and Vth is the threshold voltage of the drive transistor T3. The second reset signal line Preset2 outputs a high-level signal, the second initialization transistor T7 turns on, and the second initialization signal line Vinit2 inputs a second initialization signal to the fourth node N4 (i.e., the anode of the light-emitting device OLED). Simultaneously, the third initialization transistor T8 turns on, and the third initialization signal line Vref inputs a third initialization signal to the second node N2. The light-emission control signal line EM outputs a high-level signal, turning on the first and second light-emission control transistors T5 and T6, and the light-emitting device OLED emits light under the voltage Vdata+Vth stored on the capacitor Cst. During the holding frame time, the timing is similar to the above, except that data writing and threshold compensation are not performed. However, the second node N2 and the third node N3 are still reset. The implementation principle can be referred to the above description and will not be repeated here.

[0083] In practical applications, to prevent the display image from being affected by the ramping of signals such as data voltages within the integrated circuit, multiple rows of redundant pixel cells 101A are typically provided in the peripheral area of ​​the display panel. This peripheral area can be referred to as a blank area. Due to the use of the aforementioned 8T1C pixel driver circuit and the aforementioned timing sequence, the first EM off / Preset2 on pulse occurs in the blank area. Since no display is performed in this blank area, it does not affect the display image. In the blank area, the second initialization signal writes a load (loading) of Lx value. When the first pulse in the blank area moves to the screen display area along with the shift register 102, the second initialization signal writes a load (loading) of Ly value. When the second reset transistor T7 is turned on, the fourth node N4 is charged, and the second initialization signal voltage is pulled high. If the second initialization signal writes a load in the blank area, the amplitude of the pull-up is small, and the voltage of the fourth node N4 in the blank area is low. The brightness of the pixel unit 101 in the corresponding row is dim, and the first dark stripe appears at one-third of the display panel. As the shift register 102 continues to move downward, the second dark stripe appears at two-thirds of the display panel according to the same principle. From then on, a three-part screen appears in one frame of display, affecting the display effect.

[0084] In order to solve at least one of the above-mentioned technical problems, the embodiments of the present disclosure provide a display panel and a brightness compensation method thereof, a pixel array, and a display device. The display panel and a brightness compensation method thereof, the pixel array, and the display device provided by the embodiments of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0085] In the first aspect, an embodiment of the present disclosure provides a display panel. Figure 4 is a structural schematic diagram of a display panel provided by an embodiment of the present disclosure. As shown in Figure 4, the display panel includes: multiple rows of first pixel units 1011 and multiple rows of second pixel units 1012; the number of rows of second pixel units 1012 is less than the number of rows of first pixel units 1011; in the same frame display image, the first data voltage input to the first pixel unit 1011 is less than the second data voltage input to the second pixel unit 1012.

[0086] Taking a display panel with a resolution of 1920×1080 as an example, that is, the display panel includes 1080 rows of pixel units 101, among which the number of rows of first pixel units 1011 is relatively large, and the number of rows of second pixel units 1012 is relatively small. For example, there are only 20 rows of second pixel units 1012, and the rest are first pixel units 1011. Among them, 10 rows of second pixel units 1012 are exactly arranged where the first dark line appears in the display panel, that is, one-third of the display panel, and another 10 rows of second pixel units 1012 are exactly arranged where the second dark line appears in the display panel, that is, two-thirds of the display panel.

[0087] It is understandable that, as shown in FIG4 above, in order to prevent the data voltage and other signals in the integrated circuit from affecting the display image during the ramp-up process, multiple rows of redundant pixel units 101A are generally set in the peripheral area of ​​the display panel. The peripheral area here can be recorded as a blank area.

[0088] In the display panel provided by the embodiment of the present disclosure, in the same frame display image, the first data voltage input to the first pixel unit 1011 is less than the second data voltage input to the second pixel unit 1012, which can reduce the driving voltage of the second pixel unit 1012 in the area where dark lines originally appear, and thus can increase the driving current in the second pixel unit 1012, so that the driving currents of the first pixel unit 1011 and the second pixel unit 1012 are basically equal, thereby making the brightness of the first pixel unit 1011 and the second pixel unit 1012 basically the same, avoiding the occurrence of dark lines caused by different loads, and further improving the brightness uniformity of the display panel and improving the display effect.

[0089] The first pixel unit 101 may include a first pixel driving circuit. Figure 5 is a structural schematic diagram of the first pixel driving circuit in the display panel shown in Figure 4. As shown in Figure 5, the first pixel driving circuit includes: a first initialization transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second initialization transistor T7, a third initialization transistor T8, a storage capacitor Cst and a light-emitting device OLED.

[0090] The gate of the driving transistor T3 is connected to the first node N1, the source is connected to the second node N2, and the drain is connected to the third node N3. The gate of the data writing transistor T4 is connected to the first scan signal line Pgate, the source is connected to the data signal line Data, and the drain is connected to the second node N2. The gate of the threshold compensation transistor T2 is connected to the second scan signal line Ngate, the source is connected to the third node N3, and the drain is connected to the first node N1. One end of the storage capacitor Cst is connected to the first node N1, and the other end is connected to the first power signal line VDD. The gate of the first emission control transistor T5 is connected to the emission control signal line EM, the source is connected to the first power signal line VDD, and the drain is connected to the second node N2. The gate of the second emission control transistor T6 is connected to the emission control signal line EM, the source is connected to the third node N3, and the drain is connected to the fourth node N4. The gate of the first initialization transistor T1 is connected to the first reset signal line Preset1, the source is connected to the first initialization signal line Vinit1, and the drain is connected to the third node N3. The second initialization transistor T7 has a gate connected to the second reset signal line Preset2, a source connected to the second initialization signal line Vinit2, and a drain connected to the fourth node N4. The third initialization transistor T8 has a gate connected to the second reset signal line Preset2, a source connected to the third initialization signal line Vref, and a drain connected to the second node N2. The anode of the light-emitting device OLED is connected to the fourth node N4, and the cathode is connected to the second power signal line VSS.

[0091] The threshold compensation transistor T2 is an N-type transistor, for example, an N-type metal oxide thin film transistor. Metal oxide thin film transistors have low leakage current, thereby preventing leakage of the first node N1 through the threshold compensation transistor T2 during the light-emitting phase. Meanwhile, the first initialization transistor T1, the driving transistor T3, the data writing transistor T4, the first emission control transistor T5, the second emission control transistor T6, the second initialization transistor T7, and the third initialization transistor T8 are P-type transistors, for example, the first initialization transistor T1, the driving transistor T3, the data writing transistor T4, the first emission control transistor T5, the second emission control transistor T6, the second initialization transistor T7, and the third initialization transistor T8 are P-type low-temperature polysilicon thin film transistors. Low-temperature polysilicon thin film transistors have high carrier mobility, thereby facilitating the realization of display panels with high resolution, high response speed, high pixel density, and high aperture ratio. The first initialization signal line Vinit1, the second initialization signal line Vinit2, and the third initialization signal line Vref can output the same or different voltage signals depending on actual conditions.

[0092] FIG6 is a timing diagram of the first pixel driving circuit shown in FIG5 . The working principle of the first pixel driving circuit shown in FIG5 will be further described below in conjunction with FIG6 .

[0093] As shown in Figure 6, during the refresh frame time, the first reset signal line Preset1 outputs a low-level signal, the first initialization transistor T1 turns on, and the first initialization signal line Vinit1 inputs an initialization signal to the third node N3. The first scan signal line Pgate outputs a low-level signal, the second scan signal line Ngate outputs a high-level signal, the data write transistor T4 and the threshold compensation transistor T2 turn on, and the data signal line Data outputs a drive signal to write a voltage Vdata+Vth to the first node N1, where Vdata is the voltage of the drive signal and Vth is the threshold voltage of the drive transistor T3. The second reset signal line Preset2 outputs a high-level signal, the second initialization transistor T7 turns on, and the second initialization signal line Vinit2 inputs a second initialization signal to the fourth node N4 (i.e., the anode of the light-emitting device OLED). Simultaneously, the third initialization transistor T8 turns on, and the third initialization signal line Vref inputs a third initialization signal to the second node N2. The light-emission control signal line EM outputs a high-level signal, turning on the first and second light-emission control transistors T5 and T6, and the light-emitting device OLED emits light under the voltage Vdata+Vth stored on the capacitor Cst. During the holding frame time, the timing is similar to the above, except that data writing and threshold compensation are not performed. However, the second node N2 and the third node N3 are still reset. The implementation principle can be referred to the above description and will not be repeated here.

[0094] In practical applications, the second pixel unit 1012 may include a second pixel driving circuit. The structure and driving method of the second pixel driving circuit are the same as those of the first pixel driving circuit shown in FIG. 5 , and are not described in detail here.

[0095] In the same frame display image, the first data voltage input to the first pixel unit 1011 is less than the second data voltage input to the second pixel unit 1012, which can reduce the driving voltage of the second pixel unit 1012 in the area where dark lines originally appeared. Therefore, the driving current in the second pixel unit 1012 can be increased, so that the driving currents of the first pixel unit 1011 and the second pixel unit 1012 are basically equal, so that the brightness of the first pixel unit 1011 and the second pixel unit 1012 can be basically the same, avoiding the occurrence of dark lines caused by different second initialization signal loads, and thus improving the brightness uniformity of the display panel and improving the display effect.

[0096] In some embodiments, as shown in FIG6 , in the same frame of display image, the number of pulses of the light emitting control signal transmitted by the light emitting control signal line EM is the same as the number of pulses of the second reset signal transmitted by the second reset signal line Preset2 .

[0097] During the time of one frame display, the number of pulses of the light-emitting control signal is 3, and the corresponding number of pulses of the second reset signal is also 3. The second reset signal can control the initialization signal to be input to the fourth node N4 (i.e., the anode of the light-emitting device OLED) multiple times, and reset the voltage of the fourth node N4 multiple times to fully reset the voltage of the fourth node N4, so as to avoid the influence of the previous frame display on the current frame display, thereby improving the display effect.

[0098] In some embodiments, as shown in FIG4 , the display panel further includes: a plurality of shift registers 102 and a gating circuit 103 located in the peripheral area; each shift register 102 is connected to a row of first pixel units 1011 or a row of second pixel units 1012 through the gating circuit 103 .

[0099] The gating circuit 103 is connected to the gating signal line GE, and can adjust the refresh frequency of the display area of ​​the display panel by controlling the gating signal to control whether the output signal in the shift register 102 enters the first pixel unit 1011 and the second pixel unit 1012 in the display area within a certain period of time. For example, the refresh frequency of the display area of ​​the display panel can be 120Hz, which can maintain high-frequency refresh, and the refresh frequency of the display area of ​​the display panel can also be 40Hz, which can maintain low-frequency refresh, thereby achieving switching between high refresh frequency and low refresh frequency to save energy. It should be noted that a display cycle here can specifically be 1 second. At a high refresh frequency (120Hz), the display panel can display 120 frames of display images within 1 second, and at a low refresh frequency (40Hz), the display panel can display 40 frames of display images within 1 second. Among them, the refresh frequency can also be set as needed, and will not be listed one by one.

[0100] On the second aspect, an embodiment of the present disclosure provides a pixel array, the arrangement of which is the same as the arrangement of pixel units in the display panel shown in Figure 4. Referring to Figure 4, the pixel array includes: multiple rows of first pixel units 1011 and multiple rows of second pixel units 1012; the number of rows of second pixel units 1012 is less than the number of rows of first pixel units 1011; in the same frame display image, the first data voltage input to the first pixel unit 1011 is less than the second data voltage input to the second pixel unit 1012.

[0101] The first pixel unit 101 may include a first pixel driving circuit, which has the same structure as the first pixel driving circuit shown in Figure 5. Referring to Figure 5, the first pixel driving circuit includes: a first initialization transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second initialization transistor T7, a third initialization transistor T8, a storage capacitor Cst and a light-emitting device OLED.

[0102] The gate of the driving transistor T3 is connected to the first node N1, the source is connected to the second node N2, and the drain is connected to the third node N3. The gate of the data writing transistor T4 is connected to the first scan signal line Pgate, the source is connected to the data signal line Data, and the drain is connected to the second node N2. The gate of the threshold compensation transistor T2 is connected to the second scan signal line Ngate, the source is connected to the third node N3, and the drain is connected to the first node N1. One end of the storage capacitor Cst is connected to the first node N1, and the other end is connected to the first power signal line VDD. The gate of the first emission control transistor T5 is connected to the emission control signal line EM, the source is connected to the first power signal line VDD, and the drain is connected to the second node N2. The gate of the second emission control transistor T6 is connected to the emission control signal line EM, the source is connected to the third node N3, and the drain is connected to the fourth node N4. The gate of the first initialization transistor T1 is connected to the first reset signal line Preset1, the source is connected to the first initialization signal line Vinit1, and the drain is connected to the third node N3. The second initialization transistor T7 has a gate connected to the second reset signal line Preset2, a source connected to the second initialization signal line Vinit2, and a drain connected to the fourth node N4. The third initialization transistor T8 has a gate connected to the second reset signal line Preset2, a source connected to the third initialization signal line Vref, and a drain connected to the second node N2. The anode of the light-emitting device OLED is connected to the fourth node N4, and the cathode is connected to the second power supply signal line VSS. The threshold compensation transistor T2 is an N-type transistor, for example, an N-type metal oxide thin film transistor. Metal oxide thin film transistors have low leakage current, thereby preventing leakage of the first node N1 through the threshold compensation transistor T2 during the light-emitting phase. At the same time, the first initialization transistor T1, the driving transistor T3, the data writing transistor T4, the first emission control transistor T5, the second emission control transistor T6, the second initialization transistor T7, and the third initialization transistor T8 are P-type transistors. For example, the first initialization transistor T1, the driving transistor T3, the data writing transistor T4, the first emission control transistor T5, the second emission control transistor T6, the second initialization transistor T7, and the third initialization transistor T8 are P-type low-temperature polycrystalline silicon thin-film transistors. Low-temperature polycrystalline silicon thin-film transistors have high carrier mobility, which is conducive to realizing a display panel with high resolution, high response speed, high pixel density, and high aperture ratio. The first initialization signal line Vinit1, the second initialization signal line Vinit2, and the third initialization signal line Vref can output the same or different voltage signals according to actual conditions.

[0103] The timing diagram of the first pixel driving circuit is the same as the timing diagram of the first pixel driving circuit shown in FIG6 , and reference may be made to FIG6 .

[0104] As shown in Figure 6, during the refresh frame time, the first reset signal line Preset1 outputs a low-level signal, the first initialization transistor T1 turns on, and the first initialization signal line Vinit1 inputs an initialization signal to the third node N3. The first scan signal line Pgate outputs a low-level signal, the second scan signal line Ngate outputs a high-level signal, the data write transistor T4 and the threshold compensation transistor T2 turn on, and the data signal line Data outputs a drive signal to write a voltage Vdata+Vth to the first node N1, where Vdata is the voltage of the drive signal and Vth is the threshold voltage of the drive transistor T3. The second reset signal line Preset2 outputs a high-level signal, the second initialization transistor T7 turns on, and the second initialization signal line Vinit2 inputs a second initialization signal to the fourth node N4 (i.e., the anode of the light-emitting device OLED). Simultaneously, the third initialization transistor T8 turns on, and the third initialization signal line Vref inputs a third initialization signal to the second node N2. The light-emission control signal line EM outputs a high-level signal, turning on the first and second light-emission control transistors T5 and T6, and the light-emitting device OLED emits light under the voltage Vdata+Vth stored on the capacitor Cst. During the holding frame time, the timing is similar to the above, except that data writing and threshold compensation are not performed. However, the second node N2 and the third node N3 are still reset. The implementation principle can be referred to the above description and will not be repeated here.

[0105] In practical applications, the second pixel unit 1012 may include a second pixel driving circuit. The structure and driving method of the second pixel driving circuit are the same as those of the first pixel driving circuit shown in FIG. 5 , and are not described in detail here.

[0106] In the same frame display image, the first data voltage input to the first pixel unit 1011 is less than the second data voltage input to the second pixel unit 1012, which can reduce the driving voltage of the second pixel unit 1012 in the area where dark lines originally appeared. Therefore, the driving current in the second pixel unit 1012 can be increased, so that the driving currents of the first pixel unit 1011 and the second pixel unit 1012 are basically equal, so that the brightness of the first pixel unit 1011 and the second pixel unit 1012 can be basically the same, avoiding the occurrence of dark lines caused by different second initialization signal loads, and thus improving the brightness uniformity of the display panel and improving the display effect.

[0107] In some embodiments, as shown in FIG6 , in the same frame of display image, the number of pulses of the light emitting control signal transmitted by the light emitting control signal line EM is the same as the number of pulses of the second reset signal transmitted by the second reset signal line Preset2 .

[0108] During the time of one frame display, the number of pulses of the light-emitting control signal is 3, and the corresponding number of pulses of the second reset signal is also 3. The second reset signal can control the initialization signal to be input to the fourth node N4 (i.e., the anode of the light-emitting device OLED) multiple times, and reset the voltage of the fourth node N4 multiple times to fully reset the voltage of the fourth node N4, so as to avoid the influence of the previous frame display on the current frame display, thereby improving the display effect.

[0109] In a third aspect, embodiments of the present disclosure provide a display device comprising a display panel or a pixel array as provided in any of the aforementioned embodiments. The display device can be any product or component with a display function, such as a television, a mobile phone, a monitor, a laptop computer, a digital photo frame, or a navigation system. The implementation principles of the display device are similar to those of the aforementioned display panels and will not be further elaborated here.

[0110] Fourthly, an embodiment of the present disclosure provides a brightness compensation method for a display panel. FIG7 is a flow chart of a brightness compensation method for a display panel provided by an embodiment of the present disclosure. As shown in FIG7 , the brightness compensation method for a display panel includes the following steps S701 to S702.

[0111] S701 , inputting a first data voltage to a first pixel unit and a second data voltage to a second pixel unit according to the brightness of a pre-displayed display image; the first data voltage is lower than the second data voltage.

[0112] In the same frame display image, the first data voltage input to the first pixel unit 1011 is less than the second data voltage input to the second pixel unit 1012, which can reduce the driving voltage of the second pixel unit 1012 in the area where dark lines originally appear, thereby increasing the driving current in the second pixel unit 1012, so that the driving currents of the first pixel unit 1011 and the second pixel unit 1012 are basically equal, thereby making the brightness of the first pixel unit 1011 and the second pixel unit 1012 basically the same, avoiding the occurrence of dark lines caused by different loads, and thus improving the brightness uniformity of the display panel and improving the display effect.

[0113] S702 , fitting the data voltage difference between the first data voltage and the second data voltage according to different brightness of the display screen.

[0114] The data voltage difference between the first data voltage and the second data voltage can be fitted to calculate different data voltages corresponding to different display brightness values ​​for the same grayscale value, and different data voltages corresponding to different grayscale values ​​for the same display brightness, so as to obtain a color picture and a more delicate grayscale value compensation value, thereby further improving the display effect of the display panel and enhancing the user experience.

[0115] FIG8 is a flow chart of a brightness compensation method provided by an embodiment of the present disclosure. As shown in FIG8 , the above step S702 is to fit the data voltage difference between the first data voltage and the second data voltage according to the brightness of different display images, and specifically includes the following steps S801 to S807.

[0116] S801 , inputting data voltages corresponding to a first display brightness value and a first grayscale value to a first pixel unit and a second pixel unit in a display panel to display a first display image.

[0117] S802 : Calculate a first display brightness difference between the first display image and the preset display image according to the first display image and the preset display image.

[0118] S803 , calculating a first grayscale difference using a standard gamma curve according to the first display brightness difference.

[0119] S804 , inputting data voltages corresponding to the first display brightness value and the second grayscale value to the first pixel unit and the second pixel unit in the display panel to display a second display image.

[0120] S805 , calculating a second display brightness difference between the second display image and the preset display image according to the second display image and the preset display image.

[0121] S806 , calculating a second grayscale difference using a standard gamma curve according to the second display brightness difference.

[0122] S807 , calculating a compensation value for each grayscale value according to the first grayscale difference and the second grayscale difference.

[0123] In the above steps S801 to S807, the data voltages corresponding to different grayscale values ​​can be changed while ensuring that the display brightness value remains unchanged, so as to obtain different first grayscale differences and second grayscale differences, and the compensation value of each grayscale value can be calculated. In this way, the accuracy of the first data voltage input to the first pixel unit 1011 and the second data voltage input to the second pixel unit 1012 can be improved, thereby avoiding the phenomenon of three-part screen, thereby ensuring the brightness uniformity of the display screen, and further improving the user experience.

[0124] FIG9 is a flow chart of another brightness compensation method provided by an embodiment of the present disclosure. As shown in FIG9 , the above-mentioned step S702 is to fit the data voltage difference between the first data voltage and the second data voltage according to the brightness of different display images, and specifically includes the following steps S901 to S904.

[0125] S901 , inputting data voltages corresponding to a second display brightness value and a first grayscale value to a first pixel unit and a second pixel unit in a display panel to display a third display image.

[0126] S902 : Calculate a third display brightness difference between the third display image and the preset display image according to the third display image and the preset display image.

[0127] S903 , calculating a third grayscale difference using a standard gamma curve according to the third display brightness difference.

[0128] S904 , calculating a compensation value for each grayscale value according to the first grayscale difference and the third grayscale difference.

[0129] In the above steps S901 to S904, the data voltages corresponding to different display brightness values ​​can be changed while ensuring that the grayscale value remains unchanged, so as to obtain different first grayscale differences and third grayscale differences, and calculate the compensation value of each grayscale value. This can improve the accuracy of the first data voltage input to the first pixel unit 1011 and the second data voltage input to the second pixel unit 1012, avoid the phenomenon of three-part screen, thereby ensuring the brightness uniformity of the display screen, and further improving the user experience.

[0130] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display panel comprising a display area and a peripheral area at least disposed on one side of the display area, wherein: The display panel comprises: a plurality of rows of first pixel units and a plurality of rows of second pixel units located in the display area; the number of rows of the second pixel units is smaller than the number of rows of the first pixel units; In a same frame display image, a first data voltage input to the first pixel unit is smaller than a second data voltage input to the second pixel unit.

2. The display panel according to claim 1, wherein: The first pixel unit includes: a first pixel driving circuit; the first pixel driving circuit includes: a first initialization transistor, a threshold compensation transistor, a driving transistor, a data writing transistor, a first light emission control transistor, a second light emission control transistor, a second initialization transistor, a third initialization transistor, a storage capacitor and a light emitting device; The control electrode of the driving transistor is connected to the first node, the first electrode is connected to the second node, and the second electrode is connected to the third node; The control electrode of the data writing transistor is connected to the first scanning signal line, the first electrode is connected to the data signal line, and the second electrode is connected to the second node; The control electrode of the threshold compensation transistor is connected to the second scanning signal line, the first electrode is connected to the third node, and the second electrode is connected to the first node; One end of the storage capacitor is connected to the first node, and the other end is connected to the first power signal line; The control electrode of the first light emitting control transistor is connected to the light emitting control signal line, the first electrode is connected to the first power signal line, and the second electrode is connected to the second node; The control electrode of the second light emitting control transistor is connected to the light emitting control signal line, the first electrode is connected to the third node, and the second electrode is connected to the fourth node; The control electrode of the first initialization transistor is connected to the first reset signal line, the first electrode is connected to the first initialization signal line, and the second electrode is connected to the third node; The control electrode of the second initialization transistor is connected to the second reset signal line, the first electrode is connected to the second initialization signal line, and the second electrode is connected to the fourth node; The control electrode of the third initialization transistor is connected to the second reset signal line, the first electrode is connected to the third initialization signal line, and the second electrode is connected to the second node; The first electrode of the light emitting device is connected to the fourth node, and the second electrode is connected to the second power signal line.

3. The display panel according to claim 2, wherein: The second pixel unit includes: a second pixel driving circuit; the second pixel driving circuit has the same structure as the first pixel driving circuit.

4. The display panel according to claim 2, wherein: In the same frame of display image, the number of pulses of the light emitting control signal transmitted by the light emitting control signal line is the same as the number of pulses of the second reset signal transmitted by the second reset signal line.

5. The display panel according to claim 2, wherein: During the refresh frame time, the first initialization transistor, the second initialization transistor, and the third initialization transistor are all turned on, and the first initialization signal, the second initialization signal, and the third initialization signal are written to the voltages of the third node, the fourth node, and the second node, respectively; The data writing transistor and the threshold compensation transistor are both turned on to write a data voltage and a threshold voltage to the first node, and under the control of the first light emission control transistor and the second light emission control transistor, the driving transistor is used to drive the light emitting device to emit light; During the holding frame time, the first initialization transistor, the second initialization transistor, and the third initialization transistor are all turned on, and the first initialization signal, the second initialization signal, and the third initialization signal are written to the voltages of the third node, the fourth node, and the second node, respectively; The data writing transistor and the threshold compensation transistor are both turned off, and under the control of the first light emission control transistor and the second light emission control transistor, the driving transistor is used to drive the light emitting device to emit light. The display panel according to claim 1 , wherein: The display panel further comprises: a plurality of shift registers and a gating circuit located in the peripheral area; Each of the shift registers is connected to a row of the first pixel units or a row of the second pixel units through the gating circuit.

7. A pixel array, wherein: The pixel array includes: a plurality of rows of first pixel units and a plurality of rows of second pixel units; the number of rows of the second pixel units is smaller than the number of rows of the first pixel units; In a same frame display image, a first data voltage input to the first pixel unit is smaller than a second data voltage input to the second pixel unit.

8. The pixel array according to claim 7, wherein: The first pixel unit includes: a first pixel driving circuit; the first pixel driving circuit includes: a first initialization transistor, a threshold compensation transistor, a driving transistor, a data writing transistor, a first light emission control transistor, a second light emission control transistor, a second initialization transistor, a third initialization transistor, a storage capacitor and a light emitting device; The control electrode of the driving transistor is connected to the first node, the first electrode is connected to the second node, and the second electrode is connected to the third node; The control electrode of the data writing transistor is connected to the first scanning signal line, the first electrode is connected to the data signal line, and the second electrode is connected to the second node; The control electrode of the threshold compensation transistor is connected to the second scanning signal line, the first electrode is connected to the third node, and the second electrode is connected to the first node; One end of the storage capacitor is connected to the first node, and the other end is connected to the first power signal line; The control electrode of the first light emitting control transistor is connected to the light emitting control signal line, the first electrode is connected to the first power signal line, and the second electrode is connected to the second node; The control electrode of the second light emitting control transistor is connected to the light emitting control signal line, the first electrode is connected to the third node, and the second electrode is connected to the fourth node; The control electrode of the first initialization transistor is connected to the first reset signal line, the first electrode is connected to the first initialization signal line, and the second electrode is connected to the third node; The control electrode of the second initialization transistor is connected to the second reset signal line, the first electrode is connected to the second initialization signal line, and the second electrode is connected to the fourth node; The control electrode of the third initialization transistor is connected to the second reset signal line, the first electrode is connected to the third initialization signal line, and the second electrode is connected to the second node; The first electrode of the light emitting device is connected to the fourth node, and the second electrode is connected to the second power signal line.

9. The pixel array according to claim 8, wherein: The second pixel unit includes: a second pixel driving circuit; the second pixel driving circuit has the same structure as the first pixel driving circuit.

10. The pixel array according to claim 8, wherein: In the same frame of display image, the number of pulses of the light emitting control signal transmitted by the light emitting control signal line is the same as the number of pulses of the second reset signal transmitted by the second reset signal line.

11. The pixel array according to claim 8, wherein: During the refresh frame time, the first initialization transistor, the second initialization transistor, and the third initialization transistor are all turned on, and the first initialization signal, the second initialization signal, and the third initialization signal are written to the voltages of the third node, the fourth node, and the second node, respectively; The data writing transistor and the threshold compensation transistor are both turned on to write a data voltage and a threshold voltage to the first node, and under the control of the first light emission control transistor and the second light emission control transistor, the driving transistor is used to drive the light emitting device to emit light; During the holding frame time, the first initialization transistor, the second initialization transistor, and the third initialization transistor are all turned on, and the first initialization signal, the second initialization signal, and the third initialization signal are written to the voltages of the third node, the fourth node, and the second node, respectively; The data writing transistor and the threshold compensation transistor are both turned off, and under the control of the first light emission control transistor and the second light emission control transistor, the driving transistor is used to drive the light emitting device to emit light.

12. A display device, wherein: The display device comprises the display panel according to any one of claims 1 to 6, or the pixel array according to any one of claims 7 to 11.

13. A brightness compensation method for a display panel, wherein: The brightness compensation method of the display panel includes: According to the brightness of the pre-displayed display image, a first data voltage is input to the first pixel unit, and a second data voltage is input to the second pixel unit; the first data voltage is smaller than the second data voltage.

14. The brightness compensation method of a display panel according to claim 13, wherein: According to the brightness of the same display image that is pre-displayed, a first data voltage is input to the first pixel unit, and a second data voltage is input to the second pixel unit, and then the method further includes: According to the brightness of different display images, the data voltage difference between the first data voltage and the second data voltage is fitted.

15. The brightness compensation method of a display panel according to claim 14, wherein: Fitting the data voltage difference between the first data voltage and the second data voltage according to different brightness of the display screen includes: Inputting a data voltage corresponding to a first display brightness value and a first grayscale value to the first pixel unit and the second pixel unit in the display panel to display a first display image; Calculating a first display brightness difference between the first display image and the preset display image according to the first display image and the preset display image; Calculating a first grayscale difference using a standard gamma curve according to the first display brightness difference; Inputting a data voltage corresponding to a first display brightness value and a second grayscale value to the first pixel unit and the second pixel unit in the display panel to display a second display image; Calculating a second display brightness difference between the second display image and the preset display image according to the second display image and the preset display image; Calculating a second grayscale difference using a standard gamma curve according to the second display brightness difference; A compensation value for each grayscale value is calculated according to the first grayscale difference and the second grayscale difference.

16. The brightness compensation method of a display panel according to claim 15, wherein: According to different brightness of the display screen, the data voltage difference between the first data voltage and the second data voltage is fitted, and further comprising: Inputting a data voltage corresponding to a second display brightness value and a first grayscale value to the first pixel unit and the second pixel unit in the display panel to display a third display image; Calculating a third display brightness difference between the third display image and the preset display image according to the third display image and the preset display image; Calculating a third grayscale difference using a standard gamma curve according to the third display brightness difference; A compensation value for each grayscale value is calculated according to the first grayscale difference and the third grayscale difference.

Images