Display substrate, manufacturing method therefor, and display apparatus

Abstract

A display substrate, a manufacturing method therefor, and a display apparatus, relating to, but not limited to, the technical field of display. The display substrate comprises a display region (100); the display region (100) comprises, provided on a substrate (101), data signal lines (1), auxiliary wires (5) and signal wires (6); shapes of the data signal lines (1) comprise a line shape extending in a second direction; the plurality of data signal lines (1) are spaced apart in a first direction; the data signal lines (1) and the auxiliary wires (5) are located at different film layers; at least some of the data signal lines (1) and the auxiliary wires (5) are connected in parallel by means of connecting vias; the auxiliary wires (5) and at least some of the signal wires (6) are located at a same film layer and are disconnected from each other; and the first direction intersects with the second direction.

Description

Display substrate, manufacturing method thereof, and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on January 31, 2024, with application number 202410140721.6 and invention name “A display substrate, its preparation method, and display device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] This article relates to but is not limited to the field of display technology, and specifically to a display substrate and a preparation method thereof, and a display device. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field. Summary of the Invention

[0004] The present application provides a display substrate, including a display area, wherein the display area includes data signal lines, auxiliary routing lines, and signal routing lines arranged on a substrate, wherein the shape of the data signal lines includes a linear shape extending along a second direction, and a plurality of the data signal lines are arranged at intervals along a first direction, wherein the data signal lines and the auxiliary routing lines are located in different film layers, and at least some of the data signal lines are connected in parallel with the auxiliary routing lines through connecting vias, and the auxiliary routing lines and at least some of the signal routing lines are located in the same film layer and are disconnected from each other, and the first direction and the second direction intersect with each other.

[0005] In an exemplary embodiment, the auxiliary wiring is disposed on a side of the data signal line close to the substrate, or the auxiliary wiring is disposed on a side of the data signal line away from the substrate.

[0006] In an exemplary embodiment, the auxiliary routing lines have the same extension direction as the data signal lines, the auxiliary routing lines are connected in parallel with the data signal lines through a plurality of connecting routing lines, the shapes of the connecting routing lines include linear shapes extending along the first direction, the first ends of the connecting routing lines are all connected to the auxiliary routing lines, and the second ends of the connecting routing lines are all connected to the data signal lines through the connecting vias.

[0007] In an exemplary embodiment, the connecting trace and the auxiliary trace are connected as one body and include the same conductive material.

[0008] In an exemplary embodiment, the auxiliary trace is connected in parallel with the data signal line through at least two connecting traces, and the shape formed by the combination of the auxiliary trace and the two connecting traces includes: shape.

[0009] In an exemplary embodiment, the auxiliary wiring is located in an edge region of at least one side of the display area in the first direction, and the auxiliary wiring is connected in parallel with the data signal line located in the edge region of at least one side of the display area in the first direction.

[0010] In an exemplary embodiment, the auxiliary traces and at least a portion of the data signal lines are alternately arranged along the first direction.

[0011] In an exemplary embodiment, the signal routing line includes a first routing line, the first routing line and the auxiliary routing line are located in the same film layer, the shape of the first routing line includes a line extending along the second direction, the first routing line is located on at least one side of the auxiliary routing line in the second direction, and is disconnected from the auxiliary routing line.

[0012] In an exemplary embodiment, the first routing line and the auxiliary routing line are located on the same straight line in the second direction.

[0013] In an exemplary embodiment, the signal routing line further includes a second routing line, the second routing line and the first routing line are located in a different film layer, the shape of the second routing line includes a line extending along the first direction, the second routing line and the auxiliary routing line do not overlap in their orthographic projection on the substrate, and the second routing line is connected to at least one of the first routing lines through a third via hole.

[0014] In an exemplary embodiment, the signal routing line also includes a third routing line, the third routing line and the second routing line are located in a different film layer, the shape of the third routing line includes a line extending along the second direction, the third routing line does not overlap with the auxiliary routing line and the first routing line's positive projection on the substrate, the first end of the third routing line extends to the edge of the display area on one side in the second direction, the second end of the third routing line extends to the edge of the display area on the other side in the second direction, and the third routing line is connected to the second routing line through a fourth via hole.

[0015] In an exemplary embodiment, the third wiring is located in a middle area of ​​the display area in the first direction.

[0016] In an exemplary embodiment, the signal trace includes an initial signal line.

[0017] In an exemplary embodiment, a binding area is further included on one side of the display area in the second direction, the binding area includes lead lines arranged on the substrate, and the display area further includes connecting signal lines arranged on the substrate, the connecting signal lines are all located in different film layers from the lead lines and the data signal lines, a first end of the connecting signal line is connected to at least part of the data signal line through a first via hole, and a second end of the connecting signal line is connected to at least part of the lead lines through a second via hole.

[0018] In an exemplary embodiment, a shape of the connection signal line includes a line extending along the first direction; and a shape of the lead line includes a line extending along the second direction.

[0019] In an exemplary embodiment, the data signal line includes a first data line and a second data line, the first data line is located in edge areas on opposite sides of the display area in the first direction, the first data line is connected to the lead line through the connecting signal line, and the second data line is located in a middle area of ​​the display area in the first direction, and the second data line is directly connected to the lead line.

[0020] In an exemplary embodiment, the auxiliary trace is connected in parallel with at least a portion of the first data line.

[0021] In an exemplary embodiment, the auxiliary routing is located in an edge area of ​​at least one side of the display area in the first direction, and in a middle area of ​​the display area in the first direction, and the length of the auxiliary routing located in the edge area of ​​the display area in the second direction is greater than the length of the auxiliary routing located in the middle area of ​​the display area in the second direction.

[0022] The present application also provides a display device, comprising the aforementioned display substrate.

[0023] The present application also provides a method for preparing a display substrate, comprising:

[0024] forming auxiliary wiring and signal wiring on a substrate, wherein the auxiliary wiring and at least a portion of the signal wiring are made of the same conductive film and are disconnected from each other;

[0025] Data signal lines are formed on a substrate, wherein the shape of the data signal lines includes a linear shape extending along a second direction, and a plurality of the data signal lines are arranged at intervals along a first direction. The data signal lines and the auxiliary lines are located in different film layers, and at least some of the data signal lines and the auxiliary lines are connected in parallel through connecting vias. The auxiliary lines do not overlap with the orthographic projections of the data signal lines and the signal lines on the substrate, and the first direction and the second direction intersect with each other.

[0026] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. Other advantages of the present application can be realized and obtained by the solutions described in the description and the drawings.

[0027] Summary of the Figures

[0028] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0029] FIG1 is a schematic structural diagram of a display device;

[0030] FIG2 is a schematic structural diagram of a display substrate according to an embodiment of the present application;

[0031] FIG3 is a schematic diagram of a cross-sectional structure of a display area of ​​a display substrate;

[0032] FIG4 is a schematic structural diagram of a display substrate in related art;

[0033] FIG5 is a schematic diagram showing a planar structure of a data signal line in a substrate according to an exemplary embodiment of the present disclosure;

[0034] FIG6 is a schematic diagram showing a planar structure of a substrate according to an exemplary embodiment of the present disclosure;

[0035] FIG7 a is a schematic diagram showing a substrate after a first conductive layer is formed during the preparation process of an exemplary embodiment of the present disclosure;

[0036] FIG7 b is a schematic diagram showing a substrate after a second conductive layer is formed during the preparation process of an exemplary embodiment of the present disclosure;

[0037] FIG8 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure.

[0038] Details

[0039] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0040] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0041] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0042] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0043] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0044] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0045] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0046] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0047] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0048] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0049] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0050] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0051] FIG4 is a schematic structural diagram of a display substrate of the related art. In an exemplary embodiment, as shown in FIG4 , the display substrate of the related art includes a display area 100 ′, a binding area 200 ′ located on one side of the display area 100 ′, and a frame area 300 ′ located on the other side of the display area 100 ′.

[0052] In an exemplary embodiment, the display area 100' includes a data signal line 1' extending along the second direction D2, and a plurality of data signal lines 1' are arranged at intervals along the first direction D1. The binding area 200' may include a routing area, a driver chip area, and a binding pin area arranged in sequence along a direction away from the display area 100'. The routing area is connected to the display area 100' and includes at least a lead line 2', which is configured to connect the data signal line 1' of the display area 100'. The driver chip area may be provided with an integrated circuit (IC), which may be configured to be connected to a plurality of lead lines 2'. The binding pin area may include a binding pad, which may be configured to be bound and connected to an external flexible printed circuit (FPC). The first direction D1 and the second direction D2 are both parallel to the display substrate, and the first direction D1 intersects with the second direction D2. For example, the first direction D1 and the second direction D2 are perpendicular to each other.

[0053] In an exemplary embodiment, the lead lines 2 ′ are connected to the data signal lines 1 ′ of the display area 100 ′ in a fan-out routing manner.

[0054] The inventors of the present application have discovered through research that, in a display substrate of the related art, the display of the display area 100 ′ on two opposite sides in the first direction D1 is dark, which affects the display effect of the display substrate.

[0055] Figure 1 is a schematic diagram of the structure of a display device. As shown in Figure 1, the display device may include: a timing controller, a data driver, a scan driver, a light-emitting driver and a pixel array. The timing controller is connected to the data driver, the scan driver and the light-emitting driver respectively. The data driver is connected to a plurality of data signal lines (for example, D1 to Dn), the scan driver is connected to a plurality of scan signal lines (for example, S1 to Sm), and the light-emitting driver is connected to a plurality of light-emitting control lines (for example, E1 to Eo). Wherein, n, m and o can be natural numbers. The pixel array may include a plurality of sub-pixels Pxij, and i and j can be natural numbers. At least one sub-pixel Pxij may include: a pixel circuit and a light-emitting device connected to the pixel circuit. The pixel circuit may be connected to the scan signal line, the light-emitting control line and the data signal line respectively.

[0056] In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and clock signals, emission stop signals, etc. suitable for the specifications of the light emitting driver to the light emitting driver. The data driver may use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3, ..., and Dn. For example, the data driver may sample grayscale values ​​using the clock signal and apply data voltages corresponding to the grayscale values ​​to the data signal lines D1 to Dn on a pixel row basis. The scan driver may generate scan signals to be provided to the scan signal lines S1, S2, S3, ..., and Sm by receiving the clock signal, scan start signal, etc. from the timing controller. For example, the scan driver may sequentially provide scan signals having on-level pulses to the scan signal lines S1 to Sm. For example, the scan driver can be configured in the form of a shift register and can generate a scan signal by sequentially transmitting a scan start signal provided in the form of an on-level pulse to the next-stage circuit under the control of a clock signal. The light-emitting driver can generate a light-emitting control signal to be provided to the light-emitting control lines E1, E2, E3, ... and Eo by receiving a clock signal, an emission stop signal, etc. from a timing controller. For example, the light-emitting driver can sequentially provide an emission signal having an off-level pulse to the light-emitting control lines E1 to Eo. For example, the light-emitting driver can be configured in the form of a shift register and can generate a light-emitting control signal by sequentially transmitting an emission stop signal provided in the form of an off-level pulse to the next-stage circuit under the control of a clock signal.

[0057] FIG2 is a schematic diagram of the structure of a display substrate according to an embodiment of the present application. In an exemplary embodiment, as shown in FIG2 , the display substrate according to the present application may include a display area 100 , a binding area 200 located on one side of the display area 100 , and a frame area 300 located on the other side of the display area 100 .

[0058] In some examples, the display substrate may be a flexible substrate, and thus the display substrate may be deformable, for example, curled, bent, folded, or rolled.

[0059] In an exemplary embodiment, the binding area 200 may include a routing area, a driver chip area, and a binding pin area, which are sequentially arranged in a direction away from the display area 100. The routing area is connected to the display area 100 and includes at least lead wires, wherein the plurality of lead wires are configured to connect to the data signal lines of the display area 100. The driver chip area may include an integrated circuit (IC), which may be configured to connect to the plurality of lead wires. The binding pin area may include bonding pads, which may be configured to be bonded to an external flexible printed circuit (FPC).

[0060] In some examples, the display area 100 may be a flat area including a plurality of sub-pixels Pxij constituting a pixel array. The plurality of sub-pixels Pxij may be configured to display a dynamic image or a still image. The display area 100 may be referred to as an active area (AA).

[0061] In an exemplary embodiment, the display area 100 of the display substrate may include a plurality of pixel units arranged in a matrix. For example, at least one pixel unit may include a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and third and fourth sub-pixels emitting a third color light.

[0062] In an exemplary embodiment, the first sub-pixel may be a red sub-pixel (R) that emits red light, the second sub-pixel may be a blue sub-pixel (B) that emits blue light, and the third and fourth sub-pixels may be green sub-pixels (G) that emit green light. In some examples, the shape of the light-emitting device of the sub-pixel may be rectangular, rhombus, pentagonal, or hexagonal, and the light-emitting devices of the four sub-pixels may be arranged in a diamond shape to form an RGBG pixel arrangement. In other exemplary embodiments, the light-emitting devices of the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a square arrangement, which is not limited in this disclosure. In other exemplary embodiments, the pixel unit may include three sub-pixels, and the light-emitting devices of the three sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a triangle arrangement, which is not limited in this disclosure.

[0063] In an exemplary embodiment, a sub-pixel Pxij may include a pixel circuit and a light-emitting device. The pixel circuit is electrically connected to a scan signal line, a data signal line, and a light-emitting control line, respectively. The pixel circuit may be configured to receive a data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scan signal line and the light-emitting control line. The light-emitting device in each sub-pixel is connected to the pixel circuit of the sub-pixel, and the light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel circuit of the sub-pixel.

[0064] In an exemplary embodiment, the light emitting device may include an organic light emitting diode (OLED), a micro light emitting diode (LED), or a quantum dot light emitting diode (QLED). The sub-pixel may emit light, for example, red, green, blue, or white light, through the light emitting device.

[0065] In an exemplary embodiment, the display substrate includes a display area 100 having a rectangular shape. In some embodiments, the display area 100 may also have a circular shape, an elliptical shape, or a polygonal shape such as a triangle, a pentagon, or the like.

[0066] In an exemplary embodiment, the display substrate may be a flat panel display substrate. In some embodiments, the display substrate may also be other types of display substrates, such as a flexible display substrate, a foldable display substrate, or a rollable display substrate.

[0067] In the following, the light-emitting device in the display substrate of this embodiment is an organic light-emitting diode (OLED) as an example, but the display substrate of this embodiment is not limited to this. In another embodiment, the light-emitting device in the display substrate can be a micro light-emitting diode (LED) or a quantum dot light-emitting diode (QLED). For example, the light-emitting layer of the light-emitting device in the display substrate can include organic materials, inorganic materials, quantum dots, organic materials and quantum dots, inorganic materials and quantum dots, or organic materials, inorganic materials and quantum dots.

[0068] Figure 3 is a schematic cross-sectional view of the display region of a display substrate. Figure 3 illustrates the structure of three sub-pixels in display region 100. As shown in Figure 3, in a direction perpendicular to the display substrate, the display substrate may include: a base 101, a drive circuit layer 102, a light-emitting structure layer 103, and an encapsulation structure layer 104, sequentially disposed on base 101. In some possible implementations, the display substrate may include other film layers, such as a touch-sensitive structure layer, but this disclosure does not limit this.

[0069] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 of each sub-pixel may include a pixel circuit composed of multiple transistors and capacitors. The light-emitting structure layer 103 of each sub-pixel may include at least an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304. The anode 301 is connected to the pixel circuit, the organic light-emitting layer 303 is connected to the anode 301, and the cathode 304 is connected to the organic light-emitting layer 303. The organic light-emitting layer 303 emits light of a corresponding color under the drive of the anode 301 and the cathode 304. The encapsulation structure layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402 and a third encapsulation layer 403. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is arranged between the first encapsulation layer 401 and the third encapsulation layer 403 to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0070] In an exemplary embodiment, the organic light-emitting layer 303 may include a light-emitting layer (EML) and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In some examples, one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer of all sub-pixels may be a common layer that is connected together, and the light-emitting layers of adjacent sub-pixels may have a small amount of overlap or may be isolated from each other.

[0071] The present application provides a display substrate, including a display area, wherein the display area includes data signal lines, auxiliary routing lines, and signal routing lines arranged on a substrate, wherein the shape of the data signal lines includes a linear shape extending along a second direction, and a plurality of the data signal lines are arranged at intervals along a first direction, wherein the data signal lines and the auxiliary routing lines are located in different film layers, and at least some of the data signal lines are connected in parallel with the auxiliary routing lines through connecting vias, and the auxiliary routing lines and at least some of the signal routing lines are located in the same film layer and are disconnected from each other, and the auxiliary routing lines do not overlap with the orthographic projections of the data signal lines and the signal routing lines on the substrate, and the first direction and the second direction intersect with each other.

[0072] The display substrate of the present disclosure is described below by way of some exemplary embodiments.

[0073] FIG5 is a schematic diagram of a planar structure of data signal lines in a display substrate according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, as shown in FIG5 , the display substrate according to an exemplary embodiment of the present disclosure includes a display area 100, a binding area 200 located on one side of the display area 100, and a frame area 300 located on the other side of the display area 100.

[0074] In an exemplary embodiment, a display substrate of the exemplary embodiment of the present disclosure includes a plurality of data signal lines 1 disposed on a base. The plurality of data signal lines 1 are located in a display area 100. The plurality of data signal lines 1 are linearly shaped and extend along a second direction D2. The plurality of data signal lines 1 are arranged in a spaced-apart pattern along a first direction D1. The first ends of the data signal lines 1 extend to an edge of the display area 100 located away from the binding area 200, and the second ends of the data signal lines 1 extend to an edge of the display area 100 located near the binding area 200. The first direction D1 and the second direction D2 are both parallel to the display substrate and intersect with each other. For example, the first direction D1 and the second direction D2 are perpendicular to each other.

[0075] In an exemplary embodiment, the binding area 200 may include a routing area 210, a driver chip area 220, and a binding pin area, which are sequentially arranged in a direction away from the display area 100. The routing area 210 is connected to the display area 100 and includes at least lead wires 2 arranged on the substrate. The first ends of at least some of the lead wires 2 extend into the display area 100 and are connected to the data signal lines 1 of the display area 100. The second ends of the lead wires 2 extend to the driver chip area 220. The driver chip area 220 may include an integrated circuit 221 (IC) arranged on the substrate. The integrated circuit 221 may be connected to the second ends of multiple lead wires 2. The binding pin area may include a bonding pad arranged on the substrate. The bonding pad may be configured to be bonded to an external flexible printed circuit (FPC).

[0076] In an exemplary embodiment, the exemplary embodiment display substrate of the present disclosure further includes a connecting signal line 3 provided on the base, the connecting signal line 3 is located in the display area 100, and the shape of the connecting signal line 3 includes a line extending along the first direction D1, and a plurality of connecting signal lines 3 are arranged at intervals along the second direction D2, a first end of the connecting signal line 3 is connected to at least a portion of the data signal line 1, and a second end of the connecting signal line 3 is connected to at least a portion of the lead-out line.

[0077] In an exemplary embodiment, the plurality of data signal lines 1 include a first data line 11 and a second data line 12. The first data line 11 is located at opposite edges of the display area 100 in the first direction D1. The first data line 11 is linearly shaped, extending along the second direction D2. A first end of the first data line 11 extends to the edge of the display area 100 away from the binding area 200, and a second end of the first data line 11 extends to the edge of the display area 100 near the binding area 200. At least a portion of the first end of the lead line 2 extends into the display area 100. The first data line 11 is connected to the first end of the lead line 2 extending into the display area 100 via the connection signal line 3. The second data line 12 is located in the middle region of the display area 100 in the first direction D1. The second data line 12 is linearly shaped, extending along the second direction D2. A first end of the second data line 12 extends to the edge of the display area 100 away from the binding area 200, and a second end of the second data line 12 extends to the edge of the display area 100 near the binding area 200. At least part of the first end of the lead line 2 extends to the edge of the display area 100 near the binding area 200. The second end of the second data line 12 is connected to the first end of the lead line 2 extending to the edge of the display area 100 near the binding area 200.

[0078] In the embodiment of the present disclosure, the data signal lines of the display substrate are connected to the lead lines through the connecting signal lines, thereby preventing the data signal lines from being routed along the edge of the binding area, thereby reducing the size of the binding area.

[0079] In some embodiments, the connecting signal line may also include other shapes, such as a broken line shape, a wave shape, an arc shape, etc., which will not be described in detail in the embodiments of the present disclosure.

[0080] In an exemplary embodiment, the connection signal line 3 may be located in a different film layer from at least one of the lead line 2 and the first data line 11. For example, the connection signal line 3 is located in a different film layer from the lead line 2 and the first data line 11, and a first end of the connection signal line 3 is connected to the first data line 11 through a first via 41, and a second end of the connection signal line 3 is connected to the lead line 2 through a second via 42.

[0081] In an exemplary embodiment, the lead-out lines and the data signal lines may be located in the same film layer or in different film layers, which will not be further described in this disclosure.

[0082] Figure 6 is a schematic diagram of the planar structure of a display substrate according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, as shown in Figure 6, the display substrate according to the exemplary embodiment of the present disclosure further includes auxiliary traces 5 disposed on the base. Auxiliary traces 5 are located in the display area 100. Auxiliary traces 5 and data signal lines 1 are located in a different film layer. Auxiliary traces 5 are connected in parallel with at least a portion of the data signal lines 1 via connecting vias 501.

[0083] In the embodiment of the present disclosure, the display substrate is connected in parallel with the data signal line 1 through the auxiliary trace 5 , thereby reducing the resistance of the data signal line 1 and improving the display effect of the display substrate.

[0084] In an exemplary embodiment, the auxiliary traces may be disposed on a side of the data signal line close to the substrate, or the auxiliary traces may be disposed on a side of the data signal line away from the substrate, which will not be further elaborated herein.

[0085] In an exemplary embodiment, the auxiliary trace 5 is linear and extends along the second direction D2. The auxiliary trace 5 extends in the same direction as the data signal line 1. The auxiliary trace 5 is located on at least one side of the data signal line 1 in the first direction D1. The auxiliary trace 5 can be connected in parallel with the data signal line 1 via a plurality of connecting traces 52. The connecting traces 52 are linear and extend along the first direction D1. The plurality of connecting traces 52 are arranged at intervals along the second direction D2. The first ends of the connecting traces 52 are connected to the auxiliary trace 5, and the second ends of the connecting traces 52 are connected to the data signal line 1 through connecting vias 501.

[0086] In an exemplary embodiment, the first end of the connecting trace 52 is connected to the auxiliary trace 5 as a whole, and comprises the same conductive material and is manufactured by the same manufacturing process.

[0087] In an exemplary embodiment, the auxiliary trace 5 can be connected in parallel with the data signal line 1 through at least two connecting traces 52. The shape formed by the combination of the auxiliary trace 5 and the two connecting traces 52 includes: In some embodiments, the shape formed by the auxiliary trace 5 and the two connecting traces 52 may also include other shapes, such as a U-shape, a V-shape, etc., which will not be described in detail in the embodiments of the present disclosure.

[0088] In an exemplary embodiment, the length of the auxiliary trace 5 can be calculated based on the resistance of the auxiliary trace 5 connected in parallel with the data signal line 1. First, the resistance R1 of the data signal line 1 is calculated according to Formula 1: Data signal line resistance R1 = data signal line resistivity * data signal line length / data signal line cross-sectional area. Then, R2 is calculated according to Formula 2: Rn = R1R2 / R1+R2, where Rn is the resistance of the auxiliary trace 5 connected in parallel with the data signal line 1, R1 is the resistance of the data signal line 1, and R2 is the resistance of the auxiliary trace 5. Finally, the length of the auxiliary trace 5, i.e., the length of the auxiliary trace 5 in the second direction D2, is calculated according to Formula 3: Auxiliary trace resistance R2 = auxiliary trace resistivity * auxiliary trace length / auxiliary trace cross-sectional area.

[0089] In an exemplary embodiment, the auxiliary routing line 5 is located in an edge region of at least one side of the display area 100 in the first direction D1, and the auxiliary routing line 5 is connected in parallel with the first data line 11 located in the edge region of at least one side of the display area 100 in the first direction D1. For example, the auxiliary routing line 5 is located in edge regions on opposite sides of the display area 100 in the first direction D1, and the auxiliary routing line 5 is connected in parallel with the first data line 11 located in edge regions on opposite sides of the display area 100 in the first direction D1.

[0090] In an exemplary embodiment, the auxiliary traces 5 and the first data lines 11 are alternately arranged along the first direction D1, that is, one auxiliary trace 5 is arranged between adjacent first data lines 11, and one first data line 11 is arranged between adjacent auxiliary traces 5. The auxiliary trace 5 is connected in parallel with one of the first data lines 11 located on both sides thereof.

[0091] In the embodiment of the present disclosure, the display substrate is connected in parallel with the first data line 11 located in the edge area of ​​at least one side of the display area 100 in the first direction D1 through the auxiliary trace 5, so that the resistance of the first data line 11 can be reduced, thereby improving the display brightness on both sides of the display area 100 in the first direction D1, and solving the problem of dark display on both sides of the display area 100.

[0092] In some embodiments, the auxiliary traces may be located in the middle area of ​​the display area in the first direction D1. The auxiliary traces are connected in parallel with the second data lines through connecting vias. For example, the auxiliary traces and the second data lines are alternately arranged along the first direction D1, i.e., an auxiliary trace is arranged between adjacent second data lines, and a second data line is arranged between adjacent auxiliary traces. The auxiliary traces are connected in parallel with one of the second data lines located on both sides of the auxiliary traces.

[0093] In some embodiments, auxiliary traces may be located in edge regions on opposite sides of the display area in the first direction D1, as well as in a central region of the display area in the first direction D1. The auxiliary traces are connected in parallel to the first data signal line and the second data signal line through connecting vias. For example, the auxiliary traces and the data signal lines are alternately arranged along the first direction D1, that is, the auxiliary traces are alternately arranged with the first data line and the second data line along the first direction D1; an auxiliary trace is arranged between adjacent first data lines, an auxiliary trace is arranged between adjacent second data lines, and a first data line or a second data line is arranged between adjacent auxiliary traces. The auxiliary traces are connected to one of the data signal lines located on either side of them.

[0094] In an exemplary embodiment, the display substrate of the disclosed embodiment further includes a signal trace 6 arranged on the base, the signal trace 6 is located in the display area 100, at least part of the signal trace 6 can be located in the same film layer as the auxiliary trace 5, and the orthographic projections of the signal trace 6 and the auxiliary trace 5 on the base do not overlap.

[0095] In an exemplary embodiment, the signal trace 6 may include an initial signal line.

[0096] In an exemplary embodiment, the signal trace 6 includes a first trace 61, which is located in a different film layer from the data signal line 1. For example, the first trace 61 is located on the side of the data signal line 1 close to the substrate, or the first trace 61 is located on the side of the data signal line 1 away from the substrate.

[0097] In an exemplary embodiment, the first routing line 61 may be located in the same film layer as the auxiliary routing line 5. The shape of the first routing line 61 includes a line extending along the second direction D2, and a plurality of first routing lines 61 are arranged at intervals along the first direction D1. The first routing line 61 may be located on at least one side of the auxiliary routing line 5 in the second direction D2, and be disconnected from the auxiliary routing line 5. For example, the first routing line 61 may be located in an edge area of ​​the display area 100 in the second direction D2, the auxiliary routing line 5 may be located in a middle area of ​​the display area 100 in the second direction D2, the first routing line 61 may be located on opposite sides of the auxiliary routing line 5 in the second direction D2, the first end of the first routing line 61 extends to one side edge of the display area 100 in the second direction D2, and the second end of the first routing line 61 extends in a direction close to the auxiliary routing line 5, and is disconnected from the end of the auxiliary routing line 5.

[0098] In an exemplary embodiment, the first trace 61 may be located on the same straight line as the auxiliary trace 5 in the second direction D2.

[0099] In an exemplary embodiment, the first routing lines 61 may be located at edge regions on opposite sides of the display region 100 in the first direction D1 .

[0100] In some embodiments, the first routing line may be located in the middle area of ​​the display area in the second direction D2, the auxiliary routing line may be located in the edge area of ​​the display area in the second direction D2, the auxiliary routing line may be located on opposite sides of the first routing line in the second direction D2, the first end of the auxiliary routing line extends to one side edge of the display area in the second direction D2, and the second end of the auxiliary routing line extends in a direction close to the first routing line and is disconnected from the end of the first routing line.

[0101] In an exemplary embodiment, the signal trace 6 further includes a second trace 62. The second trace 62 can be located in a different film layer than the first trace 61. For example, the second trace 62 can be located on the side of the first trace 61 closer to the substrate, or the second trace 62 can be located on the side of the first trace 61 farther from the substrate. The second trace 62 can be located in a different film layer than the data signal line 1. For example, the second trace 62 can be located on the side of the data signal line 1 closer to the substrate, or the second trace 62 can be located on the side of the data signal line 1 farther from the substrate.

[0102] In an exemplary embodiment, the second routing line 62 is linear and extends along the first direction D1. The second routing line and the auxiliary routing line's orthographic projection on the substrate do not overlap. The second routing line 62 is located on at least one side of the auxiliary routing line 5 in the second direction D2. For example, the second routing line 62 is located on opposite sides of the auxiliary routing line 5 in the second direction D2. A first end of the second routing line 62 extends to one edge of the display area 100 in the first direction D1, and a second end of the second routing line 62 extends to the other edge of the display area 100 in the first direction D1. The second routing line and the first routing line are located in different film layers. The second routing line 62 is connected to at least one first routing line 61 via a third via 43. For example, the second routing line 62 is connected to multiple first routing lines 61 via the third via 43.

[0103] In an exemplary embodiment, the signal trace 6 further includes a third trace 63. The third trace 63 is linear and extends along the second direction D2. The orthographic projections of the third trace 63 and the auxiliary trace 5 on the substrate do not overlap. The orthographic projections of the third trace 63 and the first trace 61 on the substrate do not overlap. The third trace 63 and the first trace 61 are staggered in the second direction D2. The third trace and the second trace are located in different film layers, and at least one third trace 63 can be connected to at least one first trace 61 via a second trace 62.

[0104] In an exemplary embodiment, a first end of the third trace 63 extends to one side edge of the display area 100 in the second direction D2, and a second end of the third trace 63 extends to the other side edge of the display area 100 in the second direction D2. The third trace 63 is connected to the second trace 62 through the fourth via 44.

[0105] In an exemplary embodiment, the third routing line 63 may be located in a middle area of ​​the display area 100 in the first direction D1 .

[0106] In an exemplary embodiment, the third trace 63 can be located in a different film layer than the second trace 62. For example, the third trace 63 can be located on the side of the second trace 62 closer to the substrate, or the third trace 63 can be located on the side of the second trace 62 farther from the substrate. The third trace 63 can be located in the same or different film layer as the first trace 61. The third trace 63 can be located in a different film layer than the data signal line 1. For example, the third trace 63 can be located on the side of the data signal line 1 closer to the substrate, or the third trace 63 can be located on the side of the data signal line 1 farther from the substrate.

[0107] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0108] In an exemplary embodiment, the preparation process of the display substrate of this embodiment may include:

[0109] (1) Forming a first conductive layer. In an exemplary embodiment, forming the first conductive layer includes: first depositing a first conductive film on a substrate, patterning the first conductive film through a patterning process, so that the first conductive film forms a first conductive layer, the first conductive layer including the second trace 62 and the connecting signal line 3; then, forming a first insulating layer covering the first conductive layer on the substrate, as shown in FIG7a.

[0110] In an exemplary embodiment, the shape of the connection signal line 3 includes a line extending along the first direction D1, and the plurality of connection signal lines 3 are arranged at intervals along the second direction D2. The plurality of connection signal lines 3 are located in the edge area of ​​the display area 100 close to the binding area 200.

[0111] In an exemplary embodiment, the shape of the second trace 62 includes a line extending along the first direction D1, a first end of the second trace 62 extends to one side edge of the display area 100 in the first direction D1, and a second end of the second trace 62 extends to the other side edge of the display area 100 in the first direction D1.

[0112] (2) Forming a second conductive layer. In an exemplary embodiment, forming the second conductive layer includes: on the substrate on which the aforementioned pattern is formed, first forming a third via 43 and a fourth via 44 in the first insulating layer, wherein the third via 43 and the fourth via 44 both penetrate the first insulating layer along the thickness direction of the substrate, exposing the second trace 62; subsequently, depositing a second conductive film on the first insulating layer, patterning the second conductive film through a patterning process, so that the second conductive film forms a second conductive layer, the second conductive layer including an auxiliary trace 5, a connecting trace 52, a first trace 61, and a third trace 63, wherein the first trace 61 is connected to the second trace 62 through the third via 43, and the third trace 63 is connected to the second trace 62 through the fourth via 44, and the orthographic projections of the auxiliary trace 5 and the second trace 62 on the substrate do not overlap; subsequently, forming a second insulating layer covering the second conductive layer on the first insulating layer, as shown in FIG. 7 b.

[0113] In an exemplary embodiment, the auxiliary traces 5 are located at the edge regions of the display area 100 on opposite sides in the first direction D1. The auxiliary traces 5 are shaped like lines extending along the second direction D2. The connecting traces 52 are shaped like lines extending along the first direction D1. Two connecting traces 52 arranged at intervals along the second direction D2 are both connected to the auxiliary traces 5, forming a combination. shape.

[0114] In an exemplary embodiment, the first trace 61 may be located at an edge region of the display area in the second direction D2. The first trace 61 is located on opposite sides of the auxiliary trace 5 in the second direction D2. The first end of the first trace 61 extends to one edge of the display area 100 in the second direction D2. The second end of the first trace 61 extends in a direction close to the auxiliary trace 5 and is disconnected from the end of the auxiliary trace 5. The first trace 61 may be located in the same straight line as the auxiliary trace 5 in the second direction D2.

[0115] In an exemplary embodiment, the third trace 63 may be located in the middle region of the display area 100 in the first direction D1. The third trace 63 may be linearly shaped and extend along the second direction D2. A first end of the third trace 63 extends to one side edge of the display area 100 in the second direction D2, and a second end of the third trace 63 extends to the other side edge of the display area 100 in the second direction D2. The orthographic projections of the third trace 63 and the auxiliary trace 5 on the substrate do not overlap. The orthographic projections of the third trace 63 and the first trace 61 on the substrate do not overlap. The third trace 63 and the first trace 61 are staggered relative to each other in the second direction D2.

[0116] (3) Forming a third conductive layer. In an exemplary embodiment, forming the third conductive layer includes: on the substrate formed with the aforementioned pattern, first forming a first via 41, a second via 42, and a connecting via 501 in the second insulating layer, the first via 41 and the second via 42 both sequentially penetrating the second insulating layer and the first insulating layer along the thickness direction of the substrate, the first via 41 exposing the first end of the connecting signal line 3, the second via 42 exposing the second end of the connecting signal line 3, and the connecting via 501 penetrating the second insulating layer along the thickness direction of the substrate, exposing the second end of the connecting trace 52; subsequently, depositing a third conductive film on the second insulating layer, patterning the third conductive film through a patterning process, so that the third conductive film forms a third conductive layer, the third conductive layer including a data signal line 1 and a lead line 2, at least a portion of the data signal line 1 is connected to the first end of the connecting signal line 3 through the first via 41, at least a portion of the lead line 2 is connected to the second end of the connecting signal line 3 through the second via 42, and at least a portion of the data signal line 1 is connected to the second end of the connecting trace 52 through the connecting via 501, as shown in FIG. 6 .

[0117] FIG8 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, as shown in FIG8 , the structure of the display substrate according to the present disclosure is substantially the same as that of the display substrate shown in FIG6 , with the difference being that the auxiliary traces 5 of the display substrate according to the present disclosure are located in the edge region of at least one side of the display area 100 in the first direction D1, as well as in the middle region of the display area 100 in the first direction D1. The auxiliary traces 5 located in the edge region of the display area 100 are connected in parallel with the first data lines 11 located in the edge region of the display area 100; and the auxiliary traces 5 located in the middle region of the display area 100 are connected in parallel with the second data lines 12 located in the middle region of the display area 100.

[0118] In an exemplary embodiment, the length of the auxiliary traces 5 located in the edge region of the display area 100 in the second direction D2 is greater than the length of the auxiliary traces 5 located in the middle region of the display area 100 in the second direction D2. For example, adjacent auxiliary traces 5 have different lengths in the second direction D2, and the lengths of the auxiliary traces 5 in the second direction D2 decrease from the edge region of the display area 100 toward the middle region of the display area 100.

[0119] The present disclosure further provides a display device including the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, but the embodiments of the present invention are not limited thereto.

[0120] The present disclosure also provides a method for preparing a display substrate, comprising:

[0121] forming auxiliary wiring and signal wiring on a substrate, wherein the auxiliary wiring and at least a portion of the signal wiring are made of the same conductive film and are disconnected from each other;

[0122] Data signal lines are formed on a substrate, wherein the shape of the data signal lines includes a linear shape extending along a second direction, and a plurality of the data signal lines are arranged at intervals along a first direction. The data signal lines and the auxiliary lines are located in different film layers, and at least some of the data signal lines and the auxiliary lines are connected in parallel through connecting vias. The auxiliary lines do not overlap with the orthographic projections of the data signal lines and the signal lines on the substrate, and the first direction and the second direction intersect with each other.

[0123] In an exemplary embodiment, forming an auxiliary trace on a substrate includes:

[0124] Calculating the length of the auxiliary wiring according to the resistance of the auxiliary wiring connected in parallel with the data signal line;

[0125] The length of the auxiliary line is calculated based on the resistance of the auxiliary line connected in parallel with the data signal line, and includes:

[0126] The resistance R1 of the data signal line is calculated according to Formula 1: Resistance R1 of the data signal line = resistivity of the data signal line * length of the data signal line / cross-sectional area of ​​the data signal line;

[0127] According to formula 2: Rn = R1R2 / R1+R2, R2 is calculated, where Rn is the resistance of the auxiliary trace 5 in parallel with the data signal line 1, R1 is the resistance of the data signal line, and R2 is the resistance of the auxiliary trace;

[0128] The length of the auxiliary trace can be calculated according to Formula 3: Resistance R2 of the auxiliary trace = resistivity of the auxiliary trace * length of the auxiliary trace / cross-sectional area of ​​the auxiliary trace.

[0129] This application describes multiple embodiments, but this description is exemplary rather than restrictive, and it will be apparent to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described herein. Although many possible feature combinations are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0130] This application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features, and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive solution defined by the claims. Any features or elements of any embodiment may also be combined with features or elements from other inventive solutions to form another unique inventive solution defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this application may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the appended claims and their equivalents, the embodiments are not subject to other limitations. In addition, various modifications and changes may be made within the scope of protection of the appended claims.

[0131] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps in the specific order described. As will be understood by those skilled in the art, other orders of steps are also possible. Therefore, the specific order of the steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method and / or process should not be limited to performing their steps in the order written, and those skilled in the art can readily understand that these orders can be changed and still remain within the spirit and scope of the embodiments of the present application.

Claims

1. A display substrate, comprising a display area, the display area including data signal lines, auxiliary routing lines, and signal routing lines disposed on a substrate, the data signal lines being linearly shaped and extending along a second direction, a plurality of the data signal lines being spaced apart along a first direction, the data signal lines and the auxiliary routing lines being located in different film layers, at least some of the data signal lines being connected in parallel with the auxiliary routing lines via connecting vias, the auxiliary routing lines and at least some of the signal routing lines being located in the same film layer and being disconnected from each other, and the first direction and the second direction intersecting each other.

2. The display substrate according to claim 1, wherein The auxiliary wiring is arranged on a side of the data signal line close to the substrate, or the auxiliary wiring is arranged on a side of the data signal line away from the substrate.

3. The display substrate according to claim 1, wherein The auxiliary routing has the same extension direction as the data signal line, and the auxiliary routing is connected in parallel with the data signal line through a plurality of connecting routings. The shape of the connecting routing includes a line extending along the first direction. The first end of the connecting routing is connected to the auxiliary routing, and the second end of the connecting routing is connected to the data signal line through the connecting via.

4. The display substrate according to claim 3, wherein: The connecting wire and the auxiliary wire are connected as one body and comprise the same conductive material.

5. The display substrate according to claim 3, wherein: The auxiliary wiring is connected in parallel with the data signal line through at least two connecting wirings, and the shape formed by the combination of the auxiliary wiring and the two connecting wirings includes shape. The display substrate according to claim 1 , wherein: The auxiliary wiring is located in an edge region of at least one side of the display area in the first direction, and is connected in parallel with the data signal line located in the edge region of at least one side of the display area in the first direction.

7. The display substrate according to claim 1, wherein: The auxiliary wirings and at least a portion of the data signal lines are alternately arranged along the first direction.

8. The display substrate according to any one of claims 1 to 7, wherein: The signal routing includes a first routing, the first routing and the auxiliary routing are located in the same film layer, the shape of the first routing includes a line extending along the second direction, the first routing is located on at least one side of the auxiliary routing in the second direction, and is disconnected from the auxiliary routing.

9. The display substrate according to claim 8, wherein: The first routing line and the auxiliary routing line are located on the same straight line in the second direction.

10. The display substrate according to claim 8, wherein The signal routing also includes a second routing, the second routing and the first routing are located in a different film layer, the shape of the second routing includes a line extending along the first direction, the orthographic projections of the second routing and the auxiliary routing on the substrate do not overlap, and the second routing is connected to at least one of the first routings through a third via.

11. The display substrate according to claim 10, wherein: The signal routing also includes a third routing, the third routing and the second routing are located in a different film layer, the shape of the third routing includes a line extending along the second direction, the third routing does not overlap with the auxiliary routing and the orthographic projection of the first routing on the substrate, the first end of the third routing extends to the edge of the display area on one side in the second direction, the second end of the third routing extends to the edge of the display area on the other side in the second direction, and the third routing is connected to the second routing through a fourth via.

12. The display substrate according to claim 11, wherein: The third wiring is located in a middle area of the display area in the first direction.

13. The display substrate according to any one of claims 1 to 7, wherein: The signal traces include initial signal traces.

14. The display substrate according to any one of claims 1 to 7, wherein: It also includes a binding area located on one side of the display area in the second direction, the binding area includes lead lines arranged on the substrate, and the display area also includes connecting signal lines arranged on the substrate, the connecting signal lines are all located in different film layers from the lead lines and the data signal lines, the first end of the connecting signal line is connected to at least part of the data signal line through a first via hole, and the second end of the connecting signal line is connected to at least part of the lead line through a second via hole.

15. The display substrate according to claim 14, wherein: The shape of the connection signal line includes a line extending along the first direction; the shape of the lead line includes a line extending along the second direction.

16. The display substrate according to claim 14, wherein: The data signal line includes a first data line and a second data line, the first data line is located in the edge area on opposite sides of the display area in the first direction, the first data line is connected to the lead line through the connecting signal line, and the second data line is located in the middle area of the display area in the first direction, and the second data line is directly connected to the lead line.

17. The display substrate according to claim 16, wherein: The auxiliary wiring is connected in parallel with at least a portion of the first data lines.

18. The display substrate according to any one of claims 1 to 7, wherein: The auxiliary routing is located in an edge area of at least one side of the display area in the first direction, and in a middle area of the display area in the first direction. The length of the auxiliary routing located in the edge area of the display area in the second direction is greater than the length of the auxiliary routing located in the middle area of the display area in the second direction.

19. A display device comprising the display substrate according to any one of claims 1 to 18.

20. A method for preparing a display substrate, comprising: forming auxiliary wiring and signal wiring on a substrate, wherein the auxiliary wiring and at least a portion of the signal wiring are made of the same conductive film and are disconnected from each other; A data signal line is formed on a substrate, wherein the shape of the data signal line includes a line extending along a second direction, a plurality of the data signal lines are arranged at intervals along a first direction, the data signal line and the auxiliary wiring are located in different film layers, at least some of the data signal lines and the auxiliary wiring are connected in parallel through connecting vias, and the first direction and the second direction intersect with each other.

Images