LED backlight assembly capable of implementing black frame insertion of image at variable refresh rate, and control method

Abstract

Disclosed in the present invention are an LED backlight assembly capable of implementing black frame insertion of an image at a variable refresh rate, comprising: a plurality of backlight regions into which the LED backlight assembly is divided. When a display is performed at a first refresh rate, within a vertical synchronization signal Vsync period T at the first refresh rate, the corresponding LED current control period of each backlight region is divided into a first duration T1 and a second duration T2, T1+T2=T, the LED current within the first duration T1 being set to zero, and the LED current within the second duration T2 being set as a frame current ILed; when a liquid crystal panel performs a display at a second refresh rate, within a vertical synchronization signal Vsync period T' at the second refresh rate, the corresponding LED current control period of each backlight region is divided into a first duration T1, a second duration T2 and a third duration T3, T1+T2+T3=T', and the LED current within the third duration T3 being set as an average frame current Iavg.

Description

LED backlight assembly and control method for realizing image black insertion under variable refresh rate Technical Field

[0001] The present invention relates to the field of image display technology, and in particular to an LED backlight assembly and a control method suitable for realizing image black insertion under a variable refresh rate. Background Art

[0002] Every time a Liquid Crystal Display (LCD) refreshes an image, the liquid crystal molecules flip. High refresh rates can cause blurring and artifacts when playing fast-paced motion, negatively impacting the user experience. Traditional black frame insertion (BFI) involves inserting a black frame between two normal frames to mask the gray afterimage and eliminate artifacts, improving the viewing experience. However, this traditional black frame insertion method requires a fast LCD response time; otherwise, the inserted black frames are easily noticeable to the human eye, resulting in flicker.

[0003] Variable refresh rate (VRR) is a new technology for display panels that allows the refresh rate of the display panel to be adaptively changed based on the current processing speed of the video provider, such as the graphics processing unit (GPU). This avoids visual issues such as tearing and image retention when the GPU cannot output image frames in a timely manner. Variable refresh rate displays provide a better user experience, especially for gamers. The variable refresh rate signal makes the game picture quality higher and can reduce or eliminate problems such as image lag, freeze and frame tearing.

[0004] Based on the characteristics of the above-mentioned BFI technology and VRR technology, in the existing technology, it becomes difficult to obtain a good display effect by implementing black insertion technology under a variable refresh rate display panel. In the synchronous backlight control scheme, the backlight control signal is synchronized with the vertical synchronization signal (Vsync, the vertical synchronization signal is a pulse signal added between two frames, which indicates the end of the previous frame and the beginning of the new frame, that is, the frequency of the vertical synchronization signal is consistent with the picture refresh rate) of the input image; therefore, since the length of the frame period (that is, the period of the vertical synchronization signal Vsync) is variable, performing BFI in different frame periods will make the backlight partition current of the backlight control signal inconsistent, and the continuously changing backlight partition current will produce backlight flicker, which will make the user feel that the image is flickering. Therefore, implementing black insertion technology under a variable refresh rate will not only cause a decrease in brightness caused by the black insertion technology itself, but it is also easy to cause backlight flicker.

[0005] It can be seen from this that a new LED backlight control technology is needed in the existing technology, so that the black insertion technology can be implemented simultaneously under a variable refresh rate and a better display effect can be obtained, that is, the image can be kept at a high brightness while avoiding backlight flickering. Summary of the Invention

[0006] The technical purpose to be achieved by the present invention is to provide an LED backlight component and a control method suitable for realizing image black insertion under variable refresh rate. Based on the LED backlight component and the backlight control method, it is possible to simultaneously implement black insertion technology under variable refresh rate and obtain better display effect, that is, it is possible to maintain a high brightness of the image while avoiding backlight flicker.

[0007] Based on the above technical objectives, the present invention provides an LED backlight assembly suitable for implementing image black insertion under a variable refresh rate, the LED backlight assembly comprising:

[0008] The LED backlight assembly is divided into a plurality of backlight partitions, each of which corresponds to a pixel partition of the liquid crystal panel, and each of the pixel partitions contains a plurality of rows of liquid crystal pixels;

[0009] When the liquid crystal panel displays at a first refresh rate, the LED current control period of each backlight partition corresponding to the vertical synchronization signal Vsync period T at the first refresh rate is divided into a first duration T1 and a second duration T2, and T1+T2=T; the LED current in the first duration T1 is set to zero, and the LED current in the second duration T2 is set to the frame current I Led ;

[0010] When the liquid crystal panel displays at the second refresh rate, the LED current control period of each backlight partition corresponding to the vertical synchronization signal Vsync period T' at the second refresh rate is divided into a first duration T1, a second duration T2 and a third duration T3; and T1+T2+T3=T';

[0011] The LED current in the third time period T3 is set to the frame average current I avg , and there is:

[0012] The first refresh rate is greater than the second refresh rate.

[0013] In one embodiment, the liquid crystal pixels within the pixel partition are identical.

[0014] In one embodiment, the first refresh rate is a highest refresh rate in a variable refresh rate setting.

[0015] In one embodiment, the second duration T2 or the third duration T3 is discontinuous within a vertical synchronization signal period.

[0016] In one embodiment, when the liquid crystal panel displays at a third refresh rate, the vertical synchronization signal Vsync period T" at the third refresh rate is divided into a plurality of identical vertical synchronization signal Vsync sub-periods T" sub , in each vertical synchronization signal Vsync sub-cycle T" sub The LED current control period of each corresponding backlight partition is divided into a first duration T1, a second duration T2 and a third duration T3. And T1+T2+T3=T" sub .

[0017] In one embodiment, the first duration T1 , the second duration T2 and the third duration T3 are not arranged in a fixed order within a vertical synchronization signal period at the second refresh rate or the third refresh rate.

[0018] The present invention also provides another LED backlight control method suitable for implementing image black insertion under a variable refresh rate, the LED backlight control method comprising:

[0019] Dividing the LED backlight assembly into a plurality of backlight partitions, each backlight partition corresponds to a pixel partition of the liquid crystal panel, and each pixel partition contains a plurality of rows of liquid crystal pixels;

[0020] When the liquid crystal panel displays at a first refresh rate, the LED current control period of each backlight partition corresponding to the vertical synchronization signal Vsync period T at the first refresh rate is divided into a first duration T1 and a second duration T2, and T1+T2=T; the LED current in the first duration T1 is set to zero, and the LED current in the second duration T2 is set to the frame current I Led ;

[0021] When the liquid crystal panel displays at the second refresh rate, the LED current control period of each backlight partition corresponding to the vertical synchronization signal Vsync period T' at the second refresh rate is divided into a first duration T1, a second duration T2 and a third duration T3; and T1+T2+T3=T';

[0022] The LED current in the third time period T3 is set to the frame average current I avg , and there is:

[0023] The first refresh rate is greater than the second refresh rate.

[0024] In one embodiment, the first refresh rate is a highest refresh rate in a variable refresh rate setting.

[0025] In one embodiment, when the liquid crystal panel displays at a third refresh rate, the vertical synchronization signal Vsync period T" at the third refresh rate is divided into a plurality of identical vertical synchronization signal Vsync sub-periods T" sub , in each vertical synchronization signal Vsync sub-cycle T" sub The LED current control period of each corresponding backlight partition is divided into a first duration T1, a second duration T2 and a third duration T3. And T1+T2+T3=T" sub .

[0026] Compared with the prior art, one or more embodiments of the present invention may have the following advantages:

[0027] The present invention implements a black insertion technology under a variable refresh rate state by controlling the LED current in different time periods within the vertical synchronization signal cycle, while ensuring stable brightness of the displayed image and no backlight flicker.

[0028] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The purposes and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0030] FIG1 is a schematic diagram of the LED backlight partition structure of the present invention;

[0031] FIG2 is a schematic diagram showing the correspondence between LED backlight partitions and liquid crystal pixel partitions according to the present invention;

[0032] 3 is a timing diagram of the LED backlight partition control method at the first refresh rate in the first embodiment of the present invention;

[0033] 4 is a timing diagram of the LED backlight partition control method at the second refresh rate in the first embodiment of the present invention;

[0034] 5 is a timing diagram of the LED backlight partition control method at a third refresh rate in the second embodiment of the present invention;

[0035] FIG6 is a timing diagram of the LED backlight partition control method at the second refresh rate in the third embodiment of the present invention. DETAILED DESCRIPTION

[0036] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention is further described in detail below with reference to the accompanying drawings.

[0037] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there can be no intervening elements or layers. It should be understood that while the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another. Thus, without departing from the teachings of the present invention, a first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. Furthermore, when a second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part is present in the present invention.

[0038] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0039] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present invention. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0040] Example 1

[0041] As shown in Figure 1, the LED backlight assembly of the present invention is divided into n rows of backlight partitions, synchronized with the refresh direction of the display panel image signal. From top to bottom, the backlight partitions are row 1, row 2, and finally row n. The value of n is determined based on the requirements of the LED backlight control. A higher n indicates more backlight partitions, more precise LED backlight control, and higher assembly cost.

[0042] As shown in Figure 2, the LED backlight assembly of the present invention is arranged below the liquid crystal panel, and each backlight partition corresponds to a pixel partition of the liquid crystal panel. The pixel partition contains multiple rows of liquid crystal pixels. For example, the pixel resolution of the liquid crystal panel is 2560×1440, that is, 2K resolution, and the number of backlight partitions is n=40 rows, then the number of liquid crystal pixel rows corresponding to each backlight partition is 1440 / 40=36, that is, the first row of backlight partitions corresponds to the first 36 rows of liquid crystal pixels, the second row of backlight partitions corresponds to the second 36 rows of liquid crystal pixels, and so on.

[0043] Based on the characteristics of the LCD panel, under the LCD partitioning scheme of this embodiment, when displaying a frame of an image, all rows of LCD pixels in each pixel partition undergo LCD flipping, and the time required for this flipping is the same. Specifically, if the time from the start of flipping of the first row of LCD pixels in a pixel partition to the completion of flipping of the last row of LCD pixels in that pixel partition is t, and if we continue to use the aforementioned 2K resolution and 40 backlight partitions as an example, the time from the start of flipping of the first row of LCD pixels in a pixel partition to the completion of flipping of the 36th row of LCD pixels in that pixel partition is t, then in this embodiment, the value of t is the same for all backlight partitions.

[0044] This embodiment aims to achieve both variable refresh and image black insertion while maintaining image brightness and preventing image flicker. The technical problem to be solved is how to control the backlight LEDs to perform black insertion within the aforementioned time duration t. This technical objective has not been achieved, so this embodiment provides the following LED backlight control method.

[0045] As shown in Figure 3, when the display panel operates at the first refresh rate, the period of the vertical synchronization signal Vsync is T. In this embodiment, the first refresh rate is the highest refresh rate among the variable refresh rates of the display panel. For example, the variable refresh rate settings of the display panel include multiple options such as 180Hz, 165Hz, 144Hz, 120Hz, 75Hz, and 60Hz. In this embodiment, the first refresh rate is 180Hz. Accordingly, the period of the vertical synchronization signal Vsync at the first refresh rate is T, which is also the minimum value among the multiple refresh rates.

[0046] In this embodiment, the LED current control period of each backlight partition corresponding to the vertical synchronization signal Vsync period T under the first refresh rate is divided into a first duration T1 and a second duration T2, and the first duration T1 + the second duration T2 = the vertical synchronization signal Vsync period T. The LED current of the first duration T1 is zero, and the LED current of the second duration T2 is the frame current I Led For all backlight subareas, their first duration T1 and second duration T2 are fixed and the same. The first duration T1 is the time from the moment the first row of liquid crystal pixels in the pixel subarea corresponding to the backlight subarea begins to flip to the moment the last row of liquid crystal pixels in the backlight subarea completes flipping. Within the vertical synchronization signal Vsync period T, the time period other than the first duration T1 is the second duration T2.

[0047] It can be seen from the above technical means that in this embodiment, at the first refresh rate (highest refresh rate), when the multiple rows of liquid crystal pixels in the pixel partition corresponding to each backlight partition are in the liquid crystal molecule flipping state, the backlight LED current is zero, that is, the screen is blacked out.

[0048] In this embodiment, the first time length T1 may not strictly correspond to the time from the moment when the first row of liquid crystal pixels in the pixel partition corresponding to the backlight partition starts to flip to the moment when the last row of liquid crystal pixels in the backlight partition completes flipping according to actual conditions, that is, the first time length T1 can be selected to be set at the moment when the flipping of the pixels in the liquid crystal partition is most intense according to actual conditions, that is, it is less than the time length t. The first time length T1 may also exceed the time length t, that is, the black insertion time is longer than the liquid crystal flipping time.

[0049] In this embodiment, the first duration T1 may be greater than the second duration T2, and may be equal to or less than the second duration T2. ​​That is, the time relationship between the first duration T1 and the second duration T2 is mainly constrained by the following: first duration T1 + second duration T2 = vertical synchronization signal Vsync period T. When the first duration T1 is determined according to circumstances, the second duration T2 is also determined.

[0050] After the liquid crystal molecules are flipped, the backlight LED is turned on to display the picture. At this time, the input current of the backlight LED is the frame current I determined by the display data of the frame. Led .

[0051] The second duration T2 may be divided into a plurality of discontinuous duration segments, that is, may be distributed on both sides of the first duration T1 within the period T of the vertical synchronization signal Vsync.

[0052] It should be noted that at the first refresh rate, the nth pixel partition's flipping cutoff time does not necessarily coincide with the arrival of the next frame's Vsync; at higher refresh rates, the nth pixel partition's cutoff time may exceed the next frame's Vsync. Understandably, when continuously outputting images, there is a delay between the Vsync signal and the actual image output.

[0053] As shown in FIG4 , in this embodiment, the LED current control period of each backlight sub-zone corresponding to the vertical synchronization signal Vsync period T' at the second refresh rate (not the highest refresh rate) is divided into a first duration T1, a second duration T2, and a third duration T3. Furthermore, the first duration T1 + the second duration T2 + the third duration T3 = the vertical synchronization signal Vsync period T'.

[0054] The first time length T1 at the second refresh rate is the first time length T1 determined at the first refresh rate, and the first time length T1 is from the moment when the first row of liquid crystal pixels in the pixel partition corresponding to the backlight partition starts to flip to the moment when the last row of liquid crystal pixels in the backlight partition completes flipping.

[0055] The second duration T2 at the second refresh rate is the same as the second duration T2 determined at the first refresh rate. Similarly, within the vertical synchronization signal Vsync period T' at the second refresh rate, the time periods other than the first duration T1 and the second duration T2 are all third duration T3. The third duration T3 can be discontinuous, i.e., can be located on both sides of the vertical synchronization signal Vsync period T'.

[0056] Similarly, in the vertical synchronization signal Vsync period T' at the second refresh rate, the LED current of the first duration T1 is zero, and the LED current of the second duration T2 is the frame current I Led The LED current of the third duration T3 is the frame average current I avg , and there is:

[0057] In this embodiment, the first duration T1 and the second duration T2 determined at the first refresh rate are retained in the second refresh rate, thereby ensuring that the impact of the black screen on the brightness is consistent. At the same time, the LED current of the third duration T3 is the frame average current I avg , the average current of this frame I avg The average current of the frame within the period T of the vertical synchronization signal Vsync of the first refresh rate is consistent, thereby ensuring the consistency of the brightness of the picture at different refresh rates, thereby eliminating the backlight flicker phenomenon.

[0058] Example 2

[0059] In this embodiment, based on the aforementioned embodiment 1, a backlight LED current control strategy at a third refresh rate is added, as shown in FIG5 . The third refresh rate is also a non-highest refresh rate among the variable refresh rates.

[0060] The vertical synchronization signal Vsync period T" at the third refresh rate is divided into a plurality of identical vertical synchronization signal Vsync sub-periods T" sub , in each vertical synchronization signal Vsync sub-cycle T" sub The LED current control period of each corresponding backlight partition is divided into a first duration T1, a second duration T2 and a third duration T3. And the first duration T1 + the second duration T2 + the third duration T3 = the vertical synchronization signal Vsync sub-period T" sub The third duration T3 may be zero.

[0061] The first time length T1 under the third refresh rate is the first time length T1 determined under the first refresh rate, and the first time length T1 is from the moment when the first row of liquid crystal pixels in the pixel partition corresponding to the backlight partition starts to flip to the moment when the last row of liquid crystal pixels in the backlight partition completes flipping.

[0062] The second duration T2 at the third refresh rate is the second duration T2 determined at the first refresh rate. Similarly, the vertical synchronization signal Vsync sub-period T" at the third refresh rate sub Within the time period, except for the first time period T1 and the second time period T2, all time periods are the third time period T3.

[0063] Similarly, the vertical synchronization signal Vsync sub-period T" at the third refresh rate sub In the first time period T1, the LED current is zero, and the second time period T2, the LED current is the frame current I Led The LED current of the third duration T3 is the frame average current I avg , and there is:

[0064] In this embodiment, for a lower refresh rate (for example, below 70 Hz), backlight LED current control can be achieved by frequency doubling.

[0065] Example 3

[0066] In this embodiment, based on Embodiment 1, the LED current control period of each backlight sub-zone corresponding to the vertical synchronization signal Vsync period T' at the second refresh rate is divided into a first duration T1, a second duration T2, and a third duration T3. Furthermore, the first duration T1 + the second duration T2 + the third duration T3 = the vertical synchronization signal Vsync period T'.

[0067] Furthermore, the distribution of the first duration T1, the second duration T2, and the third duration T3 within the vertical synchronization signal Vsync period T' at the second refresh rate can be adjusted. For example, as shown in FIG6 , within the vertical synchronization signal Vsync period T' at the second refresh rate, the liquid crystal flipping period corresponds to the first duration T1, followed by the output of the third duration T3, and finally the output of the second duration T2. ​​The technical effects of this embodiment are the same as those of Example 1.

[0068] In this embodiment, the first duration T1 may not correspond to the liquid crystal flip period, and the first duration T1, the second duration T2, and the third duration T3 may be distributed in any manner within the vertical synchronization signal Vsync period T' at the second refresh rate. When the first duration T1 does not correspond to the liquid crystal flip period, the black insertion effect is degraded, but backlight flicker can still be eliminated.

[0069] The present invention may be a system, method and / or computer program product at any possible level of integrated technical detail. The computer program product may include a computer-readable storage medium (or multiple media) having computer-readable program instructions thereon for causing a processor to perform various aspects of the present invention.

[0070] A computer-readable storage medium can be a tangible device that can retain and store instructions used by an instruction execution device. The computer-readable storage medium can be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: a portable computer floppy disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanical encoding device such as a punch card or raised structure in grooves having instructions recorded thereon, and any suitable combination of the foregoing. A computer-readable storage medium, as used herein, should not be construed as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted by a wire.

[0071] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in a computer-readable storage medium within the corresponding computing / processing device.

[0072] The computer-readable program instructions for performing the operation of the present invention can be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for integrated circuits, or source code or object code written in any combination of one or more programming languages ​​and procedural programming languages. The computer-readable program instructions can be executed entirely on the user's computer, partly on the user's computer, as an independent software package, partly on the user's computer, partly on a remote computer or entirely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer by any type of network including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (for example, by using the Internet of an Internet service provider). In certain embodiments, the electronic circuit including, for example, a programmable logic circuit, a field programmable gate array (FPGA) or a programmable logic array (PLA) can execute the computer-readable program instructions by utilizing the state information of the computer-readable program instructions to personalize the electronic circuit, thereby performing various aspects of the present invention.

[0073] Various aspects of the present invention are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0074] These computer-readable program instructions may be provided to a processor of a computer, or other programmable data processing device, to produce a machine, such that the instructions, executed via the processor of the computer or other programmable data processing device, create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium capable of directing a computer, a programmable data processing device, and / or other device to operate in a specific manner, such that the computer-readable storage medium having the instructions stored therein comprises an article of manufacture that includes the instructions for implementing aspects of the functions / actions specified in the flowchart and / or block diagram blocks.

[0075] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other apparatus to cause a series of operational steps to be performed on the computer, other programmable device, or other apparatus for producing a computer-implemented process, such that the instructions executed on the computer, other programmable device, or other apparatus implement the functions / actions specified in the flowchart and / or block diagram blocks.

[0076] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of instructions, which includes one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions indicated in the blocks may occur out of the order indicated in the diagrams. For example, two blocks shown in succession may, in practice, be completed as a single step, executed concurrently, substantially concurrently, with partial or full temporal overlap, or the blocks may sometimes be executed in reverse order, depending on the functions involved. It will also be noted that each block of the block diagram and / or flowchart illustration, as well as combinations of blocks in the block diagram and / or flowchart illustration, may be implemented by a dedicated hardware-based system that performs the specified functions or actions or executes a combination of dedicated hardware and computer instructions.

[0077] The present application embodiment is described with reference to the flow chart and / or block diagram of the method, apparatus (equipment) and computer program product according to the embodiment of the present application. It should be understood that each process and / or box in the flow chart and / or block diagram and the combination of the process and / or box in the flow chart and / or block diagram can be realized by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processing machine or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for realizing the function specified in one process or multiple processes and / or one box or multiple boxes of the flow chart.

[0078] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0079] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0080] The above description is only a specific implementation case of the present invention, and the protection scope of the present invention is not limited thereto. Any modification or replacement of the present invention by any technician familiar with this technology within the technical specifications described in the present invention should be within the protection scope of the present invention.

Claims

1. An LED backlight assembly suitable for implementing image black insertion under variable refresh rate, characterized in that: The LED backlight assembly includes: The LED backlight assembly is divided into a plurality of backlight partitions, each of which corresponds to a pixel partition of the liquid crystal panel, and each of the pixel partitions contains a plurality of rows of liquid crystal pixels; When the liquid crystal panel displays at a first refresh rate, the LED current control period of each backlight partition corresponding to the vertical synchronization signal Vsync period T at the first refresh rate is divided into a first duration T1 and a second duration T2, and T1+T2=T; the LED current in the first duration T1 is set to zero, and the LED current in the second duration T2 is set to the frame current I Led ; When the liquid crystal panel displays at the second refresh rate, the LED current control period of each backlight partition corresponding to the vertical synchronization signal Vsync period T' at the second refresh rate is divided into a first duration T1, a second duration T2 and a third duration T3; and T1+T2+T3=T'; The LED current in the third time period T3 is set to the frame average current I avg , and there is: The first refresh rate is greater than the second refresh rate.

2. The LED backlight assembly according to claim 1, wherein: The liquid crystal pixels within the pixel subarea are identical.

3. The LED backlight assembly according to claim 1, wherein: The first refresh rate is the highest refresh rate in the variable refresh rate setting.

4. The LED backlight assembly according to claim 1, wherein: The second duration T2 or the third duration T3 is discontinuous within a vertical synchronization signal period.

5. The LED backlight assembly according to claim 1, wherein: When the liquid crystal panel displays at the third refresh rate, the vertical synchronization signal Vsync period T" at the third refresh rate is divided into a plurality of identical vertical synchronization signal Vsync sub-periods T" sub , in each vertical synchronization signal Vsync sub-cycle T" sub The LED current control period of each corresponding backlight partition is divided into a first duration T1, a second duration T2 and a third duration T3. And T1+T2+T3=T" sub .

6. The LED backlight assembly according to claim 5, wherein: The first duration T1, the second duration T2 and the third duration T3 are not arranged in a fixed order within a vertical synchronization signal period at the second refresh rate or the third refresh rate.

7. A method for controlling LED backlights to achieve black insertion in a variable refresh rate environment, characterized in that: The LED backlight control method includes: Dividing the LED backlight assembly into a plurality of backlight partitions, each backlight partition corresponds to a pixel partition of the liquid crystal panel, and each pixel partition contains a plurality of rows of liquid crystal pixels; When the liquid crystal panel displays at a first refresh rate, the LED current control period of each backlight partition corresponding to the vertical synchronization signal Vsync period T at the first refresh rate is divided into a first duration T1 and a second duration T2, and T1+T2=T; the LED current in the first duration T1 is set to zero, and the LED current in the second duration T2 is set to the frame current I Led ; When the liquid crystal panel displays at the second refresh rate, the LED current control period of each backlight partition corresponding to the vertical synchronization signal Vsync period T' at the second refresh rate is divided into a first duration T1, a second duration T2 and a third duration T3; and T1+T2+T3=T'; The LED current in the third time period T3 is set to the frame average current I avg , and there is: The first refresh rate is greater than the second refresh rate.

8. The LED control method according to claim 7, wherein: The first refresh rate is the highest refresh rate in the variable refresh rate setting.

9. The LED control method according to claim 7, wherein: When the liquid crystal panel displays at the third refresh rate, the vertical synchronization signal Vsync period T" at the third refresh rate is divided into a plurality of identical vertical synchronization signal Vsync sub-periods T" sub , in each vertical synchronization signal Vsync sub-cycle T" sub The LED current control period of each corresponding backlight partition is divided into a first duration T1, a second duration T2 and a third duration T3. And T1+T2+T3=T" sub .

10. A display panel, characterized in that: The display panel includes the LED backlight assembly according to any one of claims 1 to 6, or the display panel uses the LED backlight control method according to any one of claims 7 to 9.

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