An SRAM device with a reduced access time

Abstract

The present disclosure relates to a SRAM device. The SRAM device comprises memory cells, bit line pairs, and word lines. Each memory cell is connected to one of the bit line pairs, and each word line is connected to a subset of the memory cells. The SRAM device also comprises sense amplifiers, wherein each bit line pair is connected to one of the sense amplifiers. The SRAM device may comprise and OR-gate and / or a multiplexer latch. The OR-gate is connected to the word lines being a plurality of inputs. An output of the OR-gate is configured to trigger an activation of the plurality of sense amplifiers. A plurality of address lines is connected as inputs to the multiplexer latch. The multiplexer latch is configured to select one of the addresses and to latch the selected address.

Description

[0001] AN SRAM DEVICE WITH A REDUCED ACCESS TIME

[0002] TECHNICAL FIELD

[0003] The present disclosure relates to a static random access memory (SRAM) device. In particular, the disclosure is concerned with the access time and setup time of the SRAM device, and with clock inaccuracy margins associated therewith. The disclosure proposes an SRAM device in which these issues are addressed.

[0004] BACKGROUND

[0005] The setup time of an address to an SRAM array is part of the access time. The access time is the total time required from the moment a specific location in the memory array is addressed to the moment the stored data is available (e.g., until the data is read or successfully written). The address setup time refers to the time interval during which the address of the specific location to be read from or written to must be held available. In a conventional SRAM device, an address latch is used to sample an input address when the clock rises, and the setup time is set such that the address switches at the same time (no later) than the clock at an x-decoder. An x-decoder is a circuit used to select a specific word line within the memory array. It decodes the address and activates (also referred to as “asserts”) the appropriate word in the memory array.

[0006] An example of a memory array of a conventional SRAM device 100 is shown in FIG. 1. The SRAM array includes memory cells 109 - typically six transistors (6T) per memory cell - which are connected to word lines 110 (e.g., rows) and bit line pairs 111 (e.g. columns). The bit line pairs 111 are further connected to sense amplifiers 112, and the word lines 111 are further connected to the x-decoders 107 (also referred to as row or line decoders).

[0007] The above-mentioned address latch 102 is configured to receive an address on a plurality of input lines 101. Notably, a multiplexer, which is placed outside of the array and is thus not shown in FIG. 1 , may have pre-selected the address from multiple addresses. A pre-decoder 104 is further arranged between the address latch 102 and the x-decoders 107, and is connected by data lines 103 to the address latch 102.

[0008] The SRAM array is further provided with an (external) clock 115, which is converted into an internal clock 106 used to clock the address latch 102, the x-decoders 107 and a timer circuit 108 of the SRAM. The timer circuit 108 is configured to trigger a pulse of a sense amp strobe signal 114 (referred to as “sene Ik”), which is used to activate the sense amplifiers 112 and produce an output 113.

[0009] According to an exemplary operation, the address provided to and latched by the address latch 102, and is pre-decoded by the pre-decoder 104. One, and only one-word line 110 (so-called “one-hot word line”) is asserted. The bit line pairs 111 are precharged high. The asserted word line 110 drives a subset of the memory cells 109 (e.g. a row) to discharge one-bit line of each bit line pair 111, and the sense amplifiers 112 are configured to determine and drive the output 113. The timer circuit 108 is configured to determine the required time for the bit line signal (difference between the bit lines of the pair 111 ) to develop sufficiently, and then triggers sene Ik 114, in order to capture the output 113.

[0010] In particular, as shown in the timing-diagram of FIG. 2, the timer 108 is configured to set the required delay from the time t4at which the word line rises to the time t5at which the correct bit line difference is established. At t5accordingly also senclk rises. It is triggered off the time t3at which the address is pre-coded and the internal clock rises, and has an internal delay of G ’ - It is assumed for the operation of the conventional SRAM that the pre-decoded address arrives in time at the time t3, such that the timing of the rising word line 310 is determined by the clock signal. However, due to clock and address timing uncertainties, a margin has to be added to the setup time. The margin ensures that the address is valid even if it arrives late or if the clock is early. Unfortunately, this margin increases the setup time and the access time.

[0011] SUMMARY

[0012] In view of the above, this disclosure aims to reduce the access time. An objective, in order to achieve this, is to minimize the setup time, and to reduce a clock inaccuracy margin typically associated with the setup time.

[0013] These and other objectives are achieved by the solutions of this disclosure described in the independent claims. Advantageous implementations are further described in the dependent claims.

[0014] A first aspect of this disclosure provides an SRAM device comprising: a plurality of SRAM memory cells; a plurality of bit line pairs, wherein each of the plurality of the memory cells is connected to one pair of bit lines of the plurality of bit line pairs; a plurality of word lines, wherein each of the word lines is connected to a subset of the plurality of memory cells; and a plurality of sense amplifiers, wherein each pair of the plurality of bit line pairs is connected to one of the plurality of sense amplifiers; and an OR-gate, wherein the plurality of word lines is connected as a plurality of inputs to the OR-gate, and an output of the OR-gate is configured to trigger an activation of the plurality of sense amplifiers.

[0015] The memory cells are each configured to store one bit of information (data). For example, each memory cell may comprise six transistors, wherein four of the transistors are used for storing the data, and two transistors are used as access transistors. The four storage transistors may form a pair of cross-coupled inverters. The plurality of SRAM memory cells may be arranged in an array, wherein the memory array also comprises the word lines and the bit lines. In the memory array, the memory cells may be arranged in rows, e.g., each row being associated with one-word line, and in columns, e.g., each column being associated with one pair of bit lines. In particular, the memory cells and array may be laid out as in a conventional SRAM (device).

[0016] The OR-gate is used to detect the word line assertion. Generally, an OR-gate is a fundamental digital logic gate that outputs a high signal (“1”) if any of its inputs are high (“1). If all inputs are low (“0”), then it outputs a low signal (“0”). In this case, the inputs are the word line signals. The sense amplifiers are triggered by a controlled delay of the OR detection of the OR-gate, i.e., they are triggered by the rise of any word line. Thus, they are not necessarily triggered by a clock signal. This reduces the need for timing margins, and also allows an address, which corresponds to a word line to be activated, to arrive a little later. As a consequence, the setup time and the access time can be both reduced.

[0017] In an implementation of the first aspect, the OR-gate is configured to provide an output signal based on a plurality of input signals on the plurality of word lines, wherein a high output signal of the OR-gate is configured to trigger the activation of the plurality of sense amplifiers.

[0018] The high output signal refers to a “true” or logical “1” of the OR-gate, compared to a “false” or logical “0” of the OR-gate. The high output signal is typically a higher voltage than a low output signal.

[0019] In an implementation of the first aspect, a change from a low signal to a high signal on any one-word line of the plurality of word lines results in the high output signal of the OR-gate.

[0020] Low signal and high signal on a word line also related to “true’Tlogical “1” and “false’Tlogical “0”. In an implementation of the first aspect, the high output signal of the OR-gate is configured to trigger the generation of a sene Ik.

[0021] The signal referred to as senclk may be a used in a conventional SRAM device and triggers / activates the sense amplifiers, for example, to convert the voltage difference between bit lines of a bit line pair to an output that represents the stored data.

[0022] In an implementation of the first aspect, the SRAM device further comprises a timer, wherein the output signal of the OR-gate is input to the timer, and wherein the timer is configured to initiate the generation of the senclk based on the output signal of the OR-gate.

[0023] In an implementation of the first aspect, the OR-gate is based on domino technology.

[0024] An OR-gate using domino technology is a high-speed digital circuit. It pre-charges the output to a high state and conditionally discharges it if any input is high. This design based on domino technology enhances the speed and may reduce the power consumption.

[0025] In an implementation of the first aspect, the SRAM device further comprises: a plurality of address lines configured to receive a plurality of addresses, wherein each of the addresses identifies one of the plurality of word lines; and a multiplexer latch, wherein the plurality of address lines is connected as a plurality of inputs to the multiplexer latch, and the multiplexer latch is configured to select one of the addresses and to latch the selected address.

[0026] A second aspect of this disclosure provides a SRAM device comprising: a plurality of SRAM memory cells; a plurality of bit line pairs, wherein each of the memory cells is connected to one pair of the plurality of bit line pairs; a plurality of word lines, wherein each of the word lines is connected to a subset of the plurality of memory cells; a plurality of address lines configured to receive a plurality of addresses, wherein each of the addresses identifies one of the plurality of word lines; and a multiplexer latch, wherein the plurality of address lines is connected as a plurality of inputs to the multiplexer latch, and the multiplexer latch is configured to select one of the addresses and to latch the selected address.

[0027] The multiplexer latch introduces hardly any additional delay on the address path, however, using it eliminates the need for a separate multiplexer on the address path. This improves the delay of the critical address path. The multiplexer latch may replace an address input latch of a conventional SRAM device (typically arranged in the memory array). Modifying such a conventional input latch to become the multiplexer latch is a simple step, but reduces significantly the access time. The multiplexer latch of the SRAM device of the second aspect mergers the functionality of elements located inside (the address latch) and outside (the multiplexer) of the memory array of a conventional SRAM device.

[0028] In an implementation form of the second aspect, the memory cells, the bit lines, and the word lines are part of a memory array of the SRAM device, and the memory array also comprises the multiplexer latch.

[0029] The multiplexer latch in the memory array is - in contrast to the multiplexer arranged on the address path of the conventional SRAM device - outside the memory array. This conventional multiplexer can be omitted because of the twofold functionality of the multiplexer latch.

[0030] In an implementation form of the second aspect, the multiplexer latch comprises a first set of pass gates configured to select the one of the addresses, and a second set of pass gates configured to latch the selected address. In an implementation form of the second aspect, the SRAM device further comprises: a plurality of sense amplifiers, wherein each pair of the plurality of bit line pairs is connected to one of the plurality of sense amplifiers; and an OR-gate, wherein the plurality of word lines is connected as a plurality of inputs to the OR-gate, and an output of the OR-gate is configured to trigger an activation of the plurality of sense amplifiers.

[0031] The advantages of the OR-gate are as described above for the SRAM device of the first aspect, and can be combined with the advantages of the multiplexer latch described for the SRAM device of the second aspect (and vice versa).

[0032] In summary of the above aspects and implementations forms, the access time of the SRAM device can be significantly reduced by (1) eliminating the multiplexer from the address path and / or by (2) detecting the word line assertion by the OR-gate, thus allowing a minimum setup time.

[0033] It has to be noted that some entities, elements, units and means described in the present application could be implemented by hardware elements or any kind of combination thereof. Steps performed by such entities, as well as some functionalities described to be performed by the various entities, are intended to mean that the respective entity is adapted to or configured to perform the respective steps and functionalities. Even if, in the following description of specific embodiments, a specific functionality or step to be performed by external entities is not reflected in the description of a specific detailed element of that entity, which performs that specific step or functionality, it should be clear for a skilled person that these methods and functionalities can be implemented by respective hardware elements, or any kind of combination thereof.

[0034] BRIEF DESCRIPTION OF DRAWINGS

[0035] The above described aspects and implementation forms are explained in the following description in relation to the enclosed drawings, in which:

[0036] FIG. 1 shows an example of a memory array of a conventional SRAM device.

[0037] FIG. 2 shows a timing diagram of signals in the conventional SRAM device.

[0038] FIG. 3 shows an implementation of an OR-gate in an SRAM device according to this disclosure.

[0039] FIG. 4 shows an implementation of a multiplexer latch in an SRAM device according to this disclosure.

[0040] FIG. 5 shows an example of an SRAM device according to this disclosure, which includes the OR-gate and the multiplexer latch.

[0041] FIG. 6 shows an exemplary implementation of the multiplexer latch.

[0042] FIG. 7 shows a timing diagram of signals in the SRAM device according to this disclosure.

[0043] DETAILED DESCRIPTION OF EMBODIMENTS

[0044] FIG. 1 shows a SRAM device 300 according to this disclosure. The SRAM device 300 may be to a large part designed like a conventional SRAM (device). The SRAM device 300 comprises a plurality of SRAM memory cells 309, a plurality of bit line pairs 311, and a plurality of word lines 310. These may be configured and implemented like in a conventional SRAM device. The plurality of the memory cells 309 - e.g., 6T memory cells each - are each connected to one pair of bit lines of the plurality of bit line pairs 311. Further, each of the word lines 310 is connected to a subset of the plurality of memory cells 309, e.g., a row of memory cells 309 in the memory array. Like a conventional SRAM device, the SRAM device 300 also includes a plurality of sense amplifiers 312. Each pair of the plurality of bit line pairs 311 is connected to one of the plurality of sense amplifiers 312. This disclosure focuses on the differences between the conventional SRAM device and the SRAM devices of this disclosure.

[0045] In contrast to a conventional SRAM device, the SRAM device 300 of this disclosure includes an OR-gate 316 in the memory array. The plurality of word lines 310 is connected as a plurality of inputs to the OR-gate 316. An output of the OR-gate 316 is configured to trigger an activation of the plurality of sense amplifiers 312 (explained in more exemplary detail later). In particular, the OR-gate 316 is configured to provide an output signal, which is based on a plurality of input signals on the plurality of word lines 310. A high output signal of the OR-gate 316 may trigger the activation of the plurality of sense amplifiers 312, in particular, it may trigger the generation of a pulse of the above-described signal sene Ik, which is used to strobe the sense amplifiers 312. The high output signal of the OR-gate may be produced, when a signal on any one of the plurality of word lines 310 connected to the OR-gate 316 changes from a low signal to a high signal.

[0046] FIG. 4 shows an SRAM device 400 according to this disclosure. The SRAM device 400 may be to a large part designed like a conventional SRAM (device). The SRAM device 400 comprises a plurality of SRAM memory cells 309, a plurality of bit line pairs 311, and a plurality of word lines 310. These may be configured and implemented like in the conventional SRAM device. The plurality of the memory cells 309 - e.g., 6T memory cells each - are each connected to one pair of bit lines of the plurality of bit line pairs 311. Further, each of the word lines 310 is connected to a subset of the plurality of memory cells 309, e.g., a row of memory cells 309 in the memory array. Like a conventional SRAM device, the SRAM device 300 also includes a plurality of address lines 301. The address lines 301 are configured to receive a plurality of addresses, wherein each of the addresses identifies one of the plurality of word lines 310.

[0047] In contrast to a conventional SRAM device, the SRAM device 300 of this disclosure includes a multiplexer latch 302 in the memory array. The plurality of address lines 301 is connected as a plurality of inputs to the multiplexer latch 302. The multiplexer latch 302 is configured to select one of the addresses and to latch the selected address. This selected and latched address is then used to activate the corresponding word line 310 (indicated by the dashed arrows).

[0048] FIG. 5 shows an example of a memory array of an SRAM device 500 according to this disclosure. The SRAM device 500 includes similar elements as the SRAM devices 300 and 400 shown in FIG. 3 and 4, respectively, and same elements are labelled with the same reference signs and function likewise. The SRAM device 500 includes the OR-gate 316 of the SRAM device 300 and also includes the multiplexer latch 302 of the SRAM device 400.

[0049] The memory array again includes the memory cells 309 - for example, 6T memory cells - which are connected to the word lines 310 and the bit line pairs 311, respectively, and may be arranged in rows and columns as illustrated. The arrangement of the memory cells 309 may be as in a conventional SRAM array, and also the design of each memory cell 309 may be like in a conventional SRAM. The bit line pairs 311 are connected to the sense amplifiers 312, which may provide an output 313 each based on the signal difference of the respective bit line pair 311. The word lines 310 are further connected to the AND gate x- decoders 307.

[0050] The plurality of address lines 301 is configured to receive a plurality of addresses (e.g., including Io 320 and Ii 318) and a select (“sei”) signal 319. The multiplexer latch 302, being connected to the plurality of address lines 301, is configured to select one of the addresses and to latch the selected address. The multiplexer latch 302 may select the one of the addresses based on the select signals 319. A pre-decoder 304 is arranged between the multiplexer latch 302 and the x-decoders 307, and is connected by data lines 303 to the multiplexer latch 302. For instance, one of the addresses Io 320 and Ii 318 may be mux-latched and then pre-decoded. The multiplexer latch 302 uses the select signal 319 to select between the addresses. The multiplexer latch 302 may replace an external multiplexer of a conventional SRAM device, e.g., the SRAM device 100 of FIG. 1. As a consequence, the delay of said multiplexer present in the conventional SRMA device is eliminated. The latching of the selected address in the SRAM device 400 or 500, however, is functionally as in the conventional SRAM device.

[0051] Only one-word line 310 (the “hot word line”) is asserted / activated. The bit line pairs 311 are pre-charged high. The asserted word line 310 drives the subset of memory cells 309 it is connected to, so as to discharge one-bit line of each bit line pair 311, and the sense amplifiers 312 are configured to determine and drive the output 313. The timer circuit 308 is configured to determine the required time for the bit line signal to develop, and asserts the signal sene Ik 314, in order to capture the output 313. The output signal 317 of the OR-gate 316 is input to the timer 308. The timer 308 may be configured to initiate the generation of senclk 314 based on the output signal 317 of the OR-gate 316.

[0052] The SRAM memory array of the SRAM device 500 is further provided with an (external) clock 315, which is converted into an internal clock 306, wherein the internal clock 306 is used to clock / synchronize the multiplexer latch 302, the x-decoders (AND gates thereof) and the timer circuit 308.

[0053] The SRAM memory array shown in FIG. 5 further includes the OR-gate 316. All of the word lines 310 are connected to the OR-gate 316. Thus, if any one of the word lines 310 changes its signal from low to high, the OR-gate 316 generates a signal 317 (high signal), which drives the timer 308. The timer 308 may set an appropriate shorter delay than in a conventional SRAM device, e.g., the SRAM device 100 of FIG. 1.

[0054] In particular, as shown in the timing-diagram of FIG. 6, the timer 108 is configured to set the required delay from the time t6of the rise of the output 317 of the OR-gate 316 to the time t5at which the correct bit line difference is established, and thus at which senclk 314 rises. It is triggered off the time t6and has an internal delay of t5- 16. If the address is not late and the clock is not early then t2= t3and output is not delayed at all. The OR-gate 316 allows the pre-decoded address at t2later than internal clock rise at t3(t2> t3as indicated by the arrow).

[0055] The OR-gate 316 may comprises several stages, which may be used to detect the assertion of the one-hot word line 310. One, and only one, such word line signal will be asserted, and the OR-gate 316 is used to start a delay or buffer path that strobes the sense amplifiers 312. A late address will cause a late word line assertion, and accordingly the bit lines voltage development will happen later as well. Detecting the word line assertion with the OR-gate 316 enables a correct functionality (reading or writing) of the SRAM array without adding extra margin for the potentially late address.

[0056] FIG. 7 shows an example of a multiplexer latch 302. The use of the multiplexer latch 302 eliminates the need for a multiplexer on the address path, thereby further improving the delay of the critical address path. The multiplexer latch 302 of the present disclosure may have the same delay as a multiplexer, which is used external the memory array in a conventional SRAM device.

[0057] As can be seen in FIG. 7, the exemplary multiplexer latch 302 comprises a first set of pass gates 701 and a second set of pass gates 702. The first set of pass gates 701 is configured to select one of the addresses provided on the address lines 301. The second set of pass gates 702 is configured to latch the selected address. In particular, when the clock 315 (elk) is “0”, the selected address is output. When the clock 315 is “1”, the selected address is recycled (feedback (fb)) and latched, i.e., the output does not change. In summary, the present disclosure obtains the following advantages. Firstly, a shorter setup time is allowed, at least as long as no significant glitch results at the word line 310. Such a glitch may only happen in very rare circumstances, for example, if an address line falls later than the internal clock. The word line signals are allowed to be delayed, but the sense amplifiers 312 are strobed using the wide OR-gate 316 as a function of all the word lines. For instance, a late toggle of address line(s) may result in a pre-decoded signal rising late, which is compensated by the OR-gate 316. This makes the SRAM array transparent (to some degree). Secondly, the combination of the multiplexer function with the latch function in the multiplexer latch 302 improves the address path by at least one gate delay. The multiplexer of the conventional SRAM device can be removed to reduce the access time. The present disclosure has been described in conjunction with various embodiments as examples as well as implementations. However, other variations can be understood and effected by those persons skilled in the art and practicing the claimed matter, from the studies of the drawings, this disclosure and the independent claims. In the claims as well as in the description the word “comprising” does not exclude other elements or steps and the indefinite article “a” or “an” does not exclude a plurality. A single element or other unit may fulfill the functions of several entities or items recited in the claims. The mere fact that certain measures are recited in the mutual different dependent claims does not indicate that a combination of these measures cannot be used in an advantageous implementation.

Claims

CLAIMS1. A static random access memory, SRAM, device (300) comprising: a plurality of SRAM memory cells (309); a plurality of bit line pairs (311), wherein each of the plurality of the memory cells (309) is connected to one pair of bit lines of the plurality of bit line pairs (311); a plurality of word lines (310), wherein each of the word lines (310) is connected to a subset of the plurality of memory cells (309); and a plurality of sense amplifiers (312), wherein each pair of the plurality of bit line pairs (311 ) is connected to one of the plurality of sense amplifiers (312); and an OR-gate (316), wherein the plurality of word lines (310) is connected as a plurality of inputs to the OR-gate (316), and an output of the OR-gate (316) is configured to trigger an activation of the plurality of sense amplifiers (312).

2. The SRAM device (300) according to claim 1 , wherein the OR-gate (316) is configured to provide an output signal (317) based on a plurality of input signals on the plurality of word lines (310), wherein a high output signal (317) of the OR-gate (316) is configured to trigger the activation of the plurality of sense amplifiers (312).

3. The SRAM device (300) according to claim 2, wherein a change from a low signal to a high signal on any one-word line (310) of the plurality of word lines (310) results in the high output signal (317) of the OR-gate (316).

4. The SRAM device (300) according to claim 2 or 3, wherein the high output signal (317) of the OR-gate (316) is configured to trigger the generation of a pulse of a sense amplifier sampling signal, senclk (314).

5. The SRAM device (300) according to claim 4, further comprising a timer (308), wherein the output signal (317) of the OR-gate (316) is input to the timer (308), and wherein the timer (308) is configured to initiate the generation of the senclk (314) based on the output signal (317) of the OR-gate (316).

6. The SRAM device (300) according to one of the claims 1 to 5, wherein the OR-gate (316) is based on domino technology.

7. The SRAM device (300) according to one of the claims 1 to 6, wherein the SRAM device (300) further comprises: a plurality of address lines (301) configured to receive a plurality of addresses, wherein each of the addresses identifies one of the plurality of word lines (310); and a multiplexer latch (302), wherein the plurality of address lines (301) is connected as a plurality of inputs to the multiplexer latch (302), and the multiplexer latch (302) is configured to select one of the addresses and to latch the selected address.

8. A static random access memory, SRAM, device (300) comprising: a plurality of SRAM memory cells (309); a plurality of bit line pairs (311), wherein each of the memory cells (309) is connected to one pair of the plurality of bit line pairs (311); a plurality of word lines (310), wherein each of the word lines (310) is connected to a subset of the plurality of memory cells (309);a plurality of address lines (301) configured to receive a plurality of addresses, wherein each of the addresses identifies one of the plurality of word lines (310); and a multiplexer latch (302), wherein the plurality of address lines (301) is connected as a plurality of inputs to the multiplexer latch (302), and the multiplexer latch (302) is configured to select one of the addresses and to latch the selected address.

9. The SRAM device (300) according to claim 8, wherein the memory cells (309), the bit line pairs (311), and the word lines (310) are part of a memory array of the SRAM device (300), and the memory array also comprises the multiplexer latch (302).

10. The SRAM device (300) according to claim 8 or 9, wherein the multiplexer latch (302) comprises a first set of pass gates (701) configured to select the one of the addresses, and a second set of pass gates (702) configured to latch the selected address.

11. The SRAM device (300) according to one of the claims 8 to 10, wherein the SRAM device (300) further comprises: a plurality of sense amplifiers (312), wherein each pair of the plurality of bit line pairs (311 ) is connected to one of the plurality of sense amplifiers (312); and an OR-gate (316), wherein the plurality of word lines (310) is connected as a plurality of inputs to the OR-gate (316), and an output (317) of the OR-gate (316) is configured to trigger an activation of the plurality of sense amplifiers (312).

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