High-speed optoelectronic device and method for processing the same

Abstract

The invention concerns a method for processing an optoelectronic device comprising a plurality of semiconductor materials characterized by mismatched lattice parameters, wherein the light emitting layers are patterned to form strips that allow relaxation of strain within the semiconductor layers caused by the lattice mismatch, improving quantum efficiency. The patterning additionally serves to achieve significantly high densities of defects on the sidewalls of the semiconductor strips, allowing realization of higher modulation speeds through increased non-radiative recombination effects.

Description

[0001] HIGH-SPEED OPTOELECTRONIC DEVICE AND METHOD FOR PROCESSING THE SAME

[0002] The current application claims priority of German patent application DE 10 2024 102 455 . 0 dated January 29 , 2024 , the disclosure of which is incorporated herein in its entirety by reference .

[0003] The present invention concerns an optoelectronic device , in particular a pLED for high-speed applications , and a method for processing such a high-speed optoelectronic device .

[0004] BACKGROUND

[0005] The processing of optoelectronic devices and pLEDs has been made possible by a variety of semiconductor materials whose optical and electrical properties play a fundamental role in the operational characteristics of the optoelectronic devices fabricated therefrom .

[0006] A property of particular interest in the selection of semiconductor materials is the bandgap , which is inherently linked to the composition of the semiconductor compound .

[0007] Common semiconductor materials are based on I II-V group elements combined in various constellations . The most widely used material systems , named after the V group component of the semiconductor compound, are nitrides , phosphides , and arsenide . Within the material systems , semiconductor compounds may be categorized as binary, ternary, or quaternary compounds , depending on the number of elements comprising the semiconductor material .

[0008] In ternary and quaternary semiconductor compounds , the bandgap energy and lattice parameters are functions of compositional parameters . This makes them of particular interest in development of semiconductorbased devices , as parameters of relevance may be tuned by varying the material composition during manufacture .

[0009] Ternary compounds , commonly represented as AxBi-xC, are characterized by a single variable compositional parameter x , which simultaneously influences bandgap energy and lattice parameters . The bandgap energy and lattice parameters thus cannot be independently selected / tuned . A linear function can be used to determine the lattice parameters of ternary alloys given the material composition, as described by Vegard' s law .

[0010] Quaternary alloys comprising four binary compounds may be represented as AxB i -xCyD i -yand are characterized by two group II I and two group V elements . The two alternative representations , AxByCi-x-yD and ABxCyDi-x-yare used for representation of quaternary alloys comprising three binary compounds and characterized by three group II I and one group V element , or one group II I and three group V elements . The two compositional parameters x and y allow independent selection of bandgap energy and lattice parameters .

[0011] Ternary and quaternary Il l-nitrides are of importance in the manufacture of optoelectronic devices due to their tuneable bandgap . InxGai-xN has emerged as a semiconductor material for optoelectronic devices , capable of achieving electromagnetic emissions spanning from the ultraviolet range ( 363 nm) for values of x approaching zero , to the near infrared range ( 1800 nm) for values of x approaching 1 . Ternary and quaternary nitrides comprising AIN extend the tuneable output into the deep ultraviolet range , allowing light emission at wavelengths as low as 210 nm .

[0012] The various options make such ternary and quaternary I TI-nitrides interesting a variety of application including but not limited to optical communication . However , the modulation of light for such application still poses a challenge , as the requirement for the modulation speed increases . At the same time , the light emitting devices are becoming smaller and get into the pLED range that is their respective lateral dimension drops below 70pm and in particular below 20 pm and even more particular below 10 pm down to 1 pm .

[0013] It is an obj ect of the present application to provide an optoelectronic device and a method for processing an optoelectronic device that achieves increased modulation speeds while reducing internal quantum efficiency losses . SUMMARY OF THE INVENTION

[0014] This and other obj ects are addressed by the subj ect matter of the independent claims . Features and further aspects of the proposed principles are outlined in the dependent claims .

[0015] A challenge in the processing of optoelectronic devices comprising ternary nitrides is the deformation effect arising from lattice mismatch between the binary compounds InN, GaN and AIN . Increasing the value of the compositional parameter (x ) in the ternary compounds InxGai-xN and AlxGai-xN results in increased strain within the semiconductor layers . The detrimental effects of the increased strain include reduced crystal quality and development of strong piezoelectric fields within the semiconductor layers which induce the quantum- confined Stark effect ( QCSE ) . As a result , the internal quantum efficiency of the optoelectronic device decreases . This is particularly notable in the transition from blue to green wavelengths in InGaN- based optoelectronic devices , where a drastic reduction in internal quantum efficiency is observed with increase in indium concentration, resulting in an effect commonly termed the "green gap" .

[0016] In general , the optical properties of InGaN allow production of optoelectronic devices characterized by light emissions spanning the entire range of visible light based on a single material system, eliminating the need for integration of conversion elements , and allowing further reduction in pixel sizes . However , the lattice mismatch and the resultant strain, crystal defects and piezoelectric- induced polarization poses a challenge , in particular due to the significant decrease in quantum efficiency .

[0017] Reference Ley et al . ( 2019 ) describes an approach for relaxation of strain in InGaN / GaN-based light emitting devices which relies on nanoscale lateral patterning to achieve a reduction in local piezoelectric fields within the active region . The strain relaxation lowers the QCSE , reducing the spatial separation between the charge carrier wave functions , thus improving quantum efficiency . A corresponding blue-shift in the emission is observed, increasing with the degree of relaxation and excitation power . The described approach is however specifically applied to nanorods and does not address modulation frequencies .

[0018] Meanwhile , the presence of defects within the semiconductor layers , either grown in during epitaxial processes , induced by plasma-based etching processes or otherwise introduced into the semiconductor material contributes to formation of non-radiative recombination centres , at which electric field redistribution occurs , resulting in accelerated quantum efficiency decay . While the presence of high defect density effectively lowers the internal quantum efficiency of the optoelectronic device , the increased density of non-radiative recombination centres may be exploited to achieve higher modulation speeds . This is due to an increase in switch-off speed arising from the increased rate of defect-assisted non-radiative recombination .

[0019] In view of those observations , the inventors propose an optoelectronic device comprising at least one recess within the boundaries of a semiconductor stack, forming a network of connected strips with at least one lateral dimension in the submicron range . The said strips may be linear in form, curved, or a combination of linear and / or curved portions , having a length and a width . The strips are patterned such that an interruption in the continuity of the semiconductor layers results , consequently causing a relaxation of the strain arising from the lattice mismatch . The strain relaxation thus achieved allows for greater flexibility in material composition with lower efficiency losses .

[0020] The proposed principle may be implemented on a semiconductor mesa stack based on I ll-nitride materials , in particular GaN, InN and AIN, in addition to ternary and quaternary compounds comprising the same . The proposed principle is however not limited to a specific material system. Alternative semiconductor material systems may be used, provided that selected material combinations exhibit a lattice mismatch large enough to result in increased density of lattice strain defects , thereby correspondingly increasing the rate of trap-assisted non- radiative recombination . The proposed optoelectronic device , in particular a pLED, comprises a semiconductor mesa stack arranged on a surface of a growth substrate . The semiconductor layer stack comprises a first doped layer, a second doped layer , and an active layer arranged between the two doped layers . A transparent conductive layer may optionally be arranged on a surface of the second doped layer facing away from the active layer . The semiconductor layer stack is bounded by mesa etched facets , thereby forming a single device .

[0021] The semiconductor layer stack comprises at least one recess within such boundaries characterized by a depth extending at least through the optional transparent conductive oxide , the second doped layer , the active layer, and part of the first doped layer . In accordance with the proposed principle , the at least one recess forms at least one strip in the semiconductor layer stack, whereby the at least one recess causes a strain relaxation within the active layer of the at least one strip in a direction laterally perpendicular to a sidewall of the at least one strip . It should be noted that one of the mesa etched facets forming the boundaries of the semiconductor layer stack may also act as a recess . Consequently, a strip can also be formed between one of the mesa etched facets an the at least one recess .

[0022] In some aspects , the semiconductor layer stack comprises a plurality of strips , each of them either bounded by two recesses or one recess and one of the mesa etched facets forming the sidewalls of the device . Hence , one may say, the semiconductor layer stack may comprise subelements characterized by a strip-like-form with a small width and a higher length . The at least one recess results in a pattern of strips characterized by at least one lateral dimension smaller than 900 nm and in particular smaller than 800 nm and in particular smaller than 500 nm and in particular in the range between 20 nm and 400 nm and in particular in the range between 30 nm and 300 nm and in particular in the range between 20 nm and 200 nm and in particular in the range between 50 nm and 150 nm and in particular in a range smaller than a reach of the strain relaxation . The strain relaxation is an exponential decreasing function depending on the distance to the surface and several factors , optionally including for example a function of the defect density . For example , the relaxation constant may increase with an increasing defect density and vice versa , the width of the strip may in some instance be smaller than twice the theoretical edge relaxation „constant" , multiplied by a constant direct proportional w / defect density ( range 1~3 ) for dimensions here discussed . In some aspects , the edge relaxation constant is defined as the dimension where the strain reaches a value of 10% or 30% of that of bulk ( ideal , perfect crystal case ) .

[0023] A proj ected view of the strips onto a plane perpendicular to the direction of epitaxial growth shows forms with lateral dimensions ( length and width) characterized by an aspect ratio between 1 and 5 , in particular between 5 and 10 , and in some cases up to 200 . The ratio between the smallest lateral dimension and the depth of etching may be less than 1 and particular less than 0 . 5 and in particular less than 0 . 2 and in particular less than 0 . 15 .

[0024] The form of the thus produced strips includes but is not limited to a plurality of narrow, parallel wall-like structures , or a plurality of concentric elliptical ( including circular ) or polygonal narrow walllike structures , or a circular or polygonal spiral structure comprising at least one continuous narrow wall-like structure .

[0025] The proposed principle additionally concerns a method for processing an optoelectronic device . In accordance with the proposed principle , a semiconductor layer stack is deposited on a growth substrate whose choice is dependent on the selected material system . For the nitride material system, possible growth substrates may comprise sapphire , silicon or silicon carbide . Hereafter , the proposed principle will be described based on a GaN / InGaN-based semiconductor layer stack deposited on a sapphire substrate , designed to operate within the bluegreen range of wavelengths . The proposed principle is however not limited to this exemplary aspect .

[0026] In some aspects of the proposed method, the semiconductor mesa stack is deposited on a c-plane sapphire substrate that may optionally comprise a patterned surface . Deposition methods include but are not limited to metal-organic chemical vapor deposition (MOCVD) , molecular beam epitaxy (MBE ) and hydride vapor-phase epitaxy ( HVPE ) . Suitable precursors for a GaN / InGaN-based semiconductor layer stack may include ammonia , trimethylgallium and trimethylindium . Silicon and Magnesium may be used as n-type and p-type dopants respectively .

[0027] In some aspects of the proposed method, a low-temperature (LT ) GaN nucleation layer is deposited on the prepared substrate . The nucleation layer comprises small crystalline grains that act as nucleation centers for growth of high temperature GaN epi layers . Typical process parameters optimized during the growth of the nucleation layer include growth temperature , growth rate , nitridation, reactor pressure and layer thickness . The LT GaN nucleation layer may subsequently be subj ected to an annealing process .

[0028] A high temperature ( HT ) GaN buffer layer may then be deposited on the surface of the nucleation layer facing away from the growth substrate . The buffer layer may be undoped, unintentionally doped or doped at low concentration . Growth of a buffer layer before deposition of the semiconductor layer stack serves to alleviate detrimental effects that commonly arise in GaN semiconductor layers deposited directly on sapphire due to the high lattice mismatch and different thermal expansion coefficients of GaN and sapphire . The GaN buffer layer also supports achievement of higher indium concentrations in subsequently grown InGaN layers .

[0029] In a subsequent step , a first doped GaN layer is deposited on the HT GaN buffer layer . An active layer comprising InGaN is thereafter deposited on the first doped layer . The indium ( In ) composition is adj usted and optimized to achieve the desired emission wavelength, with higher In composition corresponding to longer wavelengths . The active layer comprises a multilayered structure characterized by alternating quantum well and quantum barrier layers . In some other aspects , the active layer comprises InGaN quantum wells and GaN quantum barriers . In other aspects , the active layer may comprise alternating InGaN quantum wells and quantum barriers , with the quantum barriers characterized by a significantly lower indium content (x ) than the quantum wells . In some aspects , the active layer comprises AlInGaN quantum wells and quantum barriers comprising at least one of GaN, AlGaN or InGaN . Aspects comprising a quaternary compound such as AlInGaN allow a greater tuneable range , with the Al content in this exemplary aspect allowing for an increase in the emission bandgap, and the In content allowing a shift towards longer wavelengths .

[0030] In some aspects the active layer comprises a single quantum well arranged between two quantum barriers . In other aspects the active layer comprises a plurality of quantum wells , each arranged between quantum barrier layers . In some aspects characterized by multiple quantum wells , the indium content within the active layer is substantially equal for all quantum wells . In other aspects , the indium content varies across different quantum well layers within the active layer . In a further step according to the proposed principle , a second doped GaN layer is deposited on the surface of the active layer facing away from the first doped layer .

[0031] In some aspects , the doped layers may each comprise a single layer with substantially uniform dopant concentration . In other aspects , the dopant concentration in the doped layers may exhibit a graduated variation with deposition depth . In other aspects the doped layer may comprise multiple sublayers whose characteristics , such as dopant concentration, doping gradient , and material composition are dependent on the intended function . Some sublayers may even be undoped in some instances . Examples of dedicated functionality may include current spreading and current inj ection . In some aspects , the doped layers may comprise superlattice layers adj acent to the active layer .

[0032] Some aspects of the proposed principle comprise a subsequent step whereby a charge carrier blocking layer is arranged between the active layer and the second doped layer . The charge carrier blocking layer serves to improve confinement of charge carriers to the active layers , thereby improving output power and device efficiency . In an InGaN / GaN- based optoelectronic device , such a charge carrier blocking layer may comprise at least one of AlGaN, AlInGaN or AllnN, whereby the charge carrier blocking layer may be doped to exhibit the same polarity as the second doped layer . In some further aspects , the active layer may comprise undoped cladding layers arranged adj acent to the doped layers . The cladding layers reduce aging effects arising from leakage of dopants into the active layer .

[0033] In some aspects of the proposed principle , a transparent conductive layer , in particular ITO , is deposited on the surface of the second doped layer facing away from the active layer .

[0034] In accordance with the proposed principle , a patterned photo-resist layer is deposited on the semiconductor layer stack on a surface of the layer farthest away from the growth substrate and facing away from the active layer, exposing surface portions of the semiconductor stack .

[0035] A first mesa etch is conducted to form mesa sidewalls , thereby defining an optoelectronic component . This first etch, referred to a as shallow mesa etch, also removes material of the second doped semiconductor layer and at least the active layer to form at least one recess within the semiconductor stack and more particular within the boundaries defined by the mesa sidewalls .

[0036] The at least one recess within the semiconductor layer stack extends through the optional transparent conductive layer , the second doped layer , the active layer and optionally part of the first doped layer and forming strips within the semiconductor stack . In aspects of the invention where the doped layers comprise superlattices , the minimum etching depth is such that any superlattice layers in the first doped layer comprising the second material are fully etched through .

[0037] After the first etching process , the exposed sidewalls and the at least one recess may be processed . Such processing includes but is not limited to cleaning and annealing to reduce the overall defect density to a stable and defined value . Then, a second mesa etch, referred to as deep mesa etch may be conducted at least partially through the first doped layer at the mesa sidewalls defining the optoelectronic component . This forms an optoelectronic device , which is bounded by facets generated by the deep mesa etching process , but also includes one or more strips generated by the shallow mesa etching process . The first and / or mesa etching process may include a dry etching process , a wet etching process or a combination thereof . The type and parameters of the etching process depend on the material , design choices and other parameters . In an exemplary GaN / InGaN-based optoelectronic device , dry etching may for example , be conducted using reactive ion etching ( RIE ) systems , inductively coupled plasma ( TCP ) systems , or electron cyclotron resonance ( ECR) systems employing halogen-based plasmas , either singly or in combination . Wet etching processes for nitridebased material systems may involve KOH ( optionally in combination with K2S2O8 ) , H3PO4 , C6H8O7 / H2O2 , among others , and may in some instances be pho to -as sis ted .

[0038] The etching depth is selected such that the ratio between the width of the recess and its depth is less than 1 and particular less than 0 . 5 and in particular less than 0 . 2 and in particular less than 0 . 15 . At least one lateral dimension of the strips is smaller than 900 nm and in particular smaller than 800 nm and in particular smaller than 500 nm and in particular in the range between 20 nm and 400 nm and in particular in the range between 30 nm and 300 nm and in particular in the range between 20 nm and 200 nm and in particular in the range between 50 nm and 150 nm and in particular in a range smaller than a reach of the strain relaxation . A high aspect ratio is desirable as it increases probability of carrier non-radiative recombination on the side surfaces of the semiconductor strips , which in turn improves modulation speeds . With respect to the lateral dimensions , the aspect ratios are preferably selected to maximize the available surface area along the sidewalls of the strips .

[0039] In some aspects , the lateral dimensions of the optoelectronic device produced according to the proposed principle may be increased up to 100 pm while maintaining high-speed modulation, allowing improved speed and accuracy of handling and mounting , and reducing production costs .

[0040] In some aspects , the patterning of the strips comprises a layout whereby the orientation of the lateral dimensions displays a distinct directionality, that is , whereby a summation of the longer lateral dimensions of individual strips along one lateral axis is significantly larger than a summation of the longer lateral dimensions of individual strips aligned along a second lateral axis . In this instance , the relaxation of the quantum wells occurs primarily along one lateral axis , resulting in a corresponding polarization effect . The orientation of the said polarization effect is parallel to the direction of tension, which in this case is parallel to the dominant lateral axis , that is , the axis along which the sum of longer lateral dimensions is greater .

[0041] In other aspects , the patterning of the strips is designed to distribute the longer lateral dimensions substantially evenly about different lateral axes . In some such aspects , the strips may be patterned in the form of elliptical ( including circular ) or polygonal spiral structures . In other aspects the strips may form intersecting maze-like , honeycomb, or mesh-like structures , or any suitable form whereby at least one lateral dimension is smaller than 900 nm, and whereby the lateral dimensions exhibit a substantially large aspect ratio with respect to each other . Where the lateral orientation does not exhibit a dominant lateral axis , relaxation of the quantum wells is more uniform across different lateral axes , resulting in weaker polarization effects .

[0042] In accordance with the proposed principle , in a subsequent step, a dielectric material is deposited on the exposed facets in the recesses etched into the semiconductor stack . Such dielectric material may comprise at least one of SiO2 , A12O3 , SiN or HFO . The deposition process may be achieved by atomic layer deposition (ALD) , or any suitable method capable of depositing the dielectric material in recesses characterized by nanoscale lateral dimensions and high aspect ratios . In some aspects the selected dielectric material comprises a refractive index close to a refractive index of the material of the semiconductor layer stack, in other aspects the refractive index is different to support reflection on the facets .

[0043] To achieve desired modulation speeds , the defect density on the sidewalls of the semiconductor strips , in particular in the region of the quantum well layers , is adj usted to achieve a defined density of non-radiative recombination centres without significant loss in quantum efficiency . The defect density may in some aspects be set by suitable parametrization of the ALD process , or other process steps such as annealing , cleaning , wet etching, and so on . In some aspects , the deposition of dielectric material may comprise steps involving treatment of the sidewalls of the semiconductor strips to achieve a specific defect density, and / or an introduction of defects at specific densities and locations . The modulation speed can thereby be set based on a specified non-radiative recombination rate , which is partially dependent on defect density . It is to be noted that an increase in the defect density leads to a decrease in internal quantum efficiency, thereby the design process involves a trade-off between desired modulation speed and achievable internal quantum efficiency .

[0044] In a further step according to the proposed principle , metallic contact surfaces are provided for electrical connection to the doped semiconductor layers . Such metallic contact surfaces comprise a suitable ohmic material such as Ni , Au, Cr, Ti and so on . Various alternative serial and parallel configurations are possible . A key consideration is however to ensure even distribution of current within the semiconductor strips , due to a substantially high current density occurring within the semiconductor layer stack as a result of the structuring . In some aspects the said current density may be in the range between 30A / cm2to 10 kA / cm2, in particular between 0 . 5 kA / cm2to 2 kA / cm2. In order to lower the ris k of current-related damage , some aspects of the proposed principle comprise multiple electrical contact surfaces distributed across the surface of the optoelectronic device and supplying the semiconductor layers with current from a plurality of spatially distributed supply points . In other aspects , an optional transparent conductive layer of suitable thickness is deposited on the second doped semiconductor layer to improve current density distribution within the device .

[0045] In some aspects of the proposed principle , the aforementioned metallic contacts are positioned within the recesses between the semiconductor strips , arranged on the sidewalls of the strips parallel to the direction of epitaxial growth, and extending along the top surface of the strips such that the contacts are connected at one end to the first doped layer , and at the other end to a top surface of the second doped layer facing away from the active layer , or to the transparent conductive oxide layer, where one is present . A thin layer of dielectric material is therefore arranged between the metal contact and the sidewalls of the strips to guide the path of current flow, such that no current flows into the strips through the sidewalls .

[0046] In other aspects of the proposed principle , the metal contacts are arranged on a surface of the strips corresponding to a plane formed by the smallest lateral dimension and an axis parallel to the direction of epitaxial growth . A thin layer of dielectric is arranged between the metal contacts and the face of the strips parallel to the direction of epitaxial growth, such that contact between the metal contacts and the semiconductor layer stack occurs solely at a lower part of the metal contacts arranged on the first doped layer, and at an opposite extremity of the metals contact arranged on a top surface of the second doped layer facing away from the active layer , or on the transparent conductive oxide layer, where one is present .

[0047] Further processing of the optoelectronic device may comprise additional steps including but not limited to wet or dry etching for the removal of the growth substrate , mounting on a final carrier substrate , integration of additional optical elements such as reflectors , microlenses , deposition of protective surface layers , and so on, depending on desired functionality and intended application .

[0048] SHORT DESCRIPTION OF THE DRAWINGS

[0049] Further aspects and embodiments in accordance with the proposed principle will become apparent in relation to the various embodiments and examples described in detail in connection with the accompanying drawings in which :

[0050] Figure 1 shows a plot of band gap energy and lattice constants of common Il l-nitrides used in optoelectronic applications ;

[0051] Figure 2 illustrates an initial step in the processing of an electronic device in accordance with some aspects of the proposed principle ; Figure 3 shows an optoelectronic device , in accordance with some aspects of the proposed principle ;

[0052] Figures 4A to 4C show some electrical connection approaches in accordance with some aspects of the proposed principle ;

[0053] Figures 5A and 5B show different views of the connection approaches illustrated in Figures 4A and 4B in accordance with some aspects of the proposed principle ;

[0054] Figures 6A to 6D show further electrical connection approaches in accordance with some aspects of the proposed principle ;

[0055] Figures 7 and 8 illustrate exemplary optoelectronic devices in accordance with some aspects of the proposed principle .

[0056] DETAILED DESCRIPTION

[0057] The following embodiments and examples disclose various aspects and their combinations according to the proposed principle . The embodiments and examples are not always to scale . Likewise , different elements can be displayed enlarged or reduced in size to emphasize individual aspects . It goes without saying that the individual aspects of the embodiments and examples shown in the figures can be combined with each other without further ado , without this contradicting the principle according to the invention . Some aspects show a regular structure or form. It should be noted that in practice slight differences and deviations from the ideal form may occur without , however, contradicting the inventive idea .

[0058] In addition, the individual figures and aspects are not necessarily shown in the correct size , nor do the proportions between individual elements have to be essentially correct . Some aspects are highlighted by showing them enlarged . However , terms such as "above" , "over" , "below" , "under" "larger" , "smaller" and the like are correctly represented with regard to the elements in the figures . So it is possible to deduce such relations between the elements based on the figures . Figure 1 illustrates material characteristics associated with selected group II I nitrides commonly used in semiconductor device processing . The selected nitrides , InN, GaN and AIN exhibit a range of bandgap energies corresponding to electromagnetic emissions spanning from deep ultraviolet ( ~200nm in AIN ) to near infrared ( ~1700 in InN ) . Of particular interest for optoelectronic devices operating in the visible spectrum ( 400 to 700 nm) is the ternary compound InxGai-xN, which is tunable in the range between ~365 nm to ~1700 nm for x varying from 0 to 1 . On the horizontal axis of Figure 1 , the in-plane lattice constants for the wurtzite form of the nitrides are shown . A large lattice mismatch, such as is exhibited by InN and GaN, results in strain within the semiconductor layers during epitaxial growth of , which presents in the form of cracks and dislocation defects . Such defects act as centres for non-radiative recombination of charge carriers , resulting in loss of quantum efficiency . An additional challenge arises from the high piezoelectric constant of GaN, which results in a reduction of the overlap of charge carrier wave functions . Consequently, quantum efficiencies are significantly reduced, primarily in the green range of wavelengths ( 525 to 570 nm) , approximately corresponding to indium content between 15% and 40% , depending on quantum well thickness .

[0059] Figure 2 illustrates a proposed optoelectronic device 1 comprising a semiconductor layer stack 10 . The semiconductor layer stack comprises a first doped layer 11 , a second doped layer 13 , an active layer 12 arranged between the first and second doped layers , and an optional transparent conductive layer 14 . The semiconductor layer stack 10 comprises at least one narrow recess within the semiconductor layer stack extending in the direction of epitaxial growth through the transparent conductive oxide layer 14 , the second doped layer 13 , the active layer 12 , and possibly part of the first doped layer 11 immediately adj acent to the active layer , forming a pattern of strips 101 . A dielectric material 15 is deposited within the recesses formed within the semiconductor stack .

[0060] The first doped semiconductor layer comprises a first material . The active layer comprises a second material , whereby the lattice parameters of the first and second material exhibit a mismatch sufficient to induce a substantially high density of defects within the crystal structure . The defects serve as non-radiative recombination centres . The active layer may comprise a structure of alternating quantum wells and quantum barriers , whereby the quantum wells and quantum barriers are characterized by different material compositions . The second doped semiconductor layer may comprise the first material , or in other aspects , a third material , whereby the lattice parameters of the third material and the second material may be mismatched .

[0061] The narrow strips 101 are characterized by at least one lateral dimension w smaller than 900 nm and in particular smaller than 800 nm and in particular smaller than 500 nm and in particular in the range between 20 nm and 400 nm and in particular in the range between 30 nm and 300 nm and in particular in the range between 20 nm and 200 nm and in particular in the range between 50 nm and 150 nm and in particular in a range smaller than a reach of the strain relaxation . The ratio between the depth of the strips h, and the width of the smallest lateral dimension w may be in the range between 1 and 200 , in particular between 1 and 20 , whereby the upper end of the range is limited by mechanical structural stability requirements . Additionally, a high aspect ratio between the lateral dimensions of the strips is desirable , as it allows localization of defects at relatively higher densities on the sidewalls of the strips . A higher rate of defect-assisted non-radiative recombination is associated with higher switch-off speeds , which in turn improves modulation speeds .

[0062] The desired defects on the sidewalls of the semiconductor strips may occur directly as a result of production processes such as etching, annealing , cleaning, ALD, and so on . Alternatively, a controlled insertion of defects through a doping process may be realized, whereby the semiconductor strips are initially passivated with a suitably selected dielectric material such that any surface defects produced during the etching process are healed . In a subsequent process , a suitable dopant at desired concentration is introduced to the healed surfaces , thereby localizing defects at selected density . Other approaches to induce a defined defect densities are also possible . In any case , the defect density is correlated with desired modulation speed and is suitably tuned to ensure quantum efficiency losses are maintained within acceptable ranges .

[0063] Figure 3 illustrates an initial step in a method for processing an optoelectronic device according to the proposed principle . A growth substrate 20 , is provided for epitaxial growth of a semiconductor layer stack 10 . The substrate may comprise sapphire , which may be subj ected to various preparatory steps such as cleaning and patterning on a surface corresponding to a selected crystal plane , typically the c- plane .

[0064] A first doped semiconductor layer 11 comprising a first material is deposited on a surface of the growth substrate . The thickness of the deposited layer is dependent on various process parameters . In some aspects , the first doped layer may comprise a binary nitride , in particular, GaN .

[0065] In a subsequent step, an active layer 12 is deposited on the first doped semiconductor layer . The active layer comprises alternating layers of quantum wells and quantum barriers . In accordance with the proposed principle , the active layer comprises a second material characterized by lattice parameters that exhibit a mismatch in comparison to the first material . The quantum wells may comprise the second material , whereas the quantum barriers separating the quantum wells comprise a different material . In an exemplary embodiment , the quantum wells comprise InGaN with indium composition greater than 15% , in particular between 20% and 40% , and the quantum barriers comprise GaN . In other exemplary aspects , the quantum barriers comprise InGaN with indium composition lower than 5 % . In other aspects , the quantum barriers may comprise AlGaN with an adj ustable Al composition as a design choice . The number and depth of quantum wells and barriers are selected based on desired emission characteristics of the resultant optoelectronic device .

[0066] In a further step, a second doped semiconductor layer 13 is deposited on the surface of the active layer facing away from the first doped layer . The second doped layer may comprise the first material , or a third material from a compatible material system (with the first and second materials ) , characterized by a lattice mismatch with the second material . An optional transparent conductive oxide layer 14 is deposited on a surface of the second doped layer facing away from the active layer .

[0067] The semiconductor layer stack is subsequently processed in additional steps not hereby illustrated, comprising deposition of a patterned photoresist layer, etching to form strips as previously herein described, and forming electrical contact surfaces .

[0068] The layout of electrical contact surfaces may be accomplished by various means , resulting in a variety of possible electrical layouts . Figure 4A shows a serial connection corresponding to an aspect of the proposed optoelectronic device . The narrow strips 41 , each representing an active light emitting device , are connected in a serial network, realized through the secondary metal contacts 43 that serve as intermediate connectors , such that the current flows into the optoelectronic device via a first primary metal contact 42 connected to a supply source , through the network of strips via intermediate metal connectors 43 , and out via a second primary metal contact 44 of opposite polarity, or alternatively in the reverse direction . In some aspects , the positioning of the intermediate connectors 43 is within the dielectric-filled recesses 45 between the semiconductor strips 41 . A thin layer of dielectric is arranged between the surface of the intermediate connectors facing the sidewalls of the semiconductor strips and the sidewalls of the semiconductor strips to localize electrical contact to a top surface of the second doped layer or the optional transparent conductive oxide layer facing away from the active layer . In the illustrated aspect , the first primary contact 42 provides electrical contact to the second doped layer , whereas the second primary contact 44 is arranged to provide electrical contact to the first doped layer ( not illustrated) . Alternative aspects wherein the strips are connected in serial networks are illustrated in Figures 4B and 4C . Serial network topologies as shown in the exemplary aspects presented in Figures 4A to 4C are particularly desirable where a reduced capacitance and higher current density is required . A side view of an aspect of an optoelectronic device according to the proposed principle is shown in Figure 5A, in particular, corresponding to a layout according to some aspects according to the illustration in Figure 4A. A serial connection is enabled via the intermediate connectors 43 , with a thin dielectric layer 46 arranged between the intermediate connectors and the sidewalls of the semiconductor strips 41 . In this aspect , the intermediate contacts 43 are deposited in the dielectric-filled recesses 45 between the semiconductor strips . In other aspects , the intermediate contacts may be arranged on a surface parallel to a plane formed by a vertical axis parallel to the direction of epitaxial growth and a lateral axis parallel to the smallest lateral dimension of the strips ( the width ) . The primary metal contacts 42 and 44 are arranged to provide electrical contact to the second and first doped semiconductor layers respectively .

[0069] A cross section of an aspect of the proposed device as illustrated in Figure 4B taken along the axis AA is shown in Figure 5B . In this aspect , the strips are patterned in the form of concentric circular walls . The illustrated aspect shows an exemplary serial electrical connection layout , made possible by at least one intermediate metal connector 43 , which is isolated from the sidewalls of the semiconductor strips 41 by a thin dielectric layer 46 . A conduction path is thereby formed electrically connecting the second doped layer of an individual semiconductor strip with the first doped layer of an adj acent semiconductor strip .

[0070] Further aspects relating to the layout of electrical connections to an optoelectronic device according to the proposed principles involve parallel connection of strips . A parallel network topology is particularly desirable for applications where increased capacitance is a required feature of the optoelectronic device . Figures 6A to 6D show possible arrangements of the primary metal contacts 42 and 44 in relation to the semiconductor strips 41 , whereby one primary metal contact is connected simultaneously to all strips within the parallel network at surfaces corresponding to the first doped layer , and a second primary metal contact is connected to the same strips in the parallel network at surfaces corresponding to the second doped layer, with the connection to the second doped layer achieved directly or through optional transparent conductive layers arranged thereon . Figure 6B additionally illustrates an aspect of the proposed optoelectronic device comprising strips arranged in a network characterized by variations in lateral dimensions , whereby a variety of forms and patterns may be implemented, depending on desired functionality and emission characteristics .

[0071] The semiconductor strip may be patterned to form a continuous , winding, narrow structure 41 as illustrated in Figure 7 . Arrangement of the metal contacts is hereby simplified, and such a layout may be considered a preferable alternative to the series network layouts herein illustrated in Figures 4A and 5A . A polarization effect results from the alignment of lateral dimensions of the semiconductor strips predominantly along a specific lateral axis , as indicated in the exemplary aspect shown . The direction of polarization is perpendicular to the direction of strain relaxation within the strip . Suitable distribution of current source and sink contacts serves to decrease the current density within the semiconductor stack . In the illustrated aspect , multiple primary contacts ( 42 44 ) are spatially distributed to provide electrical contact to the doped layers of the semiconductor stack .

[0072] Where polarized emissions are undesirable for the required application, relaxation along a plurality of lateral axes is achievable through structuring in a manner that allows substantially uniform relaxation in a plurality of lateral directions . Figure 8 illustrates an exemplary embodiment whereby at least one continuous , narrow strip is patterned to form a rectangular spiral , thereby allowing relaxation of the semiconductor layer stack along two mutually perpendicular lateral axes . LIST OF REFERENCES

[0073] 1 optoelectronic device

[0074] 10 semiconductor stack

[0075] 11 first doped layer

[0076] 12 active layer

[0077] 13 second doped layer

[0078] 14 transparent conductive oxide layer

[0079] 15 dielectric material

[0080] 101 semiconductor strips

[0081] 20 growth substrate

[0082] 41 active light-emitting strips

[0083] 42 first primary metal contact

[0084] 43 intermediate / secondary metal connectors

[0085] 44 second primary metal contact

[0086] 45 recess between strips

[0087] 46 dielectric layer

Claims

CLAIMS1 . Optoelectronic device comprising :- a carrier substrate ;- a light emitting element having a semiconductor layer stack bounded by mesa etched sidewalls comprising : o a first doped semiconductor layer comprising a first material ; o an active layer comprising a second material , whereby the first material comprises a lattice constant that is different to a lattice constant of the second material ; o a second doped semiconductor layer comprising at least one of :■ the first material ; or■ a third material , whereby the third material comprise a lattice constant different to a lattice constant of the second material ;- the semiconductor layer stack further comprising at least one recess extending through the second doped semiconductor layer and at least through the active layer, thereby forming at least one strip , wherein the at least one recess causes a strain relaxation within the active layer of the at least one strip in a direction laterally perpendicular to a sidewall of the at least one strip, wherein- a width of the at least one strip is smaller than twice a reach of the strain relaxation .2 . Device according to claim 1 , wherein the at least one recess comprises unequal lateral dimensions ; and / or the at least one strip comprises unequal lateral dimensions , wherein the dimension laterally perpendicular to the sidewall of the at least one strip is smaller in particular by a factor of three or more than a dimension laterally parallel to the sidewall ;the first doped semiconductor layer comprises a super lattice , in particular of the second material , and wherein the recess extends through the super lattice ; and / or at least two metal contact surfaces arranged in such a way that each provides electrical contact to each of the doped semiconductor layers .3 . Device according to claim 1 , wherein the sidewall of the at least one strip is covered by a dielectric material , in particular a material with a refractive index different to a refractive index, particularly more than 10% difference , of the material of the semiconductor layer stack; and / or in particular comprising at least one of SiCh , AI2O3 , SiN, Nb2Os or HFO; and / or wherein the at least one recess is at least partially filled by a dielectric material .4 . Device according any of the preceding claims , wherein the at least one recess comprises a plurality of substantially parallel recesses , forming a plurality of substantially parallel strips within the semiconductor stack, wherein in particular the plurality of substantially parallel strips is electrically connected in one of a series circuit , a parallel circuit and a combination thereof .5 . Device according to claim 4 , wherein the plurality of substantially parallel strips is electrically connected to each other in a network, such that all such strips comprising an individual semiconductor layer stack are operated as a common optoelectronic element .6 . Device according to claim 4 or 5 , wherein the plurality of substantially parallel strips each comprise a length that is larger, in particularly more than two times larger and in particular more than four times larger than a width of each of the substantially parallel strips .7 . Device according any of the preceding claims , wherein the at least one recess comprises a first recesses along a first direction andat least one second recess along a second direction, thereby forming one of : a strip having at least one lateral turn, such that sections of the strip are oriented to each other at a lateral angle unequal to zero ; a plurality of narrow strips separated by the first direction and at least one second recess to form mesh-like , or maze-like , or labyrinthine layouts .8 . Device according to any of the preceding claims , comprising a plurality of recesses forming a plurality of narrow strips within the semiconductor layer stack in form of concentric narrow walls spatially separated from each other .9 . Device according to any of the preceding claims , wherein sidewalls of the strips comprise a material layer arranged on the sidewalls and inducing localized defects .10 . Device according to any of the preceding claims , comprising a conductive transparent layer over at least a portion of arranged on the surface of the second doped semiconductor layer , in particular over a portion of the at least one strip .11 . Device according to any of the preceding claims , wherein a width of the at least one strip is smaller than 900 nm and in particular smaller than 800 nm and in particular smaller than 500 nm and in particular in the range between 20 nm and 400 nm and in particular in the range between 30 nm and 300 nm and in particular in the range between 20 nm and 200 nm and in particular in the range between 50 nm and 150 nm .12 . Device according to any of the preceding claims , wherein the at least one recess comprises an aspect ratio of width to depth of less than 1 and particular less than 0 . 5 and in particular less than 0 . 2 and in particular less than 0 . 15 .13 . Method of processing an optoelectronic device , comprising :- providing a growth substrate- depositing a semiconductor layer stack comprising : o a first doped semiconductor layer on the growth substrate , wherein the first doped semiconductor layer comprises a first semiconductor material ; o an active layer comprising a second semiconductor material , wherein the first and second semiconductor materials belong to the same semiconductor material system, and wherein the first and second materials comprise different lattice constants ; o a second doped semiconductor layer on the active layer, wherein the second doped semiconductor layer comprises at least one of :■ the first semiconductor material , and / or■ a third semiconductor material from the same semiconductor material system as the first semiconductor material , wherein the second and third semiconductor materials comprise different lattice constants ;- depositing a patterned mas k on the semiconductor layer stack surface facing away from the growth substrate ;- conducting a first mesa etching process to form mesa sidewalls , thereby defining an optoelectronic component and etching a material of the second doped semiconductor layer and at least the active layer to form at least one recess within the semiconductor stack; wherein the at least one recess comprises different lateral dimensions , wherein the depth of the at least one recess is such that the at least one recess extends at least through the second doped layer and the active layer; processing the at least one recess ; conducting a second mesa etch at least partially through the first doped layer at the mesa sidewalls defining the optoelectronic component ; wherein a width of the at least one strip is smaller than twice a reach of the strain relaxation .14 . Method according to claim 13 , further comprising when depositing the first doped semiconductor layer on the growth substrate depositing a superlattice adj acent to the active layer; wherein during the first mesa etching process the superlattice is etched through .15 . Method according to claim 13 or 14 , wherein the step of processing comprises- the step of depositing a dielectric material by ALD within that at least one recess ; and / or- at least one of the following :- depositing a first material on the sidewalls to induce a defined defect density corresponding to a desired modulation speed; and / or treating the sidewalls to obtain a first defined defect density on the sidewalls ; inducing a second defined defect density on the treated sidewalls , wherein the second defined defect density is greater than the first defined defect density, and corresponds to a desired modulation speed .16 . Method according to any of claims 13 to 15 , wherein at least two metal contact surfaces are arranged on side surfaces of the at least one narrow strip parallel to a plane formed by the narrowest dimension of the narrow periodic strips and a vertical axis cutting through all layers of the semiconductor stack .17 . Method according to any of claims 13 to 16 , wherein at least one additional metal connector is deposited in the at least one recess within the semiconductor stack, in addition to the at least two metal contact surfaces , and whereby the additional metal connector is electrically isolated from the sidewalls of the semiconductor strips by a layer of dielectric material , and wherein the metal connector forms an electrical connection between the plurality of strips formed by the at least one recess in thesemiconductor stack, electrically connecting the second doped layer of at least one semiconductor strip to the first doped layer of at least one other semiconductor strip .

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