Display panel and display device comprising same

Abstract

This display device comprises: a substrate; sub-pixels disposed on the substrate; a first shared wire disposed in a boundary area between sub-pixels and providing a first voltage to the sub-pixels adjacent to the boundary area; and a second shared wire disposed in the boundary area and providing a second voltage, different from the first voltage, to the sub-pixels adjacent to the boundary area.

Description

Display panel and display device including the same

[0001] The present invention relates to a display panel and a display device including the display panel.

[0002] As information technology advances, the importance of display devices, which serve as a link between users and information, is growing. In response, the use of display devices such as liquid crystal displays (LCDs), organic light-emitting displays (OLEDs), and inorganic light-emitting displays (ILDs), is increasing.

[0003] Recently, research is actively being conducted on micro LEDs, which can realize faster response speeds and higher brightness compared to conventional LEDs. In the case of inorganic light-emitting devices such as micro LEDs, if the pixel driving method of the Pulse Amplitude Modulation (PAM) method is used, such as the organic light-emitting device (Organic LED), it may be difficult to accurately achieve the desired brightness because the central wavelength of the current shifts depending on the current density. Therefore, in the case of micro LEDs, a pixel driving method of the Pulse Width Modulation (PWM) method can be used, which expresses brightness by controlling the time that the current flows to the light-emitting device.

[0004] One object of the present invention is to provide a display device in which sub-pixels share wiring.

[0005] Another object of the present invention is to provide a display panel in which sub-pixels share wiring.

[0006] In order to achieve one object of the present invention, a display device according to embodiments of the present invention includes a substrate, sub-pixels arranged on the substrate, a first shared wiring arranged in a boundary area between the sub-pixels and providing a first voltage to the sub-pixels adjacent to the boundary area, and a second shared wiring arranged in the boundary area and providing a second voltage different from the first voltage to the sub-pixels adjacent to the boundary area.

[0007] In one embodiment, at least one of the first voltage and the second voltage can be equally provided to the sub-pixels.

[0008] In one embodiment, each of the sub-pixels may include a light-emitting element, a first sub-pixel circuit that controls the light-emitting time of the light-emitting element, and a second sub-pixel circuit that provides a driving current to the light-emitting element.

[0009] In one embodiment, the first sub-pixel circuit comprises a first transistor including a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node, a first capacitor including a first electrode receiving a sweep voltage and a second electrode connected to the first node, a second transistor including a control electrode receiving a first write gate signal, a first electrode receiving a data voltage, and a second electrode connected to the second node, a third transistor including a control electrode receiving the first write gate signal, a first electrode connected to the third node, and a second electrode connected to the first node, a fourth transistor including a control electrode receiving an emission signal, a first electrode receiving a first-first power supply voltage, and a second electrode connected to the second node, a fifth transistor including a control electrode receiving the emission signal, a first electrode connected to the third node, and a second electrode connected to the second sub-pixel circuit, and a control electrode receiving a first initialization gate signal, a first capacitor receiving a first initialization voltage. It may include a sixth transistor including an electrode, and a second electrode connected to the first node.

[0010] In one embodiment, at least one of the first voltage and the second voltage may be any one of the sweep voltage, the emission signal, the first initialization gate signal, the first-first power supply voltage, and the first initialization voltage.

[0011] In one embodiment, the second sub-pixel circuit includes a seventh transistor including a control electrode connected to a fourth node connected to the first sub-pixel circuit, a first electrode connected to a fifth node, and a second electrode connected to a sixth node, a second capacitor including a first electrode receiving a first-second power voltage and a second electrode connected to the fourth node, an eighth transistor including a control electrode receiving a second write gate signal, a first electrode receiving a data voltage, and a second electrode connected to the fifth node, a ninth transistor including a control electrode receiving the second write gate signal, a first electrode connected to the sixth node, and a second electrode connected to the fourth node, a tenth transistor including a control electrode receiving an emission signal, a first electrode receiving the first-second power voltage, and a second electrode connected to the fifth node, an eleventh transistor including a control electrode receiving the emission signal, a first electrode connected to the sixth node, and a second electrode connected to the light-emitting element, a control electrode receiving a second initialization gate signal, a first initialization It may include a 12th transistor including a first electrode receiving a voltage and a second electrode connected to the fourth node, and a 13th transistor including a control electrode receiving a bias gate signal, a first electrode receiving a second initialization voltage, and a second electrode connected to the light emitting element.

[0012] In one embodiment, at least one of the first voltage and the second voltage may be any one of the second write gate signal, the emission signal, the bias gate signal, the second initialization gate signal, the first-second power supply voltage, the first initialization voltage, and the second initialization voltage.

[0013] In one embodiment, the light emitting element includes a first electrode connected to the second sub-pixel circuit and a second electrode receiving a second power supply voltage, wherein one of the first voltage and the second voltage may be the second power supply voltage.

[0014] In one embodiment, the first shared wiring and the second shared wiring are formed on the same conductive layer, and the same conductive layer includes a first conductive pattern forming the first shared wiring and extending in a first direction, and a second conductive pattern forming the second shared wiring and extending in the first direction, and a contact hole connected to the first conductive pattern and a contact hole connected to the second conductive pattern can be arranged in the first direction.

[0015] In one embodiment, the first conductive pattern may include an extension portion extending in the first direction and a connecting portion protruding in a second direction intersecting the first direction and connected to the contact hole connected to the first conductive pattern, and the second conductive pattern may include an extension portion extending in the first direction and a connecting portion protruding in a direction opposite to the second direction intersecting the first direction and connected to the contact hole connected to the second conductive pattern.

[0016] In one embodiment, the display device may further include a third shared wiring disposed in the boundary region and providing a third voltage different from the first voltage and the second voltage to the genital sub-pixels adjacent to the boundary region.

[0017] In one embodiment, the first shared wiring, the second shared wiring, and the third shared wiring are formed on the same conductive layer, and the same conductive layer includes a first conductive pattern forming the first shared wiring and extending in a first direction, a second conductive pattern forming the second shared wiring and extending in the first direction, and a third conductive pattern forming the third shared wiring and extending in the first direction, wherein a contact hole connected to the first conductive pattern, a contact hole connected to the second conductive pattern, and a contact hole connected to the third conductive pattern can be arranged in the first direction.

[0018] In one embodiment, the first conductive pattern may include an extension portion extending in the first direction and a connecting portion protruding in a second direction intersecting the first direction and connected to the contact hole connected to the first conductive pattern, the second conductive pattern may include an extension portion extending in the first direction and a connecting portion protruding in a direction opposite to the second direction intersecting the first direction and connected to the contact hole connected to the second conductive pattern, and the third conductive pattern may include a connecting portion connected to the contact hole connected to the third conductive pattern, a first extension portion connected to the connecting portion in the second direction intersecting the first direction and extending in the first direction, and a second extension portion connected to the connecting portion in a direction opposite to the second direction intersecting the first direction and extending in the first direction.

[0019] In one embodiment, the boundary region includes a first boundary region and a second boundary region, the first shared wiring is disposed in the first boundary region and provides the first voltage to the sub-pixels adjacent to the first boundary region, the second shared wiring is disposed in the second boundary region and provides the second voltage to the sub-pixels adjacent to the first boundary region, and the display device is disposed in the second boundary region, and the display device may further include a third shared wiring that provides a third voltage different from the first voltage and the second voltage to the sub-pixels adjacent to the second boundary region, and a fourth shared wiring that is disposed in the second boundary region and provides a fourth voltage different from the first voltage, the second voltage, and the third voltage to the sub-pixels adjacent to the second boundary region.

[0020] In one embodiment, the first to fourth shared wires may extend in a first direction, and the first boundary region and the second boundary region may be alternately arranged in a second direction intersecting the first direction.

[0021] In one embodiment, the sub-pixels may have a mirror structure with respect to the boundary region.

[0022] In order to achieve another object of the present invention, a display panel according to embodiments of the present invention may include a substrate, sub-pixels arranged on the substrate, a first shared wiring arranged in a boundary area between the sub-pixels and electrically connected to the sub-pixels adjacent to the boundary area, and a second shared wiring arranged in the boundary area, spaced apart from the first shared wiring, and electrically connected to the sub-pixels adjacent to the boundary area.

[0023] In one embodiment, the first shared wiring and the second shared wiring are formed on the same conductive layer, and the same conductive layer includes a first conductive pattern forming the first shared wiring and extending in a first direction, and a second conductive pattern forming the second shared wiring and extending in the first direction, and a contact hole connected to the first conductive pattern and a contact hole connected to the second conductive pattern can be arranged in the first direction.

[0024] In one embodiment, the first conductive pattern may include an extension portion extending in the first direction and a connecting portion protruding in a second direction intersecting the first direction and connected to the contact hole connected to the first conductive pattern, and the second conductive pattern may include an extension portion extending in the first direction and a connecting portion protruding in a direction opposite to the second direction intersecting the first direction and connected to the contact hole connected to the second conductive pattern.

[0025] In one embodiment, the display panel may further include a third shared wiring disposed in the boundary area, spaced apart from the first and second shared wiring, and electrically connected to the stellate sub-pixels adjacent to the boundary area.

[0026] Display panels according to embodiments of the present invention can share wiring between adjacent sub-pixels by arranging wiring in the boundary region. This ensures a high ppi, increases capacitor area, improves mura, increases the line width of the power wiring, improves IR drop, and allows for more flexible design rules, thereby improving yield.

[0027] However, the effects of the present invention are not limited to the above-described effects, and may be expanded in various ways without departing from the spirit and scope of the present invention.

[0028] Figure 1 is a block diagram showing an embodiment of a display device.

[0029] FIG. 2 is a block diagram showing an embodiment of one of the sub-pixels of FIG. 1.

[0030] Fig. 3 is a circuit diagram showing an example of a sub-pixel of Fig. 2.

[0031] Fig. 4 is a plan view showing an embodiment of the display panel of Fig. 1.

[0032] Fig. 5 is a cross-sectional view showing an embodiment of the display panel of Fig. 4.

[0033] FIG. 6 is a cross-sectional view showing another embodiment of the display panel of FIG. 4.

[0034] Figure 7 is a plan view showing the pixels of Figure 4.

[0035] Figures 8 and 9 are layout diagrams showing an example of the pixels of Figure 4.

[0036] Fig. 10 is a layout diagram showing shared wiring of a display device according to embodiments.

[0037] Fig. 11 is a layout diagram showing shared wiring of a display device according to embodiments.

[0038] Figure 12 is a block diagram showing an embodiment of a display system.

[0039] Figures 13 to 16 are perspective views showing application examples of the display system of Figure 12.

[0040] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that in the following description, only the portions necessary for understanding the operation of the present invention will be described, and the description of other portions will be omitted so as not to obscure the gist of the present invention. Furthermore, the present invention is not limited to the embodiments described herein and may be embodied in other forms. However, the embodiments described herein are provided to explain the technical idea of ​​the present invention in sufficient detail to enable those of ordinary skill in the art to easily practice it.

[0041] Throughout the specification, when a part is said to be "connected" to another part, this includes not only the case where it is "directly connected" but also the case where it is "indirectly connected" with another element in between. The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit the present invention. Throughout the specification, when a part is said to "comprise" a certain element, this does not exclude other elements unless specifically stated to the contrary, but rather means that other elements can be included. "At least one of X, Y, and Z", and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as one X, one Y, one Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XYY, YZ, ZZ). Here, "and / or" includes any combination of one or more of the configurations.

[0042] Here, terms such as "first" and "second" may be used to describe various components, but these components are not limited to these terms. These terms are used to distinguish one component from another. Accordingly, a "first component" may refer to a "second component" within the scope disclosed herein.

[0043] Spatially relative terms, such as "below," "above," and the like, may be used for descriptive purposes to describe one element or feature in relation to other elements or features as depicted in the drawings. Spatially relative terms are intended to encompass different orientations during use, operation, and / or manufacturing, in addition to the orientation depicted in the drawings. For example, if a device depicted in the drawings is turned over, elements depicted as being positioned "below" other elements or features are now positioned "above" the other elements or features. Thus, in one embodiment, the term "below" may encompass both above and below. Furthermore, the device may be oriented in other orientations (e.g., rotated 90 degrees or in other directions), and the spatially relative terms used herein are to be interpreted accordingly.

[0044] Various embodiments are described with reference to drawings schematically illustrating ideal embodiments. Accordingly, it is to be understood that the shapes may vary, for example, depending on tolerances and / or manufacturing techniques. Therefore, the embodiments disclosed herein should not be construed as limited to the specific shapes depicted, but rather to encompass, for example, variations in shapes resulting from manufacturing processes. Likewise, the shapes depicted in the drawings may not depict the actual shapes of areas of the device, and the present embodiments are not limited thereto.

[0045] Figure 1 is a block diagram showing an embodiment of a display device.

[0046] Referring to FIG. 1, the display device (DD) may include a display panel (DP), a gate driver (120), a data driver (130), a voltage generator (140), and a controller (150).

[0047] The display panel (DP) includes sub-pixels (SP). The sub-pixels (SP) can be connected to a gate driver (120) via first to m-th gate lines (GL1 to GLm). The sub-pixels (SP) can be connected to a data driver (130) via first to n-th data lines (DL1 to DLn).

[0048] The sub-pixels (SP) can generate light of two or more colors. For example, each of the sub-pixels (SP) can generate light of red, green, blue, cyan, magenta, yellow, etc.

[0049] Two or more sub-pixels among the sub-pixels (SP) can constitute (or form) one pixel (PXL). For example, the pixel (PXL) can include three sub-pixels as illustrated in FIG. 1. In this way, the pixel (PXL) can emit light of various colors and various luminances depending on the combination of light emitted from the sub-pixels included therein.

[0050] The gate driver (120) is connected to the sub-pixels (SP) arranged in the row direction through the first to m-th gate lines (GL1 to GLm). The gate driver (120) can output gate signals to the first to m-th gate lines (GL1 to GLm) in response to a gate control signal (GCS). In embodiments, the gate control signal (GCS) can include a start signal indicating the start of each frame, a horizontal synchronization signal, and the like.

[0051] The gate driver (120) may be arranged on one side of the display panel (DP). However, embodiments are not limited thereto. For example, the gate driver (120) may be divided into two or more drivers that are physically and / or logically separated, and such drivers may be arranged on one side of the display panel (DP) and the other side of the display panel (DP) opposite to the one side. In this way, the gate driver (120) may be arranged around the display panel (DP) in various forms according to embodiments.

[0052] The data driver (130) is connected to the sub-pixels (SP) arranged in the column direction through the first to nth data lines (DL1 to DLn). The data driver (130) receives image data (DATA) and a data control signal (DCS) from the controller (150). The data driver (130) operates in response to the data control signal (DCS). In embodiments, the data control signal (DCS) may include a source start signal, a source shift clock, a source output enable signal, etc.

[0053] The data driver (130) can receive voltages from the voltage generator (140). The data driver (130) can use the received voltages to apply data signals having grayscale voltages corresponding to image data (DATA) to the first to n-th data lines (DL1 to DLn). When a gate signal is applied to each of the first to m-th gate lines (GL1 to GLm), data signals corresponding to the image data (DATA) can be applied to the data lines (DL1 to DLn). Accordingly, the sub-pixels (SP) can generate light corresponding to the data signals, and the display panel (DP) can display an image.

[0054] In embodiments, the gate driver (120) and data driver (130) may include complementary metal-oxide semiconductor (CMOS) circuit elements.

[0055] The voltage generator (140) can operate in response to a voltage control signal (VCS) from the controller (150). The voltage generator (140) is configured to generate voltages and provide the generated voltages to components of the display device (DD), such as the gate driver (120), the data driver (130), and the controller (150). The voltage generator (140) can generate a plurality of voltages by receiving an input voltage from outside the display device (DD) and regulating the received voltage.

[0056] A voltage generator (140) can generate a first power supply voltage (e.g., a 1-1 power supply voltage and a 1-2 power supply voltage described below) and a second power supply voltage. The generated first and second power supply voltages can be provided to the sub-pixels (SP) through power supply lines (PL). In other embodiments, at least one of the first and second power supply voltages can be provided from outside the display device (DD).

[0057] For example, the voltage generator (140) can provide various voltages and / or signals. For example, the voltage generator (140) can provide one or more initialization voltages (e.g., the first and second initialization voltages described below) applied to the sub-pixels (SP). For example, during a sensing operation for sensing electrical characteristics of transistors and / or light-emitting elements of the sub-pixels (SP), a reference voltage can be applied to the first to n-th data lines (DL1 to DLn), and the voltage generator (140) can generate the reference voltage and transmit it to the data driver (130). For example, during a display operation for displaying an image on the display panel (DP), common pixel control signals can be applied to the sub-pixels (SP), and the voltage generator (140) can generate the pixel control signals. In embodiments, the voltage generator (140) may provide pixel control signals to the sub-pixels (SP) via pixel control lines (PXCL). In FIG. 1, the pixel control lines (PXCL) are illustrated as being connected between the voltage generator (140) and the display panel (DP), but embodiments are not limited thereto. For example, the pixel control lines (PXCL) may be connected between the gate driver (120) and the display panel (DP). In this case, the pixel control signals may be transmitted from the voltage generator (140) to the pixel control lines (PXCL) via the gate driver (120).

[0058] The controller (150) controls all operations of the display device (DD). The controller (150) receives image data (IMG) and a control signal (CTRL) corresponding to the image data (IMG) from the outside. In response to the control signal (CTRL), the controller (150) can provide a gate control signal (GCS), a data control signal (DCS), and a voltage control signal (VCS).

[0059] The controller (150) can output image data (DATA) by converting the image data (IMG) to be suitable for the display device (DD) or the display panel (DP). In embodiments, the controller (150) can output image data (DATA) by aligning the image data (IMG) to be suitable for the sub-pixels (SP) of a row unit.

[0060] Two or more of the components of the data driver (130), the voltage generator (140), and the controller (150) may be implemented in an integrated circuit (e.g., a single integrated circuit). As illustrated in FIG. 1, the data driver (130), the voltage generator (140), and the controller (150) may be included in a driver integrated circuit (DIC). In this case, the data driver (130), the voltage generator (140), and the controller (150) may be functionally separate components within the driver integrated circuit (or single driver integrated circuit) (DIC). In other embodiments, at least one of the data driver (130), the voltage generator (140), and the controller (150) may be provided as a separate component from the driver integrated circuit (DIC).

[0061] Fig. 2 is a block diagram showing an embodiment of one of the sub-pixels of Fig. 1. In Fig. 2, a sub-pixel (SPij) arranged in an ith row (i is an integer greater than or equal to 1 and less than or equal to m) and a jth column (j is an integer greater than or equal to 1 and less than or equal to n) among the sub-pixels (SP) of Fig. 1 is illustrated.

[0062] Referring to FIG. 2, a sub-pixel (SPij) may include a sub-pixel circuit (SPC) and a light-emitting element (LD).

[0063] A light emitting element (LD) is connected between a first power supply voltage node (VDDN) and a second power supply voltage node (VSSN). The first power supply voltage node (VDDN) is connected to one of the power supply lines (PL) of FIG. 1 and receives a first power supply voltage. The second power supply voltage node (VSSN) is connected to another of the power supply lines (PL) of FIG. 1 and receives a second power supply voltage. The first power supply voltage may have a higher voltage level than the second power supply voltage.

[0064] A light emitting element (LD) is connected between an anode electrode (AE) and a cathode electrode (CE). The anode electrode (AE) may be connected to a first power supply voltage node (VDDN) through a sub-pixel circuit (SPC). For example, the anode electrode (AE) may be connected to the first power supply voltage node (VDDN) through one or more transistors included in the sub-pixel circuit (SPC). The cathode electrode (CE) may be connected to a second power supply voltage node (VSSN). The light emitting element (LD) is configured to emit light according to a current flowing from the anode electrode (AE) to the cathode electrode (CE).

[0065] The sub-pixel circuit (SPC) may be connected to an i-th gate line (GLi) among the first to m-th gate lines (GL1 to GLm) of FIG. 1 and a j-th data line (DLj) among the first to n-th data lines (DL1 to DLn) of FIG. 1. In response to a gate signal received through the i-th gate line (GLi), the sub-pixel circuit (SPC) controls the light-emitting element (LD) to emit light according to a data signal received through the j-th data line (DLj). In embodiments, the sub-pixel circuit (SPC) may be further connected to the pixel control lines (PXCL) of FIG. 1. In this case, the sub-pixel circuit (SPC) may further control the light-emitting element (LD) in response to pixel control signals received through the pixel control lines (PXCL).

[0066] For these operations, a sub-pixel circuit (SPC) may include circuit elements, such as transistors and one or more capacitors.

[0067] The transistors of the sub-pixel circuit (SPC) may include P-type transistors and / or N-type transistors. In embodiments, the transistors of the sub-pixel circuit (SPC) may include MOSFETs (Metal Oxide Silicon Field Effect Transistors). In embodiments, the transistors of the sub-pixel circuit (SPC) may include amorphous silicon semiconductors, monocrystalline silicon semiconductors, polycrystalline silicon semiconductors, oxide semiconductors, and the like.

[0068] Fig. 3 is a circuit diagram showing an example of a sub-pixel of Fig. 2.

[0069] Referring to FIG. 3, the sub-pixel (SPij) may include a light-emitting element (LD), a first sub-pixel circuit (SPC1) that controls the light-emitting time of the light-emitting element (LD), and a second sub-pixel circuit (SPC2) that provides a driving current to the light-emitting element (LD).

[0070] For example, the first sub-pixel circuit (SPC1) may include a first transistor (T1), a first capacitor (C1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), and a sixth transistor (T6). The first transistor (T1) may include a control electrode connected to a first node (N1), a first electrode connected to a second node (N2), and a second electrode connected to a third node (N3). The first capacitor (C1) may include a first electrode receiving a sweep voltage (SV) and a second electrode connected to the first node (N1). The second transistor (T2) may include a control electrode receiving a first write gate signal (GWC1), a first electrode receiving a data voltage (VDATA), and a second electrode connected to a second node (N2). The third transistor (T3) may include a control electrode receiving a first write gate signal (GWC1), a first electrode connected to a third node (N3), and a second electrode connected to a first node (N1). The fourth transistor (T4) may include a control electrode receiving an emission signal (EM), a first electrode receiving a first-first power voltage (VDD1), and a second electrode connected to a second node (N2). The fifth transistor (T5) may include a control electrode receiving an emission signal (EM), a first electrode connected to a third node (N3), and a second electrode connected to a second sub-pixel circuit (SPC2) (e.g., the fourth node (N4)). The sixth transistor (T6) may include a control electrode receiving a first initialization gate signal (GI1), a first electrode receiving a first initialization voltage (VINT1), and a second electrode connected to the first node (N1).

[0071] For example, the second sub-pixel circuit (SPC2) may include a seventh transistor (T7), a second capacitor (C2), an eighth transistor (T8), a ninth transistor (T9), a tenth transistor (T10), an eleventh transistor (T11), a twelfth transistor (T12), and a thirteenth transistor (T13). The seventh transistor (T7) may include a control electrode connected to a fourth node (N4), a first electrode connected to a fifth node (N5), and a second electrode connected to a sixth node (N6). The second capacitor (C2) may include a first electrode receiving a first-second power supply voltage (VDD2) and a second electrode connected to a fourth node (N4). The eighth transistor (T8) may include a control electrode receiving a second write gate signal (GWC2), a first electrode receiving a data voltage (VDATA), and a second electrode connected to a fifth node (N5). The ninth transistor (T9) may include a control electrode receiving a second write gate signal (GWC2), a first electrode connected to a sixth node (N6), and a second electrode connected to a fourth node (N4). The tenth transistor (T10) may include a control electrode receiving an emission signal (EM), a first electrode receiving a first-second power voltage (VDD2), and a second electrode connected to a fifth node (N5). The eleventh transistor (T11) may include a control electrode receiving an emission signal (EM), a first electrode connected to a sixth node (N6), and a second electrode connected to a seventh node (N7). The twelfth transistor (T12) may include a control electrode receiving a second initialization gate signal (GI2), a first electrode receiving a first initialization voltage (VINT1), and a second electrode connected to a fourth node (N4). The 13th transistor (T13) may include a control electrode receiving a bias gate signal (BCB), a first electrode receiving a second initialization voltage (VINT2), and a second electrode connected to a seventh node (N7).

[0072] For example, the light emitting element (LD) may include a first electrode (i.e., the anode electrode (AE) of FIG. 2) connected to a seventh node (N7) and a second electrode (i.e., the cathode electrode (CE) of FIG. 2) receiving a second power supply voltage (VSS).

[0073] The first, fourth, fifth, seventh, tenth, eleventh, and thirteenth transistors (T1, T4, T5, T7, T10, T11, T13) may be P-type transistors, and the second, third, sixth, eighth, ninth, and twelfth transistors (T2, T3, T6, T8, T9, T12) may be N-type transistors. However, the embodiments are not limited thereto, and the P-type transistors may be replaced with N-type transistors, and the N-type transistors may be replaced with P-type transistors.

[0074] In one embodiment, the first transistor (T1) may include a back gate electrode receiving a first-first power supply voltage (VDD1), the second transistor (T2) may include a back gate electrode connected to a control electrode of the second transistor (T2), the third transistor (T3) may include a back gate electrode connected to a control electrode of the third transistor (T3), and the sixth transistor (T6) may include a back gate electrode receiving a first initialization gate signal (GI1).

[0075] In one embodiment, the seventh transistor (T7) may include a back gate electrode receiving the first-second power supply voltage (VDD2), the eighth transistor (T8) may include a back gate electrode connected to the control electrode of the eighth transistor (T8), the ninth transistor (T9) may include a back gate electrode connected to the control electrode of the ninth transistor (T9), and the twelfth transistor (T12) may include a back gate electrode receiving the second initialization gate signal (GI2).

[0076] The sixth transistor (T6) can provide a first initialization voltage (VINT1) to the first node (N1) in response to the first initialization gate signal (GI1). Accordingly, the voltage of the first node (N1) can be initialized to the first initialization voltage (VINT1).

[0077] The second transistor (T2) can provide a data voltage (VDATA) to the second node (N2) in response to the first write gate signal (GWC1). The third transistor (T3) can diode-connect the first transistor (T1) in response to the first write gate signal (GWC1). Accordingly, a voltage compensated for by the threshold voltage of the first transistor (T1) can be provided to the first node (N1).

[0078] The fourth transistor (T4) can provide the first power voltage (VDD1) to the first transistor (T1) in response to the emission signal (EM). The fifth transistor (T5) can provide the current generated by the first transistor (T1) to the fourth node (N4) in response to the emission signal (EM). At this time, the sweep voltage (SV) is reduced, and the point in time at which the first transistor (T1) is turned on may vary depending on the magnitude of the data voltage (VDATA). Accordingly, the point in time at which the voltage of the fourth node (N4) increases may vary, and the point in time at which the seventh transistor (T7) is turned off may vary. For example, the first sub-pixel circuit (SPC1) can control the light-emitting time of the light-emitting element (LD) by adjusting the turn-off point of the seventh transistor (T7) that provides the driving current to the light-emitting element (LD). And, the brightness of the light-emitting element (LD) can change depending on the light-emitting time (i.e., grayscale expression).

[0079] In one embodiment, the sweep voltage (SV), the second write gate signal (GWC2), the emission signal (EM), the bias gate signal (9BCB), the first initialization gate signal (GI1), and the second initialization gate signal (GI2) may be pixel control signals. For example, the pixel control signals may be provided equally (or commonly) to the sub-pixels (SP, see FIG. 1).

[0080] In one embodiment, the first write gate signal (GWC1) may be provided to the sub-pixels (SP) through the first to m-th gate lines (GL1 to GLm, see FIG. 1). For example, the first write gate signal (GWC1) may be sequentially provided to each of the gate lines (GL1 to GLm, see FIG. 1).

[0081] Fig. 4 is a plan view showing an embodiment of the display panel of Fig. 1.

[0082] Referring to FIG. 4, a display panel (DP) may include a display area (DA) and a non-display area (NDA). The display panel (DP) displays an image through the display area (DA). The non-display area (NDA) is arranged around the display area (DA).

[0083] A display panel (DP) includes sub-pixels (SP) in a display area (DA). The sub-pixels (SP) may be arranged along a first direction (DR1) and a second direction (DR2) intersecting the first direction (DR1). For example, the sub-pixels (SP) may be arranged in a matrix form along the first direction (DR1) and the second direction (DR2). As another example, the sub-pixels (SP) may be arranged in a zigzag form along the first direction (DR1) and the second direction (DR2). The arrangement of the sub-pixels (SP) may vary depending on the embodiments. The first direction (DR1) may be a row direction, and the second direction (DR2) may be a column direction.

[0084] Among a plurality of sub-pixels (SP), two or more sub-pixels can constitute (or form) a pixel (or single pixel) (PXL). In FIG. 4, the pixel (PXL) is illustrated as including three sub-pixels (SP1 to SP3), but embodiments are not limited thereto. For example, the pixel (PXL) may include two sub-pixels. Hereinafter, for convenience of explanation, it is assumed that the pixel (PXL) includes first to third sub-pixels (SP1 to SP3).

[0085] Each of the first to third sub-pixels (SP1 to SP3) can generate light of one of various colors, such as red, green, blue, cyan, magenta, yellow, etc. Hereinafter, for the sake of clarity and concise explanation, it is assumed that the first sub-pixel (SP1) generates red color light, the second sub-pixel (SP2) generates green color light, and the third sub-pixel (SP3) generates blue color light.

[0086] Each of the first to third sub-pixels (SP1 to SP3) may include at least one light-emitting element that generates light. In embodiments, the light-emitting elements of the first to third sub-pixels (SP1 to SP3) may generate light of the same color. For example, the light-emitting elements of the first to third sub-pixels (SP1 to SP3) may generate blue light. In other embodiments, the light-emitting elements of the first to third sub-pixels (SP1 to SP3) may generate light of different colors. For example, the light-emitting elements of the first to third sub-pixels (SP1 to SP3) may generate red light, green light, and blue light, respectively.

[0087] As a display panel (DP), a self-luminous display panel such as a light-emitting diode display panel (LED display panel) that uses micro-scale or nano-scale light-emitting diodes as light-emitting elements, or an organic light-emitting display panel (OLED panel) that uses organic light-emitting diodes as light-emitting elements, can be used.

[0088] Components for controlling sub-pixels (SP) may be arranged in the non-display area (NDA). Wires connected to the sub-pixels (SP), for example, the first to m-th gate lines (GL1 to GLm), the first to n-th data lines (DL1 to DLn), the power lines (PL), and the pixel control lines (PXCL) of FIG. 1, may be arranged in the non-display area (NDA).

[0089] At least one of the gate driver (120), the data driver (130), the voltage generator (140), and the controller (150) of FIG. 1 may be disposed in a non-display area (NDA) of the display panel (DP). In embodiments, the gate driver (120) may be disposed in the non-display area (NDA). In this case, the data driver (130), the voltage generator (140), and the controller (150) may be implemented as a driver integrated circuit (DIC) of FIG. 1 that is separate from the display panel (DP), and the driver integrated circuit (DIC) may be connected to wires disposed in the non-display area (NDA). In other embodiments, the gate driver (120), together with the data driver (130), the voltage generator (140), and the controller (150), may be implemented as an integrated circuit (or a single integrated circuit) that is separate from the display panel (DP).

[0090] In embodiments, the display area (DA) may have various shapes. The display area (DA) may have the shape of a closed loop including straight and / or curved edges. For example, the display area (DA) may have shapes such as a polygon, a circle, a semicircle, or an ellipse.

[0091] In some embodiments, the display panel (DP) may have a flat display surface. In other embodiments, the display panel (DP) may have an at least partially rounded display surface. In some embodiments, the display panel (DP) may be bendable, foldable, or rollable. In such cases, the display panel (DP) and / or the substrate of the display panel (DP) may include materials having flexible properties.

[0092] Fig. 5 is a cross-sectional view showing an embodiment of the display panel of Fig. 4.

[0093] Referring to FIG. 5, the display panel (DP) may include a substrate (SUB), and a pixel circuit layer (PCL), a display element layer (DPL), and a light functional layer (LFL) that are sequentially laminated in a third direction (DR3) intersecting the first and second directions (DR1, DR2) on the substrate (SUB).

[0094] The substrate (SUB) may be made of an insulating material such as glass or resin. For example, the substrate (SUB) may include a glass substrate. As another example, the substrate (SUB) may include a polyimide (PI) substrate. As yet another example, the substrate (SUB) may include a silicon wafer substrate formed using a semiconductor process.

[0095] In embodiments, the substrate (SUB) may be made of a flexible material that is bendable or foldable, and may have a single-layer structure or a multi-layer structure. For example, the flexible material may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose, and cellulose acetate propionate. However, the embodiments are not limited thereto.

[0096] A pixel circuit layer (PCL) is arranged on a substrate (SUB). The pixel circuit layer (PCL) may include insulating layers and semiconductor patterns and conductive patterns arranged between the insulating layers. The conductive patterns of the pixel circuit layer (PCL) may function as circuit elements, wirings, etc.

[0097] The circuit elements of the pixel circuit layer (PCL) may include sub-pixel circuits (SPC, see FIG. 2) of each of the sub-pixels (SP) of FIG. 4. For example, the circuit elements of the pixel circuit layer (PCL) may be provided as transistors and one or more capacitors of the sub-pixel circuit (SPC).

[0098] The wiring of the pixel circuit layer (PCL) may include wiring connected to sub-pixels (SP). The wiring of the pixel circuit layer (PCL) may include various signal lines and / or voltage lines necessary to drive the display element layer (DPL).

[0099] A display element layer (DPL) is arranged on a pixel circuit layer (PCL). The display element layer (DPL) may include light-emitting elements of sub-pixels (SP).

[0100] A light-functional layer (LFL) may be disposed on a display element layer (DPL). The light-functional layer (LFL) may include light-converting patterns having color-converting particles and / or scattering particles. For example, the color-converting particles may include quantum dots. The quantum dots may change the wavelength (or color) of light emitted from the display element layer (DPL). The light-functional layer (LFL) may further include light-scattering patterns having scattering particles. In other embodiments, the light-converting patterns and the light-scattering patterns may be omitted.

[0101] The light function layer (LFL) may further include a color filter layer comprising color filters. The color filter may selectively transmit light of a specific wavelength (or color). In other embodiments, the color filter layer may be omitted.

[0102] A window may be provided on a light-functional layer (LFL) to protect an exposed surface (or upper surface) of a display panel (DP). The window may protect the display panel (DP) from external impact. The window may be bonded to the light-functional layer (LFL) via an optically transparent adhesive (or bonding) member. The window may have a multilayer structure selected from a glass substrate, a plastic film, and a plastic substrate. This multilayer structure may be formed through a continuous process or an bonding process using an adhesive layer. All or a portion of the window may be flexible.

[0103] FIG. 6 is a cross-sectional view showing another embodiment of the display panel of FIG. 4.

[0104] Referring to FIG. 6, the display panel (DP') may include a substrate (SUB), a pixel circuit layer (PCL), a display element layer (DPL), an input sensing layer (ISL), and a light function layer (LFL). The substrate (SUB), the pixel circuit layer (PCL), the display element layer (DPL), and the light function layer (LFL) are configured similarly to the substrate (SUB), the pixel circuit layer (PCL), the display element layer (DPL), and the light function layer (LFL) described with reference to FIG. 4. Hereinafter, for convenience of explanation, redundant descriptions are omitted.

[0105] An input sensing layer (ISL) can detect user input on the upper surface (or display surface) of a display panel (DP'). The input sensing layer (ISL) may include configurations suitable for detecting external objects, such as a user's hand or pen. For example, the input sensing layer (ISL) may include touch electrodes.

[0106] Figure 7 is a plan view showing the pixels of Figure 4.

[0107] For convenience of explanation, Fig. 7 shows a first pixel (PXL1) and a second pixel (PXL2) among the pixels.

[0108] Referring to FIG. 7, the pixels (PXL1, PXL2) may include first to third sub-pixels (SP1 to SP3). The first to third sub-pixels (SP1 to SP3) may be arranged in the first direction (DR1). However, the arrangement of the pixels (PXL1, PXL2) is not limited thereto and may vary depending on embodiments. For example, the first to third sub-pixels (SP1 to SP3) may be arranged in a zigzag pattern.

[0109] First to third light-emitting elements (LD1 to LD3) may be arranged in the first to third sub-pixels (SP1 to SP3), respectively. The first light-emitting element (LD1), the second light-emitting element (LD2), and the third light-emitting element (LD3) may be inorganic light-emitting diodes including inorganic light-emitting materials. However, embodiments are not limited thereto, and for example, organic light-emitting diodes may be used.

[0110] A shared wiring described later may be placed in the boundary area (BA) between sub-pixels (SP1 to SP3). A detailed description thereof will be provided later.

[0111] Figures 8 and 9 are layout diagrams showing an example of the pixels of Figure 4.

[0112] FIGS. 8 and 9 are examples of layout diagrams showing the pixel circuit layer (PCL) of FIG. 5. For example, FIG. 8 shows a lower conductive layer (BML), a first active layer (ACT1), a first electrode layer (GAT1), a second electrode layer (GAT2), a second active layer (ACT2), a third electrode layer (GAT3), and a first conductive layer (SD1). FIG. 9 shows a second conductive layer (SD2) and a third conductive layer (SD3). The components shown in FIGS. 8 and 9 may be arranged identically for each pixel circuit (SPC, see FIG. 2). At least some of the components shown in FIGS. 8 and 9 may be connected to each other between a plurality of pixel circuits (SPC, see FIG. 2).

[0113] Referring to FIGS. 7 to 9, the sub-pixels (SP) may have a mirror structure based on the boundary area (BA). For example, as shown in FIG. 8, the first sub-pixel (SP1) and the second sub-pixel (SP) may be mirror-symmetrical, and the second sub-pixel (SP2) and the third sub-pixel (SP3) may be mirror-symmetrical. In addition, the third sub-pixel (SP3) of the first pixel (PXL1) and the first sub-pixel (SP1) of the second pixel (PXL2) may be mirror-symmetrical.

[0114] First and second shared wires (SW1, SW2) may be arranged in the first boundary area (BA1) between sub-pixels (SP). Third and fourth shared wires (SW3, SW4) may be arranged in the second boundary area (BA2) between sub-pixels (SP).

[0115] Each of the first to fourth shared wires (SW1 to SW4) can provide one of the pixel control signals (SV, GWC2, EM, BCB, GI1, GI2) and power voltages (VDD1, VDD2, VSS) to the sub-pixels (SP). For example, a wire that provides a voltage that is equally (or commonly) provided to the sub-pixels (SP) rather than a voltage that is sequentially provided to the sub-pixels (SP) can be used as the shared wire (SW).

[0116] In the present embodiment, the voltages provided by the first to fourth shared wires (SW1 to SW4) may be a bias gate signal (BCB), a second initialization voltage (VINT2), a first-first power supply voltage (VDD1), and a first-second power supply voltage (VDD2), but the embodiments are not limited thereto. For example, the voltages provided by each of the first to fourth shared wires (SW1 to SW4) may be one of the pixel control signals (SV, GWC2, EM, BCB, GI1, GI2) and power supply voltages (VDD1, VDD2, VSS).

[0117] The lower conductive layer (BML) may include first and second lower conductive patterns (BML1, BML2). The first and second lower conductive patterns (BML1, BML2) may be arranged on the same layer and may include the same material.

[0118] The bottom conductive layer (BML) may include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0119] The first active layer (ACT1) may include first-first and second-second active patterns (ACT1-1, ACT1-2). The first and second active patterns (ACT1-1, ACT1-2) may be arranged on the same layer and include the same material.

[0120] The first active layer (ACT1) may include any one of various types of semiconductors, for example, an amorphous silicon semiconductor, a monocrystalline silicon semiconductor, a polycrystalline silicon semiconductor, a low temperature poly silicon semiconductor, and an oxide semiconductor.

[0121] The first electrode layer (GAT1) may include first to seventh electrode patterns (GAT1-1 to GAT1-7). The first to seventh electrode patterns (GAT1-1 to GAT1-7) may be arranged in the same layer and may include the same material.

[0122] The first electrode layer (GAT1) may include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0123] The second electrode layer (GAT2) may include 2-1 to 2-7 electrode patterns (GAT2-1 to GAT2-7). The 2-1 to 2-7 electrode patterns (GAT2-1 to GAT2-7) may be arranged in the same layer and include the same material.

[0124] The second electrode layer (GAT2) may include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0125] The second active layer (ACT2) may include second-first to second-fourth active patterns (ACT2-1 to ACT2-4). The second-first to second-fourth active patterns (ACT2-1 to ACT2-4) may be arranged on the same layer and include the same material.

[0126] The second active layer (ACT2) may include any one of various types of semiconductors, for example, an amorphous silicon semiconductor, a monocrystalline silicon semiconductor, a polycrystalline silicon semiconductor, a polysilicon semiconductor, a low temperature polysilicon semiconductor, and an oxide semiconductor.

[0127] The third electrode layer (GAT3) may include third-first to third-fourth electrode patterns (GAT3-1 to GAT3-4). The third-first to third-fourth electrode patterns (GAT3-1 to GAT3-4) may be arranged in the same layer and may include the same material.

[0128] The third electrode layer (GAT3) may include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0129] The first conductive layer (SD1) may include first to fifteenth conductive patterns (SD1-1 to SD1-15). The first to fifteenth conductive patterns (SD1-1 to SD1-15) may be arranged on the same layer and may include the same material.

[0130] The first conductive layer (SD1) may include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0131] The 1-1 electrode pattern (GAT1-1) and the 2-1 electrode pattern (GAT2-1) can form a first capacitor (C1). The 1-4 electrode pattern (GAT1-4) and the 2-2 electrode pattern (GAT2-2) can form a second capacitor (C2).

[0132] The first lower conductive pattern (BML1) can form a back gate electrode of the first transistor (T1). The second lower conductive pattern (BML2) can form a back gate electrode of the seventh transistor (T7).

[0133] The 2-3 electrode pattern (GAT2-3) can form the back gate electrodes of the second transistor (T2) and the third transistor (T3). The 2-4 electrode pattern (GAT2-4) can form the back gate electrode of the third transistor (T3). The 2-5 electrode pattern (GAT2-5) can form the back gate electrode of the sixth transistor (T6). The 2-6 electrode pattern (GAT2-6) can form the back gate electrodes of the eighth transistor (T8) and the ninth transistor (T9). The 2-7 electrode pattern (GAT2-7) can form the back gate electrode of the twelfth transistor (T12).

[0134] The overlapping portion of the first-first active pattern (ACT1-1) and the first-first electrode pattern (GAT1-1) may constitute (or form) a part of the first transistor (T1). The first-first active pattern (ACT1-1) may be connected to the first-first conductive pattern (SD1-1) through the first contact hole (CNT1). The first-first conductive pattern (SD1-1) may be connected to the second-second active pattern (ACT2-2) through the second contact hole (CNT2).

[0135] The overlapping portion of the first-first active pattern (ACT1-1) and the first-second electrode pattern (GAT1-2) may constitute (or form) a portion of a fourth transistor (T4). The first-second electrode pattern (GAT1-1) may be connected to the first-second conductive pattern (SD1-2) through the first contact hole (CNT1). The first-second conductive pattern (SD1-2) may receive an emission signal (EM). The first-first active pattern (ACT1-1) is connected to the first-third conductive pattern (SD1-3) through the first contact hole (CNT1), the first-third conductive pattern (SD1-3) is connected to the second-fourth conductive pattern (SD2-4, see FIG. 9) through the third contact hole (CNT3), and the first-third conductive pattern (SD1-3) can receive the first-first power voltage (VDD1) through the second-fourth conductive pattern (SD2-4, see FIG. 9).

[0136] An overlapping portion of the first-first active pattern (ACT1-1) and the first-third electrode pattern (GAT1-3) may constitute (or form) a part of a fifth transistor (T5). The first-third electrode pattern (GAT1-3) may be connected to the first-second conductive pattern (SD1-2) through the first contact hole (CNT1). The first-second conductive pattern (SD1-2) may receive an emission signal (EM). The first-first active pattern (ACT1-1) may be connected to the first-fourth conductive pattern (SD1-4) through the first contact hole (CNT1). The first-fourth conductive pattern (SD1-4) may be connected to the first-fourth electrode pattern (GAT1-4) through the first contact hole (CNT1) and to the second-third active pattern (ACT2-3) through the second contact hole (CNT2).

[0137] The overlapping portion of the 2-1 active pattern (ACT2-1) and the 3-1 electrode pattern (GAT3-1) may constitute (or form) a part of a 2nd transistor (T2). A first write gate signal (GWC1) may be applied to the 3-1 electrode pattern (GAT3-1). The 2-1 active pattern (ACT2-1) may be connected to the 1-5 conductive pattern (SD1-5) through the 2nd contact hole (CNT2). The 1-5 conductive pattern (SD1-5) may be connected to the 2-5 conductive pattern (SD2-5, see FIG. 9) through the 3rd contact hole (CNT3). The 2-5th challenge pattern (SD2-5, see Fig. 9) can be connected to the 3-1st challenge pattern (SD3-1, see Fig. 9) to which a data voltage (VDATA, see Fig. 9) is applied through the 4th contact hole (CNT4, see Fig. 9).

[0138] The overlapping portion of the 2-2 active pattern (ACT2-2) and the 3-1 electrode pattern (GAT3-1) may constitute (or form) a part of a 3rd transistor (T3). A first write gate signal (GWC1) may be applied to the 3-1 electrode pattern (GAT3-1). The 2-2 active pattern (ACT2-2) may be connected to the 1-1 conductive pattern (SD1-1) through the second contact hole (CNT2). The 1-1 conductive pattern (SD1-1) may be connected to the 1-1 active pattern (ACT1-1) through the first contact hole (CNT1).

[0139] An overlapping portion of the 2-3 active pattern (ACT2-3) and the 3-2 electrode pattern (GAT3-2) may form a part of the 6th transistor (T6). The 2-3 active pattern (ACT2-3) may be connected to the 1-6th conductive pattern (SD1-6) through the second contact hole (CNT2). A first initialization voltage (VINT1) may be applied to the 1-6th conductive pattern (SD1-6). The 2-3 active pattern (ACT2-3) may be connected to the 1-7th conductive pattern (SD1-7) through the second contact hole (CNT2). The 1-7th conductive pattern (SD1-7) may be connected to the 1-1st active pattern (ACT1-1) through the first contact hole (CNT1).

[0140] The overlapping portion of the 1-2 active pattern (ACT1-2) and the 1-4 electrode pattern (GAT1-4) may constitute (or form) a part of the 7th transistor (T7). The 1-2 active pattern (ACT1-2) may be connected to the 1-4 conductive pattern (SD1-4) through the first contact hole (CNT1). The 1-2 active pattern (ACT1-2) may be connected to the 1-8 conductive pattern (SD1-8) through the first contact hole (CNT1). The 1-8 conductive pattern (SD1-8) may be connected to the 2-3 active pattern (ACT2-3) through the second contact hole (CNT2). The 1-2 active pattern (ACT1-2) may be connected to the 1-9 conductive pattern (SD1-9) through the first contact hole (CNT1). The 1-9th challenge pattern (SD1-9) can be connected to the 2-4th active pattern (ACT2-4) through the second contact hole (CNT2).

[0141] The overlapping portion of the first-second active pattern (ACT1-2) and the first-fifth electrode pattern (GAT1-5) may constitute (or form) a part of a tenth transistor (T10). The first-fifth electrode pattern (GAT1-1) may be connected to the first-tenth conductive pattern (SD1-10) through the first contact hole (CNT1). The first-fifth conductive pattern (SD1-5) may receive an emission signal (EM). The first-second active pattern (ACT1-2) is connected to the first-eleventh conductive pattern (SD1-11) through the first contact hole (CNT1), and the first-eleventh conductive pattern (SD1-11) is connected to the second-fourth conductive pattern (SD2-4, see FIG. 9) through the third contact hole (CNT3), and the first-eleventh conductive pattern (SD1-11) can receive the first-second power voltage (VDD2) through the second-fourth conductive pattern (SD2-4).

[0142] The overlapping portion of the 1-2 active pattern (ACT1-2) and the 1-6 electrode pattern (GAT1-6) may constitute (or form) a part of the 11th transistor (T11). The 1-6 electrode pattern (GAT1-6) may be connected to the 1-10th conductive pattern (SD1-10) through the first contact hole (CNT1). The 1-10th conductive pattern (SD1-10) may receive an emission signal (EM). The 1-2nd active pattern (ACT1-1) may be connected to the 1-11th conductive pattern (SD1-11) through the first contact hole (CNT1). The 1-8th conductive pattern (SD1-8) may be connected to the 2-3rd active pattern (ACT2-3) through the second contact hole (CNT2). The first-second active pattern (ACT1-2) can be connected to the first-twelfth conductive pattern (SD1-12) through the first contact hole (CNT1). The first-twelfth conductive pattern (SD1-12) can be connected to the second-seventh conductive pattern (SD2-7, see Fig. 9) through the third contact hole (CNT3). The second-seventh conductive pattern (SD2-7, see Fig. 9) can be connected to the third-third conductive pattern (SD3-3, see Fig. 9) through the fourth contact hole (CNT4, see Fig. 9).

[0143] The overlapping portion of the 1-2 active pattern (ACT1-2) and the 1-7 electrode pattern (GAT1-7) may constitute (or form) a part of the 13th transistor (T13). The 1-7 electrode pattern (GAT1-7) may be connected to the 1-13 conductive pattern (SD1-13) through the first contact hole (CNT1). The 1-13 conductive pattern (SD1-13) may be connected to the 2-1 conductive pattern (SD2-1, see FIG. 9) through the third contact hole (CNT3). The 2-1 conductive pattern (SD2-1) may receive a bias gate signal (BCB). The 1-2 active pattern (ACT1-2) may be connected to the 1-12 conductive pattern (SD1-12). The 1-12th conductive pattern (SD1-12) can be connected to the 2-7th conductive pattern (SD2-7, see FIG. 9) through the third contact hole (CNT3). The 1-2nd active pattern (ACT1-2) can be connected to the 1-14th conductive pattern (SD1-14) through the first contact hole (CNT1). The 1-14th conductive pattern (SD1-14) can be connected to the 2-2nd conductive pattern (SD2-2, see FIG. 9) through the third contact hole (CNT3). A second initialization voltage (VINT2) can be applied to the 2-2nd conductive pattern (SD2-2).

[0144] The overlapping portion of the 2-4 active pattern (ACT2-4) and the 3-3 electrode pattern (GAT3-3) may constitute (or form) a part of the 8th transistor (T8). A second write gate signal (GWC2) may be applied to the 3-3 electrode pattern (GAT3-3). The 2-4 active pattern (ACT2-4) may be connected to the 1-15 conductive pattern (SD1-15) through the second contact hole (CNT2). The 1-15 conductive pattern (SD1-15) may be connected to the 2-6 conductive pattern (SD2-6, see FIG. 9) through the third contact hole (CNT3). The 2-6th challenge pattern (SD2-6, see Fig. 9) can be connected to the 3-1st challenge pattern (SD3-1, see Fig. 9) to which a data voltage (VDATA, see Fig. 9) is applied through the 4th contact hole (CNT4, see Fig. 9).

[0145] The overlapping portion of the 2-3 active pattern (ACT2-3) and the 3-3 electrode pattern (GAT3-3) may constitute (or form) a part of the ninth transistor (T9). A second write gate signal (GWC2) may be applied to the 3-3 electrode pattern (GAT3-3). The 2-3 active pattern (ACT2-3) may be connected to the 1-8 conductive pattern (SD1-8) through the second contact hole (CNT2). The 1-8 conductive pattern (SD1-8) may be connected to the 1-2 active pattern (ACT1-2) through the first contact hole (CNT1).

[0146] The overlapping portion of the 2-3 active pattern (ACT2-3) and the 3-4 electrode pattern (GAT3-4) may constitute (or form) a part of the 12th transistor (T12). The 2-3 active pattern (ACT2-3) may be connected to the 1-6 conductive pattern (SD1-6) through the second contact hole (CNT2). A first initialization voltage (VINT1) may be applied to the 1-6 conductive pattern (SD1-6). The 2-3 active pattern (ACT2-3) may be connected to the 1-9 conductive pattern (SD1-9) through the second contact hole (CNT2). The 1-9 conductive pattern (SD1-9) may be connected to the 1-2 active pattern (ACT1-2) through the first contact hole (CNT1).

[0147] Referring to FIGS. 8 and 9, the second conductive layer (SD1) may include 2-1 to 2-7 conductive patterns (SD2-1 to SD2-7). The 2-1 to 2-6 conductive patterns (SD2-1 to SD2-7) may be arranged on the same layer and may include the same material.

[0148] The second to seventh challenge patterns (SD2-1 to SD2-7) may include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0149] The third conductive layer (SD3) may include third-first to third-third conductive patterns (SD3-1 to SD3-3). The third-first to third-third conductive patterns (SD3-1 to SD3-3) may be arranged on the same layer and include the same material.

[0150] The 3-1 to 3-3 challenge patterns (SD3-1 to SD3-3) may include at least one material among copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0151] The boundary area (BA) may include a first boundary area (BA1) and a second boundary area (BA2). The first boundary area (BA1) and the second boundary area (BA2) may be arranged alternately in the first direction (DR1).

[0152] The shared wiring (e.g., the first and second shared wiring (SW1, SW2)) arranged in the first boundary area (BA1) and the shared wiring (e.g., the third and fourth shared wiring (SW3, SW4)) arranged in the second boundary area (BA2) may be different. Since the shared wiring (SW) is arranged in the boundary area (BA) to provide voltage to the sub-pixels (SP) on the side (e.g., facing sides), even if the two boundary areas (BA1, BA2) are arranged alternately, each shared wiring (SW) can provide voltage to all the sub-pixels (SP).

[0153] The second-first conductive pattern (SD2-1) can form a first shared wiring (SW1). The second-first conductive pattern (SD2-1) is arranged in the first boundary area (BA1) and can be connected to the first-thirteenth conductive pattern (SD1-13) through the third contact hole (CNT3). The first-thirteenth conductive pattern (SD1-13) can be connected to the first-seventh electrode pattern (GAT1-7) through the first contact hole (CNT1). Due to the mirror structure, the first-seventh electrode pattern (GAT1-7) can provide a bias gate signal (BCB) to the thirteenth transistors (T13) of two adjacent sub-pixels (SP).

[0154] The second-second conductive pattern (SD2-2) can form a second shared wiring (SW2). The second-second conductive pattern (SD2-2) is arranged in the first boundary area (BA1) and can be connected to the first-14th conductive pattern (SD1-14) through the third contact hole (CNT3). The first-14th conductive pattern (SD1-14) can be connected to the first-2nd active pattern (ACT1-2). Due to the mirror structure, the first-14th active pattern (SD1-14) can provide a second initialization voltage (VINT2) to the 13th transistors (T13) of two adjacent sub-pixels (SP).

[0155] The second-first and second-second conductive patterns (SD2-1, SD2-2) may extend in the second direction (DR2). For example, the third contact hole (CNT3) connected to the second-first conductive pattern (SD2-1) and the third contact hole (CNT3) connected to the second-second conductive pattern (SD2-2) may be arranged in the second direction (DR2).

[0156] For example, the second-first challenge pattern (SD2-1) may include an extension extending in the second direction (DR2) and a protrusion protruding in the first direction (DR1). For example, the protrusion may be connected to a third contact hole (CNT3).

[0157] For example, the second-second challenge pattern (SD2-2) may include an extension extending in the second direction (DR2) and a protrusion protruding in a direction opposite to the first direction (DR1). For example, the protrusion may be connected to a third contact hole (CNT3).

[0158] The second-third conductive pattern (SD2-3) can form a third shared wiring (SW3). The third shared wiring (SW3) can receive the first-first power voltage (VDD1). The second-third conductive pattern (SD2-3) is arranged in the second boundary area (BA2) and can be connected to the first-third conductive pattern (SD1-3) through the third contact hole (CNT3). The first-third conductive pattern (SD1-3) can be connected to the first-first active pattern (ACT1-1) through the first contact hole (CNT1). Due to the mirror structure, the first-third conductive pattern (SD1-3) can provide the first-first power voltage (VDD1) to the fourth transistors (T4) of two adjacent sub-pixels (SP).

[0159] The 2-4th conductive pattern (SD2-4) can form a 4th shared wiring (SW4). The 4th shared wiring (SW4) can receive the 1-2nd power voltage (VDD2). The 2-4th conductive pattern (SD2-4) is arranged in the 2nd boundary area (BA2) and can be connected to the 1-11th conductive pattern (SD1-11) through the 3rd contact hole (CNT3). The 1-11th conductive pattern (SD1-11) can be connected to the 1-2nd active pattern (ACT1-2). Due to the mirror structure, the 1-11th conductive pattern (SD1-11) can provide the 1-2nd power voltage (VDD2) to the 10th transistors (T10) of two adjacent sub-pixels (SP).

[0160] The second-third and second-fourth conductive patterns (SD2-3, SD2-4) may extend in the second direction (DR2). For example, the third contact hole (CNT3) connected to the second-third conductive pattern (SD2-3) and the third contact hole (CNT3) connected to the second-fourth conductive pattern (SD2-4) may be arranged in the second direction (DR2).

[0161] For example, the second-third challenge pattern (SD2-3) may include an extension extending in a second direction (DR2) and a protrusion protruding in a first direction (DR1). For example, the protrusion may be connected to a third contact hole (CNT3).

[0162] For example, the second-fourth challenge pattern (SD2-4) may include an extension extending in the second direction (DR2) and a protrusion protruding in a direction opposite to the first direction (DR1). For example, the protrusion may be connected to a third contact hole (CNT3).

[0163] In this way, by arranging contact holes (e.g., the third contact hole (CNT3)) connected to the shared wirings (SW) within the same boundary area (BA1, BA2) in an extending direction to cross each other, the shared wirings (SW) can be arranged in one boundary area (BA).

[0164] The third-first conductive pattern (SD3-1) can form a data line (DL1 to DLn, see Fig. 1) to which a data voltage (VDATA) is applied. The third-first conductive pattern (SD3-1) can be connected to the second-fifth and second-sixth conductive patterns (SD2-5, SD2-6) through the fourth contact hole (CNT4).

[0165] A second power voltage (VSS) can be applied to the third-second conductive pattern (SD3-2). The third-second conductive pattern (SD3-2) can be connected to a light-emitting element (LD, see FIG. 7).

[0166] The second-seventh conductive pattern (SD2-7) can be connected to the first-twelfth conductive pattern (SD1-12) through the third contact hole (CNT3). The second-seventh conductive pattern (SD2-7) can be connected to the third-third conductive pattern (SD3-3) through the fourth contact hole (CNT4). The third-third conductive pattern (SD3-3) can form the first to third anode electrodes (AE1 to AE3) of the first to third light-emitting elements (LD1 to LD3, see FIG. 7), respectively.

[0167] In this embodiment, the first to fourth shared wires (SW1 to SW4) are shown to be arranged on the second conductive layer (SD2), but the embodiments are not limited thereto.

[0168] Fig. 10 is a layout diagram showing shared wiring of a display device according to embodiments.

[0169] The display device according to the present embodiments is substantially the same as the configuration of the display device described with reference to FIGS. 1 to 9, except for the arrangement of the third contact hole (CNT3) connected to the shared wiring (SW), and therefore the same reference numbers and reference symbols are used for the same or similar components, and redundant descriptions are omitted.

[0170] Referring to Fig. 10, the third contact holes (CNT3) connected to the shared wiring (SW) do not necessarily have to be arranged in a straight line in the second direction (DR2). For example, the third contact hole (CNT3) connected to the first shared wiring (SW1) and the third contact hole (CNT3) connected to the second shared wiring (SW2) may not be arranged in a straight line in the second direction (DR2). For example, the third contact hole (CNT3) connected to the third shared wiring (SW3) and the third contact hole (CNT3) connected to the fourth shared wiring (SW4) may not be arranged in a straight line in the second direction (DR2).

[0171] Fig. 11 is a layout diagram showing shared wiring of a display device according to embodiments.

[0172] The display device according to the present embodiments is substantially the same as the configuration of the display device described with reference to FIGS. 1 to 9, except that three shared wires (SW) are arranged in one boundary area (BA), and therefore the same reference numbers and reference symbols are used for the same or similar components, and redundant descriptions are omitted.

[0173] Referring to Fig. 10, first to third shared wires (SW1 to SW3) may be arranged in the first boundary area (BA1). Fourth to sixth shared wires (SW4 to SW6) may be arranged in the second boundary area (BA2).

[0174] The first to sixth shared wires (SW1 to SW6) may extend in the second direction (DR2). The third contact holes (CNT3) connected to each of the first to third shared wires (SW1 to SW3) may be arranged in the second direction (DR2). The third contact holes (CNT3) connected to each of the fourth to sixth shared wires (SW4 to SW6) may be arranged in the second direction (DR2).

[0175] Each of the first to sixth shared wires (SW1 to SW6) can provide one of the pixel control signals (SV, GWC2, EM, BCB, GI1, GI2, see FIG. 3) and power supply voltages (VDD1, VDD2, VSS, see FIG. 3) to the sub-pixels (SP, see FIG. 7). For example, a wire that provides a voltage that is equally (or commonly) provided to the sub-pixels (SP) rather than a voltage that is sequentially provided to the sub-pixels (SP, see FIG. 7) can be used as the shared wire (SW).

[0176] For example, the first and fourth shared wires (SW1, SW4) may include an extension extending in the second direction (DR2) and a protrusion protruding in the first direction (DR1). For example, the protrusion may be connected to the third contact hole (CNT3).

[0177] For example, the second and fifth shared wires (SW2, SW5) may include an extension extending in the second direction (DR2) and a protrusion protruding in a direction opposite to the first direction (DR1). For example, the protrusion may be connected to the third contact hole (CNT3).

[0178] For example, the third and sixth shared wirings (SW3, SW6) may include a connecting portion connected to the third contact hole (CNT3), a first extension portion connected to the connecting portion in a first direction (DR1) and extending in a second direction (DR2), and a second extension portion connected to the connecting portion in a direction opposite to the first direction (DR1) and extending in the second direction (DR2).

[0179] In this embodiment, three shared wirings (SW) may be placed in one boundary area (BA), but the number of shared wirings (SW) placed in one boundary area (BA) may be greater than three.

[0180] Figure 12 is a block diagram showing an embodiment of a display system.

[0181] Referring to FIG. 12, the display system (1000) may include a processor (1100) and a display device (1200).

[0182] The processor (1100) can perform various tasks and calculations. In embodiments, the processor (1100) may include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), etc. The processor (1100) can be connected to other components of the display system (1000) via a bus system and control them.

[0183] The processor (1100) can transmit image data (IMG) and a control signal (CTRL) to the display device (1200). The display device (1200) can display an image based on the image data (IMG) and the control signal (CTRL). The display device (1200) can be configured similarly to the display device (DD) described with reference to FIG. 1. In this case, the image data (IMG) and the control signal (CTRL) can be provided as the image data (IMG) and the control signal (CTRL) of FIG. 1, respectively.

[0184] The display system (1000) may include a computing system that provides an image display function, such as a smart watch, a mobile phone, a smart phone, a portable computer, a tablet personal computer, a watch phone, an automotive display, smart glasses, a portable multimedia player (PMP), a navigation system, an ultra mobile personal computer (UMPC), etc. In addition, the display system (1000) may include at least one of a head mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0185] Figures 13 to 16 are perspective views showing application examples of the display system of Figure 12.

[0186] Referring to FIG. 13, the display system (1000) of FIG. 12 can be applied to a smart watch (2000) including a display unit (2100) and a strap unit (2200).

[0187] The smartwatch (2000) may be a wearable electronic device. For example, the smartwatch (2000) may have a structure in which a strap portion (2200) is attached to the user's wrist. Here, a display system (1000) and / or a display device (1200) may be applied to the display portion (2100), so that image data including time information may be provided to the user.

[0188] Referring to FIG. 14, the display system (1000) of FIG. 12 can be applied to an automotive display system (3000). Here, the automotive display system (3000) can include a computing system provided inside and / or outside a vehicle to provide image data.

[0189] For example, the display system (1000) and / or the display device (1200) may be applied to at least one of an infotainment panel (3100), a cluster (3200), a co-driver display (3300), a head-up display (3400), a side mirror display (3500), and a rear seat display (3600) provided in a vehicle.

[0190] Referring to FIG. 15, the display system (1000) of FIG. 12 can be applied to smart glasses (4000). The smart glasses (4000) may be a wearable electronic device that can be worn on a user's head. For example, the smart glasses (4000) may be a wearable device for augmented reality.

[0191] Smart glasses (4000) may include a frame (4100) and a lens unit (4200). The frame (4100) may include a housing (4110) that supports the lens unit (4200) and a leg unit (4120) for a user to wear. The leg unit (4120) is connected to the housing (4110) via a hinge and may be folded or unfolded relative to the housing (4110).

[0192] The frame (4100) may be equipped with a battery, a touch pad, a microphone, a camera, etc. In addition, the frame (4100) may be equipped with a projector that outputs light, a processor that controls light signals, etc.

[0193] The lens unit (4200) may include an optical member that transmits or reflects light. For example, the lens unit (4200) may include glass, transparent synthetic resin, or the like.

[0194] In order for the user's eyes to recognize visual information, the lens unit (4200) can reflect an image by an optical signal transmitted from the projector of the frame (4100) onto the rear surface of the lens unit (4200) (e.g., the surface facing the user's eyes). For example, the user can recognize visual information such as the time and date displayed on the lens unit (4200). At this time, the projector and / or the lens unit (4200) may be a type of display device. The display device (1200) may be applied to the projector and / or the lens unit (4200).

[0195] Referring to FIG. 16, the display system (1000) of FIG. 12 can be applied to a head-mounted display device (500).

[0196] The head-mounted display device (5000) may be a wearable electronic device that can be worn on a user's head. For example, the head-mounted display device (5000) may be a wearable device for virtual reality or mixed reality.

[0197] A head-mounted display device (5000) may include a head-mounted band (5100) and a display device storage case (5200). The head-mounted band (5100) may be connected to the display device storage case (5200). The head-mounted band (5100) may include horizontal bands and / or vertical bands for securing the head-mounted display device (5000) to a user's head. The horizontal band may surround the side of the user's head, and the vertical band may surround the upper part of the user's head. However, embodiments are not limited thereto. For example, the head-mounted band (5100) may be implemented in the form of eyeglass frames, helmets, etc.

[0198] The display device storage case (5200) can store the display system (1000) and / or the display device (1200).

[0199] Although specific embodiments and applications have been described herein, other embodiments and variations may be derived from the above description. Accordingly, the scope of the present invention is not limited to these embodiments, but extends to the claims set forth below, various obvious modifications, and equivalents.

[0200] The present invention can be applied to display devices and electronic devices including the same. For example, the present invention can be applied to digital TVs, 3D TVs, mobile phones, smart phones, tablet computers, VR devices, PCs, home electronic devices, laptop computers, PDAs, PMPs, digital cameras, music players, portable game consoles, navigation systems, and the like.

[0201] Although the present invention has been described with reference to the above embodiments, it will be understood by those skilled in the art that various modifications and changes can be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below.

Claims

1. Substrate; Sub-pixels arranged on the above substrate; A first shared wiring positioned in a boundary area between the sub-pixels and providing a first voltage to the sub-pixels adjacent to the boundary area; and A display device comprising a second shared wiring arranged in the boundary area and providing a second voltage different from the first voltage to the sub-pixels adjacent to the boundary area.

2. A display device according to claim 1, characterized in that at least one of the first voltage and the second voltage is equally provided to the sub-pixels.

3. In the first paragraph, each of the sub-pixels light emitting element; A first sub-pixel circuit that controls the light-emitting time of the light-emitting element; and A display device characterized by including a second sub-pixel circuit that provides driving current to the light-emitting element.

4. In the third paragraph, the first sub-pixel circuit A first transistor including a control electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; A first capacitor including a first electrode receiving a sweep voltage and a second electrode connected to the first node; A second transistor including a control electrode receiving a first write gate signal, a first electrode receiving a data voltage, and a second electrode connected to the second node; A third transistor including a control electrode receiving the first write gate signal, a first electrode connected to the third node, and a second electrode connected to the first node; A fourth transistor including a control electrode receiving an emission signal, a first electrode receiving a first-first power supply voltage, and a second electrode connected to the second node; A fifth transistor including a control electrode receiving the emission signal, a first electrode connected to the third node, and a second electrode connected to the second sub-pixel circuit; and A display device comprising a sixth transistor including a control electrode receiving a first initialization gate signal, a first electrode receiving a first initialization voltage, and a second electrode connected to the first node.

5. A display device according to claim 4, wherein at least one of the first voltage and the second voltage is any one of the sweep voltage, the emission signal, the first initialization gate signal, the first-first power supply voltage, and the first initialization voltage.

6. In the third paragraph, the second sub-pixel circuit A seventh transistor including a control electrode connected to a fourth node connected to the first sub-pixel circuit, a first electrode connected to a fifth node, and a second electrode connected to a sixth node; A second capacitor including a first electrode receiving the first-second power supply voltage and a second electrode connected to the fourth node; An eighth transistor including a control electrode receiving a second write gate signal, a first electrode receiving a data voltage, and a second electrode connected to the fifth node; A ninth transistor including a control electrode receiving the second write gate signal, a first electrode connected to the sixth node, and a second electrode connected to the fourth node; A tenth transistor including a control electrode receiving an emission signal, a first electrode receiving the first-second power supply voltage, and a second electrode connected to the fifth node; An 11th transistor including a control electrode receiving the emission signal, a first electrode connected to the sixth node, and a second electrode connected to the light-emitting element; A 12th transistor including a control electrode receiving a second initialization gate signal, a first electrode receiving a first initialization voltage, and a second electrode connected to the fourth node; and A display device comprising a 13th transistor including a control electrode receiving a bias gate signal, a first electrode receiving a second initialization voltage, and a second electrode connected to the light emitting element.

7. A display device according to claim 6, wherein at least one of the first voltage and the second voltage is any one of the second write gate signal, the emission signal, the bias gate signal, the second initialization gate signal, the first-second power supply voltage, the first initialization voltage, and the second initialization voltage.

8. In the third paragraph, the light emitting element includes a first electrode connected to the second sub-pixel circuit and a second electrode receiving a second power voltage, A display device, characterized in that one of the first voltage and the second voltage is the second power supply voltage.

9. In the first paragraph, the first shared wiring and the second shared wiring are formed on the same conductive layer, The same challenge layer as above A first conductive pattern forming the first shared wiring and extending in the first direction; and forming the second shared wiring and including a second conductive pattern extending in the first direction; A display device characterized in that the contact hole connected to the first conductive pattern and the contact hole connected to the second conductive pattern are arranged in the first direction.

10. In the 9th paragraph, the first conductive pattern includes an extension portion extending in the first direction and a connection portion protruding in a second direction intersecting the first direction and connected to the contact hole connected to the first conductive pattern, A display device characterized in that the second conductive pattern includes an extension portion extending in the first direction and a connection portion protruding in a direction opposite to the second direction intersecting the first direction and connected to the contact hole connected to the second conductive pattern.

11. In paragraph 1, A display device characterized in that it further includes a third shared wiring that is arranged in the boundary area and provides a third voltage different from the first voltage and the second voltage to the genital sub-pixels adjacent to the boundary area.

12. In the 11th paragraph, the first shared wiring, the second shared wiring, and the third shared wiring are formed on the same conductive layer, The same challenge layer as above A first conductive pattern forming the first shared wiring and extending in a first direction; A second conductive pattern forming the second shared wiring and extending in the first direction; forming the third shared wiring and including a third conductive pattern extending in the first direction; A display device characterized in that the contact hole connected to the first conductive pattern, the contact hole connected to the second conductive pattern, and the contact hole connected to the third conductive pattern are arranged in the first direction.

13. In the 12th paragraph, the first conductive pattern includes an extension portion extending in the first direction and a connection portion protruding in a second direction intersecting the first direction and connected to the contact hole connected to the first conductive pattern, The second conductive pattern includes an extension portion extending in the first direction and a connection portion protruding in a direction opposite to the second direction intersecting the first direction and connected to the contact hole connected to the second conductive pattern, A display device characterized in that the third conductive pattern includes a connecting portion connected to the contact hole connected to the third conductive pattern, a first extension portion connected to the connecting portion in the second direction intersecting the first direction and extending in the first direction, and a second extension portion connected to the connecting portion in a direction opposite to the second direction intersecting the first direction and extending in the first direction.

14. In the first paragraph, the boundary region includes a first boundary region and a second boundary region, The first shared wiring is arranged in the first boundary region and provides the first voltage to the sub-pixels adjacent to the first boundary region, The second shared wiring is arranged in the second boundary area and provides the second voltage to the sub-pixels adjacent to the first boundary area, A third shared wiring arranged in the second boundary area and providing a third voltage different from the first voltage and the second voltage to the sub-pixels adjacent to the second boundary area; and A display device characterized in that it further includes a fourth shared wiring that is arranged in the second boundary area and provides a fourth voltage different from the first voltage, the second voltage, and the third voltage to the sub-pixels adjacent to the second boundary area.

15. In the 14th paragraph, the first to fourth shared wires extend in the first direction, A display device characterized in that the first boundary area and the second boundary area are alternately arranged in a second direction intersecting the first direction.

16. A display device according to claim 1, characterized in that the sub-pixels have a mirror structure based on the boundary area.

17. Substrate; Sub-pixels arranged on the above substrate; A first shared wiring disposed in a boundary area between the sub-pixels and electrically connected to the sub-pixels adjacent to the boundary area; and A display panel comprising a second shared wiring disposed in the boundary area, spaced apart from the first shared wiring, and electrically connected to the sub-pixels adjacent to the boundary area.

18. In the 17th paragraph, the first shared wiring and the second shared wiring are formed on the same conductive layer, The same challenge layer as above A first conductive pattern forming the first shared wiring and extending in the first direction; and forming the second shared wiring and including a second conductive pattern extending in the first direction; A display panel characterized in that the contact hole connected to the first conductive pattern and the contact hole connected to the second conductive pattern are arranged in the first direction.

19. In the 18th paragraph, the first conductive pattern includes an extension portion extending in the first direction and a connection portion protruding in a second direction intersecting the first direction and connected to the contact hole connected to the first conductive pattern, A display panel characterized in that the second conductive pattern includes an extension portion extending in the first direction and a connection portion protruding in a direction opposite to the second direction intersecting the first direction and connected to the contact hole connected to the second conductive pattern.

20. In paragraph 17, A display panel further comprising a third shared wiring disposed in the boundary area, spaced apart from the first and second shared wiring, and electrically connected to the genital sub-pixels adjacent to the boundary area.

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