Display device and display system comprising same

Abstract

This display device comprises a display element layer disposed on a substrate, the display element layer comprising: anode and cathode electrodes; a first reflective electrode disposed on the anode electrode; a second reflective electrode disposed on the cathode electrode; a light-emitting element comprising first and second bonding electrodes; a first organic layer disposed on the light-emitting element, and disposed between the anode and cathode electrodes in planar view; a first transparent electrode electrically and directly connecting the first reflective electrode and first bonding electrode; and a second transparent electrode directly and electrically connecting the second reflective electrode and second bonding electrode.

Description

Display device and display system including the same

[0001] The present disclosure relates to a display device and a display system including the same.

[0002] As information technology advances, the importance of display devices, which serve as a link between users and information, is growing. In response, the use of display devices such as liquid crystal displays (LCDs), organic light-emitting displays (OLEDs), and inorganic light-emitting displays (ILDs), is increasing.

[0003] Some display devices are becoming increasingly miniaturized. Consequently, the size of pixels (or sub-pixels) and the spacing between pixels (or sub-pixels) in display devices (or display panels) are gradually decreasing. Consequently, methods for preventing short-circuiting caused by residue that may occur during the display device manufacturing process may be necessary.

[0004] An object of the present disclosure is to provide a display device and a display system including the same, which are prevented from being short-circuited by residue.

[0005] The technical problems to be achieved by the present disclosure are not limited to those described herein, and other technical problems not mentioned herein will be clearly understood by those skilled in the art through the description of the present disclosure.

[0006] A display device according to embodiments of the present invention may include a display element layer disposed on a substrate, wherein the display element layer may include a light-emitting element including an anode electrode and a cathode electrode, a first reflective electrode disposed on the anode electrode, a second reflective electrode disposed on the cathode electrode, a first bonding electrode, and a second bonding electrode, a first organic layer disposed on the light-emitting element and disposed between the anode electrode and the cathode electrode when viewed in a plan view, a first transparent electrode directly electrically connecting the first reflective electrode and the first bonding electrode; and a second transparent electrode directly electrically connecting the second reflective electrode and the second bonding electrode.

[0007] In embodiments, the display device further includes sub-pixels arranged in a first direction, the anode electrode includes anode electrodes corresponding to each of the sub-pixels, and the first organic layer can extend in the first direction.

[0008] In embodiments, the display device may further include a second organic layer disposed on the light emitting element and disposed between the anode electrodes when viewed in a plan view.

[0009] In embodiments, the second organic layer extends in a second direction that is perpendicular to the first direction, and the first organic layer may be disposed at one end of the second organic layer when viewed in a plan view.

[0010] In embodiments, the second organic layer may extend in the first direction and overlap a portion of each of the anode electrodes.

[0011] In embodiments, the first transparent electrode may be disposed on the second organic layer.

[0012] In embodiments, the display device further includes a third organic layer disposed on the other end of the second organic layer when viewed in a plan view, wherein the third organic layer can extend in the first direction.

[0013] In embodiments, the display device further includes a fourth organic layer disposed on the light-emitting element and extending in the second direction when viewed in a plan view; and a fifth organic layer extending in the first direction when viewed in a plan view, wherein the first organic layer may be disposed at one end of the fourth organic layer and the fifth organic layer may be disposed at the other end of the fourth organic layer.

[0014] In embodiments, the fourth organic layer may overlap a portion of the cathode electrode when viewed in plan view.

[0015] In embodiments, the second transparent electrode may be disposed on the fourth organic layer.

[0016] In embodiments, the fifth organic layer may overlap a portion of the cathode electrode when viewed in plan view.

[0017] In embodiments, the display element layer may further include an overcoat layer disposed within the opening in which the first reflective electrode, the second reflective electrode, and the light-emitting element are disposed.

[0018] In embodiments, the overcoat layer is directly adjacent to the light emitting element.

[0019] In embodiments, the display element layer may be disposed on an upper side of the substrate, and the first bonding electrode and the second bonding electrode may face a lower side of the substrate.

[0020] In embodiments, the anode electrode and the cathode electrode may be disposed in the same layer and may include the same conductive material.

[0021] In embodiments, the first transparent electrode and the second transparent electrode may be patterned after patterning the first organic layer.

[0022] In embodiments, the first reflective electrode and the second reflective electrode may be disposed in the same layer and may include the same reflective conductive material.

[0023] In embodiments, the first transparent electrode and the second transparent electrode may be disposed in the same layer and may include the same transparent conductive material.

[0024] In embodiments, the first bonding electrode and the second bonding electrode are disposed on the side and bottom surfaces of the light-emitting element, and the first bonding electrode and the second bonding electrode may be spaced apart from each other.

[0025] A display system according to embodiments of the present invention includes a display device including a processor providing image data and a control signal; and a display panel configured to display an image corresponding to the image data in response to the control signal, wherein the display panel may include: a light-emitting element including an anode electrode and a cathode electrode; a first reflective electrode disposed on the anode electrode; a second reflective electrode disposed on the cathode electrode; a first bonding electrode and a second bonding electrode; a first organic layer disposed on the light-emitting element and disposed between the anode electrode and the cathode electrode when viewed in a plan view; a first transparent electrode directly electrically connecting the first reflective electrode and the first bonding electrode; and a second transparent electrode directly electrically connecting the second reflective electrode and the second bonding electrode.

[0026] According to an embodiment of the present disclosure, a display device and a display system including the same can be provided, which prevent short circuits due to residue.

[0027] The above and other aspects, features and advantages of specific embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings.

[0028] Figure 1 is a block diagram showing an embodiment of a display device.

[0029] FIG. 2 is a block diagram showing an embodiment of one of the sub-pixels of FIG. 1.

[0030] FIG. 3 is a plan view showing an embodiment of the display panel of FIG. 1.

[0031] Fig. 4 is a cross-sectional view showing an embodiment of the display panel of Fig. 3.

[0032] FIG. 5 is a cross-sectional view showing another embodiment of the display panel of FIG. 3.

[0033] FIG. 6 is a plan view showing an embodiment of one of the pixels of FIG. 3.

[0034] Fig. 7 is a cross-sectional view taken along line II' of Fig. 6.

[0035] FIG. 8a is a plan view showing an embodiment of the present invention including an organic layer.

[0036] Figure 8b is a cross-sectional view taken along line II-II' of Figure 8a.

[0037] FIG. 9 is a plan view showing another embodiment of the present invention including an organic layer.

[0038] FIG. 10 is a plan view showing another embodiment of the present invention including an organic layer.

[0039] FIG. 11a is a plan view showing an embodiment of the present invention including an organic layer.

[0040] Figure 11b is a cross-sectional view taken along line Ⅲ-Ⅲ' of Figure 11a.

[0041] Figure 11c is a cross-sectional view taken along line Ⅳ-Ⅳ' of Figure 11a.

[0042] FIG. 12 is a plan view showing another embodiment of the present invention including an organic layer.

[0043] Figure 13 is a block diagram showing an embodiment of a display system.

[0044] Figures 14 to 17 are perspective views showing application examples of the display system of Figure 13.

[0045] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that in the following description, only the portions necessary for understanding the operation of the present invention will be described, and the description of other portions will be omitted so as not to obscure the gist of the present invention. Furthermore, the present invention is not limited to the embodiments described herein and may be embodied in other forms. However, the embodiments described herein are provided to explain the technical idea of ​​the present invention in sufficient detail to enable those of ordinary skill in the art to easily practice it.

[0046] When an element, such as a layer, is referred to as being "over," "connected to," or "joined to" another element or layer, there may be intervening elements or layers that are directly over, connected to, or joined to the other element or layer. However, when an element or layer is referred to as being "over," "directly connected to," or "directly joined to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" may refer to a physical, electrical, and / or fluid connection, with or without intervening elements. "At least one of X, Y, and Z," and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as one X, one Y, one Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XYY, YZ, ZZ). Herein, "and / or" includes any combination of one or more of those configurations.

[0047] Here, terms such as "first" and "second" may be used to describe various components, but these components are not limited to these terms. These terms are used to distinguish one component from another. Accordingly, a "first component" may refer to a "second component" within the scope disclosed herein.

[0048] Spatially relative terms, such as "below," "above," and the like, may be used for descriptive purposes to describe one element or feature in relation to other elements or features as depicted in the drawings. Spatially relative terms are intended to encompass different orientations during use, operation, and / or manufacturing, in addition to the orientation depicted in the drawings. For example, if a device depicted in the drawings is turned over, elements depicted as being positioned "below" other elements or features are now positioned "above" the other elements or features. Thus, in one embodiment, the term "below" may encompass both above and below. Furthermore, the device may be oriented in other orientations (e.g., rotated 90 degrees or in other directions), and the spatially relative terms used herein are to be interpreted accordingly.

[0049] Various embodiments are described with reference to drawings schematically illustrating ideal embodiments. Accordingly, it is to be understood that the shapes may vary, for example, depending on tolerances and / or manufacturing techniques. Therefore, the embodiments disclosed herein should not be construed as limited to the specific shapes depicted, but rather to encompass, for example, variations in shapes resulting from manufacturing processes. Likewise, the shapes depicted in the drawings may not depict the actual shapes of areas of the device, and the present embodiments are not limited thereto.

[0050] In this field, some embodiments are described and illustrated in the accompanying drawings in terms of functional blocks, units, components, and / or modules. Those skilled in the art will appreciate that these blocks, units, components, and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc., which may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. When the blocks, units, components, and / or modules are implemented by microprocessors or other similar hardware, they may be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and optionally may be driven by firmware and / or software. Furthermore, each block, unit, component, and / or module may be implemented by dedicated hardware, or a combination of dedicated hardware that performs some functions and processors (e.g., one or more programmed microprocessors and associated circuitry) that perform other functions. Additionally, each block, unit, portion, and / or module of some embodiments may be physically separated into two or more interacting and individual blocks, units, portions, and / or modules without departing from the scope of the disclosure. Furthermore, the blocks, units, portions, and / or modules of some embodiments may be physically combined into more complex blocks, units, portions, and / or modules without departing from the scope of the disclosure.

[0051] The term "and / or" includes any combination of one or more of the associated constructs. For example, "A and / or B" can be understood to mean "A, B, or A and B."

[0052] For the purposes of this disclosure, the phrase "at least one of A and B" may be interpreted as A alone, B alone, or any combination of A and B. Additionally, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as X alone, Y alone, Z alone, or any combination of two or more of X, Y, and Z.

[0053] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art relevant to this disclosure. Terms defined in commonly used dictionaries should be interpreted to have a meaning consistent with their meaning in the context of the relevant technology and disclosure, and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0054] Figure 1 is a block diagram showing an embodiment of a display device.

[0055] Referring to FIG. 1, the display device (DD) may include a display panel (DP), a gate driver (12), a data driver (13), a voltage generator (14), and a controller (15).

[0056] A display panel (DP) may include sub-pixels (SP). The sub-pixels (SP) may be connected to a gate driver (12) via first to m-th gate lines (GL1 to GLm). The sub-pixels (SP) may be connected to a data driver (13) via first to n-th data lines (DL1 to DLn).

[0057] The sub-pixels (SP) can generate light of two or more colors. For example, each of the sub-pixels (SP) can generate light of a color such as red, green, blue, cyan, magenta, yellow, etc.

[0058] Two or more sub-pixels among the sub-pixels (SP) can constitute a pixel (PXL). For example, the pixel (PXL) can include three sub-pixels as illustrated in FIG. 1. In this way, the pixel (PXL) can emit light of various colors and various luminances depending on the combination of light emitted from the sub-pixels (SP) included in it.

[0059] The gate driver (12) can be connected to the sub-pixels (SP) arranged in the row direction through the first to m-th gate lines (GL1 to GLm). The gate driver (12) can output gate signals to the first to m-th gate lines (GL1 to GLm) in response to a gate control signal (GCS). In embodiments, the gate control signal (GCS) can include a start signal indicating the start of each frame, a horizontal synchronization signal, and the like.

[0060] The gate driver (12) may be arranged on one side of the display panel (DP). However, embodiments are not limited thereto. For example, the gate driver (12) may be divided into two or more drivers that are physically and / or logically separated, and such drivers may be arranged on one side of the display panel (DP) and on the other side of the display panel (DP) opposite to the one side. In this way, the gate driver (12) may be arranged around the display panel (DP) in various forms according to embodiments.

[0061] The data driver (13) can be connected to the sub-pixels (SP) arranged in the column direction through the first to n-th data lines (DL1 to DLn). The data driver (13) can receive image data (DATA) and a data control signal (DCS) from the controller (15). The data driver (13) can operate in response to the data control signal (DCS). In embodiments, the data control signal (DCS) can include a source start signal, a source shift clock, a source output enable signal, etc.

[0062] The data driver (13) can receive voltages from the voltage generator (14). The data driver (13) can use the received voltages to apply data signals having grayscale voltages corresponding to image data (DATA) to the first to n-th data lines (DL1 to DLn). When a gate signal is applied to each of the first to m-th gate lines (GL1 to GLm), data signals corresponding to the image data (DATA) can be applied to the data lines (DL1 to DLn). Accordingly, the sub-pixels (SP) can generate light corresponding to the data signals, and the display panel (DP) can display an image.

[0063] In embodiments, the gate driver (12) and the data driver (13) may include complementary metal-oxide semiconductor (CMOS) circuit elements.

[0064] The voltage generator (14) can operate in response to a voltage control signal (VCS) from the controller (15). The voltage generator (14) can be configured to generate voltages and provide the generated voltages to components of the display device (DD), such as the gate driver (12), the data driver (13), and the controller (15). The voltage generator (14) can generate voltages by receiving an input voltage from outside the display device (DD) and regulating the received voltage.

[0065] A voltage generator (14) can generate a first power voltage and a second power voltage. The generated first and second power voltages can be provided to the sub-pixels (SP) through power lines (PL). In other embodiments, at least one of the first and second power voltages can be provided from outside the display device (DD).

[0066] The voltage generator (14) can provide various voltages and / or signals. For example, the voltage generator (14) can provide one or more initialization voltages to be applied to the sub-pixels (SP). For example, during a sensing operation for sensing electrical characteristics of transistors and / or light-emitting elements of the sub-pixels (SP), a predetermined reference voltage (e.g., a predetermined or selectable reference voltage) can be applied to the first to n-th data lines (DL1 to DLn), and the voltage generator (14) can generate the reference voltage and transmit it to the data driver (13). For example, during a display operation for displaying an image on the display panel (DP), common pixel control signals can be applied to the sub-pixels (SP), and the voltage generator (14) can generate the pixel control signals. In embodiments, the voltage generator (14) can provide pixel control signals to the sub-pixels (SP) through the pixel control lines (PXCL). Although FIG. 1 illustrates that pixel control lines (PXCL) can be connected between a voltage generator (14) and a display panel (DP), embodiments are not limited thereto. For example, pixel control lines (PXCL) can be connected between a gate driver (12) and a display panel (DP). In this case, pixel control signals can be transmitted from a voltage generator (140) to the pixel control lines (PXCL) through the gate driver (12).

[0067] The controller (15) can control all operations of the display device (DD). The controller (15) can receive input image data (IMG) and a corresponding control signal (CTRL) from the outside. In response to the control signal (CTRL), the controller (15) can provide a gate control signal (GCS), a data control signal (DCS), and a voltage control signal (VCS).

[0068] The controller (15) can convert input image data (IMG) to be suitable for a display device (DD) or a display panel (DP) and output image data (DATA). In embodiments, the controller (15) can output image data (DATA) by aligning the input image data (IMG) to be suitable for sub-pixels (SP) in a row unit.

[0069] Two or more components of the data driver (13), the voltage generator (14), and the controller (15) may be mounted on a single integrated circuit. As illustrated in FIG. 1, the data driver (13), the voltage generator (14), and the controller (15) may be included in a driver integrated circuit (DIC). In this case, the data driver (13), the voltage generator (14), and the controller (15) may be functionally separate components within a single driver integrated circuit (DIC). In other embodiments, at least one of the data driver (13), the voltage generator (14), and the controller (15) may be provided as a separate component from the driver integrated circuit (DIC).

[0070] Fig. 2 is a block diagram showing an embodiment of one of the sub-pixels of Fig. 1. In Fig. 2, a sub-pixel (SPij) arranged in an ith row (i is an integer greater than or equal to 1 and less than or equal to m) and a jth column (j is an integer greater than or equal to 1 and less than or equal to n) among the sub-pixels (SP) of Fig. 1 is exemplarily illustrated.

[0071] Referring to FIG. 2, a sub-pixel (SPij) may include a sub-pixel circuit (SPC) and a light-emitting element (LD).

[0072] A light emitting element (LD) can be connected between a first power supply voltage node (VDDN) and a second power supply voltage node (VSSN). The first power supply voltage node (VDDN) can be connected to one of the power supply lines (PL) of FIG. 1 and can receive a first power supply voltage. The second power supply voltage node (VSSN) can be connected to another of the power supply lines (PL) of FIG. 1 and can receive a second power supply voltage. The first power supply voltage can have a voltage level greater than the second power supply voltage.

[0073] A light emitting element (LD) may be connected between an anode electrode (AE) and a cathode electrode (CE). The anode electrode (AE) may be connected to a first power voltage node (VDDN) through a sub-pixel circuit (SPC). For example, the anode electrode (AE) may be connected to the first power voltage node (VDDN) through one or more transistors included in the sub-pixel circuit (SPC). The cathode electrode (CE) may be connected to a second power voltage node (VSSN). The light emitting element (LD) may be configured to emit light according to a current flowing from the anode electrode (AE) to the cathode electrode (CE).

[0074] The sub-pixel circuit (SPC) may be connected to the ith gate line (GLi) among the first to mth gate lines (GL1 to GLm) of FIG. 1 and to the jth data line (DLj) among the first to nth data lines (DL1 to DLn) of FIG. 1. In response to a gate signal received through the ith gate line (GLi), the sub-pixel circuit (SPC) controls the light-emitting element (LD) to emit light according to a data signal received through the jth data line (DLj). In embodiments, the sub-pixel circuit (SPC) may be further connected to the pixel control lines (PXCL) of FIG. 1. In this case, the sub-pixel circuit (SPC) may further control the light-emitting element (LD) in response to pixel control signals received through the pixel control lines (PXCL).

[0075] For these operations, a sub-pixel circuit (SPC) may include circuit elements, such as transistors and one or more capacitors.

[0076] The transistors of the sub-pixel circuit (SPC) may include P-type transistors and / or N-type transistors. In embodiments, the transistors of the sub-pixel circuit (SPC) may include MOSFETs (Metal-Oxide-Silicon-Field-Effect Transistors). In embodiments, the transistors of the sub-pixel circuit (SPC) may include an amorphous silicon semiconductor, a monocrystalline silicon semiconductor, a polycrystalline silicon semiconductor, an oxide semiconductor, or the like.

[0077] FIG. 3 is a plan view showing an embodiment of the display panel of FIG. 1.

[0078] Referring to FIG. 3, a display panel (DP) may include a display area (DA) and a non-display area (NDA). The display panel (DP) may display an image through the display area (DA). The non-display area (NDA) may be positioned around the display area (DA).

[0079] A display panel (DP) may include sub-pixels (SP) in a display area (DA). The sub-pixels (SP) may be arranged in a first direction (DR1) and a second direction (DR2) intersecting the first direction (DR1). For example, the sub-pixels (SP) may be arranged in a matrix form along the first direction (DR1) and the second direction (DR2). As another example, the sub-pixels (SP) may be arranged in a zigzag form along the first direction (DR1) and the second direction (DR2). The arrangement of the sub-pixels (SP) may vary depending on the embodiments. The first direction (DR1) may be a row direction, and the second direction (DR2) may be a column direction.

[0080] Two or more sub-pixels among the sub-pixels (SP) can constitute one pixel (PXL). In FIG. 3, the pixel (PXL) is illustrated as including three sub-pixels (SP1 to SP3), but embodiments are not limited thereto. For example, the pixel (PXL) can include two sub-pixels. Hereinafter, for convenience of explanation, it is assumed that the pixel (PXL) includes first to third sub-pixels (SP1 to SP3).

[0081] Each of the first to third sub-pixels (SP1 to SP3) can generate light of one of various colors, such as red, green, blue, cyan, magenta, yellow, etc. Hereinafter, for the sake of clarity and concise explanation, it is assumed that the first sub-pixel (SP1) is configured to generate red color light, the second sub-pixel (SP2) is configured to generate green color light, and the third sub-pixel (SP3) generates blue color light.

[0082] Each of the first to third sub-pixels (SP1 to SP3) may include at least one light-emitting element configured to generate light. In embodiments, the light-emitting elements of the first to third sub-pixels (SP1 to SP3) may generate light of the same color. For example, the light-emitting elements of the first to third sub-pixels (SP1 to SP3) may generate blue light. In other embodiments, the light-emitting elements of the first to third sub-pixels (SP1 to SP3) may generate light of different colors. For example, the light-emitting elements of the first to third sub-pixels (SP1 to SP3) may generate red light, green light, and blue light, respectively.

[0083] As a display panel (DP), a self-luminous display panel such as a light-emitting diode display panel (LED display panel) that uses micro-scale or nano-scale light-emitting diodes as light-emitting elements, or an organic light-emitting display panel (OLED panel) that uses organic light-emitting diodes as light-emitting elements, can be used.

[0084] Components for controlling sub-pixels (SP) may be placed in the non-display area (NDA). Wires connected to the sub-pixels (SP), for example, the first to m-th gate lines (GL1 to GLm), the first to n-th data lines (DL1 to DLn), the power lines (PL), and the pixel control lines (PXCL) of FIG. 1, may be placed in the non-display area (NDA).

[0085] At least one of the gate driver (12), the data driver (13), the voltage generator (14), and the controller (15) of FIG. 1 may be disposed in a non-display area (NDA) of the display panel (DP). In embodiments, the gate driver (12) may be disposed in the non-display area (NDA). In this case, the data driver (13), the voltage generator (14), and the controller (15) may be implemented as a driver integrated circuit (DIC) of FIG. 1 that is separate from the display panel (DP), and the driver integrated circuit (DIC) may be connected to wires disposed in the non-display area (NDA). In other embodiments, the gate driver (12) may be implemented as a single integrated circuit that is separate from the display panel (DP) together with the data driver (13), the voltage generator (14), and the controller (15).

[0086] In embodiments, the display area (DA) may have various shapes. The display area (DA) may have the shape of a closed loop including straight and / or curved edges. For example, the display area (DA) may have shapes such as a polygon, a circle, a semicircle, or an ellipse.

[0087] In some embodiments, the display panel (DP) may have a flat display surface. In other embodiments, the display panel (DP) may have an at least partially rounded display surface. In some embodiments, the display panel (DP) may be bendable, foldable, or rollable. In such cases, the display panel (DP) and / or the substrate of the display panel (DP) may include materials having flexible properties.

[0088] Fig. 4 is a cross-sectional view showing an embodiment of the display panel of Fig. 3.

[0089] Referring to FIG. 4, the display panel (DP) may include a substrate (SUB), and a pixel circuit layer (PCL), a display element layer (DPL), and a light functional layer (LFL) that are sequentially laminated in a third direction (DR3) intersecting the first and second directions (DR1, DR2) on the substrate (SUB).

[0090] The substrate (SUB) may be made of an insulating material such as glass or resin. For example, the substrate (SUB) may include a glass substrate. As another example, the substrate (SUB) may include a polyimide (PI) substrate. As yet another example, the substrate (SUB) may include a silicon wafer substrate formed using a semiconductor process.

[0091] In embodiments, the substrate (SUB) may be made of a flexible material that is bendable or foldable, and may have a single-layer structure or a multi-layer structure. For example, the flexible material may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose, and cellulose acetate propionate. However, the embodiments are not limited thereto.

[0092] A pixel circuit layer (PCL) may be arranged on a substrate (SUB). The pixel circuit layer (PCL) may include insulating layers and semiconductor patterns and conductive patterns arranged between the insulating layers. The conductive patterns of the pixel circuit layer (PCL) may function as circuit elements, wirings, etc.

[0093] The circuit elements of the pixel circuit layer (PCL) may include a sub-pixel circuit (SPC, see FIG. 2) of each of the sub-pixels (SP) of FIG. 3. In other words, the circuit elements of the pixel circuit layer (PCL) may be provided as transistors and one or more capacitors of the sub-pixel circuit (SPC).

[0094] The wiring of the pixel circuit layer (PCL) may include wiring connected to sub-pixels (SP). The wiring of the pixel circuit layer (PCL) may include various signal lines and / or voltage lines necessary to drive the display element layer (DPL).

[0095] A display element layer (DPL) may be arranged on a pixel circuit layer (PCL). The display element layer (DPL) may include light-emitting elements of sub-pixels (SP).

[0096] A light-functional layer (LFL) may be disposed on a display element layer (DPL). The light-functional layer (LFL) may include light-converting patterns having color-converting particles and / or scattering particles. For example, the color-converting particles may include quantum dots. The quantum dots may change the wavelength (or color) of light emitted from the display element layer (DPL). The light-functional layer (LFL) may further include light-scattering patterns having scattering particles. In embodiments, the light-converting patterns and the light-scattering patterns may be omitted.

[0097] The light function layer (LFL) may further include a color filter layer including color filters. The color filter may selectively transmit light of a specific wavelength (or color). In embodiments, the color filter layer may be omitted.

[0098] A window may be provided on a light-functional layer (LFL) to protect an exposed surface (or upper surface) of a display panel (DP). The window may protect the display panel (DP) from external impact. The window may be bonded to the light-functional layer (LFL) via an optically transparent adhesive (or bonding) member. The window may have a multilayer structure selected from a glass substrate, a plastic film, and a plastic substrate. This multilayer structure may be formed through a continuous process or an bonding process using an adhesive layer. All or a portion of the window may be flexible.

[0099] FIG. 5 is a cross-sectional view showing another embodiment of the display panel of FIG. 3.

[0100] Referring to FIG. 5, the display panel (DP') may include a substrate (SUB), a pixel circuit layer (PCL), a display element layer (DPL), an input sensing layer (ISL), and a light function layer (LFL). The substrate (SUB), the pixel circuit layer (PCL), the display element layer (DPL), and the light function layer (LFL) are configured similarly to the substrate (SUB), the pixel circuit layer (PCL), the display element layer (DPL), and the light function layer (LFL) described with reference to FIG. 4, respectively. Hereinafter, redundant descriptions are omitted.

[0101] An input sensing layer (ISL) can detect user input on the upper surface (or display surface) of a display panel (DP'). The input sensing layer (ISL) may include configurations suitable for detecting external objects, such as a user's hand or pen. For example, the input sensing layer (ISL) may include touch electrodes.

[0102] FIG. 6 is a plan view showing an embodiment of one of the pixels of FIG. 3.

[0103] Referring to FIG. 6, a pixel (PXL) may include first to third sub-pixels (SP1 to SP3). The first to third sub-pixels (SP1 to SP3) may be arranged in a first direction (DR1). However, the arrangement of the pixel (PXL) is not limited thereto and may vary depending on embodiments. For example, the first to third sub-pixels (SP1 to SP3) may be arranged in a zigzag pattern.

[0104] First to third anode electrodes (AE1 to AE3) may be respectively disposed in the first to third sub-pixels (SP1 to SP3). The first anode electrode (AE1) may be provided as an anode electrode (AE, see FIG. 2) connected to a sub-pixel circuit (SPC, see FIG. 2) of the first sub-pixel (SP1). The second anode electrode (AE2) may be provided as an anode electrode (AE) connected to a sub-pixel circuit (SPC) of the second sub-pixel (SP2). The third anode electrode (AE3) may be provided as an anode electrode (AE) connected to a sub-pixel circuit (SPC) of the third sub-pixel (SP3).

[0105] The cathode electrode (CE) may be spaced apart from the first to third anode electrodes (AE1 to AE3). The cathode electrode (CE) may be arranged at the same height as the first to third anode electrodes (AE1 to AE3). The cathode electrode (CE) may be spaced apart from the first to third anode electrodes (AE1 to AE3) in a second direction (DR2). In embodiments, the cathode electrode (CE) may extend in the first direction (DR1) and may be used as a common electrode for the pixel (PXL) and other pixels adjacent to the pixel (PXL). Although not shown, the cathode electrode (CE) may extend in the second direction (DR2) as well as the first direction (DR1) and may be used as a common electrode for all of the sub-pixels (SP) of FIG. 3. In this way, the cathode electrode (CE) may have various shapes. In embodiments, the first to third anode electrodes (AE1 to AE3) and the cathode electrode (CE) may include the same conductive material.

[0106] First to third light-emitting elements (LD1 to LD3) may be arranged on first to third anode electrodes (AE1 to AE3) and a cathode electrode (CE). The first light-emitting element (LD1) may be electrically connected to the first anode electrode (AE1) and the cathode electrode (CE). The first light-emitting element (LD1) may be provided as a light-emitting element (LD, see FIG. 2) connected to a sub-pixel circuit (SPC) of a first sub-pixel (SP1). The second light-emitting element (LD2) may be electrically connected to the second anode electrode (AE2) and the cathode electrode (CE). The second light-emitting element (LD2) may be provided as a light-emitting element (LD) connected to a sub-pixel circuit (SPC) of a second sub-pixel (SP2). The third light-emitting element (LD3) may be electrically connected to the third anode electrode (AE3) and the cathode electrode (CE). The third light-emitting element (LD3) may be provided as a light-emitting element (LD) connected to the sub-pixel circuit (SPC) of the third sub-pixel (SP3).

[0107] The first light-emitting element (LD1), the second light-emitting element (LD2), and the third light-emitting element (LD3) may be inorganic light-emitting diodes containing inorganic light-emitting materials. However, embodiments are not limited thereto, and for example, organic light-emitting diodes may be used.

[0108] Fig. 7 is a cross-sectional view taken along line II' of Fig. 6.

[0109] Referring to FIGS. 6 and 7, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially arranged on a substrate (SUB).

[0110] A pixel circuit layer (PCL) may include insulating layers, semiconductor patterns, and conductive patterns stacked on a substrate (SUB). The insulating layers may include a buffer layer (BFL), one or more interlayer insulating layers (ILD), and one or more passivation layers (PSV1, PSV2). The semiconductor patterns and conductive patterns may be positioned between the insulating layers. The conductive patterns may include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0111] As described with reference to FIG. 2, each of the first to third sub-pixels (SP1 to SP3) may include a sub-pixel circuit (SPC, see FIG. 2) including transistors and one or more capacitors. The semiconductor patterns and conductive patterns of the pixel circuit layer (PCL) may function as transistors and capacitors of the sub-pixel circuit (SPC). In addition, the conductive patterns of the pixel circuit layer (PCL) may further function as wirings, for example, the first to m-th gate lines (GL1 to GLm), the first to n-th data lines (DL1 to DLn), the power lines (PL), and the pixel control lines (PXCL) of FIG. 1.

[0112] A buffer layer (BFL) may be disposed on one surface of a substrate (SUB). The buffer layer (BFL) may prevent impurities from diffusing into circuit elements and wirings included in a pixel circuit layer (PCL). The buffer layer (BFL) may include an inorganic insulating layer including an inorganic material. In embodiments, the buffer layer (BFL) may include at least one of a metal oxide such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). The buffer layer (BFL) may be provided as a single layer or multiple layers. When the buffer layer (BFL) is provided as multiple layers, each layer may be formed of the same material or different materials.

[0113] In embodiments, one or more barrier layers may be disposed between the substrate (SUB) and the buffer layer (BFL). Each of the barrier layers may comprise polyimide.

[0114] A transistor (T_SP1) may be placed on the buffer layer (BFL). The transistor (T_SP1) may be any one of the transistors of the sub-pixel circuit (SPC) included in the first sub-pixel (SP1). For example, the transistor (T_SP1) may be understood as a transistor connected to the first anode electrode (AE1) among the transistors of the sub-pixel circuit (SPC).

[0115] The transistor (T_SP1) may include a semiconductor pattern (SCP), a gate electrode (GE), a first terminal (ET1), and a second terminal (ET2). The first terminal (ET1) may be either a source electrode or a drain electrode, and the second terminal (ET2) may be the other of the source electrode and the drain electrode. For example, the first terminal (ET1) may be a source electrode, and the second terminal (ET2) may be a drain electrode.

[0116] A semiconductor pattern (SCP) may be disposed on a buffer layer (BFL). The semiconductor pattern (SCP) may include a first contact region contacting a first terminal (ET1) and a second contact region contacting a second terminal (ET2). A region between the first contact region and the second contact region may be a channel region. The channel region may overlap with a gate electrode (GE) of the transistor (T_SP1). The channel region may be a semiconductor pattern that is not doped with impurities and may be an intrinsic semiconductor. The first contact region and the second contact region may be semiconductor patterns doped with impurities. For example, a p-type impurity may be used as the impurity, but embodiments are not limited thereto.

[0117] The semiconductor pattern (SCP) may include at least one of various types of semiconductors, for example, an amorphous silicon semiconductor, a monocrystalline silicon semiconductor, a polycrystalline silicon semiconductor, a low-temperature polysilicon semiconductor, and an oxide semiconductor.

[0118] Interlayer insulating layers (ILDs) sequentially stacked on a semiconductor pattern (SCP) may be arranged. The interlayer insulating layers (ILDs) may be inorganic insulating layers including an inorganic material. For example, each of the interlayer insulating layers (ILDs) may include at least one of a metal oxide such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). However, the interlayer insulating layers (ILDs) are not limited thereto. For example, at least one of the interlayer insulating layers (ILDs) may include an organic insulating layer including an organic material.

[0119] Interlayer insulating layers (ILDs) can electrically isolate conductive patterns and / or semiconductor patterns disposed between the interlayer insulating layers (ILDs). For example, the interlayer insulating layers (ILDs) can include a gate insulating layer (GI) disposed on a semiconductor pattern (SCP). The gate insulating layer (GI) can be disposed between the semiconductor pattern (SCP) and the gate electrode (GE) such that the gate electrode (GE) is spaced apart from the semiconductor pattern (SCP). In embodiments, the gate insulating layer (GI) can be provided over the entire surface of the semiconductor pattern (SCP) and the buffer layer (BFL) to cover (or overlap) the semiconductor pattern (SCP) and the buffer layer (BFL). As the number of layers required for forming the conductive patterns and / or semiconductor patterns increases, the number of interlayer insulating layers (ILDs) can increase.

[0120] A gate electrode (GE) may be disposed on a gate insulating layer (GI). The gate electrode (GE) may overlap a channel region of a semiconductor pattern (SCP). In embodiments, the gate electrode (GE) may be provided as a single layer including at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag). In embodiments, the gate electrode (GE) may be provided as a multilayer including at least one material selected from the group consisting of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), and silver (Ag), which are low-resistance materials. However, embodiments are not limited thereto.

[0121] The first and second terminals (ET1, ET2) may be disposed on interlayer insulating layers (ILD). The first and second terminals (ET1, ET2) may contact a semiconductor pattern (SCP) through contact holes penetrating the interlayer insulating layers (ILD). The first and second terminals (ET1, ET2) may contact first and second contact areas of the semiconductor pattern (SCP), respectively. Each of the first and second terminals (ET1, ET2) may include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0122] Although the first and second terminals (ET1, ET2) are illustrated as separate electrodes electrically connected to the semiconductor pattern (SCP), embodiments are not limited thereto. In embodiments, the first terminal (ET1) may be a first contact region adjacent to one side of a channel region of the semiconductor pattern (SCP), and the second terminal (ET2) may be a second contact region adjacent to the other side of the channel region. In this case, the first terminal (ET1) may be electrically connected to the light emitting element (LD) via a connecting means, such as a bridge electrode, disposed on at least one of the interlayer insulating layers (ILD).

[0123] In embodiments, the transistor (T_SP1) may be formed of a low-temperature polysilicon transistor. However, embodiments are not limited thereto. For example, the transistor (T_SP1) may also be formed of an oxide semiconductor transistor. In embodiments, the sub-pixel circuit of the first sub-pixel (SP1) may include transistors of different types. For example, the transistor (T_SP1) may be formed of a low-temperature polysilicon transistor, and the other transistors of the first sub-pixel (SP1) may be formed of oxide semiconductor transistors. In this case, the oxide semiconductor of the oxide semiconductor transistor may be formed on at least one of the interlayer insulating layers (ILD) other than the insulating layer on which the semiconductor pattern (SCP) of the transistor (T_SP1) is formed.

[0124] In the embodiments, the transistor (T_SP1) is described as an example of a transistor having a top gate structure, but the embodiments are not limited thereto. For example, the transistor (T_SP1) may be a transistor having a bottom gate structure. The structure of the transistor (T_SP1) may be changed in various ways.

[0125] At least some of the various wirings of the display panel (DP) and / or display device (DD) may be further arranged on the interlayer insulating layers (ILD).

[0126] A first passivation layer (PSV1) may be disposed on the interlayer insulating layers (ILD) and the first and second terminals (ET1, ET2). The passivation layer may also be referred to as a protective layer or a via layer. The first passivation layer (PSV1) protects components disposed thereunder and may provide a flat upper surface.

[0127] A connection pattern (CP) may be arranged on the first passivation layer (PSV1). The connection pattern (CP) may penetrate the first passivation layer (PSV1) and be connected to the first terminal (ET1) of the transistor (T_SP1). The connection pattern (CP) may include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0128] At least some of the various wires of the display panel (DP) and / or the display device (DD) may be further arranged on the first passivation layer (PSV1).

[0129] A second passivation layer (PSV2) may be disposed on the connection pattern (CP) and the first passivation layer (PSV1). The second passivation layer (PSV2) may protect components disposed thereunder and provide a flat upper surface.

[0130] Each of the first and second passivation layers (PSV1, PSV2) may include an inorganic insulating layer including an inorganic material and / or an organic insulating layer including an organic material. The inorganic insulating layer may include, for example, at least one of a metal oxide such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). The organic insulating layer may include, for example, at least one of an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and a benzocyclobutene resin.

[0131] The first and second passivation layers (PSV1, PSV2) may comprise the same material as one of the interlayer insulating layers (ILD), but embodiments are not limited thereto. Each of the first and second passivation layers (PSV1, PSV2) may be provided as a single layer, but may also be provided as multiple layers.

[0132] A display element layer (DPL) may be disposed on the second passivation layer (PSV2). The display element layer (DPL) may include a first anode electrode (AE1), a cathode electrode (CE), first and second reflective electrodes (RFE1, RFE2), a first light-emitting element (LD1), an overcoat layer (OCL), a third passivation layer (PSV3), and a capping layer (CPL).

[0133] A first anode electrode (AE1) and a cathode electrode (CE) can be arranged on the pixel circuit layer (PCL).

[0134] The first anode electrode (AE1) can be electrically connected to the connection pattern (CP) through a contact hole penetrating the second passivation layer (PSV2). In this way, the first anode electrode (AE1) can be electrically connected to the first transistor (T_SP1).

[0135] The cathode electrode (CE) may be spaced apart from the first anode electrode (AE1) in the first direction (DR1). The cathode electrode (CE) may be electrically connected to the second power voltage node (VSSN) of FIG. 2. Accordingly, the second power voltage applied to the second power voltage node (VSSN) may be transmitted to the cathode electrode (CE).

[0136] A first reflective electrode (RFE1) may be disposed on the first anode electrode (AE1). The first reflective electrode (RFE1) may be disposed on a side surface of the first anode electrode (AE1). For example, the first reflective electrode (RFE1) may be disposed to surround the first anode electrode (AE1).

[0137] A second reflective electrode (RFE2) may be disposed on the cathode electrode (CE). The second reflective electrode (RFE2) may be disposed on a side of the cathode electrode (CE). For example, the second reflective electrode (RFE2) may be disposed to surround the cathode electrode (CE).

[0138] The first and second reflective electrodes (RFE1, RFE2) may include conductive materials suitable for reflecting light. Accordingly, the light emission efficiency of the first light-emitting element (LD1) may be improved. The first and second reflective electrodes (RFE1, RFE2) may include the same reflective conductive material. In embodiments, the first and second reflective electrodes (RFE1, RFE2) may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. However, the embodiments are not limited thereto.

[0139] An overcoat layer (OCL) may be disposed within a first opening (OP1) in which the first and second reflective electrodes (RFE1, RFE2) and the first light-emitting element (LD1) are disposed. The overcoat layer (OCL) may fix the first light-emitting element (LD1) so that it does not move. The overcoat layer (OCL) may protect components disposed thereunder from foreign substances such as dust and moisture. For example, the overcoat layer (OCL) may include at least one of an inorganic insulating layer and an organic insulating layer. For example, the overcoat layer (OCL) may include epoxy, but embodiments are not limited thereto.

[0140] The first light-emitting element (LD1) may include first and second bonding electrodes (BDE1, BDE2) facing in the same direction (e.g., opposite to the third direction (DR3)).

[0141] The first bonding electrode (BDE1) may be arranged in contact with the side surface of the first light-emitting element (LD1) and the lower surface of the first light-emitting element (LD1). The first bonding electrode (BDE1) may be arranged on the overcoat layer (OCL), and may be arranged between the first light-emitting element (LD1) and the overcoat layer (OCL).

[0142] The first bonding electrode (BDE1) may be electrically connected to a first semiconductor layer (not shown) included in the first light-emitting element (LD1). The first semiconductor layer may include, for example, at least one p-type semiconductor layer. For example, the first semiconductor layer may include at least one semiconductor material selected from the group consisting of gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be a p-type semiconductor layer doped with a first conductive dopant (or p-type dopant), such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), or the like. However, the material constituting the first semiconductor layer is not limited thereto, and various other materials may also constitute the first semiconductor layer. In one embodiment of the present invention, the first semiconductor layer may include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or p-type dopant).

[0143] The second bonding electrode (BDE2) may be arranged in contact with the side surface of the first light-emitting element (LD1) and the lower surface of the first light-emitting element (LD1). The second bonding electrode (BDE2) may be arranged on the overcoat layer (OCL), and may be arranged between the first light-emitting element (LD1) and the overcoat layer (OCL). The first bonding electrode (BDE1) and the second bonding electrode (BDE2) may be spaced apart from each other.

[0144] The second bonding electrode (BDE2) may be connected to a second semiconductor layer (not shown). The second semiconductor layer may include, for example, at least one n-type semiconductor layer. For example, the second semiconductor layer may include at least one semiconductor material selected from the group consisting of gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be an n-type semiconductor layer doped with a first conductive dopant (or n-type dopant), such as silicon (Si), germanium (Ge), or tin (Sn). However, the material constituting the second semiconductor layer is not limited thereto, and various other materials may also constitute the second semiconductor layer. In one embodiment of the present invention, the second semiconductor layer may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or n-type dopant).

[0145] The first transparent electrode (ITO1) can directly electrically connect the first reflective electrode (RFE1) and the first bonding electrode (BDE1). Accordingly, the first bonding electrode (BDE1) can be electrically connected to the first anode electrode (AE1) via the first transparent electrode (ITO1) and the first reflective electrode (RFE1).

[0146] The first transparent electrode (ITO1) can be disposed on the side of the first light-emitting element (LD1), the exposed portion of the first bonding electrode (BDE1), the exposed portion of the overcoat layer (OCL), and the exposed portion of the first reflective electrode (RFE1).

[0147] The second transparent electrode (ITO2) can directly electrically connect the second reflective electrode (RFE2) and the second bonding electrode (BDE2). Accordingly, the second bonding electrode (BDE2) can be electrically connected to the cathode electrode (CE) via the second transparent electrode (ITO2) and the second reflective electrode (RFE2).

[0148] The second transparent electrode (ITO2) can be disposed on the side of the first light-emitting element (LD1), the exposed portion of the second bonding electrode (BDE2), the exposed portion of the overcoat layer (OCL), and the exposed portion of the second reflective electrode (RFE2).

[0149] In embodiments, the first and second transparent electrodes (ITO1, ITO2) may be configured to be substantially transparent or translucent to satisfy a predetermined light transmittance (e.g., a predetermined or selectable light transmittance). The first transparent electrode (ITO1) and the second transparent electrode (ITO2) may be disposed on the same display element layer (DPL) and may include the same transparent conductive material. In embodiments, the first and second transparent electrodes (ITO1, ITO2) may include at least one of various transparent conductive materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), etc. However, the material of the first and second transparent electrodes (ITO1, ITO2) is not limited thereto.

[0150] However, when the width between the first light-emitting element (LD1) and the second light-emitting element (LD2) is narrow during the patterning process of the first and second transparent electrodes (ITO1, ITO2), the first and second transparent electrodes (ITO1, ITO2) may be flattened without following the lower step of the first light-emitting element (LD1) and the second light-emitting element (LD2), resulting in residue.

[0151] Accordingly, a short circuit may occur between at least one of the first to third anode electrodes (AE1 to AE3) and the cathode electrode (CE), or a short circuit may occur between the first to third anode electrodes (AE1 to AE3). To prevent a short circuit due to residue, an organic layer may be disposed before patterning the first and second transparent electrodes (ITO1, ITO2). A more detailed description of this will be provided later with reference to FIGS. 8A to 12.

[0152] Although it is illustrated that the first and second transparent electrodes (ITO1, ITO2) may not be disposed on top of the first light-emitting element (LD1), this is not limited to the first and second transparent electrodes (ITO1, ITO2) and, according to an embodiment of the present invention, the first and second transparent electrodes (ITO1, ITO2) may be disposed from the top of the first light-emitting element (LD1) to the first and second reflective electrodes (RFE1, RF2).

[0153] A third passivation layer (PSV3) may be disposed on the first and second transparent electrodes (ITO1, ITO2). The third passivation layer (PSV3) may protect components disposed thereunder and provide a flat upper surface. The third passivation layer (PSV3) may include the same material as either of the first and second passivation layers (PSV1, PSV2), but embodiments are not limited thereto.

[0154] In embodiments, the third passivation layer (PSV3) may not be disposed on the upper surface (LTS) of the first light-emitting element (LD1). The first light-emitting element (LD1) may protrude into the light-functional layer (LFL). The first light-emitting element (LD1) may be at least partially positioned within the second opening (OP2) of the bank (BNK). For example, the height of the upper surface (LTS) of the first light-emitting element (LD1) from the substrate (SUB) may be greater than the lowermost edge (RBE) of the reflective layer (RFL). Accordingly, light emitted from the first light-emitting element (LD1) may be provided to the light-functional layer (LFL) at a relatively high rate.

[0155] The capping layer (CPL) may be disposed on the third passivation layer (PSV3). The capping layer (CPL) may protect components under the capping layer (CPL), such as the first light-emitting element (LD1), from external moisture and humidity. In embodiments, the capping layer (CPL) may not be disposed on the upper surface of the first light-emitting element (LD1). In other embodiments, the capping layer (CPL) may entirely cover the first light-emitting element (LD1) and the third passivation layer (PSV3). The capping layer (CPL) may include at least one of a metal oxide, such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). However, the material of the capping layer (CPL) is not limited thereto.

[0156] The pixel circuit layer (PCL) and display element layer (DPL) of the first sub-pixel (SP1) have been described above. Each of the second and third sub-pixels (SP2, SP3) of FIG. 6 may also be configured similarly to the first sub-pixel (SP1), unless otherwise described herein.

[0157] A light functional layer (LFL) may be disposed on a capping layer (CPL). The light functional layer (LFL) may include a bank (BNK), a reflective layer (RFL), a fourth passivation layer (PSV4), a first light conversion pattern (CCP1), a low-refractive-index layer (LRL), and a color filter layer (CFL).

[0158] A bank (BNK) may be arranged on a capping layer (CPL). The bank (BNK) may have a second opening (OP2) overlapping a first opening (OP1). The bank (BNK) may be configured to include a light-blocking material to prevent light mixing between adjacent sub-pixels. In embodiments, the bank (BNK) may include an organic material. For example, the bank (BNK) may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0159] A reflective layer (RFL) may be disposed on the side surfaces of the bank (BNK) adjacent to the second opening (OP2). The reflective layer (RFL) is configured to reflect incident light, thereby improving light emission efficiency. The reflective layer (RFL) may include a material suitable for reflecting light. The reflective layer (RFL) may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. However, the embodiments are not limited thereto.

[0160] On the capping layer (CPL), a fourth passivation layer (PSV4) may be disposed within the second opening (OP2). The fourth passivation layer (PSV4) may protect components disposed thereunder and provide a flat upper surface. The fourth passivation layer (PSV4) may include the same material as at least one of the first to third passivation layers (PSV1 to PSV3), but embodiments are not limited thereto.

[0161] On the fourth passivation layer (PSV4), a first light conversion pattern (CCP1) can be arranged within a second opening (OP2).

[0162] The first light conversion pattern (CCP1) may include color conversion particles and / or scattering particles. The color conversion particles may change the wavelength of incident light to convert the incident light into light of a different color. The color conversion particles may scatter the incident light. In embodiments, the color conversion particles may be quantum dots. The scattering particles may scatter the incident light.

[0163] The first sub-pixel (SP1) may be a red sub-pixel. When the first light-emitting element (LD1) emits blue light, the first light conversion pattern (CCP1) may include first color conversion particles (QD1) configured to convert blue light into red light. When the first light-emitting element (LD1) emits red light, the first light conversion pattern (CCP1) may include scattering particles. In this way, the particles included in the first light-conversion pattern (CCP1) may be variously changed depending on the first light-emitting element (LD1).

[0164] A low-refractive-index layer (LRL) may be disposed on the bank (BNK), the reflective layer (RFL), and the first light conversion pattern (CCP1). The low-refractive-index layer (LRL) may have a lower refractive index than the first light conversion pattern (CCP1). The first color filter (CF1) may have a higher refractive index than the low-refractive-index layer (LRL). However, embodiments are not limited thereto, and the first color filter (CF1) may have a refractive index that is lower than or equal to the low-refractive-index layer (LRL). The low-refractive-index layer (LRL) may be configured to refract or totally reflect light depending on an incident angle of the light. For example, the low-refractive-index layer (LRL) may provide light that has passed through the first light conversion pattern (CCP1) back to the first light conversion pattern (CCP1). Accordingly, the light conversion efficiency of the first light conversion pattern (CCP1) may be improved.

[0165] A color filter layer (CFL) may be disposed on a low refractive index layer (LRL). The color filter layer (CFL) may include a first color filter (CF1) and light blocking patterns (LBP). The first color filter (CF1) may overlap a first light conversion pattern (CCP1). The first color filter (CF1) may selectively transmit light of a desired wavelength range. When the first sub-pixel (SP1) is a red sub-pixel, the first color filter (CF1) may include a red color filter. The light blocking patterns (LBP) may include at least one of various types of light-blocking materials.

[0166] Fig. 8a is a plan view showing an embodiment of the present invention including an organic layer. Fig. 8b is a cross-sectional view taken along line II-II' of Fig. 8a. Since the pixel (PXL) of Fig. 8a is similar to the pixel (PXL) of Fig. 6, redundant description is omitted. For the sake of brevity, Fig. 8b shows only the display element layer (DPL) among the substrate (SUB), pixel circuit layer (PCL), display element layer (DPL), and light function layer (LFL) shown in Fig. 7.

[0167] Referring to FIG. 8a, the organic layer (100) may be disposed between the cathode electrode (CE) and the first to third anode electrodes (AE1 to AE3) along the first direction (DR1) when viewed in a plan view. Referring to FIG. 8b, the organic layer (100) may be disposed on the first and second light-emitting elements (LD1, LD2). After patterning the organic layer (100), the first and second transparent electrodes (ITO1, ITO2) may be patterned.

[0168] Since the organic layer (100) is formed before the first and second transparent electrodes (ITO1, ITO2) are formed, short circuits due to residues remaining during the patterning process of the first and second transparent electrodes (ITO1, ITO2) can be prevented.

[0169] Fig. 9 is a plan view showing another embodiment of the present invention including an organic layer. Since the pixel (PXL) of Fig. 9 is similar to the pixel (PXL) of Fig. 8a, a redundant description is omitted.

[0170] Referring to FIG. 9, the organic layer (100) may include a first organic layer (110) and a second organic layer (120). The first organic layer (110) may be disposed between the cathode electrode (CE) and the first to third anode electrodes (AE1 to AE3) along a first direction (DR1). The second organic layer (120) may be disposed between the first to third anode electrodes (AE1 to AE3) along a second direction (DR2). Unlike what is illustrated in FIG. 9, the second organic layer (120) may extend along the second direction (DR2).

[0171] Fig. 10 is a plan view showing another embodiment of the present invention including an organic layer. Since the pixel (PXL) of Fig. 10 is similar to the pixel (PXL) of Fig. 9, a redundant description is omitted.

[0172] Referring to FIG. 10, the organic layer (100) may include a first organic layer (110), a second organic layer (120), and a third organic layer (130). The first organic layer (110) may be disposed between the cathode electrode (CE) and the first to third anode electrodes (AE1 to AE3) along a first direction (DR1). The second organic layer (120) may be disposed between the first to third anode electrodes (AE1 to AE3) along a second direction (DR2). The first organic layer (110) may be disposed at one end of the second organic layer (120). The third organic layer (130) may be disposed at the other end of the second organic layer (120) along the first direction (DR1).

[0173] Fig. 11a is a plan view showing an embodiment of the present invention including an organic layer. Fig. 11b is a cross-sectional view taken along line Ⅲ-Ⅲ' of Fig. 11a. Fig. 11c is a cross-sectional view taken along line Ⅳ-Ⅳ' of Fig. 11a.

[0174] Since the pixel (PXL) of Fig. 11a is similar to the pixel (PXL) of Fig. 10, a redundant description is omitted. For the sake of brevity, Figs. 11b and 11c illustrate only the display element layer (DPL) among the substrate (SUB), pixel circuit layer (PCL), display element layer (DPL), and light function layer (LFL) illustrated in Fig. 7.

[0175] Referring to FIG. 11A, the organic layer (100) may include a first organic layer (110), a second organic layer (120), and a third organic layer (130). The first organic layer (110) may be disposed between the cathode electrode (CE) and the first to third anode electrodes (AE1 to AE3) along a first direction (DR1). The second organic layer (120) may be disposed between the first to third anode electrodes (AE1 to AE3) along a second direction (DR2). In addition, the second organic layer (120) may extend in the first direction (DR1) to overlap a portion of each of the first to third anode electrodes (AE1 to AE3) and a portion of each of the first to third light-emitting elements (LD1 to LD3) for a process margin.

[0176] Referring to FIGS. 11b and 11c, the organic layer (100) may be disposed between the first light-emitting element (LD1) and the first transparent electrode (ITO1). In addition, the organic layer (100) may overlap a portion of the first light-emitting element (LD1) and a portion of the first anode electrode (AE1), and may overlap a portion of the second light-emitting element (LD2) and a portion of the second anode electrode (AE2).

[0177] After patterning the organic layer (100), the first and second transparent electrodes (ITO1, ITO2) can be patterned. Accordingly, a short circuit caused by residues of the first and second transparent electrodes (ITO1, ITO2) can be prevented from occurring between the first anode electrode (AE1) and the second anode electrode (AE2). In addition, a short circuit caused by residues of the first and second transparent electrodes (ITO1, ITO2) can be prevented from occurring between one of the first to third anode electrodes (AE1 to AE3) and the cathode electrode (CE).

[0178] Fig. 12 is a plan view showing another embodiment of the present invention including an organic layer. Since the pixel (PXL) of Fig. 12 is similar to the pixel (PXL) of Fig. 11a, a redundant description is omitted.

[0179] Referring to FIG. 12, the organic layer (100) may include a first organic layer (110), a second organic layer (120), a third organic layer (130), a fourth organic layer (140), and a fifth organic layer (150). In an embodiment, in order to planarize the organic layer (100), the organic layer (100) may be arranged except for a portion for contact between the first and second transparent electrodes (ITO1, ITO2) and the first and second bonding electrodes (BDE1, BDE2) and a portion for contact between the first and second transparent electrodes (ITO1, ITO2) and the first and second reflective electrodes (RFE1, RFE2).

[0180] The fourth organic layer (140) may be disposed between the first to third light-emitting elements (LD1 to LD3) along the second direction (DR2). The fourth organic layer (140) may overlap a portion of the cathode electrode (CE). In addition, the fourth organic layer (140) may overlap a portion of each of the first to third light-emitting elements (LD1 to LD3) for process margin.

[0181] The fifth organic layer (150) may be arranged along the first direction (DR1). The fifth organic layer (150) may overlap a portion of the cathode electrode (CE). The first organic layer (110) may be arranged at one end of the fourth organic layer (140). The fifth organic layer (150) may be arranged at the other end of the fourth organic layer (140).

[0182] The first to fifth organic layers (110 to 150) described through FIGS. 8A to 12 are only distinguished according to the arrangement direction for convenience of explanation, and the first to fifth organic layers (110 to 150) include the same organic material and can be provided as a single organic layer (100). The organic layer (100) can be arranged on the light-emitting elements (LD1 to LD3).

[0183] Figure 13 is a block diagram showing an embodiment of a display system.

[0184] Referring to FIG. 13, the display system (1000) may include a processor (1100) and a display device (1200).

[0185] The processor (1100) can perform various tasks and calculations. In embodiments, the processor (1100) may include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), etc. The processor (1100) can be connected to other components of the display system (1000) via a bus system and control them.

[0186] The processor (1100) can transmit image data (IMG) and a control signal (CTRL) to the display device (1200). The display device (1200) can display an image based on the image data (IMG) and the control signal (CTRL). The display device (1200) can be configured similarly to the display device (DD) described with reference to FIG. 1. In this case, the image data (IMG) and the control signal (CTRL) can be provided as the input image data (IMG) and the control signal (CTRL) of FIG. 1, respectively.

[0187] The display system (1000) may include a computing system that provides an image display function, such as a smart watch, a mobile phone, a smart phone, a portable computer, a tablet personal computer, a watch phone, an automotive display, smart glasses, a portable multimedia player (PMP), a navigation system, an ultra mobile personal computer (UMPC), etc. In addition, the display system (1000) may include at least one of a head mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0188] Figures 14 to 17 are perspective views showing application examples of the display system of Figure 13.

[0189] Referring to FIG. 14, the display system (1000) of FIG. 13 can be applied to a smart watch (2000) including a display unit (2100) and a strap unit (2200).

[0190] The smartwatch (2000) may be a wearable electronic device. For example, the smartwatch (2000) may have a structure in which a strap portion (2200) is attached to the user's wrist. Here, a display system (1000) and / or a display device (1200) may be applied to the display portion (2100), so that image data including time information may be provided to the user.

[0191] Referring to FIG. 15, the display system (1000) of FIG. 13 may be applied to an automotive display system (3000). Here, the automotive display system (3000) may include a computing system provided inside and / or outside a vehicle to provide image data.

[0192] For example, the display system (1000) and / or the display device (1200) may be applied to at least one of an infotainment panel (3100), a cluster (3200), a co-driver display (3300), a head-up display (3400), a side mirror display (3500), and a rear seat display (3600) provided in a vehicle.

[0193] Referring to FIG. 16, the display system (1000) of FIG. 13 can be applied to smart glasses (4000). The smart glasses (4000) may be a wearable electronic device that can be worn on a user's head. For example, the smart glasses (4000) may be a wearable device for augmented reality.

[0194] Smart glasses (4000) may include a frame (4100) and a lens unit (4200). The frame (4100) may include a housing (4110) that supports the lens unit (4200) and a leg unit (4120) for a user to wear. The leg unit (4120) is connected to the housing (4110) via a hinge and may be folded or unfolded relative to the housing (4110).

[0195] The frame (4100) may be equipped with a battery, a touch pad, a microphone, a camera, etc. In addition, the frame (4100) may be equipped with a projector that outputs light, a processor that controls light signals, etc.

[0196] The lens unit (4200) may include an optical member that transmits or reflects light. For example, the lens unit (4200) may include glass, transparent synthetic resin, or the like.

[0197] In order for the user's eyes to recognize visual information, the lens unit (4200) can reflect an image by an optical signal transmitted from the projector of the frame (4100) onto the rear surface of the lens unit (4200) (e.g., the surface facing the user's eyes). For example, the user can recognize visual information such as the time and date displayed on the lens unit (4200). At this time, the projector and / or the lens unit (4200) may be a type of display device. The display device (1200) may be applied to the projector and / or the lens unit (4200).

[0198] Referring to FIG. 17, the display system (1000) of FIG. 13 can be applied to a head-mounted display device (500).

[0199] The head-mounted display device (5000) may be a wearable electronic device that can be worn on a user's head. For example, the head-mounted display device (5000) may be a wearable device for virtual reality or mixed reality.

[0200] A head-mounted display device (5000) may include a head-mounted band (5100) and a display device storage case (5200). The head-mounted band (5100) may be connected to the display device storage case (5200). The head-mounted band (5100) may include horizontal bands and / or vertical bands for securing the head-mounted display device (5000) to a user's head. The horizontal band may be configured to surround the side of the user's head, and the vertical band may be configured to surround the upper portion of the user's head. However, embodiments are not limited thereto. For example, the head-mounted band (5100) may be implemented in the form of eyeglass frames, helmets, etc.

[0201] The display device storage case (5200) can store the display system (1000) and / or the display device (1200).

[0202] The above description is merely an example of the technical features of the present disclosure, and those skilled in the art will appreciate various modifications and variations. Accordingly, the embodiments of the present disclosure described above may be implemented individually or in combination with one another.

[0203] The embodiments disclosed in this disclosure do not limit the technical concepts of this disclosure, but rather serve to illustrate the technical concepts of this disclosure. The scope of the technical concepts of this disclosure is not limited by these embodiments. The scope of protection of this disclosure should be interpreted by the following claims, and all technical concepts within the equivalent scope should be construed as being included within the scope of this disclosure.

Claims

1. Includes a display element layer arranged on a substrate, The above display element layer, Anode electrode and cathode electrode; A first reflective electrode disposed on the anode electrode; A second reflective electrode disposed on the cathode electrode; A light emitting element comprising a first bonding electrode and a second bonding electrode; A first organic layer disposed on the light-emitting element and disposed between the anode electrode and the cathode electrode when viewed in a planar view; A first transparent electrode that directly electrically connects the first reflective electrode and the first bonding electrode; and A display device including a second transparent electrode that directly electrically connects the second reflective electrode and the second bonding electrode.

2. In paragraph 1, Further comprising sub-pixels arranged in the first direction, The anode electrode includes anode electrodes corresponding to each of the sub-pixels, A display device in which the first organic layer extends in the first direction.

3. In paragraph 2, A display device further comprising a second organic layer disposed on the light emitting element and disposed between the anode electrodes when viewed in a plan view.

4. In paragraph 3, The second organic layer extends in a second direction that is perpendicular to the first direction, A display device in which the first organic layer is disposed on one end of the second organic layer when viewed on a plane.

5. In paragraph 4, A display device in which the second organic layer extends in the first direction and overlaps a portion of each of the anode electrodes when viewed in a plan view.

6. In paragraph 5, A display device in which the first transparent electrode is disposed on the second organic layer.

7. In paragraph 4, Further comprising a third organic layer disposed on the other end of the second organic layer when viewed on a plane, A display device in which the third organic layer extends in the first direction.

8. In paragraph 7, A fourth organic layer disposed on the light-emitting element and extending in the second direction when viewed in a plane; and When viewed on a plane, it further includes a fifth organic layer extending in the first direction, A display device in which the first organic layer is disposed on one end of the fourth organic layer, and the fifth organic layer is disposed on the other end of the fourth organic layer.

9. In paragraph 8, A display device in which the fourth organic layer overlaps a portion of the cathode electrode when viewed in a plan view.

10. In paragraph 9, A display device in which the second transparent electrode is disposed on the fourth organic layer.

11. In paragraph 8, A display device in which the fifth organic layer overlaps a portion of the cathode electrode when viewed in a plan view.

12. In paragraph 1, A display device wherein the display element layer further includes an overcoat layer disposed within an opening in which the first reflective electrode, the second reflective electrode, and the light-emitting element are disposed.

13. In paragraph 12, A display device in which the above overcoat layer is directly adjacent to the light-emitting element.

14. In paragraph 1, The above display element layer is arranged on the upper side of the substrate, A display device in which the first bonding electrode and the second bonding electrode face downward toward the substrate.

15. In paragraph 1, A display device wherein the anode electrode and the cathode electrode are arranged in the same layer and include the same conductive material.

16. In paragraph 1, A display device in which the first transparent electrode and the second transparent electrode are patterned after patterning the first organic layer.

17. In paragraph 1, A display device in which the first reflective electrode and the second reflective electrode are arranged on the same layer and include the same reflective conductive material.

18. In paragraph 1, A display device wherein the first transparent electrode and the second transparent electrode are arranged in the same layer and include the same transparent conductive material.

19. In paragraph 1, The first bonding electrode and the second bonding electrode are arranged on the side and bottom surfaces of the light-emitting element, A display device wherein the first bonding electrode and the second bonding electrode are spaced apart from each other.

20. A processor providing image data and control signals; and A display device including a display panel configured to display an image corresponding to the image data in response to the control signal, The above display panel, Anode electrode and cathode electrode; A first reflective electrode disposed on the anode electrode; A second reflective electrode disposed on the cathode electrode; A light emitting element comprising a first bonding electrode and a second bonding electrode; A first organic layer disposed on the light-emitting element and disposed between the anode electrode and the cathode electrode when viewed in a planar view; A first transparent electrode that directly electrically connects the first reflective electrode and the first bonding electrode; and A display system comprising a second transparent electrode that directly electrically connects the second reflective electrode and the second bonding electrode.

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