Low power communications in a single-wire bus apparatus

Abstract

Low power communications in a single-wire bus apparatus (72) are disclosed. The single-wire bus apparatus (72) includes a master circuit (74) and multiple slave circuits (76) configured to carry out forward and reverse communications over the single-wire bus (78) in forward and reverse data symbols. Herein, in each of the reverse data symbols, the master circuit (74) first asserts a higher bus voltage on the single-wire bus (78) to provide each slave circuit (76) with an opportunity to harvest power and then tri-states the single-wire bus (78) to allow each slave circuit to communicate to the master circuit (74). Specifically, when the single-wire bus (78) is tri-stated, each slave circuit (76) can pull the single-wire bus (78) to a lower bus voltage or maintain the single-wire bus at the higher bus voltage to signify different values in the reverse data symbol. The combination of opportunistic charging and low power data encoding makes each slave circuit (76) power self-sufficient with a reduced footprint.

Description

LOW POWER COMMUNICATIONS IN A SINGLE-WIRE BUS APPARATUSRelated Applications

[0001] This application claims the benefit of U.S. provisional patent application serial number 63 / 627,272, filed on January 31 , 2024, the disclosure of which is hereby incorporated herein by reference in its entirety.Field of the Disclosure

[0002] The technology of the disclosure relates generally to communications over a single-wire communication bus in an electronic device.Background

[0003] Mobile communication devices have become increasingly common in current society. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from being pure communication tools into sophisticated mobile multimedia centers that enable enhanced user experiences.

[0004] To provide the redefined user experience, a state-of-the-art wireless communication device (e.g., smartphone) is equipped with a variety of electrical circuits to support various applications and enable various user experiences. In addition, the wireless communication device also employs a variety of communication buses to enable inter-circuit and intra-circuit communications. As an example, a two-wire radio frequency front-end (RFFE) bus can enable a transceiver circuit(s) to communicate with a power amplifier circuit, a power management circuit, and / or an antenna circuit. A multi-wire, high-bandwidth memory bus can enable time-critical direct access to a memory circuit, and a multi-wire general purpose input / output (GPIO) bus can bridge communications to an external peripheral device.

[0005] However, not all communications require a multi-wire bus like the RFFE bus, the memory bus, and the GPIO bus. In some cases, a single-wireserial bus may be sufficient or even desired for carrying out low-speed and / or low-bandwidth communications between certain types of circuits (e.g., antennas tuners, sensors, and switches).

[0006] Aspects disclosed in the detailed description are related to low power communications in a single-wire bus apparatus. The single-wire bus apparatus includes a master circuit and multiple slave circuits configured to carry out forward (a.k.a. master-to-slave) and reverse (a.k.a. slave-to-master) communications over the single-wire bus in forward (master-to-slave) and reverse (slave-to-master) data symbols. Herein, in each of the reverse data symbols, the master circuit first asserts a higher bus voltage on the single-wire bus to provide each slave circuit with an opportunity to harvest power and then tri-states the single-wire bus to allow each slave circuit to communicate to the master circuit. Specifically, when the single-wire bus is tri-stated, each slave circuit can pull the single-wire bus to a lower bus voltage or maintain the singlewire bus at the higher bus voltage to signify different values in the reverse data symbol. The combination of opportunistic charging and low power data encoding makes it possible for each slave circuit to become power self-sufficient with a reduced footprint.

[0007] In one aspect, a single-wire bus apparatus is provided. The singlewire bus apparatus includes a master circuit. The master circuit is coupled to a single-wire bus consisting of one wire. The master circuit is configured to assert a higher bus voltage on the single-wire bus for a first interval and then tri-state the single-wire bus for a second interval in each of multiple reverse data symbols. The single-wire bus apparatus also includes multiple slave circuits. Each of the multiple slave circuits is coupled to the single-wire bus. Each of the multiple slave circuits is configured to pull the single-wire bus down to a lower bus voltage during the second interval in a respective one of the multiple reverse data symbols to thereby communicate a first value to the master circuit. Each of the multiple slave circuits is also configured to maintain the single-wire bus at thehigher bus voltage during the second interval in the respective one of the multiple reverse data symbols to thereby communicate a second value different from the first value to the master circuit.

[0008] In another aspect, a wireless device is provided. The wireless device includes a master circuit. The master circuit is coupled to a single-wire bus consisting of one wire. The master circuit is configured to assert a higher bus voltage on the single-wire bus for a first interval and then tri-state the single-wire bus for a second interval in each of multiple reverse data symbols. The wireless device also includes multiple slave circuits. Each of the multiple slave circuits is coupled to the single-wire bus. Each of the multiple slave circuits is configured to pull the single-wire bus down to a lower bus voltage during the second interval in a respective one of the multiple reverse data symbols to thereby communicate a first value to the master circuit. Each of the multiple slave circuits is also configured to maintain the single-wire bus at the higher bus voltage during the second interval in the respective one of the multiple reverse data symbols to thereby communicate a second value different from the first value to the master circuit.

[0009] In another aspect, a method for configuring a single-wire bus apparatus is provided. The method includes coupling a master circuit to a singlewire bus consisting of one wire. The method also includes configuring the master circuit to assert a higher bus voltage on the single-wire bus for a first interval and then tri-state the single-wire bus for a second interval in each of multiple reverse data symbols. The method also includes coupling each of multiple slave circuits to the single-wire bus. The method also includes configuring each of the multiple slave circuits to pull the single-wire bus down to a lower bus voltage during the second interval in a respective one of the multiple reverse data symbols to thereby communicate a first value to the master circuit. The method also includes configuring each of the multiple slave circuits to maintain the single-wire bus at the higher bus voltage during the second interval in the respective one of the multiple reverse data symbols to thereby communicate a second value different from the first value to the master circuit.

[0010] Those skilled in the art will appreciate the scope of the disclosure and realize additional aspects thereof after reading the following detailed description in association with the accompanying drawings.Brief Description of the Drawings

[0011] The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0012] Figure 1 A is a schematic diagram of an exemplary conventional singlewire bus apparatus in which a master circuit is configured to communicate with a slave circuit(s) over a single-wire bus;

[0013] Figure 1 B is a schematic diagram providing an exemplary illustration of one or more bus telegrams communicated from the master circuit to the slave circuit(s) over the single-wire bus of Figure 1 A;

[0014] Figure 1 C is a schematic diagram providing an exemplary illustration of one or more bus telegrams communicated from the slave circuit(s) to the master circuit over the single-wire bus of Figure 1 A;

[0015] Figure 1 D is a schematic diagram providing an exemplary illustration of a bus symbol modulated based on a voltage pulse-width modulation (PWM) to represent a voltage PWM value one (“1 ”);

[0016] Figure 1 E is a schematic diagram providing an exemplary illustration of the bus symbol modulated based on the voltage PWM to represent a voltage PWM value zero (“0”);

[0017] Figure 1 F is a schematic diagram providing an exemplary detailed illustration of some technical challenges associated with the master circuit and the slave circuit(s) in the conventional single-wire bus apparatus of Figure 1 ;

[0018] Figure 1 G is a graphic diagram illustrating a cumulative voltage drooping problem in the slave circuit(s) in Figure 1 F;

[0019] Figure 2 is a schematic diagram of an exemplary single-wire bus apparatus wherein a master circuit and a slave circuit(s) are configured to carryout reverse communications utilizing a low power waveform of the present disclosure;

[0020] Figures 3A and 3B are schematic diagrams providing detailed illustrations of the low power waveform for carrying out reverse communications in the single-wire bus apparatus of Figure 2;

[0021] Figure 4 is a schematic diagram providing an exemplary illustration of the slave circuit(s) in Figure 2;

[0022] Figure 5 is a schematic diagram illustrating a daisy-chain topology of a single-wire bus apparatus;

[0023] Figure 6 is a schematic diagram of an exemplary user element (e.g., a wireless device) wherein the single-wire bus apparatuses of Figures 2 and 5 can be provided; and

[0024] Figure 7 is a flowchart of an exemplary process for configuring the single-wire bus apparatuses of Figures 2 and 5.Detailed Description

[0025] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0026] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0027] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being "over" or extending "over" another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly over" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0028] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0029] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including" when used herein specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0030] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0031] Aspects disclosed in the detailed description are related to low power communications in a single-wire bus apparatus. The single-wire bus apparatus includes a master circuit and multiple slave circuits configured to carry out forward (a.k.a. master-to-slave) and reverse (a.k.a. slave-to-master) communications over the single-wire bus in forward (master-to-slave) and reverse (slave-to-master) data symbols. Herein, in each of the reverse data symbols, the master circuit first asserts a higher bus voltage on the single-wire bus to provide each slave circuit with an opportunity to harvest power and then tri-states the single-wire bus to allow each slave circuit to communicate to the master circuit. Specifically, when the single-wire bus is tri-stated, each slave circuit can pull the single-wire bus to a lower bus voltage or maintain the singlewire bus at the higher bus voltage to signify different values in the reverse data symbol. The combination of opportunistic charging and low power data encoding makes it possible for each slave circuit to become power self-sufficient with a reduced footprint.

[0032] Before discussing a single-wire bus apparatus of the present disclosure, starting at Figure 2, a brief overview of a conventional single-wire bus apparatus is first provided with reference to Figures 1A-1 G to help understand basic operations of the conventional single-wire bus and the technical problems to be solve herein.

[0033] In this regard, Figure 1 A is a schematic diagram of an exemplary conventional single-wire bus apparatus 10 in which a master circuit 12 is configured to communicate with a number of slave circuits 14(1 )-14(M) over a single-wire bus 16 coupled to a master port 18. As such, the master circuit 12and the slave circuits 14(1 )-14(M) may only communicate with each other in an alternate fashion (e.g., by time-division).

[0034] The master circuit 12 is configured to always initiate a bus telegram communication over the single-wire bus 16 by communicating a bus telegram(s) to one or more of the slave circuits 14(1 )-14(M). As such, the conventional single-wire bus apparatus 10 is also known as a “master-slave bus architecture.” The slave circuits 14(1 )-14(M) may provide a data payload(s) to the master circuit 12 over the single-wire bus 16 in response to receiving the bus telegram(s) from the master circuit 12. Hereinafter, the bus telegram(s) communicated from the master circuit 12 to the slave circuits 14(1)-14(M) is referred to as “a forward bus telegram(s)” and the data payload(s) communicated from the slave circuits 14(1 )-14(M) to the master circuit 12 are referred to as “a reverse bus telegram(s).”

[0035] Figure 1 B is a schematic diagram providing an exemplary illustration of one or more bus telegrams 20, 22 communicated from the master circuit 12 to any of the slave circuits 14(1 )-14(M) over the single-wire bus 16 of Figure 1 A. Each of the bus telegrams 20, 22 begins with an SOS sequence 24, followed by a bus command sequence 26. The bus command sequence 26 includes a write command frame 28 and a write data frame 30. The write command frame 28 includes a command field 32 (denoted as “CMD”), which is encoded with a binary value “100” to indicate a register-write operation. The write data frame 30 includes a write data period 34. The write data period 34 can include one or more write data symbols Ts modulated to carry data to the slave circuits 14(1 )- 14(M) during the register-write operation. In this regard, the bus telegrams 20, 22 may be an example of the forward bus telegram(s). In context of the present disclosure, the write data symbols Ts are also referred to as forward data symbols.

[0036] The SOS sequence 24 always precedes the bus command sequence 26 and is always communicated from the master circuit 12 to the slave circuits 14(1 )-14(M). The bus telegram 22, which succeeds the bus telegram 20, may be separated from the bus telegram 20 by a fast-charge period 36 that starts at timeTi and ends at time T2 (T2 > T1) and an idle period 38 that starts at time T2 and ends at time T3 (T3 > T2). Collectively, a duration between time T1 and T3 is also referred to as a suspension period (T3 - T1).

[0037] The fast-charge period 36 is configured to allow each of the slave circuits 14(1 )-14(M) to draw a higher charging current via the single-wire bus 16 and harvest power from the higher charging current. In this regard, the singlewire bus 16 is said to be in a fast-charge state during the fast-charge period 36. The idle period 38 may be a no-activity period in which the master circuit 12 and the slave circuits 14(1 )-14(M) may be inactive to help conserve power. Accordingly, the single-wire bus 16 is said to be in an idle state during the idle period 38.

[0038] The bus command sequence 26 in each of the bus telegrams 20, 22 includes a slave address field 40 and is followed by a bus park period 42 and subsequently an acknowledgement (ACK) symbols field 44 that includes four ACK symbols Ts. The slave address field 40 can be used to address the slave circuits 14(1 )-14(M). The bus park period 42 may be used to switch between the forward and the reverse communication modes. The ACK symbols Ts can be used by up to four of the slave circuits 14(1 )-14(M) to acknowledge a respective receipt of the data carried in the write data period 34. Given that the ACK symbols Ts are each associated with a symbol duration Ts and communicated immediately before the fast-charge period 36, each of the slave circuits 14(1 )- 14(M) can determine the time T1 to start the fast-charge period 36 by counting four ACKs communicated in the four ACK symbols Ts from the end of the bus park period 42. In context of the present disclosure, the ACK symbols Ts in the ACK symbols field 44 are one type of reverse data symbols.

[0039] Each of the slave circuits 14(1 )-14(M) is uniquely identified by a respective unique slave identification (IISID). As such, the bus command sequence 26 in the bus telegrams 20, 22 can be a unicast command sequence destined to any one of the slave circuits 14(1 )-14(M) when the slave address field 40 contains the IISID of the any one of the slave circuits 14(1 )-14(M). The bus command sequence 26 in the bus telegrams 20, 22 can also be a multicastcommand sequence destined to a subset of the slave circuits 14(1 )-14(M) when the slave address field 40 contains a group slave identification (GSID) corresponding to the subset of the slave circuits 14(1 )-14(M). Furthermore, the bus command sequence 26 in the bus telegrams 20, 22 can be a broadcast command sequence destined to all of the slave circuits 14(1 )-14(M) when the slave address field 40 contains a broadcast slave identification (BSID).

[0040] Figure 1 C is a schematic diagram providing an exemplary illustration of one or more bus telegrams 46, 48 communicated from the slave circuits 14(1 )- 14(M) to the master circuit 12 over the single-wire bus 16 of Figure 1 A. Common elements between Figures 1 B and 1 C are shown therein with common element numbers and will not be re-described herein.

[0041] Each of the bus telegrams 46, 48 includes the bus command sequence 26. The bus command sequence 26 includes a read command frame 50 and a read data frame 52, separated by a bus park period 42. The read command frame 50 includes the command field 32 (denoted as “CMD”), which is encoded with a binary value “010” to indicate a register-read operation. The read data frame 52 includes a read data period 54, which includes one or more read data symbols Ts modulated to carry data payloads to the master circuit 12 during the register-read operation. The master circuit 12 first communicates the read command frame 50 to the slave circuits 14(1 )-14(M) identified by the slave address field 40 to initiate the register-read operation. The master circuit 12 then tri-states during the bus park period 42, which is sandwiched between the read command frame 50 and the read data frame, to yield control of the single-wire bus 16 to the slave circuits 14(1)-14(M). Subsequently, the slave circuits 14(1 )- 14(M) can begin sending the data payloads in one or more read data symbols Ts in the read data period 54. In this regard, the bus telegrams 46, 48 may be an example of both the forward and the reverse bus telegram(s). In context of the present disclosure, the read data symbols Ts are another type of reverse data symbols.

[0042] With reference back to Figure 1 A, the master circuit 12 is configured to suspend the bus telegram communication over the single-wire bus 16 during thesuspension period (T3 - T1). Accordingly, the master circuit 1 and the slave circuits 14(1 )-14(M) are configured to refrain from communicating the bus telegram(s) and data payload(s) from time T1 to T3. In this regard, the single-wire bus 16 can be said to be in a suspension mode between time T1 and T3. During the suspension period (T3 - T1), the master circuit 12 maintains the single-wire bus 16 at a bus voltage VBUS of a high voltage level VHIGH (VHIGH > 0 V). As such, the slave circuits 14(1 )-14(M) can each draw a charging current over the singlewire bus 16 to thereby harvest power from the master circuit 12.

[0043] Outside the suspension period (T3 - T1), the write data symbols Ts in the write data period 34 and the read data symbols Ts in the read data period 54 can be modulated by toggling the bus voltage VBUS between the high voltage level VHIGH and a low voltage level VLOW (VLOW < VHIGH), as illustrated in Figures 1 D and 1 E. Figure 1 D is a schematic diagram providing an exemplary illustration of a bus symbol Ts modulated based on a voltage PWM to represent a voltage PWM value one (“1 ”).

[0044] The bus symbol Ts, which can be any of the write data symbols Ts, the read data symbols Ts, and the ACK symbols Ts, is modulated based on a predefined low-voltage interval 56 and a predefined high-voltage interval 58 that are configured according to a predefined configuration ratio. To represent the voltage PWM value “1 ,” the predefined low-voltage interval 56 is shorter than the predefined high-voltage interval 58. For example, the bus symbol Ts can include 16 digitally controlled oscillators (DCOs) and the predefined configuration ratio between the predefined low-voltage interval 56 and the predefined high-voltage interval 58 is 25% to 75% (or 1 to 3). In a non-limiting example, the DCOs are derived from a clock running at the master circuit 12. Accordingly, the predefined low-voltage interval 56 lasts for four (4) DCOs and the predefined high-voltage interval 58 lasts for twelve (12) DCOs.

[0045] In this regard, to modulate the bus symbol Ts to represent the voltage PWM value “1 ,” the bus voltage VBUS is first asserted at a low voltage level VLOW (VBUS = VLOW) for the predefined low-voltage interval 56 and then at the high voltage level VHIGH (VHIGH > VLOW) for the predefined high-voltage interval 58.

[0046] Figure 1 E is a schematic diagram providing an exemplary illustration of a voltage PWM symbol Ts modulated to represent a voltage PWM value zero (“0”). Common elements between Figures 1 D and 1 E are shown therein with common element numbers and will not be re-described herein.

[0047] To represent the voltage PWM value “0,” the predefined low-voltage interval 56 is longer than the predefined high-voltage interval 58. Based on the same example in Figure 1 D, the predefined low-voltage interval 56 lasts for 12 DCOs and the predefined high-voltage interval 58 lasts for 4 DCOs. Accordingly, to modulate the bus symbol Ts to represent the voltage PWM value “0,” the bus voltage VBUS is first asserted at the lower voltage level VLOW (VBUS = VLOW) for the predefined low-voltage interval 56 and then at the high voltage level VHIGH (VBUS = VHIGH) for the predefined high-voltage interval 58.

[0048] Figure 1 F is a schematic diagram providing an exemplary detailed illustration of some technical challenges associated with the master circuit 12 and the slave circuit 14(1 )-14(M) in the conventional single-wire bus apparatus 10 of Figure 1 A. Common elements between Figures 1 A and 1 F are shown therein with common element numbers and will not be re-described herein.

[0049] Each of the slave circuits 14(1 )-14(M) can be configured to include an input node 60, a slave bus driver 62, a switch 64, and a power harvesting circuit 66. Specifically, the input node 60 is coupled to the single-wire bus 16, the switch 64 is coupled to the input node 60, and the power harvesting circuit 66 is coupled to the switch 64. The power harvesting circuit 66 may be implemented as a resistor-capacitor (RC) circuit that includes a resistor R (with a resistance R, e.g., 200 Q) and a holding capacitor CHOLD (with a capacitance CHOLD, e.g.,470 nF). Each of the slave circuits 14(1 )-14(M) also includes a slave bypass capacitor CSBYP (with a capacitance CSBYP, e.g., 20 pF), which is coupled between the input node 60 and a ground (GND).

[0050] The master circuit 12 can include an output node 68, a master bus driver 70, and a master bypass capacitor CMBYP (with a capacitance CMBYP, e.g., 20 pF). The output node 68 is coupled to the single-wire bus 16, and the master bypass capacitor CMBYP is coupled between the output node 68 and the GND.Herein, the master bus driver 70 is configured to initiate forward and reverse communications with each of the slave circuits 14(1 )-14(M) using the bus telegrams 20, 22 in Figure 1 B and the bus telegrams 46, 48 in Figure 1 C. The master bus driver 70 is also configured to enable and disable fast-charge during the fast-charge period 36.

[0051] The slave bus driver 62 is configured to close the switch 64 during the suspension period (T3 - T1) to couple the power harvesting circuit 66 to the input node 60. As such, each of the slave circuits 14(1 )-14(M) can draw a bus current IBUS to charge the holding capacitor CHOLD to a local voltage VCAP. Outside the suspension period (T3 - T1), the slave bus driver 62 opens the switch 64 to decouple the power harvesting circuit 66 from the input node 60. As a result, the holding capacitor CHOLD will be discharged to power the slave bus driver 62.

[0052] A figure-of-merit of the power harvesting circuit 66 can be defined by an RC time constant T (T = R x CHOLD), which represents a time required to charge the holding capacitor CHOLD to a certain percentage (e.g., 63.2%) of the full capacity. Understandably, the shorter the RC time constant T, the quicker the power harvesting circuit 66 can harvest energy. In this regard, it may be desirable to shorten the RC time constant T by reducing the resistance R and / or the capacitance CHOLD. Unfortunately, reducing the capacitance CHOLD may bring several technical challenges.

[0053] In the conventional single-wire bus apparatus 10, the master circuit is configured to assert the bus voltage VBUS on the single-wire bus 16 at a start of each of the read data symbols Ts and the ACK symbols Ts. Each of the slave circuits 14(1 )-14(M) is required to maintain the bus voltage VBUS to signify a logic zero “0” (e.g., binary “0”) in any of the read data symbols Ts and the ACK symbols Ts. Each of the slave circuits 14(1)-14(M) is further required to pull the single-wire bus 16 to a higher bus voltage VBUSH (VBUSH > VBUS) to signify a logic one “1 ” (e.g., binary “1 ”) in any of the read data symbols Ts and the ACK symbols Ts.

[0054] Given that each of the master bypass capacitor CMBYP and the slave bypass capacitor CSBYP can have a capacitance of 20 pF and the single-wire bus16 can also have an equivalent capacitance CBUS, the slave bus driver 62 must overcome a total of 350 pF capacitance to signify the logic “1 ” to the master circuit 12. The holding capacitor CHOLD in each of the slave circuits 14(1 )-14(M) has to have a sufficiently large capacitance (e.g., 470 pF) to store sufficient power for each of the slave circuits 14(1 )-14(M) to overcome the 350 pF total capacitance, which will inevitably increase the footprint of the slave circuits 14(1 )- 14(M). In this regard, a first technical problem to be solved herein is to reduce the capacitance of the holding capacitor CHOLD to help reduce the footprint of the slave circuits 14(1 )-14(M).

[0055] Moreover, the 470 pF capacitance of the holding capacitor CHOLD will significantly increase the RC time constant T of the power harvesting circuit 66 to hinder the ability of the power harvesting circuit 66 to harvest power as quickly as needed. As a result, the power harvesting circuit 66 can suffer a cumulative voltage droop in back-to-back bus telegrams.

[0056] Figure 1 G is a graphic diagram illustrating a cumulative voltage drooping problem suffered by each of the slave circuits 14(1 )-14(M) in Figure 1 F. Specifically, Figure 1 G shows a cumulative drooping of the local voltage VCAP in two consecutive (a.k.a. back-to-back) bus write telegrams, such as the bus telegrams 20, 22 in Figure 1 B. Common elements between Figures 1 B, 1 F, and 1 G are shown therein or referenced with common element numbers and will not be re-described herein.

[0057] During each of the write telegrams, the local voltage VCAP experiences a droop because the holding capacitor CHOLD powers the slave bus driver 62. During the fast-charge period 36 in each of the write telegrams, the holding capacitor CHOLD is charged by the bus current IBUS. For the first 500 / zs of the bus telegram (prior to the fast-charge period 36), the holding capacitor CHOLD does not get much charge because of a large RC time constant T of the power harvesting circuit 66, the master bypass capacitor CMBYP, the slave bypass capacitor CSBYP, and the bus capacitance CBUS. During the fast-charge period 36, the holding capacitor CHOLD only gets partially charged due to the large RC time constant T of the power harvesting circuit 66. As a result, the holdingcapacitor CHOLD can suffer a cumulative droop in the local voltage VCAP over time. As shown herein, the cumulative droop can be as much as 100 mV.

[0058] The cumulative droop can have an adverse impact in the slave circuits 14(1 )-14(M). Specifically, because of the cumulative droop in the local voltage VCAP, each of the slave circuits 14(1 )-14(M) already has a 10OmV deficit when attempting to pull up the bus voltage VBUS to the higher bus voltage VBUSH. AS a result, the slave circuits 14(1 )-14(M) may not have a sufficient amount of the local voltage VCAP to pull up the bus voltage VBUS to signify the logic “1 ” to the master circuit 12. In addition, since the local voltage VCAP is the primary power source of the slave circuits 14(1)-14(M), the cumulative droop means less voltage headroom for each of the slave circuits 14(1 )-14(M) to operate. As such, a second technical problem to be solved herein is to reduce power consumption of the slave circuits 14(1 )-14(M) to reduce demand for the local voltage VCAP, thus making it possible to reduce the capacitance of the holding capacitor CHOLD to help reduce the cumulative droop in the local voltage VCAP.

[0059] In this regard, Figure 2 is a schematic diagram of an exemplary singlewire bus apparatus 72 configured according to embodiments of the present disclosure to solve the above identified technical problems associated with the conventional single-wire bus apparatus of Figures 1 A and 1 F. Herein, the singlewire bus apparatus 72 includes a master circuit 74 and multiple slave circuits 76(1 )-76(M). In an embodiment, the slave circuits 76(1 )-76(M) are coupled in parallel to the master circuit 74 via a single-wire bus 78. As described in detail below, the single-wire bus apparatus 72 is configured to communicate reverse data symbols, such as the read data symbols Ts in the bus telegrams 46, 48 in Figure 1 C and the ACK symbols Ts in the bus telegrams 20, 22 in Figure 1 B, based on a low power waveform that is designed to reduce the amount of energy each of the slave circuits 76(1 )-76(M) needs to locally store. As a result, each of the slave circuits 76(1 )-76(M) can be sufficiently powered by a local voltage VCAP supplied by a much smaller holding capacitor CHOLD (e.g., 1 nF). By employing the smaller holding capacitor CHOLD in the slave circuits 76(1 )-76(M), it is possibleto reduce the footprint of the slave circuits 76(1 )-76(M) and help mitigate the cumulative voltage droop as shown in Figure 1 G.

[0060] In an embodiment, each of the slave circuits 76(1 )-76(M) can be configured to include an input node 80, a slave bus driver 82, a switch 84, and a power harvesting circuit 86. Specifically, the input node 80 is coupled to the single-wire bus 78, the switch 84 is coupled to the input node 80, and the power harvesting circuit 86 is coupled to the switch 84. The power harvesting circuit 86 may be implemented as an RC circuit that includes a resistor R (with a resistance R, e.g., 200 Q) and a holding capacitor CHOLD (with a capacitance CHOLD, e.g.,1 nF). Each of the slave circuits 76(1 )-76(M) also includes a slave bypass capacitor CSBYP (with a capacitance CSBYP, e.g., 20 pF), which is coupled between the input node 80 and the GND.

[0061] The master circuit 74 can include an output node 88, a master bus driver 90, and a master bypass capacitor CMBYP (with a capacitance CMBYP, e.g., 20 pF. The output node 88 is coupled to the single-wire bus 78, and the master bypass capacitor CMBYP is coupled between the output node 88 and the GND. Herein, the master bus driver 90 is configured to initiate forward and reverse communications with each of the slave circuits 14(1 )-14(M) using the bus telegrams 20, 22 in Figure 1 B and the bus telegrams 46, 48 in Figure 1 C. The master bus driver 90 is also configured to enable and disable a fast-charge during the fast-charge period 36. Unlike the master bus driver 70 in the conventional single-wire bus apparatus 10 of Figure 1 F, the master bus driver 90 is further configured to initiate the low power waveform at the start of each reverse data symbol.

[0062] The slave bus driver 82 is configured to close the switch 84 during the suspension period (T3 - T1) to couple the power harvesting circuit 86 to the input node 80. As such, each of the slave circuits 76(1 )-76(M) can draw a bus current IBUS to charge the holding capacitor CHOLD to the local voltage VCAP. Outside the suspension period (T3 - T1), the slave bus driver 82 opens the switch 84 to decouple the power harvesting circuit 86 from the input node 60. As a result, the holding capacitor CHOLD will be discharged to power the slave bus driver 82.

[0063] Unlike the slave bus driver 62 in Figure 1 F, the slave bus driver 82 is configured to communicate in the reverse data symbols utilizing the low power waveform, which is further discussed next with reference to Figures 3A and 3B. Figures 3A and 3B are schematic diagrams providing detailed illustrations of the low power waveform for carrying out reverse communications in the single-wire bus apparatus 72 of Figure 2. Common elements between Figures 3A and 3B are shown therein with common element numbers and will not be re-described herein.

[0064] Figure 3A illustrates the low power waveform whereby each of the slave circuits 76(1 )-76(M) in Figure 2 can be utilized to signify a logic “0” in a reverse read data symbol Ts or a negative acknowledgment (NAK) in a reverse ACK symbol Ts to the master circuit 74 over the single-wire bus 78. Herein, the logic “0” and the NAK are collectively referred to as “a first value.”

[0065] Herein, the low power waveform is divided into a first interval INTi and a second interval INT2. During the first interval INT1, the master circuit 74 first asserts a higher bus voltage VBUSH on the single-wire bus 78. Shortly after asserting the higher bus voltage VBUSH (e.g., after 1 clock cycle), the master circuit 74 enables a fast-charge period 92 to allow each of the slave circuits 76(1 )-76(M) to opportunistically recharge the holding capacitor CHOLD.Accordingly, each of the slave circuits 76(1 )-76(M) closes the switch 84 such that the bus current IBUS can recharge the holding capacitor CHOLD. Prior to ending the first interval INT1, the master circuit 74 disables the fast-charge period 92 and each of the slave circuits 76(1 )-76(M), in turn, opens the switch 84.

[0066] The master circuit 74 is configured to tri-state the single-wire bus 78 during the second interval INT2, which will leave the single-wire bus 78 with the higher bus voltage VBUSH. The slave bus driver 82 in each of the slave circuits 76(1 )-76(M) is configured to maintain the single-wire bus 78 at the higher bus voltage VBUSH during the second interval INT2 to signify the logic “0” (e.g., binary “0”) or the NAK to the master circuit 74.

[0067] Figure 3B illustrates the low power waveform whereby each of the slave circuits 76(1 )-76(M) in Figure 2 can be utilized to signify a logic “1 ” in areverse read data symbol Ts or an ACK in a reverse ACK symbol Ts to the master circuit 74 over the single-wire bus 78. Herein, the logic “1 ” and the ACK are collectively referred to as “a second value.”

[0068] Herein, during the second interval INT2, the slave bus driver 82 in each of the slave circuits 76(1 )-76(M) is configured to pull the single-wire bus 78 from the higher bus voltage VBUSH down to a lower bus voltage VBUSL (VBUSL < VBUSH) to signify the logic “1 ” (e.g., binary “1 ”) or the ACK. Understandably, by pulling the single-wire bus 78 down to the lower bus voltage VBUSL, as opposed to pulling up to the higher bus voltage VBUSH as in the conventional single-wire bus apparatus 10, it is possible to drastically reduce the amount of energy each of the slave circuits 76(1 )-76(M) needs to locally store, thus making it possible to employ a much smaller holding capacitor CHOLD (e.g., 1 nF) to help reduce the footprint of the slave circuits 76(1 )-76(M). Further, the smaller holding capacitor CHOLD can also significantly reduce the RC time constant T of the power harvesting circuit 86. As a result, the power harvesting circuit 86 can harvest sufficient power quickly to thereby mitigate or even eliminate the cumulative voltage droop shown in Figure 1 G.

[0069] Notably, the slave bus driver 82 may only need to assert the lower bus voltage VBUSL on the single-wire bus 78 for a portion of the second interval INT2. The single-wire bus 78 will remain tri-stated, and stay with the lower bus voltage VBUSL, for the rest of the second interval INT2. Given that the single-wire bus 78 has been pulled down to the lower bus voltage VBUSL in the present reverse data symbol Ts, the master circuit 74 needs to reassert the higher bus voltage VBUSH on the single-wire bus 78 during the first interval INT1 in the immediately succeeding reverse data symbol Ts.

[0070] With reference back to Figure 2, to allow each of the slave circuits 76(1 )-76(M) to opportunistically recharge the holding capacitor CHOLD during the fast-charge period 92, each of the slave circuits 76(1 )-76(M) further includes a fast-charging switch SWFC coupled in series with a smaller fast-charging resistor R1 (e.g., 1 Q). During the fast-charge period 92, the slave bus driver 82 in each of the slave circuits 76(1 )-76(M) closes the fast-charging switch SWFC to therebyallow each of the slave circuits 76(1 )-76(M) to opportunistically recharge the holding capacitor CHOLD during the fast-charge period 92. The slave bus driver 82 in each of the slave circuits 76(1 )-76(M) opens the fast-charging switch SWFC outside the fast-charge period 92.

[0071] Figure 4 is a schematic diagram providing an exemplary illustration of the slave circuits 76(1 )-76(M) in Figure 2. Common elements between Figures 2 and 4 are shown therein with common element numbers and will not be redescribed herein.

[0072] In an embodiment, the slave bus driver 82 includes an n-type fieldeffect transistor (NFET) 94, a data transmitter 96, and a data receiver 98. The NFET 94 is driven by the local voltage VCAP to pull the single-wire bus 78 down to the lower bus voltage BUSL during the second interval INT2 to thereby communicate the logic “1 ” or the ACK to the master circuit 74.

[0073] Notably, employing the smaller holding capacitor CHOLD in the slave circuits 76(1 )-76(M) can reduce setup time of the slave circuits 76(1 )-76(M). As a result, the slave circuits 76(1 )-76(M) can be rearranged based on a daisy- chained topology. Figure 5 is a schematic diagram of a single-wire bus apparatus 72A wherein the slave circuits 76(1 )-76(M) are coupled to the master circuit 74 based on a daisy-chained topology. Common elements between Figures 2 and 5 are shown therein with common element numbers and will not be re-described herein.

[0074] The single-wire bus apparatus 72 of Figure 2 and the single-wire bus apparatus 72A of Figure 5 can be provided in a user element (e.g., wireless device) to support the embodiments described above. In this regard, Figure 6 is a schematic diagram of an exemplary user element 100 wherein the single-wire bus apparatus 72 of Figure 2 and the single-wire bus apparatus 72A of Figure 5 can be provided.

[0075] Herein, the user element 100 can be any type of user elements, such as mobile terminals, smart watches, tablets, computers, navigation devices, access points, and like wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN),Bluetooth, and near field communications. The user element 100 will generally include a control system 102, a baseband processor 104, transmit circuitry 106, receive circuitry 108, antenna switching circuitry 110, multiple antennas 112, and user interface circuitry 1 14. In a non-limiting example, the control system 102 can be a field-programmable gate array (FPGA), as an example. In this regard, the control system 102 can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receive circuitry 108 receives radio frequency signals via the antennas 112 and through the antenna switching circuitry 110 from one or more base stations. A low noise amplifier and a filter cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter(s) (ADC).

[0076] The baseband processor 104 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations, as will be discussed in greater detail below. The baseband processor 104 is generally implemented in one or more digital signal processors (DSPs) and application specific integrated circuits (ASICs).

[0077] For transmission, the baseband processor 104 receives digitized data, which may represent voice, data, or control information, from the control system 102, which it encodes for transmission. The encoded data is output to the transmit circuitry 106, where a digital-to-analog converter(s) (DAC) converts the digitally encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission, and deliver the modulated carrier signal to the antennas 1 12 through the antenna switching circuitry 110. The multiple antennas 1 12 and the replicated transmit and receive circuitries 106, 108 may providespatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0078] In an embodiment, the single-wire bus apparatus 72 and the singlewire bus apparatus 72A can be provided in the antenna switching circuitry 1 10 to enable communications between the antenna switching circuitry 1 10 and the antennas 1 12. In other embodiments, the single-wire bus apparatus 72 and the single-wire bus apparatus 72A may also be utilized to enable communications between the antenna switching circuitry 110, the transmit circuitry 106, and / or the receive circuitry 108.

[0079] The single-wire bus apparatus 72 of Figure 2 and the single-wire bus apparatus 72A of Figure 5 can be configured according to a process. In this regard, Figure 7 is a flowchart of an exemplary process 200 for configuring the single-wire bus apparatus 72 of Figure 2 and the single-wire bus apparatus 72A of Figure 5.

[0080] Herein, the process 200 includes coupling the master circuit 74 to the single-wire bus 78 consisting of one wire (step 202). The process 200 also includes configuring the master circuit 74 to assert the higher bus voltage VBUSH on the single-wire bus 78 for the first interval INTi and then tri-state the singlewire bus 78 for the second interval INT2 in each of the reverse data symbols Ts (step 204). The process 200 also includes coupling each of the slave circuits 76(1 )-76(N) to the single-wire bus 78 (step 206). The process 200 also includes configuring each of the slave circuits 76(1 )-76(N) to pull the single-wire bus 78 down to the lower bus voltage VBUSL during the second interval INT2 in a respective one of the reverse data symbols Ts to thereby communicate the first value “1 ” or ACK to the master circuit 74 (step 208). The process also includes configuring each of the slave circuits 76(1 )-76(N) to maintain the single-wire bus 78 at the higher bus voltage VBUSH during the second interval INT2 in the respective one of the reverse data symbols Ts to thereby communicate a second value “0” or NAK different from the first value “1 ” or ACK to the master circuit 74 (step 210).

[0081] Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims

ClaimsWhat is claimed is:1 . A single-wire bus apparatus comprising: a master circuit coupled to a single-wire bus consisting of one wire and configured to assert a higher bus voltage on the single-wire bus for a first interval and then tri-state the single-wire bus for a second interval in each of a plurality of reverse data symbols; and a plurality of slave circuits each coupled to the single-wire bus and configured to: pull the single-wire bus down to a lower bus voltage during the second interval in a respective one of the plurality of reverse data symbols to thereby communicate a first value to the master circuit; and maintain the single-wire bus at the higher bus voltage during the second interval in the respective one of the plurality of reverse data symbols to thereby communicate a second value different from the first value to the master circuit.

2. The single-wire bus apparatus of claim 1 , wherein: the plurality of reverse data symbols comprises a plurality of read data symbols; and each of the plurality of slave circuits is further configured to: pull the single-wire bus down to the lower bus voltage during the second interval in a respective one of the plurality of read data symbols to thereby communicate a binary one “1 ” as the first value to the master circuit; and maintain the single-wire bus at the higher bus voltage during the second interval in the respective one of the plurality of read data symbols to thereby communicate a binary zero “O’ as the second value to the master circuit.

3. The single-wire bus apparatus of claim 1 , wherein: the plurality of reverse data symbols comprises a plurality of acknowledgement (ACK) symbols; and each of the plurality of slave circuits is further configured to: pull the single-wire bus down to the lower bus voltage during the second interval in a respective one of the plurality of ACK symbols to thereby communicate an ACK as the first value to the master circuit; and maintain the single-wire bus at the higher bus voltage during the second interval in the respective one of the plurality of ACK symbols to thereby communicate a negative acknowledgment (NAK) as the second value to the master circuit.

4. The single-wire bus apparatus of claim 1 , wherein the master circuit is further configured to reassert the higher bus voltage on the single-wire bus at a respective start of each of the plurality of reverse data symbols if any of the plurality of slave circuits has pulled the single-wire bus down to the lower bus voltage in an immediately preceding one of the plurality of reverse data symbols.

5. The single-wire bus apparatus of claim 1 , wherein the master circuit is further configured to enable a fast-charge period during the first interval in each of the plurality of reverse data symbols such that each of the plurality of slave circuits can harvest power from the master circuit during the fast-charge period.

6. The single-wire bus apparatus of claim 5, wherein the master circuit is further configured to: enable the fast-charge period in each of the plurality of slave circuits after starting the first interval in each of the plurality of reverse data symbols; anddisable the fast-charge period in each of the plurality of slave circuits prior to ending the first interval in each of the plurality of reverse data symbols.

7. The single-wire bus apparatus of claim 5, wherein each of the plurality of slave circuits comprises: a holding capacitor coupled to the single-wire bus via a switch, the switch is closed during the fast-charge period such that the holding capacitor can be charged by a bus current drawn from the master circuit via the single-wire bus; and a slave bus driver comprises an n-type field-effect transistor (NFET) configured to pull the single-wire bus down to the lower bus voltage during the second interval to thereby communicate the first value to the master circuit.

8. The single-wire bus apparatus of claim 1 , wherein the plurality of slave circuits is coupled in parallel to the single-wire bus.

9. The single-wire bus apparatus of claim 1 , wherein the plurality of slave circuits is daisy-chained to the single-wire bus.

10. A wireless device comprising: a master circuit coupled to a single-wire bus consisting of one wire and configured to assert a higher bus voltage on the single-wire bus for a first interval and then tri-state the single-wire bus for a second interval in each of a plurality of reverse data symbols; and a plurality of slave circuits each coupled to the single-wire bus and configured to: pull the single-wire bus down to a lower bus voltage during the second interval in a respective one of the plurality of reversedata symbols to thereby communicate a first value to the master circuit; and maintain the single-wire bus at the higher bus voltage during the second interval in the respective one of the plurality of reverse data symbols to thereby communicate a second value different from the first value to the master circuit.1 1 . The wireless device of claim 10, wherein: the plurality of reverse data symbols comprises a plurality of read data symbols; and each of the plurality of slave circuits is further configured to: pull the single-wire bus down to the lower bus voltage during the second interval in a respective one of the plurality of read data symbols to thereby communicate binary one “1 ” as the first value to the master circuit; and maintain the single-wire bus at the higher bus voltage during the second interval in the respective one of the plurality of read data symbols to thereby communicate a binary zero “O’ as the second value to the master circuit.

12. The wireless device of claim 10, wherein: the plurality of reverse data symbols comprises a plurality of acknowledgement (ACK) symbols; and each of the plurality of slave circuits is further configured to: pull the single-wire bus down to the lower bus voltage during the second interval in a respective one of the plurality of ACK symbols to thereby communicate an ACK as the first value to the master circuit; and maintain the single-wire bus at the higher bus voltage during the second interval in the respective one of the plurality of ACK symbols to thereby communicate a negativeacknowledgment (NAK) as the second value to the master circuit.

13. The wireless device of claim 10, wherein the master circuit is further configured to reassert the higher bus voltage on the single-wire bus at a respective start of each of the plurality of reverse data symbols if any of the plurality of slave circuits has pulled the single-wire bus down to the lower bus voltage in an immediately preceding one of the plurality of reverse data symbols.

14. The wireless device of claim 10, wherein the master circuit is further configured to enable a fast-charge period during the first interval in each of the plurality of reverse data symbols such that each of the plurality of slave circuits can harvest power from the master circuit during the fast-charge period.

15. The wireless device of claim 14, wherein the master circuit is further configured to: enable the fast-charge period in each of the plurality of slave circuits after starting the first interval in each of the plurality of reverse data symbols; and disable the fast-charge period in each of the plurality of slave circuits prior to ending the first interval in each of the plurality of reverse data symbols.

16. The wireless device of claim 14, wherein each of the plurality of slave circuits comprises: a holding capacitor coupled to the single-wire bus via a switch, the switch is closed during the fast-charge period such that the holding capacitor can be charged by a bus current drawn from the master circuit via the single-wire bus; and a slave bus driver comprises an n-type field-effect transistor (NFET) configured to pull the single-wire bus down to the lower bus voltageduring the second interval to thereby communicate the first value to the master circuit.

17. The wireless device of claim 10, wherein the plurality of slave circuits is coupled in parallel to the single-wire bus.

18. The wireless device of claim 10, wherein the plurality of slave circuits is daisy-chained to the single-wire bus.

19. A method for configuring a single-wire bus apparatus comprising: coupling a master circuit to a single-wire bus consisting of one wire; configuring the master circuit to assert a higher bus voltage on the singlewire bus for a first interval and then tri-state the single-wire bus for a second interval in each of a plurality of reverse data symbols; coupling each of a plurality of slave circuits to the single-wire bus; configuring each of the plurality of slave circuits to pull the single-wire bus down to a lower bus voltage during the second interval in a respective one of the plurality of reverse data symbols to thereby communicate a first value to the master circuit; and configuring each of the plurality of slave circuits to maintain the single-wire bus at the higher bus voltage during the second interval in the respective one of the plurality of reverse data symbols to thereby communicate a second value different from the first value to the master circuit.

20. The method of claim 19, further comprising daisy-chaining the plurality of slave circuits to the single-wire bus.

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