Shift register unit and driving method therefor, gate driver circuit, and display device

Abstract

A shift register unit and a driving method therefor, a gate driver circuit, and a display device, relating to the technical field of display. In the shift register unit, a pre-charging circuit (01) can control the potential of a control node (P) on the basis of gating signals provided by a plurality of gating ends (D0…Dm); a charging circuit (02) can control the potential of a pull-up node (Q) on the basis of the potential of the control node (P) and a clock signal; and a reset circuit (03) can control the potentials of the control node (P) and of the pull-up node (Q) on the basis of a reset signal; and then, each output circuit (04) among a plurality of output circuits (04) can control the on / off of output ends (Scout1...Scoutn) and output clock ends (CLKS1…CLKSn) on the basis of the potential of the pull-up node (Q). In this way, regional gating can be achieved by flexibly setting gating signals, so that a plurality of output units can flexibly output gate driving signals to a plurality of rows of pixels in each region, so as to drive the plurality of rows of pixels to emit light. That is, the shift register unit can flexibly refresh the pixels for regions on the basis of a display picture.

Description

Shift register unit and driving method thereof, gate driving circuit and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular to a shift register unit and driving method thereof, a gate driving circuit and a display device. BACKGROUND

[0002] With the progress of display technology, a gate driving circuit is usually arranged on a display panel by using a gate driver on array (GOA) technology to facilitate a narrow frame design.

[0003] In the related art, the gate driving circuit usually includes a plurality of GOA units connected in cascade, and the plurality of GOA units are connected in one-to-one correspondence with a plurality of rows of pixels on the display panel and are used to transmit a gate driving signal to the plurality of rows of pixels row by row to light up the pixels row by row, that is, to realize row-by-row scanning and refreshing, so that the display panel can display a picture.

[0004] However, the driving mode of the gate driving circuit in the related art is single, and cannot flexibly refresh different regions on the display panel according to a display picture.

[0005] SUMMARY

[0006] A shift register unit and driving method thereof, a gate driving circuit and a display device are provided. The technical solutions are as follows:

[0007] In one aspect, a shift register unit is provided, which includes:

[0008] A pre-charge circuit is connected with at least two gate control terminals, a first clock terminal, a second clock terminal and a control node, respectively, and is used to control the on-off of the first clock terminal and the control node in response to a gate signal provided by each of the gate control terminals, a first clock signal provided by the first clock terminal and a second clock signal provided by the second clock terminal.

[0009] A charging circuit is connected with the control node, the second clock terminal, a third clock terminal, a first power supply terminal and a pull-up node, respectively, and is used to control the on-off of the first power supply terminal and the pull-up node in response to the potential of the control node and a third clock signal provided by the third clock terminal, and to control the on-off of the third clock terminal and the pull-up node in response to the second clock signal.

[0010] A reset circuit is connected with a reset terminal, a second power supply terminal, the control node and the pull-up node, respectively, and is used to control the on-off of the second power supply terminal and the control node in response to a reset signal provided by the reset terminal, and to control the on-off of the second power supply terminal and the pull-up node.

[0011] at least two output circuits, respectively connected with the pull-up node, one-to-one corresponding at least two output clock terminals and one-to-one corresponding at least two output terminals, each of the output circuits being configured to control the on-off of the corresponding one of the output clock terminals and the output terminal to output a gate drive signal through the output terminal in response to the potential of the pull-up node.

[0012] Optionally, the pre-charge circuit comprises:

[0013] a gating sub-circuit, respectively connected with the at least two gating terminals, the second clock terminal and an intermediate node, and configured to control the on-off of the second clock terminal and the intermediate node in response to the gating signals provided by each of the gating terminals;

[0014] an auxiliary control sub-circuit, respectively connected with the first clock terminal, the second clock terminal and the intermediate node, and configured to control the on-off of the second clock terminal and the intermediate node in response to the first clock signal;

[0015] a pre-charge sub-circuit, respectively connected with the intermediate node, the first clock terminal and the control node, and configured to control the on-off of the first clock terminal and the control node in response to the potential of the intermediate node and the first clock signal.

[0016] Optionally, the gating sub-circuit comprises at least two gating transistors.

[0017] The gates of the at least two gating transistors are connected with the at least two gating terminals one-to-one, the first poles of the at least two gating transistors are connected with the second clock terminal, and the second poles of the at least two gating transistors are connected with the intermediate node.

[0018] Optionally, the auxiliary control sub-circuit comprises an auxiliary control transistor.

[0019] The gate of the auxiliary control transistor is connected with the first clock terminal, the first pole of the auxiliary control transistor is connected with the second clock terminal, and the second pole of the auxiliary control transistor is connected with the intermediate node.

[0020] Optionally, the pre-charge sub-circuit is further connected with the first power terminal and is configured to store the potential of the control node based on the first power signal; the pre-charge sub-circuit comprises a first pre-charge transistor, a second pre-charge transistor and a first storage capacitor.

[0021] The gate of the first pre-charge transistor is connected with the intermediate node, the first pole of the first pre-charge transistor is connected with the first clock terminal, and the second pole of the first pre-charge transistor is connected with the control node.

[0022] The gate and the first pole of the second pre-charge transistor are connected with the first clock end, and the second pole of the second pre-charge transistor is connected with the control node;

[0023] One end of the first storage capacitor is connected with the first power supply end, and the other end of the first storage capacitor is connected with the control node.

[0024] Optionally, the shift register unit further comprises:

[0025] A pull-down control circuit is connected with the control node, the second clock end, the third clock end, a control power supply end, the pull-up node and the pull-down node respectively, and is configured to control the on-off of the second clock end and the pull-down node in response to the potential of the control node and the third clock signal, control the on-off of the control power supply end and the pull-down node in response to the second clock signal, and control the on-off of the second clock end and the pull-down node in response to the potential of the pull-up node;

[0026] A pull-down circuit is connected with the pull-down node, the second power supply end, the pull-up node and the at least two output ends respectively, and is configured to control the on-off of the second power supply end and the pull-up node in response to the potential of the pull-down node, and control the on-off of the second power supply end and each of the output ends;

[0027] The control power supply end is shared by the second clock end or the first power supply end.

[0028] Optionally, the pull-down control circuit is further connected with the second power supply end, and is configured to store the potential of the pull-down node based on the second power supply signal; the pull-down control circuit comprises a first pull-down control transistor, a second pull-down control transistor, a third pull-down control transistor, a fourth pull-down control transistor and a second storage capacitor;

[0029] The gate of the first pull-down control transistor is connected with the control node, the first pole of the first pull-down control transistor is connected with the second pole of the second pull-down control transistor, and the second pole of the first pull-down control transistor is connected with the pull-down node;

[0030] The gate of the second pull-down control transistor is connected with the third clock end, and the first pole of the second pull-down control transistor is connected with the second clock end;

[0031] The gate of the third pull-down control transistor is connected with the second clock end, the first pole of the third pull-down control transistor is connected with the control power supply end, and the second pole of the third pull-down control transistor is connected with the pull-down node;

[0032] a gate of the fourth pull-down control transistor is connected with the pull-up node, a first pole of the fourth pull-down control transistor is connected with the second clock end, and a second pole of the fourth pull-down control transistor is connected with the pull-down node;

[0033] one end of the second storage capacitor is connected with the second power end, and the other end of the second storage capacitor is connected with the pull-down node.

[0034] Optionally, the pull-down circuit comprises a first pull-down transistor and at least two second pull-down transistors.

[0035] a gate of the first pull-down transistor is connected with the pull-down node, a first pole of the first pull-down transistor is connected with the second power end, and a second pole of the first pull-down transistor is connected with the pull-up node;

[0036] gates of the at least two second pull-down transistors are all connected with the pull-down node, first poles of the at least two second pull-down transistors are all connected with the second power end, and second poles of the at least two second pull-down transistors are connected with the at least two output ends one by one.

[0037] Optionally, the shift register unit further comprises:

[0038] a first isolation circuit connected between the control node and the pull-down control circuit, and further connected with the first power end, and used for controlling the control node and the pull-down control circuit to be turned on in response to the first power signal.

[0039] Optionally, the first isolation circuit comprises a first isolation transistor.

[0040] a gate of the first isolation transistor is connected with the first power end, a first pole of the first isolation transistor is connected with the control node, and a second pole of the first isolation transistor is connected with the pull-down control circuit.

[0041] Optionally, the shift register unit further comprises:

[0042] a second isolation circuit connected between the pull-up node and the at least two output circuits, and further connected with the first power end, and used for controlling the pull-up node and the at least two output circuits to be turned on in response to the first power signal.

[0043] Optionally, the second isolation circuit comprises at least two isolation sub-circuits.

[0044] The at least two isolation sub-circuits are connected one-to-one with the at least two output sub-circuits and are also connected with the first power supply end and the pull-up node, and each of the isolation sub-circuits is configured to control the pull-up node and a corresponding one of the output sub-circuits to be connected or disconnected in response to the first power supply signal.

[0045] Optionally, each of the isolation sub-circuits comprises a second isolation transistor.

[0046] The gate of the second isolation transistor is connected with the first power supply end, the first pole of the second isolation transistor is connected with the pull-up node, and the second pole of the second isolation transistor is connected with a corresponding one of the output sub-circuits.

[0047] Optionally, the charging circuit comprises a first charging transistor, a second charging transistor, and a third charging transistor.

[0048] The gate of the first charging transistor is connected with the control node, the first pole of the first charging transistor is connected with the first power supply end, and the second pole of the first charging transistor is connected with the first pole of the second charging transistor.

[0049] The gate of the second charging transistor is connected with the third clock end, and the second pole of the second charging transistor is connected with the pull-up node.

[0050] The gate of the third charging transistor is connected with the second clock end, the first pole of the third charging transistor is connected with the third clock end, and the second pole of the third charging transistor is connected with the pull-up node.

[0051] Optionally, the reset circuit comprises a first reset transistor and a second reset transistor.

[0052] The gate of the first reset transistor is connected with the reset end, the first pole of the first reset transistor is connected with the second power supply end, and the second pole of the first reset transistor is connected with the control node.

[0053] The gate of the second reset transistor is connected with the reset end, the first pole of the second reset transistor is connected with the second power supply end, and the second pole of the second reset transistor is connected with the pull-up node.

[0054] Optionally, each of the output sub-circuits comprises an output transistor and a third storage capacitor.

[0055] The gate of the output transistor is connected with the pull-up node, the first pole of the output transistor is connected with a corresponding one of the output clock ends, and the second pole of the output transistor is connected with a corresponding one of the output ends.

[0056] One end of the third storage capacitor is connected with the pull-up node, and the other end of the third storage capacitor is connected with the corresponding output terminal.

[0057] Optionally, the shift register unit comprises four output circuits.

[0058] The pre-charge circuit is connected with eight gate terminals.

[0059] In another aspect, a driving method of a shift register unit is provided, which is used to drive the shift register unit as described in the above aspect; the method comprises:

[0060] In the reset phase, the reset circuit controls the second power terminal to be conductive with the control node and the pull-up node respectively in response to the reset signal provided by the reset terminal;

[0061] In the set phase, the pre-charge circuit controls the first clock terminal to be conductive with the control node in response to the first clock signal provided by the first clock terminal;

[0062] In the gate-on phase, the pre-charge circuit controls the first clock terminal to be conductive with the control node in response to the gate-on signal provided by each of the at least two gate terminals and the second clock signal provided by the second clock terminal, and the charge circuit controls the third clock terminal to be conductive with the pull-up node in response to the second clock signal provided by the second clock terminal;

[0063] In the input phase, the charge circuit controls the first power terminal to be conductive with the pull-up node in response to the third clock signal provided by the third clock terminal and the potential of the control node;

[0064] In the output phase, each of the at least two output circuits controls one corresponding output clock terminal to be conductive with one corresponding output terminal in response to the potential of the pull-up node.

[0065] In yet another aspect, a gate drive circuit is provided, which comprises: a plurality of groups of shift register units, each group of the shift register units comprising: at least two shift register units as described in the above aspect;

[0066] Each group of the shift register units shares the first clock terminal, the second clock terminal, the third clock terminal, the output clock terminal and the gate terminal, and each group of the shift register units is configured to receive different gate-on signals provided by the at least two gate terminals.

[0067] In still another aspect, a display device is provided, which comprises: a display panel, and a gate drive circuit as described in the above aspect.

[0068] The display panel includes a plurality of pixels, the gate drive circuit is connected with the plurality of pixels, and is used for transmitting a gate drive signal to the plurality of pixels to drive the plurality of pixels to emit light. BRIEF DESCRIPTION OF DRAWINGS

[0069] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0070] FIG. 1 is a structural schematic diagram of a shift register unit according to an embodiment of the present disclosure;

[0071] FIG. 2 is a structural schematic diagram of another shift register unit according to an embodiment of the present disclosure;

[0072] FIG. 3 is a structural schematic diagram of another shift register unit according to an embodiment of the present disclosure;

[0073] FIG. 4 is a structural schematic diagram of another shift register unit according to an embodiment of the present disclosure;

[0074] FIG. 5 is a circuit structural schematic diagram of a shift register unit according to an embodiment of the present disclosure;

[0075] FIG. 6 is a circuit structural schematic diagram of another shift register unit according to an embodiment of the present disclosure;

[0076] FIG. 7 is a circuit structural schematic diagram of another shift register unit according to an embodiment of the present disclosure;

[0077] FIG. 8 is a flow schematic diagram of a driving method of a shift register unit according to an embodiment of the present disclosure;

[0078] FIG. 9 is a structural schematic diagram of a gate drive circuit according to an embodiment of the present disclosure;

[0079] FIG. 10 is a structural schematic diagram of another gate drive circuit according to an embodiment of the present disclosure;

[0080] FIG. 11 is a working timing schematic diagram of a gate drive circuit according to an embodiment of the present disclosure;

[0081] FIG. 12 is a working timing schematic diagram of another gate drive circuit according to an embodiment of the present disclosure;

[0082] FIG. 13 is a timing schematic diagram of a gate drive circuit according to an embodiment of the present disclosure;

[0083] FIG. 14 is a structural schematic diagram of a display device according to an embodiment of the present disclosure;

[0084] Fig. 15 is a schematic diagram of a circuit structure of a pixel according to an embodiment of the present disclosure;

[0085] Fig. 16 is a schematic diagram of a working timing of a pixel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0086] For the purpose, technical solutions and advantages of the present disclosure to be clearer, the embodiments of the present disclosure will be described in further detail below with reference to the drawings.

[0087] It should be noted that the transistors used in all embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics, and the transistors used in the embodiments of the present disclosure are mainly switching transistors according to their functions in the circuit. Since the source and drain of the switching transistor used here are symmetrical, the source and drain can be interchangeable, and the source is referred to as the first pole and the drain is referred to as the second pole, or the drain is referred to as the first pole and the source is referred to as the second pole. According to the form in the drawings, the middle end of the transistor is the gate, the signal input end is the source, and the signal output end is the drain. In addition, the switching transistor used in the embodiments of the present disclosure can include any one of a P-type transistor and an N-type transistor or a combination thereof. Among them, the P-type transistor is turned on when the gate is low voltage, and is turned off when the gate is high voltage, and the N-type transistor is turned on when the gate is high voltage, and is turned off when the gate is low voltage. In addition, the plurality of signals in each embodiment correspond to a first potential and a second potential, and the first potential and the second potential only represent that the potential of the signal has two different states, and do not represent that the first potential or the second potential has a specific value.

[0088] High-end displays have relatively strict requirements on image quality, especially game professional displays, which usually require high refresh rate. In order to better accommodate both low power consumption and high refresh rate, a partition high refresh rate technology (which can also be referred to as frame rate conversion technology) is generally used, which separately uses high refresh rate for dynamic pictures. This technology requires that each GOA unit in the gate drive circuit can work flexibly and have random gating capability. In addition, with the increase of resolution, and the popularity of virtual reality (VR) display, augmented reality (AR) and three-dimensional (3-dimension, 3D) display applications, in order to reduce the amount of frame transmission data, the gate drive circuit also needs to have random gating capability.

[0089] Currently, in one implementation, each GOA unit in the gate drive circuit provides gate drive signals to multiple rows of pixels in the display row by row, so that the multiple rows of pixels are turned on row by row, that is, real-time adjustment cannot be achieved according to the to-be-displayed picture, and the current display requirements cannot be met. In another implementation, multiple rows of pixels are divided into partitions, and the multiple GOA units included in the gate drive circuit are also designed in partitions, so that local control of high brushing in a partition can be achieved. However, after the gate drive circuit is partitioned, the GOA units in each partition are no longer cascaded, so it is necessary to separately set an enable signal terminal STU for the GOA units in each partition to drive the GOA units in the partition to work, and in some implementations, it is also necessary to separately set a dummy GOA for the GOA units in each partition. In this way, not only the hardware complexity and cost are increased, but also the number of partitions is limited.

[0090] Based on this, the embodiment of the present disclosure provides a decoder type GOA unit, which can make the gate drive circuit have a random strobe capability when applied to the gate drive circuit, and is especially suitable for a display that needs to be partitioned for high brushing. FIG. 1 is a structural schematic diagram of a shift register unit provided by the embodiment of the present disclosure. As shown in FIG. 1, the shift register unit includes a pre-charge circuit 01, a charging circuit 02, a reset circuit 03, and at least two output circuits 04.

[0091] The pre-charge circuit 01 is connected with at least two strobe terminals D0……Dm, a first clock terminal CLK1, a second clock terminal CLK2, and a control node P, and is configured to control the on-off of the first clock terminal CLK1 and the control node P in response to a strobe signal provided by each of the at least two strobe terminals D0……Dm, a first clock signal provided by the first clock terminal CLK1, and a second clock signal provided by the second clock terminal CLK2. m is an integer greater than 1. For example, m can be 7, 9, or other.

[0092] For example, in the same period, the potential of the first clock signal and the potential of the second clock signal are generally opposite. Thus, assuming that the potential of the strobe signal provided by any one of the strobe terminals is the first potential, the pre-charge circuit 01 can control the first clock terminal CLK1 and the control node P to be conductive when the potential of the first clock signal is the first potential and the potential of the second clock signal is the second potential, so that the first clock terminal CLK1 transmits the first clock signal of the first potential to the control node P; and can control the first clock terminal CLK1 and the control node P to be conductive when the potential of the second clock signal is the first potential and the potential of the first clock signal is the second potential, so that the first clock terminal CLK1 transmits the first clock signal of the second potential to the control node P. And assuming that the potential of the strobe signal provided by each of the strobe terminals is the second potential, the pre-charge circuit 01 can control the first clock terminal CLK1 and the control node P to be disconnected when the potential of the first clock signal is the first potential and the potential of the second clock signal is the second potential, and can control the first clock terminal CLK1 and the control node P to be disconnected when the potential of the second clock signal is the first potential and the potential of the first clock signal is the second potential.

[0093] That is, the current shift register unit can be enabled or disabled by controlling the potential of the strobe signal provided by each of the at least two strobe terminals D0 to Dm. If the current shift register unit is enabled, the signal can be normally output, and if the current shift register unit is not enabled, the signal will not be output, so that the purpose of controlling the refresh frequency can be achieved.

[0094] Optionally, the frequency of the strobe signal provided by each of the strobe terminals D0 to Dm can be sequentially reduced, that is, the pulse of the strobe signal provided by each of the strobe terminals can be sequentially reduced.

[0095] Optionally, in the embodiment of the present disclosure, the first potential can be a valid potential, and the second potential can be an invalid potential. For the P-type transistor in the circuit, the first potential can be a low potential relative to the second potential. For the N-type transistor in the circuit, the first potential can be a high potential relative to the second potential.

[0096] The charging circuit 02 is connected with the control node P, the second clock terminal CLK2, the third clock terminal CLK3, the first power terminal VGL and the pull-up node Q respectively, and is configured to control the connection and disconnection of the first power terminal VGL and the pull-up node Q in response to the potential of the control node P and the third clock signal provided by the third clock terminal CLK3, and control the connection and disconnection of the third clock terminal CLK3 and the pull-up node Q in response to the second clock signal.

[0097] For example, the charging circuit 02 is capable of controlling the first power supply end VGL to be connected to the pull-up node Q when the potential of the control node P is the first potential and the potential of the third clock signal is the first potential, so that the first power supply end VGL transmits the first power supply signal to the pull-up node Q; and is capable of controlling the first power supply end VGL to be disconnected from the pull-up node Q when the potential of the control node P is the second potential and / or the potential of the third clock signal is the second potential. Similarly, the charging circuit 02 is capable of controlling the third clock end CLK3 to be connected to the pull-up node Q when the potential of the second clock signal is the first potential, so that the third clock end CLK3 transmits the third clock signal to the pull-up node Q; and is capable of controlling the third clock end CLK3 to be disconnected from the pull-up node Q when the potential of the second clock signal is the second potential. The potential of the first power supply signal can be a low potential.

[0098] The reset circuit 03 is connected with the reset end TRS, the second power supply end VGH, the control node P and the pull-up node Q respectively, and is configured to control the connection and disconnection between the second power supply end VGH and the control node P, and the connection and disconnection between the second power supply end VGH and the pull-up node Q in response to a reset signal provided by the reset end TRS.

[0099] For example, the reset circuit 03 is capable of controlling the second power supply end VGH to be connected to the control node P and the pull-up node Q when the potential of the reset signal is the first potential, so that the second power supply end VGH transmits the second power supply signal to the control node P and the pull-up node Q; and is capable of controlling the second power supply end VGH to be disconnected from the control node P and the pull-up node Q when the potential of the reset signal is the second potential. The potential of the second power supply signal is a high potential.

[0100] The at least two output circuits 04 are respectively connected with the pull-up node Q, one-to-one corresponding at least two output clock ends CLKS1……CLKSn and one-to-one corresponding at least two output ends Scout1……Scoutn. Each output circuit 04 is configured to control the connection and disconnection between the corresponding one output clock end and one output end in response to the potential of the pull-up node Q, so as to output a gate drive signal through the output end. Wherein, n is an integer greater than 1. For example, n can be 2, 4 or other.

[0101] For example, each output circuit 04 is capable of controlling the corresponding one output clock end to be connected to one output end when the potential of the pull-up node Q is the first potential, so that the output clock end transmits an output clock signal to the output end; and is capable of controlling the corresponding one output clock end to be disconnected from one output end when the potential of the pull-up node Q is the second potential. The output end can be connected with a pixel in a display panel through a gate line, and is configured to output a gate drive signal to the pixel.

[0102] To sum up, the shift register unit provided in the embodiment of the present disclosure includes a pre-charge circuit, a charge circuit, a reset circuit and at least two output circuits. The pre-charge circuit can control the potential of a control node based on the gate signals provided by a plurality of gate terminals; the charge circuit can control the potential of a pull-up node based on the potential of the control node and a clock signal; the reset circuit can control the potential of the control node and the pull-up node based on a reset signal; and each of the plurality of output circuits can control the on-off of an output terminal and an output clock terminal based on the potential of the pull-up node. In this way, the gate signals can be flexibly output to the pixels in each sub-region by flexibly setting the gate signals, so that the plurality of output units can flexibly output the gate driving signals to the pixels in each sub-region to drive the pixels to emit light. That is, the shift register unit provided in the embodiment of the present disclosure can flexibly refresh the pixels according to the sub-regions of the display screen.

[0103] Optionally, FIG. 2 is a structural schematic diagram of another shift register unit provided in the embodiment of the present disclosure. As shown in FIG. 2, the shift register unit can further include a pull-down control circuit 05 and a pull-down circuit 06.

[0104] The pull-down control circuit 05 can be connected with the control node P, the second clock terminal CLK2, the third clock terminal CLK3, the control power supply terminal V1, the pull-up node Q and the pull-down node QB respectively, and can be used to control the on-off of the second clock terminal CLK2 and the pull-down node QB in response to the potential of the control node P and the third clock signal, control the on-off of the control power supply terminal V1 and the pull-down node QB in response to the second clock signal, and control the on-off of the second clock terminal CLK2 and the pull-down node QB in response to the potential of the pull-up node Q.

[0105] For example, the pull-down control circuit 05 can control the second clock terminal CLK2 to be connected to the pull-down node QB when the potential of the control node P and / or the potential of the third clock signal is the first potential, so that the second clock terminal CLK2 transmits the second clock signal to the pull-down node QB; and can control the second clock terminal CLK2 to be disconnected from the pull-down node QB when the potential of the control node P and / or the potential of the third clock signal is the second potential. Similarly, the pull-down control circuit 05 can control the control power terminal V1 to be connected to the pull-down node QB when the potential of the second clock signal is the first potential, so that the control power terminal V1 transmits the control power signal to the pull-down node QB; and can control the control power terminal V1 to be disconnected from the pull-down node QB when the potential of the second clock signal is the second potential. Similarly, the pull-down control circuit 05 can control the second clock terminal CLK2 to be connected to the pull-down node QB when the potential of the pull-up node Q is the first potential, so that the second clock terminal CLK2 transmits the second clock signal to the pull-down node QB; and can control the second clock terminal CLK2 to be disconnected from the pull-down node QB when the potential of the pull-up node Q is the second potential.

[0106] The control power terminal V1 can be shared with the second clock terminal CLK2 or the first power terminal VGL. It can be understood that, since the first power terminal VGL can continuously provide the first power signal with the low potential, by setting the control power terminal V1 to be shared with the first power terminal VGL, it is helpful to supplement the potential of the pull-down node QB when low-frequency driving.

[0107] For example, when low-frequency driving, the duration of the low potential of the second clock signal increases, and the potential of the pull-down node QB also continuously decreases. At this time, the first power signal with the low potential can compensate for the loss of the potential of the pull-down node QB through the leakage current of the pull-down control circuit 05, thereby ensuring that the stability of the potential of the pull-down node QB is good.

[0108] The pull-down circuit 06 can be connected to the pull-down node QB, the second power terminal VGH, the pull-up node Q and at least two output terminals Scout1, …, Scoutn respectively, and can be used to control the connection and disconnection of the second power terminal VGH and the pull-up node Q, and the connection and disconnection of the second power terminal VGH and each output terminal in response to the potential of the pull-down node QB.

[0109] For example, the pull-down circuit 06 can control the second power terminal VGH to be connected to the pull-up node Q and each output terminal when the potential of the pull-down node QB is the first potential, so that the second power terminal VGH transmits the second power signal to the pull-up node Q and each output terminal; and can control the second power terminal VGH to be disconnected from the pull-up node Q and each output terminal when the potential of the pull-down node QB is the second potential.

[0110] Optionally, continuing to refer to FIG. 2, it can also be seen that the shift register unit can further comprise a first isolation circuit 07.

[0111] The first isolation circuit 07 can be connected between the control node P and the pull-down control circuit 05, and can also be connected with the first power supply end VGL, and can be used to control the control node P and the pull-down control circuit 05 to be turned on in response to the first power supply signal.

[0112] It can be understood that by providing the first isolation circuit 07, the pull-down control circuit 05 can be prevented from being mistakenly operated due to the leakage of the control node P, that is, the working reliability of the pull-down control circuit 05 can be ensured to be better.

[0113] Optionally, continuing to refer to FIG. 2, it can also be seen that the shift register unit can further comprise a second isolation circuit 08.

[0114] The second isolation circuit 08 can be connected between the pull-up node Q and the at least two output circuits 04, and can also be connected with the first power supply end VGL, and can be used to control the pull-up node Q and the at least two output circuits 04 to be turned on in response to the first power supply signal.

[0115] Like the first isolation circuit 07, by providing the second isolation circuit 08, the output circuit 04 can be prevented from being mistakenly operated due to the leakage of the pull-up node Q, that is, the working reliability of the output circuit 04 can be ensured to be better. In addition, the potential of the pull-up node Q can also be prevented from being affected due to the change of the potential at the node connected between the second isolation circuit 08 and the output circuit 04, that is, the potential stability of the pull-up node Q can also be ensured to be better.

[0116] Optionally, taking the example that the control power supply end V1 and the second clock end CLK2 are shared, FIG. 3 shows a structural schematic diagram of another shift register unit. Taking the example that the control power supply end V1 and the first power supply end VGL are shared, FIG. 4 shows a structural schematic diagram of still another shift register unit. It can be seen from FIG. 3 and FIG. 4 that the pre-charge circuit 01 can comprise a gating sub-circuit 011, an auxiliary control sub-circuit 012 and a pre-charge sub-circuit 013.

[0117] The gating sub-circuit 011 can be connected with the at least two gating ends D0…Dm, the second clock end CLK2 and the intermediate node N respectively, and can be used to control the second clock end CLK2 and the intermediate node N to be turned on or off in response to the gating signal provided by each gating end. The gating sub-circuit 011 can also be referred to as a decoding circuit.

[0118] For example, the gating sub-circuit 011 can control the second clock terminal CLK2 to be connected to the intermediate node N when the potential of the gating signal provided at any gating terminal is the first potential, so that the second clock terminal CLK2 transmits the second clock signal to the intermediate node N; and can control the second clock terminal CLK2 to be disconnected from the intermediate node N when the potential of the gating signal provided at each gating terminal is the second potential.

[0119] The auxiliary control circuit 012 can be connected to the first clock terminal CLK1, the second clock terminal CLK2 and the intermediate node N respectively, and can be configured to control the second clock terminal CLK2 to be connected to or disconnected from the intermediate node N in response to the first clock signal.

[0120] For example, the auxiliary control circuit 012 can control the second clock terminal CLK2 to be connected to the intermediate node N when the potential of the first clock signal is the first potential, so that the second clock terminal CLK2 transmits the second clock signal to the intermediate node N; and can control the second clock terminal CLK2 to be disconnected from the intermediate node N when the potential of the first clock signal is the second potential.

[0121] The pre-charge sub-circuit 013 can be connected to the intermediate node N, the first clock terminal CLK1 and the control node P respectively, and can be configured to control the first clock terminal CLK1 to be connected to or disconnected from the control node P in response to the potential of the intermediate node N and the first clock signal.

[0122] For example, the pre-charge sub-circuit 013 can control the first clock terminal CLK1 to be connected to the control node P when the potential of the intermediate node N is the first potential and / or the potential of the first clock signal is the first potential, so that the first clock terminal CLK1 transmits the first clock signal to the control node P; and can control the first clock terminal CLK1 to be disconnected from the control node P when the potential of the intermediate node N is the second potential and the potential of the first clock signal is the second potential.

[0123] Optionally, with reference to FIGS. 3 and 4, it can also be seen that the second isolation circuit 08 can include at least two isolation sub-circuits 081.

[0124] The at least two isolation sub-circuits 081 can be connected to the at least two output circuits 04 one by one, and can also be connected to the first power supply terminal VGL and the pull-up node Q. Each isolation sub-circuit 081 can be configured to control the pull-up node Q to be connected to or disconnected from a corresponding one of the output circuits 04 in response to the first power supply signal.

[0125] That is, in the embodiments of the present disclosure, for each output circuit 04, one isolation sub-circuit 081 can be correspondingly arranged to isolate the pull-up node Q from the output circuit 04, so as to ensure that each output circuit 04 can work reliably.

[0126] Optionally, continuing to refer to FIG. 2 to FIG. 4, it can be seen that the shift register unit shown therein each includes four output circuits 04. Correspondingly, the four output circuits 04 can be connected with one-to-one corresponding four output clock terminals CLKS1, CLKS2, CLKS3 and CLKS4, and can be connected with one-to-one corresponding four output terminals Scout(i), Scout(i+1), Scout(i+2) and Scout(i+3). i is an integer greater than 0 and less than or equal to n.

[0127] In addition, the second isolation circuit 08 can include four isolation sub-circuits 081 as shown in FIG. 3 and FIG. 4. The nodes where the four isolation sub-circuits 081 are connected with the four output circuits 04 are respectively identified as Q1, Q2, Q3 and Q4, also known as output nodes. On this basis, it can be considered that each output circuit 04 controls the on-off of the corresponding output clock terminal and output terminal in response to the potential of the corresponding output node.

[0128] Optionally, continuing to refer to FIG. 2 to FIG. 4, it can be seen that in the shift register unit shown therein, the pre-charge circuit 01 is connected with eight gating terminals D0, D1, D2, D3, D4, D5, D6 and D7. It can be understood that with reference to FIG. 3 and FIG. 4, the gating sub-circuit 011 included in the pre-charge circuit 01 can be connected with the eight gating terminals D0 to D7.

[0129] Optionally, continuing to refer to FIG. 3 and FIG. 4, it can be seen that the pre-charge sub-circuit 013 can also be connected with the first power supply terminal VGL, and can be used to store the potential of the control node P based on the first power supply signal. In this way, the potential of the control node P can be maintained.

[0130] Optionally, continuing to refer to FIG. 3 and FIG. 4, it can be seen that the pull-down control circuit 05 can also be connected with the second power supply terminal VGH, and can be used to store the potential of the pull-down node QB based on the second power supply signal. In this way, the potential of the pull-down node QB can be maintained.

[0131] Optionally, on the basis of FIG. 3, FIG. 5 shows a schematic diagram of the circuit structure of a shift register unit. On the basis of FIG. 4, FIG. 6 shows another schematic diagram of the circuit structure of a shift register unit. As shown in FIG. 5 and FIG. 6, the gating sub-circuit 011 can include at least two gating transistors T11…T1m.

[0132] The gates of the at least two gating transistors T11…T1m can be connected with one-to-one corresponding at least two gating terminals D0…Dm, the first poles of the at least two gating transistors T11…T1m can each be connected with the second clock terminal CLK2, and the second poles of the at least two gating transistors T11…T1m can each be connected with the intermediate node N.

[0133] It can be understood that since the structures shown in FIG. 3 and FIG. 4 each include eight strobe terminals D0 to D7, the circuit structures shown in FIG. 5 and FIG. 6 each include eight strobe transistors T11 to T18. The gates of the eight strobe transistors T11 to T18 can be connected in one-to-one correspondence with the eight strobe terminals D0 to D7.

[0134] Optionally, it can be seen from FIG. 5 and FIG. 6 that the auxiliary control sub-circuit 012 can include an auxiliary control transistor T20.

[0135] The gate of the auxiliary control transistor T20 can be connected with the first clock terminal CLK1, the first pole of the auxiliary control transistor T20 can be connected with the second clock terminal CLK2, and the second pole of the auxiliary control transistor T20 can be connected with the intermediate node N.

[0136] Optionally, it can be seen from FIG. 5 and FIG. 6 that the pre-charge sub-circuit 013 can include a first pre-charge transistor T31, a second pre-charge transistor T32 and a first storage capacitor Cst1.

[0137] The gate of the first pre-charge transistor T31 can be connected with the intermediate node N, the first pole of the first pre-charge transistor T31 can be connected with the first clock terminal CLK1, and the second pole of the first pre-charge transistor T31 can be connected with the control node P.

[0138] The gate and the first pole of the second pre-charge transistor T32 can be connected with the first clock terminal CLK1, and the second pole of the second pre-charge transistor T32 can be connected with the control node P.

[0139] One end of the first storage capacitor Cst1 can be connected with the first power terminal VGL, and the other end of the first storage capacitor Cst1 can be connected with the control node P. That is, the first storage capacitor Cst1 can be connected in series between the first power terminal VGL and the control node P.

[0140] Optionally, it can be seen from FIG. 5 and FIG. 6 that the pull-down control circuit 05 can include a first pull-down control transistor T41, a second pull-down control transistor T42, a third pull-down control transistor T43, a fourth pull-down control transistor T44 and a second storage capacitor Cst2.

[0141] The gate of the first pull-down control transistor T41 can be connected with the control node P, the first pole of the first pull-down control transistor T41 can be connected with the second pole of the second pull-down control transistor T42, and the second pole of the first pull-down control transistor T41 can be connected with the pull-down node QB.

[0142] The gate of the second pull-down control transistor T42 can be connected with the third clock end CLK3, and the first pole of the second pull-down control transistor T42 can be connected with the second clock end CLK2.

[0143] The gate of the third pull-down control transistor T43 can be connected with the second clock end CLK2, the first pole of the third pull-down control transistor T43 can be connected with the control power end V1, and the second pole of the third pull-down control transistor T43 can be connected with the pull-down node QB. For example, in FIG. 5, the control power end V1 is the second clock end CLK2; in FIG. 6, the control power end V1 is the first power end VGL.

[0144] The gate of the fourth pull-down control transistor T44 can be connected with the pull-up node Q, the first pole of the fourth pull-down control transistor T44 can be connected with the second clock end CLK2, and the second pole of the fourth pull-down control transistor T44 can be connected with the pull-down node QB.

[0145] One end of the second storage capacitor Cst2 can be connected with the second power end VGH, and the other end of the second storage capacitor Cst2 can be connected with the pull-down node QB. That is, the second storage capacitor Cst2 can be connected in series between the second power end VGH and the pull-down node QB.

[0146] Optionally, it can be seen from FIG. 5 and FIG. 6 that the pull-down circuit 06 can include a first pull-down transistor T50 and at least two second pull-down transistors T51…T5n.

[0147] The gate of the first pull-down transistor T50 can be connected with the pull-down node QB, the first pole of the first pull-down transistor T50 can be connected with the second power end VGH, and the second pole of the first pull-down transistor T50 can be connected with the pull-up node Q.

[0148] The gates of the at least two second pull-down transistors T51…T5n can be connected with the pull-down node QB, the first poles of the at least two second pull-down transistors T51…T5n can be connected with the second power end VGH, and the second poles of the at least two second pull-down transistors T51…T5n can be connected with the at least two output ends Scout1…Scoutn one by one.

[0149] It can be understood that, since the structures shown in FIG. 3 and FIG. 4 both include four output circuits 04 corresponding to the four output ends Scout(i) to Scout(i+3), the circuit structures shown in FIG. 5 and FIG. 6 both include four second pull-down transistors T51, T52, T53 and T54. The second poles of the four second pull-down transistors T51 to T54 can be connected with the four output ends Scout(i) to Scout(i+3) one by one.

[0150] Optionally, with continued reference to FIGS. 5 and 6, it can be seen that the first isolation circuit 07 can include a first isolation transistor T60.

[0151] The gate of the first isolation transistor T60 can be connected with the first power terminal VGL, the first pole of the first isolation transistor T60 can be connected with the control node P, and the second pole of the first isolation transistor T60 can be connected with the pull-down control circuit 05. It can be understood that it can be connected with the gate of the first pull-down control transistor T41. That is, the gate of the first pull-down control transistor T41 can be indirectly connected with the control node P through the first isolation transistor T60.

[0152] Optionally, with continued reference to FIGS. 5 and 6, it can be seen that each isolation sub-circuit 081 can include a second isolation transistor T6x.

[0153] The gate of the second isolation transistor T6x can be connected with the first power terminal VGL, the first pole of the second isolation transistor T6x can be connected with the pull-up node Q, and the second pole of the second isolation transistor T6x can be connected with the corresponding output circuit 04. It can be understood that it can be connected with the output node.

[0154] As shown in the structure including four isolation sub-circuits 081 in FIGS. 3 and 4, the circuit structure shown in FIGS. 5 and 6 includes four second isolation transistors T61, T62, T63 and T64. The four second isolation transistors T61 to T64 are respectively connected with the four output circuits 04 one by one.

[0155] Optionally, with continued reference to FIGS. 5 and 6, it can be seen that the charging circuit 02 can include a first charging transistor T71, a second charging transistor T72 and a third charging transistor T73.

[0156] The gate of the first charging transistor T71 can be connected with the control node P, the first pole of the first charging transistor T71 can be connected with the first power terminal VGL, and the second pole of the first charging transistor T71 can be connected with the first pole of the second charging transistor T72.

[0157] The gate of the second charging transistor T72 can be connected with the third clock terminal CLK3, and the second pole of the second charging transistor T72 can be connected with the pull-up node Q.

[0158] The gate of the third charging transistor T73 can be connected with the second clock terminal CLK2, the first pole of the third charging transistor T73 can be connected with the third clock terminal CLK3, and the second pole of the third charging transistor T73 can be connected with the pull-up node Q.

[0159] Optionally, with reference to FIGS. 5 and 6, it can be seen that the reset circuit 03 can include a first reset transistor T81 and a second reset transistor T82.

[0160] The gate of the first reset transistor T81 can be connected with the reset terminal TRS, the first electrode of the first reset transistor T81 can be connected with the second power terminal VGH, and the second electrode of the first reset transistor T81 can be connected with the control node P.

[0161] The gate of the second reset transistor T82 can be connected with the reset terminal TRS, the first electrode of the second reset transistor T82 can be connected with the second power terminal VGH, and the second electrode of the second reset transistor T82 can be connected with the pull-up node Q.

[0162] Optionally, with reference to FIGS. 5 and 6, it can be seen that each output circuit 04 can include an output transistor T9x and a third storage capacitor Cst3x.

[0163] The gate of the output transistor T9x can be connected with the pull-up node Q, the first electrode of the output transistor T9x can be connected with the corresponding output clock terminal, and the second electrode of the output transistor T9x can be connected with the corresponding output terminal.

[0164] One end of the third storage capacitor Cst3x can be connected with the pull-up node Q, and the other end of the third storage capacitor Cst3x can be connected with the corresponding output terminal.

[0165] It can be understood that, on the basis of including the second isolation circuit 08, the gate of the output transistor T9x can be indirectly connected with the pull-up node Q through the second isolation transistor T6x, and one end of the third storage capacitor Cst3x can be indirectly connected with the pull-up node Q through the second isolation transistor T6x. The connection node of the gate of the output transistor T9x and one end of the third storage capacitor Cst3x with the second isolation transistor T6x is referred to as an output node.

[0166] As described above, based on the structure shown in FIG. 3 and FIG. 4, the circuit structure shown in FIG. 5 and FIG. 6 includes four output transistors T91, T92, T93 and T94, and includes four third storage capacitors Cst31, Cst32, Cst33 and Cst34. The gates of the four output transistors T91 to T94 are connected to the four output nodes Q1 to Q4 one by one, the first poles of the four output transistors T91 to T94 are connected to the four output clock terminals CLKS1 to CLKS4 one by one, and the second poles of the four output transistors T91 to T94 are connected to the four output terminals Scout(i) to Scout(i+3) one by one. One end of the four third storage capacitors Cst31, Cst32, Cst33 and Cst34 is connected to the four output nodes Q1 to Q4 one by one, and the other end of the four third storage capacitors Cst31, Cst32, Cst33 and Cst34 is connected to the four output terminals Scout(i) to Scout(i+3) one by one.

[0167] As described above, when the potential of the second clock signal provided by the second clock terminal CLK2 is the second potential (e.g., the high potential), the potential of the pull-down node QB can be maintained by the second storage capacitor Cst2. When low-frequency driving, the duration of the potential of the second clock signal at the first potential (e.g., the low potential) increases, causing the potential of the pull-down node QB to continuously decrease through the fourth pull-down control transistor T44. At this time, the structure shown in FIG. 6 is relative to the structure shown in FIG. 5, and because the first pole of the third pull-down control transistor T43 is connected to the first power terminal VGL that continuously provides the low potential, the drain current of the third pull-down control transistor T43 can compensate for the loss of the potential of the pull-down node QB through the first power terminal VGL, thereby ensuring that the potential stability of the pull-down node QB is good.

[0168] In addition, as described above, because of the presence of the third storage capacitor Cst3x in the output circuit 04, and because of the coupling effect of the capacitor, the potential of the output node (e.g., Q1 to Q4) will change. By setting the second isolation circuit 08, i.e., setting the second isolation transistor T6x to isolate the pull-up node Q and the output node, the embodiment of the present disclosure can ensure that the potential of the pull-up node Q is not affected by the coupling effect of the capacitor, i.e., the potential stability of the pull-up node Q is good.

[0169] Optionally, in one implementation, three clock signal lines can be provided in the display panel for the first clock terminal CLK1, the second clock terminal CLK2 and the third clock terminal CLK3 to be connected to, and for providing clock signals. Alternatively, in another implementation, four clock signal lines can also be provided in the display panel for the first clock terminal CLK1, the second clock terminal CLK2 and the third clock terminal CLK3 to be connected to, and for providing clock signals. On this basis, as shown in the circuit structure of another shift register unit in FIG. 7, the first clock terminal CLK1 can also be replaced by the clock terminal CLK2, the second clock terminal CLK2 can also be replaced by the clock terminal CLK3, and the third clock terminal CLK3 can also be replaced by the clock terminal CLK4.

[0170] It can be understood that, compared with the other implementation, the above-mentioned implementation has fewer clock signal lines to be provided, is more convenient for wiring, simplifies the process, saves costs, and is beneficial to narrow-frame design. While the other implementation has more clock signal lines to be provided, which can ensure that the output waveform can be better overlapped, and meet the output requirements of large size and high PPI. PPI (pixels per inch) refers to the number of pixels that can be provided in 1 inch of the display panel, and is used to represent the resolution.

[0171] Optionally, each transistor in the structures shown in FIGS. 5 to 7 is a P-type transistor. Correspondingly, as described above, the first potential can be a low potential, and the second potential can be a high potential. Of course, in some other embodiments, each transistor can also be an N-type transistor, on the basis of which, as described above, the first potential can be a high potential, and the second potential can be a low potential; or, part of the transistors can be P-type transistors, and the other part of the transistors can be N-type transistors.

[0172] In summary, the embodiments of the present disclosure provide a shift register unit. The shift register unit includes a pre-charge circuit, a charge circuit, a reset circuit and at least two output circuits. The pre-charge circuit can control the potential of a control node based on the gate signals provided by a plurality of gate terminals; the charge circuit can control the potential of a pull-up node based on the potential of the control node and a clock signal; the reset circuit can control the potential of the control node and the pull-up node based on a reset signal; and each output circuit in the plurality of output circuits can control the on-off of an output terminal and an output clock terminal based on the potential of the pull-up node. In this way, the gate signals can be flexibly output to the pixels in each sub-region by flexibly setting the gate signals, so as to drive the pixels in the plurality of rows to emit light. That is, the shift register unit provided by the embodiments of the present disclosure can flexibly refresh the pixels according to the sub-regions of the display picture.

[0173] FIG. 8 is a flow chart of a driving method of a shift register unit according to an embodiment of the present disclosure. The method is used to drive the shift register unit as shown in any one of FIGS. 1 to 7. As shown in FIG. 8, the method comprises the following steps.

[0174] In the reset stage, the potential of the reset signal provided by the reset terminal can be the first potential.

[0175] In the reset stage, the potential of the reset signal provided by the reset terminal can be the first potential.

[0176] In the set stage, the potential of the first clock signal provided by the first clock terminal can be the first potential.

[0177] In the set stage, the potential of the first clock signal provided by the first clock terminal can be the first potential.

[0178] In the gating stage, the potential of the second clock signal provided by the second clock terminal can be the first potential.

[0179] In the gating stage, the potential of the second clock signal provided by the second clock terminal can be the first potential.

[0180] In the output stage, the potential of the pull-up node can control the conduction between the corresponding one of the output clock terminals and the corresponding one of the output terminals.

[0181] In the output stage, the potential of the pull-up node can control the conduction between the corresponding one of the output clock terminals and the corresponding one of the output terminals.

[0182] In the output stage, the potential of the pull-up node can control the conduction between the corresponding one of the output clock terminals and the corresponding one of the output terminals.

[0183] It can be understood that the driving method has substantially the same technical effects as the aforementioned shift register unit embodiments, and thus the technical effects of the driving method will not be described again for the sake of brevity.

[0184] FIG. 9 is a structural schematic diagram of a gate drive circuit according to an embodiment of the present disclosure. As shown in FIG. 9, the gate drive circuit comprises a plurality of groups of shift register units GOA, each group of shift register units GOA comprising at least two shift register units Gate GOA as shown in any one of FIGS. 1 to 7.

[0185] Each group of shift register units GOA shares the first clock terminal CLK1, the second clock terminal CLK2, the third clock terminal CLK3, the output clock terminals CLKS1...CLKSn and the gate terminals D0...Dm, and each group of shift register units GOA is configured to receive different gate signals provided by at least two gate terminals.

[0186] For example, referring to FIG. 9, which is a structural schematic diagram of a gate driving circuit taking the circuit structure of the shift register unit shown in FIG. 5 as an example. In addition, FIG. 10 also schematically shows another structural schematic diagram of a gate driving circuit taking the structure shown in FIG. 7 as an example.

[0187] In the gate driving circuits shown in FIG. 9 and FIG. 10, each shift register unit is connected with four output terminals Scout(i) to Scout(i+3). For example, the first shift register unit Gate GOA(1) is connected with four output terminals Scout(1) to Scout(4); the second shift register unit Gate GOA(2) is connected with four output terminals Scout(5) to Scout(8); and so on. In addition, each group of shift register units GOA is connected with eight gate terminals D0 to D7, and the difference is that each shift register unit in the first group of shift register units GOA receives gate signals provided by the eight gate terminals D0 to D7; each shift register unit in the second group of shift register units GOA receives gate signals provided by the eight gate terminals D0' and D1 to D7. The gate signal provided by D0' is the inverse signal of the gate signal provided by D0. For example, assuming that the gate signal provided by D0 is 1, indicating high, then the gate signal provided by D0' is 0, indicating low. In addition, the difference between FIG. 9 and FIG. 10 is that:

[0188] Each group of shift register units GOA shown in FIG. 9 includes three shift register units, such as Gate GOA(1), Gate GOA(2) and Gate GOA(3). In addition, the first clock terminal CLK1, the second clock terminal CLK2 and the third clock terminal CLK3 in each shift register unit can be connected with three clock signal lines, which are also identified as CLK1 to CLK3. Correspondingly, the four output clock terminals CLKS1 to CLKS4 corresponding to the four output terminals Scout(i) to Scout(i+3) can be connected with 12 clock signal lines CLKE1 to CLKE12.

[0189] Each group of shift register units GOA shown in FIG. 10 includes four shift register units, such as Gate GOA(1), Gate GOA(2), Gate GOA(3), and Gate GOA(4). In addition, the first clock terminal CLK2, the second clock terminal CLK3, and the third clock terminal CLK4 in each shift register unit can be connected with four clock signal lines, which are also marked as CLK1 to CLK4. Correspondingly, the four output clock terminals CLKS1 to CLKS4 corresponding to the four output terminals Scout(i) to Scout(i+3) can be connected with 16 clock signal lines CLKE1 to CLKE16.

[0190] For example, referring to the structure shown in FIG. 5 in combination with FIG. 9, FIG. 11 shows a signal timing diagram of another gate driving circuit. For example, referring to the structure shown in FIG. 7 in combination with FIG. 10, FIG. 12 shows a working timing diagram of a gate driving circuit. In addition, FIG. 11 and FIG. 12 show timing diagrams corresponding to shift register units connected with pixels in the first row to the fourth row in the gate driving circuit. As can be seen from FIG. 11 and FIG. 12, the working of each group of shift register units can be divided into five stages t01 to t05.

[0191] It can be understood that, for the structure shown in FIG. 5, the clock signal line connected with the first clock terminal can refer to the clock signal line CLK1 connected with the clock terminal CLK1; the clock signal line connected with the second clock terminal can refer to the clock signal line CLK2 connected with the clock terminal CLK2; and the clock signal line connected with the third clock terminal can refer to the clock signal line CLK3 connected with the clock terminal CLK3. For the structure shown in FIG. 7, the clock signal line connected with the first clock terminal can refer to the clock signal line CLK2 connected with the clock terminal CLK2; the clock signal line connected with the second clock terminal can refer to the clock signal line CLK3 connected with the clock terminal CLK3; and the clock signal line connected with the third clock terminal can refer to the clock signal line CLK4 connected with the clock terminal CLK4.

[0192] The following describes the structure shown in FIG. 5 in combination with FIG. 11:

[0193] Before the stage t01, the reset terminal TRS can first provide a low-potential reset signal, so that the first reset transistor T81 and the second reset transistor T82 are both turned on, and then the second power supply terminal VGH transmits a high-potential second power supply signal to the control node P and the pull-up node Q.

[0194] In stage t01, the clock signal line CLK1 connected with the first clock end CLK1 can provide a low potential first clock signal, so that the auxiliary control transistor T20 and the second pre-charge transistor T32 are both turned on, thereby the first clock end CLK1 can transmit the low potential first clock signal to the control node P, and the second clock end CLK2 can transmit the high potential second clock signal to the intermediate node N. That is, in stage t01, the potential of the control node P can be set low. Correspondingly, stage t01 is also called P point setting stage. In addition, it can also be seen from FIG. 11 that in stage t01, the eight gating ends D0 to D7 all provide low potential gate signals, i.e. the potentials of the gate signals are all set low, at this time, the gating stage has not yet been entered.

[0195] In stage t02, first, since each shift register unit is connected with the eight gating ends D0 to D7, it can be known that the gate signals provided by the eight gating ends D0 to D7 can correspond to 256 states. And in stage t02, for the first group of shift register units connected with the first 16 output ends Scout(1) to Scout(16), the potentials of the gate signals provided by the eight gating ends D0 to D7 are all high potentials. Correspondingly, the eight gating transistors T11 to T18 in the first group of shift register units can all be turned off, and the potential of the intermediate node N remains the high potential of the last stage. And for the second group of shift register units connected with the 16 output ends Scout(17) to Scout(32), the potential of the gate signal provided by the gating end D0 of the eight gating ends D0 to D7 can be a low potential, and the potentials of the gate signals provided by the remaining gating ends can be high potentials. Correspondingly, at least the gating transistor T11 in the second group of shift register units can be turned on, thereby the second clock end CLK2 can transmit the second clock signal to the intermediate node N. In addition, it can also be seen from FIG. 11 that in stage t02, since the clock signal line CLK2 connected with the second clock end CLK2 can provide a low potential second clock signal, the potential of the intermediate node N can be set low through the turned-on gating transistor T11.

[0196] In stage t03, the clock signal line CLK3 connected with the third clock terminal CLK3 can provide a low third clock signal, so that the second charging transistor T72 is turned on. Because the potential of the control node P can be kept as the low potential of the last stage under the holding action of the first storage capacitor Cst1, the first charging transistor T71 is also turned on, and the first power terminal VGL transmits the low first power signal to the pull-up node Q. Because the four second isolation transistors T61 to T64 can be kept turned on based on the low first power signal, the potentials of the four output nodes Q1 to Q4 are further lowered, and the four output transistors T91 to T94 are turned on. In addition, based on the potentials of the control node P and the third clock signal being low, and the potential of the pull-up node Q being low, the first pull-down control transistor T41, the second pull-down control transistor T42 and the fourth pull-down control transistor T44 are turned on, and the second clock terminal CLK2 transmits the second clock signal to the pull-down control node QB. Because the potential of the second clock signal is high in stage t03, the potential of the pull-down control node QB is high.

[0197] In stage t04, under the coupling action of the third storage capacitor Cst3, the potentials of the four output nodes Q1 to Q4 are further sequentially lowered, so that the four output transistors T91 to T94 are fully turned on. The clock signal lines CLKE1 to CLKE4 connected with the four output clock terminals CLKS1 to CLKS4 sequentially provide low clock signals. In turn, low signals can be sequentially output to the four output terminals Scout1 to Scout4.

[0198] At stage t05, among the eight strobe terminals D0 to D7, the strobe signal provided by the strobe terminal D0 jumps to low level, so that the second group of shift register units is strobed, while the first group of shift register units is no longer strobed. At this time, for the second group of shift register units, the gating transistor T11 included therein can be turned on, the second clock terminal CLK2 can transmit the low-level second clock signal to the intermediate node N, and the potential of the intermediate node N is lowered. Correspondingly, the first pre-charge transistor T31 can be turned on, and the first clock terminal CLK1 can transmit the low-level first clock signal to the control node P, and the potential of the control node P is lowered. In combination with the low-level third clock signal provided by the third clock terminal CLK3, the first pull-down control transistor T41 and the second pull-down control transistor T42 can be turned on, and the second clock terminal CLK2 further transmits the low-level second clock signal to the pull-down control node QB, and the potential of the pull-down control node QB is lowered. Correspondingly, the first pull-down transistor T50 and the four second pull-down transistors T51 to T54 can be turned on, and then the second power supply terminal VGH can output the high-level second power supply signal to the pull-up node Q and the four output terminals Scout1 to Scout4, and the potential of the pull-up node Q and the potentials of the signals output by the four output terminals Scout1 to Scout4 are all high. On the basis of the pull-up node Q being high, because the four second isolation transistors T61 to T64 can be kept turned on based on the low-level first power supply signal, the potentials of the four output nodes Q1 to Q4 can be further raised. The stage t05 can also be referred to as a reset stage, and the stage t05 can be repeatedly performed when the shift register unit is not strobed.

[0199] It can be understood that in combination with FIG. 11, it can also be seen that the stage t05 can actually be divided into three stages t05a, t05b and t05c executed in sequence. FIG. 12 is the same as FIG. 11, and will not be described again.

[0200] In stage t05a, the clock signal line CLK2 connected with the second clock terminal CLK2 can provide the second clock signal with low potential, while the potential of the first clock signal and the potential of the third clock signal can both be high potential, and the potential of the strobe signal provided by the strobe terminal D0 can be low potential. Correspondingly, the third pull-down control transistor T43 and the strobe transistor T11 can both be turned on, so as to make the second clock terminal CLK2 transmit the second clock signal with low potential to the intermediate node N and the pull-down control node QB respectively, i.e., the potential of the intermediate node N and the potential of the pull-down control node QB are both set low. Correspondingly, the first pre-charge transistor T31 can be turned on, so as to make the first clock terminal CLK1 transmit the first clock signal to the control node P. Since the potential of the first clock signal is high potential in stage t05a, the potential of the control node P can be set high. In addition, the first pull-down transistor T50 and the four second pull-down transistors T51-T54 can all be turned on, so as to make the second power supply terminal VGH output the second power supply signal with high potential to the pull-up node Q and the four output terminals Scout1-Scout4, i.e., the potential of the pull-up node Q and the potential of the signals output by the four output terminals Scout1-Scout4 can both be set high. On the basis of the potential of the pull-up node Q being set high, the four output transistors T91-T94 can all be turned off.

[0201] In stage t05b, the clock signal line CLK3 connected with the third clock terminal CLK3 can provide the second clock signal with low potential, while the potential of the first clock signal and the potential of the second clock signal can both be high potential, and the potential of the strobe signal provided by the strobe terminal D0 can be low potential. Correspondingly, the strobe transistor T11 can be turned on, so as to make the second clock terminal CLK2 transmit the second clock signal with high potential to the intermediate node N, i.e., the potential of the intermediate node N is set high, so that the first pre-charge transistor T31 is turned off. In addition, since the potential of the first clock signal is high potential, the second pre-charge transistor T32 can also be turned off. It can be known that in this stage t05b, the control node P can be in a floating state, maintaining the high potential of the previous stage (i.e., stage t05a). Correspondingly, the first pull-down control transistor T41 can be turned off. In addition, under the storage effect of the second storage capacitor Cst2, the potential of the pull-down control node QB can also maintain the low potential of the previous stage (i.e., stage t05a).

[0202] At stage t05c, the clock signal line CLK1 connected with the first clock terminal CLK1 can provide the first clock signal with a low potential, the potential of the second clock signal and the potential of the third clock signal can both be high potentials, and the potential of the strobe signal provided by the selection terminal D0 can be a low potential. Correspondingly, the selection transistor T11, the auxiliary control transistor T20 and the second pre-charge transistor T32 can all be turned on, so that the first clock terminal CLK1 can transmit the first clock signal with a low potential to the control node P, and the second clock terminal CLK2 can transmit the second clock signal with a high potential to the intermediate node N, i.e., the potential of the control node P can be lowered and the potential of the intermediate node N can be raised.

[0203] In addition, as shown in FIG. 5, according to the foregoing description, for a plurality of shift register unit GOA, the potentials of the strobe signals provided by the eight selection terminals D0 to D7 can be controlled to select the shift register unit Gate GOA in any one of the plurality of shift register unit GOA, so that the selected shift register unit GOA can output the gate driving signal to the connected pixel through the output terminal, and the other shift register unit GOA not selected can not output the gate driving signal, thereby flexibly controlling the refresh frequency of the pixel connected with any one of the shift register unit.

[0204] In addition, FIG. 13 also shows a timing diagram of a strobe signal. As shown in FIG. 13, among the eight selection terminals D0 to D7, the frequencies of the strobe signals provided by the first selection terminal D0 to the eighth selection terminal D7 can also be sequentially reduced as described above. In FIG. 13, the first selection terminal D0 is taken as an example. D0 can refer to the strobe signal with an invalid potential provided by the selection terminal D0, and De0 can refer to the strobe signal with a valid potential provided by the selection terminal D0. The other selection terminals are the same, and will not be described here.

[0205] It can be understood that the gate driving circuit has basically the same technical effects as the foregoing shift register unit embodiments, and therefore the technical effects of the gate driving circuit will not be described again for the purpose of brevity.

[0206] FIG. 14 is a structural schematic diagram of a display device according to an embodiment of the present disclosure. As shown in FIG. 14, the display device includes a display panel 10 and a gate driving circuit 00 as shown in FIG. 9 or FIG. 10.

[0207] The display panel 10 includes a plurality of pixels, and the gate driving circuit 00 is connected with the plurality of pixels and is configured to transmit a gate driving signal to the plurality of pixels to drive the plurality of pixels to emit light.

[0208] Optionally, FIG. 15 shows a schematic diagram of a circuit structure of a pixel. As shown in FIG. 15, the pixel can include a pixel circuit and a light emitting element L1. The pixel circuit can include seven transistors M1 to M7 and one capacitor Cst. The pixel circuit is connected with six signal lines, i.e., a pull-up power supply line ELVDD, a gate line Scan(i), a reset control line Scan(i-1), a light emitting control line EM(i), a data signal line Data, and a reset line Init, respectively. The pixel circuit of this architecture is also referred to as a 7T-1C-6L (i.e., seven transistors, one capacitor, and six signal lines) circuit architecture. In addition, the light emitting element L1 is also connected with a pull-down power supply line ELVSS.

[0209] In the pixel circuit, the transistor M1 is a driving transistor, the transistors M2 to M7 are switching transistors, a gate-source voltage difference Vgs of the transistor T1 can be stored in the capacitor Cst, and a driving current I is determined according to the gray scale data. In addition, the transistors M2 and M7 can control the transistor M1 to output the driving current to the light emitting element L1 as a light emitting driving signal under the control of signals provided by the six signal lines, so that the light emitting element L1 can reliably emit light based on the light emitting driving signal and a pull-down power supply signal provided by the pull-down power supply line ELVSS. The transistors M5 and M6 of the transistors M2 to M7 are mainly used to control the transistor M1 to be turned on or turned off with the light emitting element L1 based on a signal provided by the light emitting control line EM(i), i.e., to block the driving current I or to make the driving current I flow into the light emitting element L1. Accordingly, it can be known that the signal provided by the light emitting control line EM(i) can be used for dimming.

[0210] Optionally, the light emitting element L1 can be an organic light-emitting diode (OLED), and FIG. 15 also schematically shows a parasitic capacitor Coled formed between the cathode and the anode of the OLED. In addition, each transistor in the pixel shown in FIG. 15 is a P-type transistor.

[0211] Taking the structure shown in FIG. 15 as an example, FIG. 16 schematically shows a working timing diagram of a pixel. As can be seen from FIG. 16, the pixel light emission can include a stage 1, a stage 2, and a stage 3.

[0212] In the stage 1, the reset control line Scan(i-1) can provide a reset control signal with an effective potential, so that the transistor M4 is turned on, and then the reset line Init outputs a reset signal to the gate of the transistor M1, so as to reset the gate of the transistor M1. In the stage 2, the gate line Scan(i) can provide a gate drive signal with an effective potential, so that the transistors M2, M3 and M7 are all turned on, and then the data line Data outputs a data signal to the first electrode of the transistor M1, the reset line Init outputs a reset signal to the light emitting element L1 to reset the light emitting element L1, and the gate and the second electrode of the transistor M1 are turned on. In the stage 3, the light emitting control line EM(i) can provide a light emitting control signal with an effective potential, so that the transistors M5 and M6 are all turned on, and then the transistor M1 generates a drive current, and the drive current is output to the light emitting element L1, so as to drive the light emitting element L1 to emit light.

[0213] Therefore, it can be known that, in the gate drive circuit provided by the embodiment of the present disclosure, the output end Scout(i) of the shift register unit can be connected with the gate line Scan(i) in the pixel shown in FIG. 15, and is used to output the gate drive signal shown in FIG. 16 to the gate line Scan(i), so as to drive the pixel to emit light.

[0214] Optionally, the display device described in the embodiment of the present disclosure can be any product or component with display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame or a navigator.

[0215] It can be understood that the terms used in the embodiments of the present disclosure are only used to explain the embodiments of the present disclosure, and are not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood as the general meaning understood by those skilled in the art in the field of the present disclosure.

[0216] As used in the specification and claims of this patent application, the terms "first", "second", or "third" and the like, as well as similar terms, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Also, the terms "one" or "a" or "an" do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items. The terms "including" and / or "containing", or the like, mean encompassing the elements listed thereafter, and equivalents thereof, without precluding other elements omitted, "upper", "lower", "left" or "right" are only used to represent relative positional relationship, when the absolute position of the described object is changed, the relative positional relationship can also be changed accordingly. "Connected" means electrical connection. "And / or" means that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist together, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after.

[0217] The above only describes optional embodiments of the present disclosure, and is not intended to limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A shift register unit, comprising: a pre-charge circuit, connected with at least two gate terminals, a first clock terminal, a second clock terminal and a control node respectively, and configured to control the on-off of the first clock terminal and the control node in response to a gate signal provided by each of the gate terminals, a first clock signal provided by the first clock terminal and a second clock signal provided by the second clock terminal; a charge circuit, connected with the control node, the second clock terminal, a third clock terminal, a first power terminal and a pull-up node respectively, and configured to control the on-off of the first power terminal and the pull-up node in response to a potential of the control node and a third clock signal provided by the third clock terminal, and to control the on-off of the third clock terminal and the pull-up node in response to the second clock signal; a reset circuit, connected with a reset terminal, a second power terminal, the control node and the pull-up node respectively, and configured to control the on-off of the second power terminal and the control node in response to a reset signal provided by the reset terminal, and to control the on-off of the second power terminal and the pull-up node; at least two output circuits, connected with the pull-up node, one-to-one corresponding at least two output clock terminals and one-to-one corresponding at least two output terminals respectively, each of the output circuits configured to control the on-off of a corresponding one of the output clock terminals and one of the output terminals in response to a potential of the pull-up node, so as to output a gate drive signal through the output terminal.

2. The shift register cell of claim 1, wherein, The pre-charge circuit comprises: a gate sub-circuit, connected with the at least two gate terminals, the second clock terminal and an intermediate node respectively, and configured to control the on-off of the second clock terminal and the intermediate node in response to a gate signal provided by each of the gate terminals; an auxiliary control sub-circuit, connected with the first clock terminal, the second clock terminal and the intermediate node respectively, and configured to control the on-off of the second clock terminal and the intermediate node in response to a first clock signal; a pre-charge electronic circuit, connected with the intermediate node, the first clock terminal and the control node respectively, and configured to control the on-off of the first clock terminal and the control node in response to a potential of the intermediate node and the first clock signal.

3. The shift register cell of claim 2, wherein, The gate sub-circuit comprises: at least two gate transistors; gates of the at least two gate transistors are connected with the at least two gate terminals one-to-one, first poles of the at least two gate transistors are connected with the second clock terminal, and second poles of the at least two gate transistors are connected with the intermediate node.

4. The shift register cell of claim 2 or 3, wherein, The auxiliary control sub-circuit comprises: an auxiliary control transistor; a gate of the auxiliary control transistor is connected with the first clock terminal, a first pole of the auxiliary control transistor is connected with the second clock terminal, and a second pole of the auxiliary control transistor is connected with the intermediate node.

5. The shift register cell of any of claims 2 to 4, wherein, The pre-charge electronic circuit is further connected with the first power terminal, and is configured to store a potential of the control node based on the first power signal; The pre-charge electronic circuit comprises: a first pre-charge transistor, a second pre-charge transistor and a first storage capacitor; A gate of the first pre-charge transistor is connected with the intermediate node, a first pole of the first pre-charge transistor is connected with the first clock end, and a second pole of the first pre-charge transistor is connected with the control node; A gate and a first pole of the second pre-charge transistor are both connected with the first clock end, and a second pole of the second pre-charge transistor is connected with the control node; One end of the first storage capacitor is connected with the first power supply end, and the other end of the first storage capacitor is connected with the control node.

6. The shift register cell of any one of claims 1 to 5, wherein, The shift register unit further comprises: A pull-down control circuit is connected with the control node, the second clock end, the third clock end, a control power supply end, the pull-up node and a pull-down node respectively, and is used for controlling the on-off of the second clock end and the pull-down node in response to the potential of the control node and the third clock signal, controlling the on-off of the control power supply end and the pull-down node in response to the second clock signal, and controlling the on-off of the second clock end and the pull-down node in response to the potential of the pull-up node; The pull-down control circuit is further connected with the second power supply end, and is used for storing the potential of the pull-down node based on the second power supply signal; The pull-down control circuit comprises a first pull-down control transistor, a second pull-down control transistor, a third pull-down control transistor, a fourth pull-down control transistor and a second storage capacitor; A gate of the first pull-down control transistor is connected with the control node, a first pole of the first pull-down control transistor is connected with a second pole of the second pull-down control transistor, and a second pole of the first pull-down control transistor is connected with the pull-down node; 7. The shift register cell of claim 6, wherein, A gate of the second pull-down control transistor is connected with the third clock end, and a first pole of the second pull-down control transistor is connected with the second clock end; A gate of the third pull-down control transistor is connected with the second clock end, a first pole of the third pull-down control transistor is connected with the control power supply end, and a second pole of the third pull-down control transistor is connected with the pull-down node; A gate of the fourth pull-down control transistor is connected with the pull-up node, a first pole of the fourth pull-down control transistor is connected with the second clock end, and a second pole of the fourth pull-down control transistor is connected with the pull-down node; One end of the second storage capacitor is connected with the second power supply end, and the other end of the second storage capacitor is connected with the pull-down node. The pull-down circuit comprises a first pull-down transistor and at least two second pull-down transistors. ​ ​ 8. The shift register cell of claim 6 or 7, wherein, ​ The gate of the first pull-down transistor is connected with the pull-down node, the first pole of the first pull-down transistor is connected with the second power supply end, and the second pole of the first pull-down transistor is connected with the pull-up node. The gates of the at least two second pull-down transistors are connected with the pull-down node, the first poles of the at least two second pull-down transistors are connected with the second power supply end, and the second poles of the at least two second pull-down transistors are connected with the at least two output ends one by one. The shift register unit further comprises:

9. The shift register cell of any of claims 6 to 8, wherein, A first isolation circuit is connected between the control node and the pull-down control circuit, and is further connected with the first power supply end, and is used for controlling the control node and the pull-down control circuit to be turned on in response to the first power supply signal. The first isolation circuit comprises a first isolation transistor.

10. The shift register cell of claim 9, wherein, The gate of the first isolation transistor is connected with the first power supply end, the first pole of the first isolation transistor is connected with the control node, and the second pole of the first isolation transistor is connected with the pull-down control circuit. The shift register unit further comprises:

11. The shift register cell of any one of claims 1 to 10, wherein, A second isolation circuit is connected between the pull-up node and the at least two output circuits, and is further connected with the first power supply end, and is used for controlling the pull-up node and the at least two output circuits to be turned on in response to the first power supply signal. The second isolation circuit comprises at least two isolation sub-circuits.

12. The shift register cell of claim 11, wherein, The at least two isolation sub-circuits are connected with the at least two output circuits one by one, and are further connected with the first power supply end and the pull-up node, and each isolation sub-circuit is used for controlling the pull-up node and a corresponding output circuit to be turned on in response to the first power supply signal. Each isolation sub-circuit comprises a second isolation transistor.

13. The shift register cell of claim 12, wherein, The gate of the second isolation transistor is connected with the first power supply end, the first pole of the second isolation transistor is connected with the pull-up node, and the second pole of the second isolation transistor is connected with a corresponding output circuit. The charging circuit comprises a first charging transistor, a second charging transistor and a third charging transistor. The gate of the first charging transistor is connected with the control node, the first pole of the first charging transistor is connected with the first power supply end, and the second pole of the first charging transistor is connected with the first pole of the second charging transistor.

14. The shift register cell of any one of claims 1 to 13, wherein, The gate of the second charging transistor is connected with the third clock end, and the second pole of the second charging transistor is connected with the pull-up node. The gate of the third charging transistor is connected with the second clock end, the first pole of the third charging transistor is connected with the third clock end, and the second pole of the third charging transistor is connected with the pull-up node. The reset circuit comprises a first reset transistor and a second reset transistor. The gate of the first reset transistor is connected with the reset end, the first pole of the first reset transistor is connected with the second power supply end, and the second pole of the first reset transistor is connected with the control node.

15. The shift register cell of any one of claims 1 to 14, wherein, ​ ​ A gate of the second reset transistor is connected with the reset terminal, a first electrode of the second reset transistor is connected with the second power terminal, and a second electrode of the second reset transistor is connected with the pull-up node.

16. The shift register cell of any one of claims 1 to 15, wherein, Each of the output circuits comprises an output transistor and a third storage capacitor. A gate of the output transistor is connected with the pull-up node, a first electrode of the output transistor is connected with the corresponding output clock terminal, and a second electrode of the output transistor is connected with the corresponding output terminal. One end of the third storage capacitor is connected with the pull-up node, and the other end of the third storage capacitor is connected with the corresponding output terminal.

17. The shift register cell of any one of claims 1 to 16, wherein, The shift register unit comprises four of the output circuits. The pre-charge circuit is connected with eight of the gating terminals.

18. A driving method of a shift register unit, for driving the shift register unit according to any one of claims 1 to 17; the method comprising: in a reset phase, the reset circuit controls the second power terminal to be conductive with the control node and the pull-up node respectively in response to a reset signal provided by the reset terminal; in a set phase, the pre-charge circuit controls the first clock terminal to be conductive with the control node in response to a first clock signal provided by the first clock terminal; in a gating phase, the pre-charge circuit controls the first clock terminal to be conductive with the control node in response to a gating signal provided by each of the at least two gating terminals and a second clock signal provided by the second clock terminal, and the charge circuit controls the third clock terminal to be conductive with the pull-up node in response to the second clock signal provided by the second clock terminal; in an input phase, the charge circuit controls the first power terminal to be conductive with the pull-up node in response to a third clock signal provided by the third clock terminal and a potential of the control node; in an output phase, each of the at least two output circuits controls a corresponding one of the output terminals to be conductive with a corresponding one of the output clock terminals in response to a potential of the pull-up node.

19. A gate drive circuit, the gate drive circuit comprising: a plurality of groups of shift register units, each of the groups of shift register units comprising at least two of the shift register units according to any one of claims 1 to 17; wherein the groups of shift register units share the first clock terminal, the second clock terminal, the third clock terminal, the output clock terminal and the gating terminals, and each of the groups of shift register units is configured to receive different gating signals provided by the at least two gating terminals.

20. A display device comprising: a display panel, and the gate driving circuit according to claim 19; wherein the display panel comprises a plurality of pixels, the gate driving circuit is connected with the plurality of pixels and is configured to transmit gate driving signals to the plurality of pixels to drive the plurality of pixels to emit light. ​

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