Shift register unit and driving method therefor, light-emission control circuit, and display apparatus

Abstract

Provided are a shift register unit and a driving method therefor, a light-emission control circuit, and a display apparatus, relating to the technical field of display. The shift register unit comprises a preceding-stage decoding circuit and at least two subsequent-stage driving circuits. The preceding-stage decoding circuit is capable of controlling the potential of a control node on the basis of a gating signal provided by at least one gating terminal and a clock signal provided by a clock terminal. Each of the subsequent-stage driving circuits is capable of outputting a first power supply signal or a second power supply signal to a subsequent-stage output terminal on the basis of the potential of the control node. Hence, partitioned gating can be achieved by flexibly configuring gating signals, so that various subsequent-stage driving circuits in different shift register units can flexibly output light-emission control signals to multiple rows of pixels, thereby driving the multiple rows of pixels to emit light. That is, the shift register unit can flexibly refresh pixels on the basis of display-frame partitioning.

Description

Shift register unit and driving method thereof, light emitting control circuit, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register unit and a driving method thereof, a light emitting control circuit, and a display device. Background Art

[0002] Similar to the gate driving circuit, the light emitting control circuit can also be disposed on the display panel using gate driver on array (GOA) technology to facilitate a narrow frame design.

[0003] In the related art, the light-emitting control circuit usually includes multiple cascaded GOA units, which are connected one-to-one to multiple rows of pixels on the display panel and are used to transmit light-emitting control signals to the multiple rows of pixels row by row to light up the pixels row by row, that is, to achieve row-by-row scanning and refreshing, so that the display panel can display the picture.

[0004] However, the light emitting control circuit in the related art has a single driving mode and cannot flexibly refresh different area partitions on the display panel according to the display image.

[0005] Summary of the Invention

[0006] Provided are a shift register unit and a driving method thereof, a light emitting control circuit, and a display device. The technical solution is as follows:

[0007] In one aspect, a shift register unit is provided, the shift register unit comprising: a front-stage decoding circuit and at least two rear-stage driving circuits;

[0008] The pre-stage decoding circuit includes: a pre-charging circuit, which is respectively connected to at least two strobe terminals, a first clock terminal, a second clock terminal, and a control node, and is used to control the connection and disconnection between the first clock terminal and the control node in response to a strobe signal provided by each of the strobe terminals, a first clock signal provided by the first clock terminal, and a second clock signal provided by the second clock terminal; each of the post-stage driving circuits includes:

[0009] an input circuit, connected to the control node, the control clock terminal, the input clock terminal, and the subsequent pull-up node, respectively, and configured to control the connection and disconnection between the input clock terminal and the subsequent pull-up node in response to the potential of the control node, the control clock signal provided by the control clock terminal, and the input clock signal provided by the input clock terminal;

[0010] a rear-stage pull-down control circuit, connected to the control node, the control clock terminal, the rear-stage pull-up node, the first power terminal, and the rear-stage pull-down node, respectively, and configured to control the connection and disconnection between the control clock terminal and the rear-stage pull-down node in response to the potential of the control node, and to control the connection and disconnection between the first power terminal and the rear-stage pull-down node in response to the potential of the rear-stage pull-up node;

[0011] a subsequent pull-down circuit, connected to the subsequent pull-down node, the first power supply terminal, and the subsequent output terminal, respectively, and configured to control the connection and disconnection between the first power supply terminal and the subsequent output terminal in response to the potential of the subsequent pull-down node;

[0012] The post-stage output circuit is respectively connected to the post-stage pull-up node, the second power supply terminal and the post-stage output terminal, and is used to control the on-off of the second power supply terminal and the post-stage output terminal in response to the potential of the post-stage pull-up node, so as to output a light-emitting control signal through the post-stage output terminal.

[0013] Optionally, the subsequent pull-down control circuit includes:

[0014] a first pull-down control subcircuit, connected to the control node, the control clock terminal, and the subsequent pull-down node, respectively, and configured to control the connection and disconnection between the control clock terminal and the subsequent pull-down node in response to the potential of the control node;

[0015] The second pull-down control subcircuit is respectively connected to the subsequent pull-up node, the first power supply terminal and the subsequent pull-down node, and is used to control the connection and disconnection between the first power supply terminal and the subsequent pull-down node in response to the potential of the subsequent pull-up node.

[0016] Optionally, the first pull-down control subcircuit includes: a first transistor;

[0017] The gate of the first transistor is connected to the control node, the first electrode of the first transistor is connected to the control clock terminal, and the second electrode of the first transistor is connected to the subsequent pull-down node.

[0018] Optionally, the second pull-down control subcircuit includes: a second transistor;

[0019] The gate of the second transistor is connected to the subsequent pull-up node, the first electrode of the second transistor is connected to the first power supply terminal, and the second electrode of the second transistor is connected to the subsequent pull-down node.

[0020] Optionally, the post-stage driving circuit further includes:

[0021] The first holding circuit is connected between the first pull-down control sub-circuit and the subsequent pull-down node, and is also connected to the control clock terminal, and is used to control the on-off of the first pull-down control sub-circuit and the subsequent pull-down node in response to the control clock signal.

[0022] Optionally, the first holding circuit includes: a third transistor;

[0023] The gate of the third transistor is connected to the control clock terminal, the first electrode of the third transistor is connected to the first pull-down control sub-circuit, and the second electrode of the third transistor is connected to the subsequent pull-down node.

[0024] Optionally, the post-stage driving circuit further includes:

[0025] The second holding circuit is connected to the first power supply terminal and the subsequent pull-down node respectively, and is used to maintain the potential of the subsequent pull-down node based on a first power supply signal provided by the first power supply terminal.

[0026] Optionally, the second holding circuit includes: a first capacitor;

[0027] One end of the first capacitor is connected to the first power supply end, and the other end of the first capacitor is connected to the subsequent pull-down node.

[0028] Optionally, the post-stage driving circuit further includes:

[0029] The subsequent stage isolation circuit is connected between the subsequent stage pull-up node and the subsequent stage output circuit, and is also connected to the second power supply terminal, and is used to control the subsequent stage pull-up node and the subsequent stage output circuit to be conductive in response to the second power supply signal.

[0030] Optionally, the post-stage isolation circuit includes: a fourth transistor;

[0031] The gate of the fourth transistor is connected to the second power supply terminal, the first electrode of the fourth transistor is connected to the subsequent pull-up node, and the second electrode of the fourth transistor is connected to the subsequent output circuit.

[0032] Optionally, the subsequent pull-down circuit includes: a fifth transistor;

[0033] The gate of the fifth transistor is connected to the subsequent pull-down node, the first electrode of the fifth transistor is connected to the first power supply terminal, and the second electrode of the fifth transistor is connected to the subsequent output terminal.

[0034] Optionally, the fifth transistor includes: a first sub-transistor and a second sub-transistor connected in series;

[0035] The gate of the first sub-transistor and the gate of the second sub-transistor are both connected to the subsequent pull-down node, the first electrode of the first sub-transistor is connected to the first power supply terminal, the second electrode of the first sub-transistor is connected to the first electrode of the second sub-transistor, and the second electrode of the second sub-transistor is connected to the subsequent output terminal; the subsequent driving circuit further includes:

[0036] The anti-leakage circuit is respectively connected to the post-stage output terminal, the second power supply terminal and the series node of the first sub-transistor and the second sub-transistor, and is used to control the connection and disconnection of the second power supply terminal and the series node in response to the potential of the post-stage output terminal.

[0037] Optionally, the anti-leakage circuit includes: a sixth transistor;

[0038] The gate of the sixth transistor is connected to the subsequent stage output terminal, the first electrode of the sixth transistor is connected to the second power supply terminal, and the second electrode of the sixth transistor is connected to the series node.

[0039] Optionally, the input circuit includes: a seventh transistor, an eighth transistor and a ninth transistor;

[0040] The gate electrode and the first electrode of the seventh transistor are both connected to the input clock terminal, and the second electrode of the seventh transistor is connected to the subsequent pull-up node;

[0041] The gate of the eighth transistor is connected to the control node, the first electrode of the eighth transistor is connected to the second electrode of the ninth transistor, and the second electrode of the eighth transistor is connected to the subsequent pull-up node;

[0042] The gate of the ninth transistor is connected to the control clock terminal, and the first electrode of the ninth transistor is connected to the input clock terminal.

[0043] Optionally, the post-stage output circuit includes: a tenth transistor and a second capacitor;

[0044] The gate of the tenth transistor is connected to the subsequent stage pull-up node, the first electrode of the tenth transistor is connected to the second power supply terminal, and the second electrode of the tenth transistor is connected to the subsequent stage output terminal;

[0045] One end of the second capacitor is connected to the subsequent stage pull-up node, and the other end of the second capacitor is connected to the subsequent stage output terminal.

[0046] Optionally, the pre-charging circuit is further connected to the second power supply terminal and is configured to store the potential of the control node based on the second power supply signal; and the pre-decoding circuit further includes:

[0047] a charging circuit, connected to the control node, the second clock terminal, the third clock terminal, the second power supply terminal, and the previous-stage pull-up node, respectively, and configured to control the connection and disconnection between the second power supply terminal and the previous-stage pull-up node in response to the potential of the control node and a third clock signal provided by the third clock terminal, and to control the connection and disconnection between the third clock terminal and the previous-stage pull-up node in response to the second clock signal;

[0048] a reset circuit, connected to the reset terminal, the first power terminal, the control node, and the previous-stage pull-up node, respectively, and configured to control the connection and disconnection between the first power terminal and the control node, and the connection and disconnection between the first power terminal and the previous-stage pull-up node, in response to a reset signal provided by the reset terminal;

[0049] At least two front-stage output circuits are respectively connected to the front-stage pull-up node, the at least two output clock terminals corresponding to each other, and the at least two front-stage output terminals corresponding to each other, each of the front-stage output circuits being configured to control the connection and disconnection between a corresponding output clock terminal and a corresponding front-stage output terminal in response to the potential of the front-stage pull-up node;

[0050] a front-stage pull-down control circuit, connected to the control node, the second clock terminal, the third clock terminal, the first power terminal, the second power terminal, the front-stage pull-up node, and the front-stage pull-down node, respectively, and configured to control the connection and disconnection between the second clock terminal and the front-stage pull-down node in response to the potential of the control node and the third clock signal, control the connection and disconnection between the second power terminal and the front-stage pull-down node in response to the second clock signal, control the connection and disconnection between the second clock terminal and the front-stage pull-down node in response to the potential of the front-stage pull-up node, and store the potential of the front-stage pull-down node based on the first power signal;

[0051] The front-stage pull-down circuit is respectively connected to the front-stage pull-down node, the first power supply terminal, the front-stage pull-up node and the at least two front-stage output terminals, and is used to control the on-off connection between the first power supply terminal and the front-stage pull-up node in response to the potential of the front-stage pull-down node, and to control the on-off connection between the first power supply terminal and each of the front-stage output terminals, so as to output a gate drive signal through the front-stage output terminal.

[0052] Optionally, the pre-stage decoding circuit further includes:

[0053] a first front-stage isolation circuit, connected between the control node and the front-stage pull-down control circuit, and further connected to the second power supply terminal, and configured to control conduction between the control node and the front-stage pull-down control circuit in response to the second power supply signal;

[0054] The second front-stage isolation circuit is connected between the front-stage pull-up node and the at least two front-stage output circuits, and is also connected to the second power supply terminal, and is used to control the front-stage pull-up node and the at least two front-stage output circuits to be conductive in response to the second power supply signal.

[0055] In another aspect, a method for driving a shift register unit is provided, for driving the shift register unit according to the above aspect; the method comprising:

[0056] In the first stage, in the pre-decoding circuit, the precharge circuit controls the first clock terminal to be conductive with the control node in response to a gating signal provided by each of the at least two gating terminals, a first clock signal provided by the first clock terminal, and a second clock signal provided by the second clock terminal;

[0057] In the second stage, in each subsequent-stage driving circuit, the subsequent-stage input circuit controls the input clock terminal to be conductively connected to the subsequent-stage pull-up node in response to the potential of the control node, the control clock signal provided by the control clock terminal, and the input clock signal provided by the input clock terminal; the subsequent-stage pull-down control circuit controls the control clock terminal to be conductively connected to the subsequent-stage pull-down node in response to the potential of the control node; and the subsequent-stage pull-down circuit controls the first power supply terminal to be conductively connected to the subsequent-stage output terminal in response to the potential of the subsequent-stage pull-down node;

[0058] In the third stage, in each of the post-stage driving circuits, the post-stage input circuit controls the input clock terminal and the post-stage pull-up node to be connected in response to the input clock signal, the post-stage pull-down control circuit controls the control clock terminal and the post-stage pull-down node to be connected in response to the potential of the control node, and controls the first power supply terminal and the post-stage pull-down node to be connected in response to the potential of the post-stage pull-up node, and the post-stage output circuit controls the second power supply terminal and the post-stage output terminal to be connected in response to the potential of the post-stage pull-up node.

[0059] In another aspect, a light emitting control circuit is provided, the light emitting control circuit comprising: a plurality of groups of shift register units, each group of the shift register units comprising: at least two shift register units as described in the above aspect;

[0060] Each group of shift register units shares a first clock terminal, a second clock terminal, a control clock terminal, an input clock terminal and a strobe terminal, and each group of shift register units is configured to receive different strobe signals provided by at least two of the strobe terminals.

[0061] In another aspect, a display device is provided, comprising: a display panel, and the light emitting control circuit as described in the above-mentioned further aspect;

[0062] The display panel includes a plurality of pixels, and the light emitting control circuit is connected to the plurality of pixels and is used to transmit a light emitting control signal to the plurality of pixels to drive the plurality of pixels to emit light. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0064] FIG1 is a schematic structural diagram of a shift register unit provided by an embodiment of the present disclosure;

[0065] FIG2 is a schematic structural diagram of another shift register unit provided by an embodiment of the present disclosure;

[0066] FIG3 is a schematic structural diagram of another shift register unit provided by an embodiment of the present disclosure;

[0067] FIG4 is a schematic structural diagram of another shift register unit provided by an embodiment of the present disclosure;

[0068] FIG5 is a schematic diagram of a circuit structure of a post-stage driving circuit provided in an embodiment of the present disclosure;

[0069] FIG6 is a schematic diagram of the circuit structure of another post-stage driving circuit provided in an embodiment of the present disclosure;

[0070] FIG7 is a schematic diagram of a circuit structure of another post-stage driving circuit provided in an embodiment of the present disclosure;

[0071] FIG8 is a schematic diagram of a circuit structure of another post-stage driving circuit provided in an embodiment of the present disclosure;

[0072] FIG9 is a schematic structural diagram of a pre-decoding circuit provided by an embodiment of the present disclosure;

[0073] FIG10 is a schematic structural diagram of another pre-stage decoding circuit provided in an embodiment of the present disclosure;

[0074] FIG11 is a schematic diagram of the circuit structure of a pre-stage decoding circuit provided in an embodiment of the present disclosure;

[0075] FIG12 is a schematic structural diagram of another shift register unit provided in an embodiment of the present disclosure;

[0076] FIG13 is a schematic diagram of a circuit structure of a shift register unit provided in an embodiment of the present disclosure;

[0077] FIG14 is a schematic flow chart of a driving method of a shift register unit provided in an embodiment of the present disclosure;

[0078] FIG15 is a schematic structural diagram of a light emitting control circuit provided in an embodiment of the present disclosure;

[0079] FIG16 is a schematic diagram of the working timing of a shift register unit provided by an embodiment of the present disclosure;

[0080] FIG17 is a timing diagram of a strobe signal provided by an embodiment of the present disclosure;

[0081] FIG18 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure;

[0082] FIG19 is a schematic diagram of a circuit structure of a pixel provided by an embodiment of the present disclosure;

[0083] FIG20 is a schematic diagram of the working timing of a pixel provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0084] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0085] It should be noted that the transistors used in all embodiments of the present disclosure can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Based on their function in the circuit, the transistors used in the embodiments of the present disclosure are primarily switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their source and drain are interchangeable. The source is referred to as the first electrode and the drain as the second electrode, or the drain is referred to as the first electrode and the source as the second electrode. According to the configuration in the accompanying drawings, the middle end of the transistor is defined as the gate, the signal input end as the source, and the signal output end as the drain. Furthermore, the switching transistors used in the embodiments of the present disclosure may include either a P-type transistor or an N-type transistor, or a combination thereof. A P-type transistor is turned on when the gate voltage is low and turned off when the gate voltage is high, while an N-type transistor is turned on when the gate voltage is high and turned off when the gate voltage is low. Furthermore, multiple signals in each embodiment correspond to a first potential and a second potential. The first potential and the second potential merely represent that the potential of the signal has two different states and do not represent that the first potential or the second potential has a specific value.

[0086] High-end displays have more stringent requirements on image quality, especially professional gaming displays, which usually require a higher refresh rate. In order to better match low power consumption and high refresh rate, partitioned high refresh technology (also known as intra-frame frequency conversion technology) is generally adopted, and high refresh is used separately for dynamic images. This technology requires that each GOA unit in the gate drive circuit and each GOA unit in the light-emitting control circuit can work flexibly and have random gating capabilities. In addition, with the increase in resolution and the popularity of virtual reality (VR) display, augmented reality (AR) and three-dimensional (3D) display applications, in order to reduce the amount of frame transmission data, the gate drive circuit and the light-emitting control circuit are also required to have random gating capabilities.

[0087] However, each GOA unit in a common gate drive circuit can provide a gate drive signal to the multi-row pixels in the display row by row, so that the multi-row pixels are turned on row by row, and it is impossible to make real-time adjustments according to the picture to be displayed, and it is impossible to meet the current display requirements. Or in some implementations, it is also considered to partition the multi-row pixels, and accordingly, the multiple GOA units included in the gate drive circuit are also designed in a partitioning manner, so that a certain partition high refresh can be locally controlled. However, after the gate drive circuit is partitioned, because the GOA units of each partition are no longer cascaded, it is necessary to separately set the start signal terminal STU for the GOA units of each partition to drive the GOA units in the partition to work, and in some implementation methods, it is also necessary to separately set a dummy GOA for the GOA units of each partition. In this way, not only the hardware complexity and cost are increased, but also the number of partitions is limited. However, it is currently impossible to achieve partitioning work for the light-emitting control circuit, and it does not have random gating capability.

[0088] Based on this, the present disclosure provides a decoder-type GOA unit. When applied to a light-emitting control circuit, it can provide the light-emitting control circuit with random gating capability, making it particularly suitable for displays requiring high refresh rates in different zones. Figure 1 is a schematic diagram of the structure of a shift register unit provided by the present disclosure. As shown in Figure 1, the shift register unit includes: a pre-stage decoding circuit 10 and at least two post-stage driver circuits 00.

[0089] 2 , it can be seen that the pre-decoding circuit 10 includes a pre-charging circuit 11 .

[0090] The precharge circuit 11 is respectively connected to at least two strobe terminals D0 ... Dm, a first clock terminal CLK1, a second clock terminal CLK2, and a control node P, and is configured to control the connection and disconnection between the first clock terminal CLK1 and the control node P in response to a strobe signal provided by each of the at least two strobe terminals D0 ... Dm, a first clock signal provided by the first clock terminal CLK1, and a second clock signal provided by the second clock terminal CLK2. Here, m is an integer greater than 1. For example, m can be 7, 9, or other integers.

[0091] For example, in the same time period, the potential of the first clock signal and the potential of the second clock signal are generally opposite. Therefore, assuming that the potential of the selection signal provided by any selection terminal is the first potential, the pre-charge circuit 11 can control the first clock terminal CLK1 to be conductive with the control node P when the potential of the first clock signal is the first potential and the potential of the second clock signal is the second potential, so that the first clock terminal CLK1 transmits the first clock signal of the first potential to the control node P; and can control the first clock terminal CLK1 to be conductive with the control node P when the potential of the second clock signal is the first potential and the potential of the first clock signal is the second potential, so that the first clock terminal CLK1 transmits the first clock signal of the second potential to the control node P. Assuming that the potential of the selection signal provided by each selection terminal is the second potential, the pre-charging circuit 11 can control the first clock terminal CLK1 to be connected to the control node P when the potential of the first clock signal is the first potential and the potential of the second clock signal is the second potential, so that the first clock terminal CLK1 transmits the first clock signal to the control node P; and can control the first clock terminal CLK1 to be disconnected from the control node P when the potential of the second clock signal is the first potential and the potential of the first clock signal is the second potential.

[0092] That is, the current shift register unit can be enabled or disabled by controlling the potential of the enable signal provided by each of the at least two enable terminals D0 ... Dm. If the current shift register unit is enabled, it can output a signal normally; if the current shift register unit is disabled, it will not output a signal, thereby achieving the purpose of controlling the refresh frequency.

[0093] Optionally, from the gate terminal D0 to the gate terminal Dm, the frequencies of the gate signals provided by the gate terminals may decrease in sequence, that is, the pulses of the gate signals provided by the gate terminals may decrease in sequence.

[0094] Optionally, in the disclosed embodiment, the first potential may be an effective potential, and the second potential may be an ineffective potential. For a P-type transistor in the circuit, the first potential may be a low potential relative to the second potential. For an N-type transistor in the circuit, the first potential may be a high potential relative to the second potential.

[0095] 2 , it can be seen that each subsequent-stage driving circuit 00 includes an input circuit 01 , a subsequent-stage pull-down control circuit 02 , a subsequent-stage pull-down circuit 03 , and a subsequent-stage output circuit 04 .

[0096] Among them, the input circuit 01 is respectively connected to the control node P, the control clock terminal CLKE, the input clock terminal CLKP and the subsequent pull-up node Q_em, and is used to control the on and off of the input clock terminal CLKP and the subsequent pull-up node Q_em in response to the potential of the control node P, the control clock signal provided by the control clock terminal CLKE and the input clock signal provided by the input clock terminal CLKP.

[0097] For example, the input circuit 01 can control the input clock terminal CLKP to be connected to the subsequent pull-up node Q_em when the potential of the control node P is a first potential and the potential of the control clock signal is the first potential, or control the input clock terminal CLKP to be connected to the subsequent pull-up node Q_em when the potential of the input clock signal is the first potential, so that the input clock terminal CLKP transmits the input clock signal to the subsequent pull-up node Q_em; and can control the input clock terminal CLKP to be disconnected from the subsequent pull-up node Q_em when the potential of the control node P is a second potential and / or the potential of the control clock signal is the second potential, or control the input clock terminal CLKP to be disconnected from the subsequent pull-up node Q_em when the potential of the input clock signal is the second potential.

[0098] The rear-stage pull-down control circuit 02 is respectively connected to the control node P, the control clock terminal CLKE, the rear-stage pull-up node Q_em, the first power supply terminal VGH and the rear-stage pull-down node QB_em, and is used to control the connection and disconnection of the control clock terminal CLKE and the rear-stage pull-down node QB_em in response to the potential of the control node P, and to control the connection and disconnection of the first power supply terminal VGH and the rear-stage pull-down node QB_em in response to the potential of the rear-stage pull-up node Q_em.

[0099] For example, the rear-stage pull-down control circuit 02 can control the control clock terminal CLKE to be conductive with the rear-stage pull-down node QB_em when the potential of the control node P is at a first potential, so that the control clock terminal CLKE transmits a control clock signal to the rear-stage pull-down node QB_em; and can control the control clock terminal CLKE to be disconnected from the rear-stage pull-down node QB_em when the potential of the control node P is at a second potential. Similarly, the rear-stage pull-down control circuit 02 can control the first power terminal VGH to be conductive with the rear-stage pull-down node QB_em when the potential of the rear-stage pull-up node Q_em is at a first potential, so that the first power terminal VGH transmits a first power signal to the rear-stage pull-down node QB_em; and can control the first power terminal VGH to be disconnected from the rear-stage pull-down node QB_em when the potential of the rear-stage pull-up node Q_em is at a second potential. The potential of the first power signal can be a high potential.

[0100] The subsequent pull-down circuit 03 is connected to the subsequent pull-down node QB_em, the first power supply terminal VGH and the subsequent output terminal EM respectively, and is used to control the connection and disconnection of the first power supply terminal VGH and the subsequent output terminal EM in response to the potential of the subsequent pull-down node QB_em.

[0101] For example, the rear-stage pull-down circuit 03 can control the first power supply terminal VGH and the rear-stage output terminal EM to be connected when the potential of the rear-stage pull-down node QB_em is a first potential, so that the first power supply terminal VGH transmits a first power supply signal to the rear-stage output terminal EM; and can control the first power supply terminal VGH to be disconnected from the rear-stage output terminal EM when the potential of the rear-stage pull-down node QB_em is a second potential.

[0102] The subsequent-stage output circuit 04 is connected to the subsequent-stage pull-up node Q_em, the second power supply terminal VGL, and the subsequent-stage output terminal EM, respectively. Responsive to the potential of the subsequent-stage pull-up node Q_em, the subsequent-stage output circuit 04 controls the connection between the second power supply terminal VGL and the subsequent-stage output terminal EM, thereby outputting a light-emission control signal through the subsequent-stage output terminal EM. Thus, the subsequent-stage driver circuit 00 also serves as the shift register unit included in the light-emission control circuit.

[0103] For example, the subsequent-stage output circuit 04 can control the second power supply terminal VGL to be conductively connected to the subsequent-stage output terminal EM when the potential of the subsequent-stage pull-up node Q_em is at a first potential, so that the second power supply terminal VGL transmits a second power signal to the subsequent-stage output terminal EM; and can control the second power supply terminal VGL to be disconnected from the subsequent-stage output terminal EM when the potential of the subsequent-stage pull-up node Q_em is at a second potential. The potential of the second power signal can be a low potential.

[0104] 1 , the pre-stage decoding circuit 10 and at least two post-stage driving circuits 00 can be connected to the same control node P. The pre-stage decoding circuit 10 can control the potential of the control node P based on a strobe signal and a clock signal. The at least two post-stage driving circuits 00 can each output a light emission control signal through a post-stage output terminal EM based on the potential of the control node P.

[0105] It will be understood that, referring to FIG. 1 , at least two subsequent driver circuits 00 can be connected to at least two output terminals EM1 ... EMn in a one-to-one correspondence, and these at least two output terminals EM1 ... EMn can be connected to multiple rows of pixels in a one-to-one correspondence. Furthermore, each subsequent driver circuit 00 can be connected to a different control clock terminal CLKE and a different output clock terminal CLKP, so that light emission control signals are output row by row to the multiple rows of pixels. Here, n can be an integer greater than 1. For example, n can be 2, 4, or other values.

[0106] In summary, an embodiment of the present disclosure provides a shift register unit. The shift register unit includes: a front-stage decoding circuit and at least two rear-stage driving circuits. The front-stage decoding circuit is capable of controlling the potential of a control node based on a gating signal provided by at least one gating terminal and a clock signal provided by a clock terminal. In each rear-stage driving circuit, the input circuit and the rear-stage pull-down control circuit are capable of controlling the potential of the rear-stage pull-up node and the potential of the rear-stage pull-down node respectively based on the potential of the control node, so that the rear-stage pull-down circuit outputs a first power signal to the rear-stage output terminal based on the potential of the rear-stage pull-down node, and the rear-stage output circuit outputs a second power signal to the rear-stage output terminal based on the potential of the rear-stage pull-up node. In this way, partition gating can be achieved by flexibly setting the gating signal, so that each rear-stage driving circuit in different shift register units flexibly outputs a light-emitting control signal to multiple rows of pixels to drive multiple rows of pixels to emit light. That is, the shift register unit provided by the embodiment of the present disclosure can flexibly refresh pixels according to the partitioning of the display screen.

[0107] Alternatively, FIG3 is a schematic structural diagram of another shift register unit provided by an embodiment of the present disclosure. As shown in FIG3 , the subsequent pull-down control circuit 02 may include: a first pull-down control sub-circuit 021 and a second pull-down control sub-circuit 022 .

[0108] Among them, the first pull-down control sub-circuit 021 can be connected to the control node P, the control clock terminal CLKE and the subsequent pull-down node QB_em respectively, and can be used to control the connection and disconnection of the control clock terminal CLKE and the subsequent pull-down node QB_em in response to the potential of the control node P.

[0109] For example, the first pull-down control sub-circuit 021 can control the control clock terminal CLKE to be connected to the subsequent pull-down node QB_em when the potential of the control node P is a first potential; and can control the control clock terminal CLKE to be disconnected from the subsequent pull-down node QB_em when the potential of the control node P is a second potential.

[0110] The second pull-down control sub-circuit 022 can be connected to the subsequent pull-up node Q_em, the first power supply terminal VGH and the subsequent pull-down node QB_em respectively, and can be used to control the connection and disconnection of the first power supply terminal VGH and the subsequent pull-down node QB_em in response to the potential of the subsequent pull-up node Q_em.

[0111] For example, the second pull-down control sub-circuit 022 can control the first power supply terminal VGH and the subsequent pull-down node QB_em to be connected when the potential of the subsequent pull-up node Q_em is a first potential; and can control the first power supply terminal VGH to be disconnected from the subsequent pull-down node QB_em when the potential of the subsequent pull-up node Q_em is a second potential.

[0112] Optionally, based on FIG3 , FIG4 shows a structural diagram of another shift register unit provided by an embodiment of the present disclosure. Referring to FIG4 , it can be seen that the subsequent stage driving circuit 00 may further include: a first holding circuit 05 .

[0113] The first holding circuit 05 can be connected between the first pull-down control sub-circuit 021 and the subsequent pull-down node QB_em, and can also be connected to the control clock terminal CLKE, and is used to control the on and off of the first pull-down control sub-circuit 021 and the subsequent pull-down node QB_em in response to the control clock signal.

[0114] For example, the first holding circuit 05 can control the first pull-down control sub-circuit 021 to be connected to the subsequent pull-down node QB_em when the potential of the control clock signal is the first potential; and can control the first pull-down control sub-circuit 021 to be disconnected from the subsequent pull-down node QB_em when the potential of the control clock signal is the second potential.

[0115] That is, the first pull-down control sub-circuit 021 can be indirectly connected to the subsequent pull-down node QB_em via the first holding circuit 05. Thus, when the potential of the control clock signal is the second potential (e.g., a high potential), the first holding circuit 05 can reliably control the first pull-down control sub-circuit 021 to be disconnected from the subsequent pull-down node QB_em, thereby preventing the control clock signal from leaking to the subsequent pull-down node QB_em via the first pull-down control sub-circuit 021. In other words, the potential of the subsequent pull-down node QB_em can be well maintained.

[0116] Optionally, it can be seen from FIG. 4 that the subsequent driving circuit 00 may further include a second holding circuit 06 .

[0117] The second holding circuit 06 can be connected to the first power supply terminal VGH and the subsequent pull-down node QB_em, respectively, and can be used to maintain the potential of the subsequent pull-down node QB_em based on the first power supply signal provided by the first power supply terminal VGH. In this way, the potential of the subsequent pull-down node QB_em can be further better maintained.

[0118] Optionally, it can be seen from FIG. 3 and FIG. 4 that the subsequent driving circuit 00 may further include: a subsequent isolation circuit 07 .

[0119] The subsequent isolation circuit 07 can be connected between the subsequent pull-up node Q_em and the subsequent output circuit 04, and can also be connected to the second power supply terminal VGL, and can be used to control the subsequent pull-up node Q_em and the subsequent output circuit 04 to be conductive in response to the second power supply signal.

[0120] It is understandable that by providing the post-stage isolation circuit 07 , it is possible to prevent the post-stage output circuit 04 from malfunctioning due to leakage of the pull-up node Q_em, thereby ensuring better operating reliability of the post-stage output circuit 04 .

[0121] Alternatively, based on Figure 3, Figure 5 shows a schematic circuit structure diagram of a shift register unit. Based on Figure 4, Figure 6 shows a schematic circuit structure diagram of another shift register unit. Referring to Figures 5 and 6, it can be seen that the first pull-down control sub-circuit 021 can include: a first transistor T1.

[0122] A gate of the first transistor T1 may be connected to the control node P, a first electrode of the first transistor T1 may be connected to the control clock terminal CLKE, and a second electrode of the first transistor T1 may be connected to the subsequent pull-down node QB_em.

[0123] Optionally, with continued reference to FIG. 5 and FIG. 6 , it can be seen that the second pull-down control sub-circuit 022 may include: a second transistor T2 .

[0124] A gate of the second transistor T2 may be connected to the subsequent pull-up node Q_em, a first electrode of the second transistor T2 may be connected to the first power supply terminal VGH, and a second electrode of the second transistor T2 may be connected to the subsequent pull-down node QB_em.

[0125] Optionally, with continued reference to FIG. 6 , it can be seen that the first holding circuit 05 may include: a third transistor T3 .

[0126] The gate of the third transistor T3 can be connected to the control clock terminal CLKE, the first electrode of the third transistor T3 can be connected to the first pull-down control sub-circuit 021, and the second electrode of the third transistor T3 can be connected to the subsequent pull-down node QB_em. It is understood that the first electrode of the third transistor T3 can be connected to the second electrode of the first transistor T1 included in the first pull-down control sub-circuit 021.

[0127] Optionally, with continued reference to FIG. 6 , it can be seen that the second holding circuit 06 may include: a first capacitor C1 .

[0128] One end of the first capacitor C1 may be connected to the first power supply terminal VGH, and the other end of the first capacitor C1 may be connected to the subsequent pull-down node QB_em. That is, the first capacitor C1 may be connected in series between the first power supply terminal VGH and the subsequent pull-down node QB_em.

[0129] Optionally, with continued reference to FIG. 5 and FIG. 6 , it can be seen that the post-stage isolation circuit 07 may include: a fourth transistor T4 .

[0130] A gate of the fourth transistor T4 may be connected to the second power supply terminal VGL, a first electrode of the fourth transistor T4 may be connected to the subsequent pull-up node Q_em, and a second electrode of the fourth transistor T4 may be connected to the subsequent output circuit O4.

[0131] Optionally, with continued reference to FIG. 5 and FIG. 6 , it can be seen that the subsequent pull-down circuit 03 may include: a fifth transistor T5 .

[0132] A gate of the fifth transistor T5 may be connected to the subsequent pull-down node QB_em, a first electrode of the fifth transistor T5 may be connected to the first power supply terminal VGH, and a second electrode of the fifth transistor T5 may be connected to the subsequent output terminal EM.

[0133] Optionally, based on Figure 6, Figure 7 shows a schematic diagram of a circuit structure of another shift register unit. As shown in Figure 7, the fifth transistor T5 may include: a first sub-transistor T51 and a second sub-transistor T52 connected in series.

[0134] The gates of the first sub-transistor T51 and the second sub-transistor T52 can both be connected to the subsequent-stage pull-down node QB_em. The first electrode of the first sub-transistor T51 can be connected to the first power supply terminal VGH. The second electrode of the first sub-transistor T51 can be connected to the first electrode of the second sub-transistor T52. The second electrode of the second sub-transistor T52 can be connected to the subsequent-stage output terminal EM. Furthermore, the subsequent-stage driving circuit 00 can further include a leakage prevention circuit 08.

[0135] The leakage protection circuit 08 can be connected to the subsequent output terminal EM, the second power supply terminal VGL and the series node S of the first sub-transistor T51 and the second sub-transistor T52 respectively, and can be used to control the connection and disconnection of the second power supply terminal VGL and the series node S in response to the potential of the subsequent output terminal EM.

[0136] For example, the anti-leakage circuit 08 can control the second power supply terminal VGL and the series node S to be connected when the potential of the subsequent output terminal EM is the first potential, so that the second power supply terminal VGL transmits the second power supply signal to the series node S; and can control the second power supply terminal VGL to be disconnected from the series node S when the potential of the subsequent output terminal EM is the second potential.

[0137] It is understood that when the potential of the subsequent-stage pull-down node QB_em is at a first potential (e.g., a low potential), the subsequent-stage pull-down circuit 03 can control the first power supply terminal VGH to be conductive with the subsequent-stage output terminal EM, so that the first power supply terminal VGH transmits a high-potential first power supply signal to the subsequent-stage output terminal EM. Furthermore, the leakage prevention circuit 08 can control the second power supply terminal VGL to be disconnected from the series node S. When the potential of the subsequent-stage pull-up node Q_em is at a first potential (e.g., a low potential), the subsequent-stage output circuit 04 can control the second power supply terminal VGL to be conductive with the subsequent-stage output terminal EM, so that the second power supply terminal VGL transmits a low-potential first power supply signal to the subsequent-stage output terminal EM. Furthermore, the leakage prevention circuit 08 can control the second power supply terminal VGL to be conductive with the series node S. In this way, leakage current in the subsequent-stage pull-down circuit 03 can be reduced.

[0138] Optionally, based on Figure 7, Figure 8 shows a circuit structure diagram of another shift register unit. As shown in Figure 8, the leakage protection circuit 08 may include: a sixth transistor T6.

[0139] A gate of the sixth transistor T6 may be connected to the subsequent-stage output terminal EM, a first electrode of the sixth transistor T6 may be connected to the second power supply terminal VGL, and a second electrode of the sixth transistor T6 may be connected to the series node S.

[0140] Optionally, with continued reference to FIG. 5 to FIG. 8 , it can be seen that the input circuit 01 may include: a seventh transistor T7 , an eighth transistor T8 , and a ninth transistor T9 .

[0141] The gate electrode and the first electrode of the seventh transistor T7 may both be connected to the input clock terminal CLKP, and the second electrode of the seventh transistor T7 may be connected to the subsequent pull-up node Q_em.

[0142] A gate of the eighth transistor T8 may be connected to the control node P, a first electrode of the eighth transistor T8 may be connected to a second electrode of the ninth transistor T9 , and a second electrode of the eighth transistor T8 may be connected to a subsequent-stage pull-up node Q_em.

[0143] A gate of the ninth transistor T9 may be connected to the control clock terminal CLKE, and a first electrode of the ninth transistor T9 may be connected to the input clock terminal CLKP.

[0144] Optionally, it can be seen from FIG. 5 to FIG. 8 that the subsequent output circuit 04 may include: a tenth transistor T10 and a second capacitor C2 .

[0145] A gate of the tenth transistor T10 may be connected to the subsequent pull-up node Q_em, a first electrode of the tenth transistor T10 may be connected to the second power supply terminal VGL, and a second electrode of the tenth transistor T10 may be connected to the subsequent output terminal EM.

[0146] One end of the second capacitor C2 can be connected to the subsequent pull-up node Q_em, and the other end of the second capacitor C2 can be connected to the subsequent output terminal EM. That is, the second capacitor C2 can be connected in series between the subsequent pull-up node Q_em and the subsequent output terminal EM.

[0147] Optionally, FIG9 is a schematic diagram of the structure of a pre-stage decoding circuit provided in an embodiment of the present disclosure. As shown in FIG9 , the pre-charge circuit 11 may also be connected to the second power supply terminal VGL and may be used to store the potential of the control node based on the second power supply signal. Furthermore, the pre-stage decoding circuit 10 may further include: a charging circuit 12, a reset circuit 13, at least two pre-stage output circuits 14, a pre-stage pull-down control circuit 15, and a pre-stage pull-down circuit 16.

[0148] Among them, the charging circuit 12 can be connected to the control node P, the second clock terminal CLK2, the third clock terminal CLK3, the second power supply terminal VGL and the previous stage pull-up node Q respectively, and can be used to control the connection and disconnection of the second power supply terminal VGL and the previous stage pull-up node Q in response to the potential of the control node P and the third clock signal provided by the third clock terminal CLK3, and can control the connection and disconnection of the third clock terminal CLK3 and the previous stage pull-up node Q in response to the second clock signal.

[0149] For example, the charging circuit 12 can control the second power supply terminal VGL to be conductive with the previous-stage pull-up node Q when the potential of the control node P is at a first potential and the potential of the third clock signal is at a first potential, so that the second power supply terminal VGL transmits the second power supply signal to the previous-stage pull-up node Q. Furthermore, when the potential of the control node P is at a second potential and / or the potential of the third clock signal is at a second potential, the charging circuit 12 can control the second power supply terminal VGL to be disconnected from the previous-stage pull-up node Q. Similarly, when the potential of the second clock signal is at a first potential, the charging circuit 12 can control the third clock terminal CLK3 to be conductive with the previous-stage pull-up node Q, so that the third clock terminal CLK3 transmits the third clock signal to the previous-stage pull-up node Q. Furthermore, when the potential of the second clock signal is at a second potential, the charging circuit 12 can control the third clock terminal CLK3 to be disconnected from the previous-stage pull-up node Q.

[0150] The reset circuit 13 can be connected to the reset terminal TRS, the first power supply terminal VGH, the control node P and the previous stage pull-up node Q respectively, and can be used to control the connection and disconnection of the first power supply terminal VGH and the control node P in response to the reset signal provided by the reset terminal TRS, and control the connection and disconnection of the first power supply terminal VGH and the previous stage pull-up node Q.

[0151] For example, the reset circuit 13 can control the first power supply terminal VGH to be connected to the control node P when the potential of the reset signal is a first potential, and control the first power supply terminal VGH to be connected to the previous-stage pull-up node Q, so that the first power supply terminal VGH transmits the first power supply signal to the control node P and the previous-stage pull-up node Q; and can control the first power supply terminal VGH to be disconnected from the control node P and control the first power supply terminal VGH to be disconnected from the previous-stage pull-up node Q when the potential of the reset signal is a second potential.

[0152] At least two front-stage output circuits 14 can be respectively connected to the front-stage pull-up node Q, at least two corresponding output clock terminals CLKS1...CLKSn and at least two corresponding front-stage output terminals Scout1...Scoutn. Each front-stage output circuit 14 can be used to control the connection and disconnection of a corresponding output clock terminal and a front-stage output terminal in response to the potential of the front-stage pull-up node Q.

[0153] For example, each front-stage output circuit 14 can control a corresponding output clock terminal to be connected to a front-stage output terminal when the potential of the front-stage pull-up node Q is a first potential, so that the output clock terminal transmits an output clock signal to the front-stage output terminal; and can control a corresponding output clock terminal to be disconnected from a front-stage output terminal when the potential of the front-stage pull-up node Q is a second potential. The front-stage output terminal can be connected to a pixel in the display panel through a gate line and is used to output a gate drive signal to the pixel.

[0154] The front-stage pull-down control circuit 15 can be connected to the control node P, the second clock terminal CLK2, the third clock terminal CLK3, the first power supply terminal VGH, the second power supply terminal VGL, the front-stage pull-up node Q and the front-stage pull-down node QB, respectively, and can be used to control the on-off of the second clock terminal CLK2 and the front-stage pull-down node QB in response to the potential of the control node P and the third clock signal, control the on-off of the second power supply terminal VGL and the front-stage pull-down node QB in response to the second clock signal, control the on-off of the second clock terminal CLK2 and the front-stage pull-down node QB in response to the potential of the front-stage pull-up node, and can store the potential of the front-stage pull-down node QB based on the first power supply signal.

[0155] For example, the front-stage pull-down control circuit 15 can control the second clock terminal CLK2 to be conductive with the front-stage pull-down node QB when the potential of the control node P is a first potential and the potential of the third clock signal is a first potential, so that the second clock terminal CLK2 transmits the second clock signal to the front-stage pull-down node QB; and can control the second clock terminal CLK2 to be disconnected from the front-stage pull-down node QB when the potential of the control node P and / or the potential of the third clock signal is a second potential. Similarly, the pull-down control circuit 15 can control the second power supply terminal VGL to be conductive with the front-stage pull-down node QB when the potential of the second clock signal is a first potential, so that the second power supply terminal VGL transmits the second power supply signal to the front-stage pull-down node QB; and can control the second power supply terminal VGL to be disconnected from the front-stage pull-down node QB when the potential of the second clock signal is a second potential. Similarly, the pull-down control circuit 15 can control the second clock terminal CLK2 to be connected to the previous pull-down node QB when the potential of the previous pull-up node Q is the first potential, so that the second clock terminal CLK2 transmits the second clock signal to the previous pull-down node QB; and can control the second clock terminal CLK2 to be disconnected from the previous pull-down node QB when the potential of the previous pull-up node Q is the second potential.

[0156] Optionally, in some embodiments, the second power supply terminal VGL connected to the front-stage pull-down control circuit 15 may also be shared with the second clock terminal CLK2 , thereby simplifying wiring.

[0157] The front-stage pull-down circuit 16 can be connected to the front-stage pull-down node QB, the first power supply terminal VGH, the front-stage pull-up node Q, and at least two front-stage output terminals Scout1 ... Scoutn, respectively. In response to the potential of the front-stage pull-down node QB, the front-stage pull-up node Q can be controlled to be connected and disconnected, and the first power supply terminal VGH can be controlled to be connected and disconnected with each front-stage output terminal, so as to output a gate drive signal through the front-stage output terminal. Thus, the front-stage decoding circuit 10 can refer to a shift register unit included in the gate drive circuit.

[0158] For example, the front-stage pull-down circuit 16 can control the first power supply terminal VGH to be connected to the front-stage pull-up node Q when the potential of the front-stage pull-down node QB is a first potential, and control the first power supply terminal VGH to be connected to each front-stage output terminal, so that the first power supply terminal VGH transmits a first power supply signal to the front-stage pull-up node Q and each front-stage output terminal; and can control the first power supply terminal VGH to be disconnected from the front-stage pull-up node Q when the potential of the front-stage pull-down node QB is a second potential, and control the first power supply terminal VGH to be disconnected from each front-stage output terminal.

[0159] Optionally, it can be seen from FIG. 9 that the pre-stage decoding circuit 10 may further include: a first pre-stage isolation circuit 17 and a second pre-stage isolation circuit 18 .

[0160] The first front-stage isolation circuit 17 can be connected between the control node P and the front-stage pull-down control circuit 15, and can also be connected to the second power supply terminal VGL, and can be used to control the control node P and the front-stage pull-down control circuit 15 to be conductive in response to the second power supply signal.

[0161] It is understandable that by providing the first front-stage isolation circuit 17 , malfunction of the front-stage pull-down control circuit 15 caused by leakage of the control node P can be prevented, thereby ensuring better operating reliability of the front-stage pull-down control circuit 15 .

[0162] The second front-stage isolation circuit 18 can be connected between the front-stage pull-up node Q and at least two front-stage output circuits 14, and can also be connected to the second power supply terminal VGL, and can be used to control the front-stage pull-up node Q and at least two front-stage output circuits 14 to be conductive in response to the second power supply signal.

[0163] Similar to the first pre-stage isolation circuit 17, the provision of the second pre-stage isolation circuit 18 can prevent malfunction of the pre-stage output circuit 14 due to leakage at the pre-stage pull-up node Q, thereby ensuring the high reliability of the pre-stage output circuit 14. Furthermore, the provision of the second pre-stage isolation circuit 18 can prevent changes in the potential at the node connecting the second isolation circuit 08 and the output circuit 04 from affecting the potential of the pull-up node Q, thereby ensuring the high stability of the potential of the pull-up node Q.

[0164] Alternatively, based on Figure 9 , Figure 10 shows another schematic diagram of the structure of a pre-decoding circuit. As shown in Figure 10 , the pre-charging circuit 11 may include: a gating sub-circuit 111 , an auxiliary control sub-circuit 112 , and a pre-charging sub-circuit 113 .

[0165] The gating sub-circuit 111 can be connected to at least two gating terminals D0 ... Dm, the second clock terminal CLK2, and the intermediate node N, and can be used to control the connection and disconnection between the second clock terminal CLK2 and the intermediate node N in response to a gating signal provided by each gating terminal. The gating sub-circuit 111 can also be called a decoding circuit.

[0166] For example, the gating sub-circuit 111 can control the second clock terminal CLK2 to be connected to the intermediate node N when the potential of the gating signal provided by any gating terminal is the first potential, so that the second clock terminal CLK2 transmits the second clock signal to the intermediate node N; and can control the second clock terminal CLK2 to be disconnected from the intermediate node N when the potential of the gating signal provided by each gating terminal is the second potential.

[0167] The auxiliary control circuit 112 may be connected to the first clock terminal CLK1 , the second clock terminal CLK2 and the intermediate node N respectively, and may be configured to control the connection and disconnection between the second clock terminal CLK2 and the intermediate node N in response to the first clock signal.

[0168] For example, the auxiliary control circuit 112 can control the second clock terminal CLK2 to be connected to the intermediate node N when the potential of the first clock signal is the first potential, so that the second clock terminal CLK2 transmits the second clock signal to the intermediate node N; and can control the second clock terminal CLK2 to be disconnected from the intermediate node N when the potential of the first clock signal is the second potential.

[0169] The pre-charge sub-circuit 113 can be connected to the intermediate node N, the first clock terminal CLK1, the second power supply terminal VGL and the control node P respectively, and can be used to control the connection and disconnection of the first clock terminal CLK1 and the control node P in response to the potential of the intermediate node N and the first clock signal, and store the potential of the control node P based on the second power supply signal.

[0170] For example, the pre-charging sub-circuit 113 can control the first clock terminal CLK1 to be connected to the control node P when the potential of the intermediate node N is the first potential and / or the potential of the first clock signal is the first potential, so that the first clock terminal CLK1 transmits the first clock signal to the control node P; and can control the first clock terminal CLK1 to be disconnected from the control node P when the potential of the intermediate node N is the second potential and the potential of the first clock signal is the second potential.

[0171] Optionally, it can be seen from FIG. 10 that the second front-stage isolation circuit 18 may include at least two isolation sub-circuits 181 .

[0172] The at least two isolation sub-circuits 181 may be connected to at least two front-stage output circuits 14 in a one-to-one correspondence, and may also be connected to the second power supply terminal VGL and the front-stage pull-up node Q. Each isolation sub-circuit 181 may be configured to control the connection between the front-stage pull-up node Q and a corresponding front-stage output circuit 04 in response to the first power supply signal.

[0173] That is, in the embodiment of the present disclosure, for each pre-stage output circuit 14, an isolation sub-circuit 181 can be provided to isolate the pre-stage pull-up node Q from the pre-stage output circuit 04, thereby ensuring that each pre-stage output circuit 14 can work reliably.

[0174] Alternatively, referring to FIG9 and FIG10 , it can be seen that the shift register units shown therein each include: four pre-stage output circuits 14, i.e., n is 4. Accordingly, the four pre-stage output circuits 14 can be connected to four output clock terminals CLKS1, CLKS2, CLKS3, and CLKS4 in a one-to-one correspondence, and can be connected to four output terminals Scout(i), Scout(i+1), Scout(i+2), and Scout(i+3) in a one-to-one correspondence. i is an integer greater than 0 and less than or equal to n. For example, if i is 1, the four output terminals are Scout(1) to Scout(4), respectively.

[0175] Furthermore, the second front-stage isolation circuit 18 may include four isolation sub-circuits 181, as shown in FIG10 . The nodes connecting the four isolation sub-circuits 181 to the four front-stage output circuits 14 are labeled Q1, Q2, Q3, and Q4, respectively, also referred to as output nodes. Based on this, it can be considered that each front-stage output circuit 14 controls the connection between the corresponding output clock terminal and the front-stage output terminal in response to the potential of the corresponding output node.

[0176] Alternatively, referring to FIG9 and FIG10 , it can be seen that in the shift register unit shown therein, the gating sub-circuit 011 is connected to eight gating terminals D0 , D1 , D2 , D3 , D4 , D5 , D6 and D7 , that is, m is 7.

[0177] Alternatively, based on Figure 10 , Figure 11 shows a schematic circuit diagram of a pre-decoding circuit according to an embodiment of the present disclosure. As shown in Figure 11 , the gating subcircuit 111 may include at least two gating transistors T11 ... T1m. The auxiliary control subcircuit 112 may include an auxiliary control transistor T20. The pre-charging subcircuit 113 may include a first pre-charging transistor T31, a second pre-charging transistor T32, and a first storage capacitor Cst1.

[0178] The gates of the at least two gate transistors T11 ... T1m can be connected to the at least two gate terminals D0 ... Dm in a one-to-one correspondence, the first electrodes of the at least two gate transistors T11 ... T1m can be connected to the second clock terminal CLK2, and the second electrodes of the at least two gate transistors T11 ... T1m can be connected to the intermediate node N. It can be understood that because the structure shown in Figure 10 includes eight gate terminals D0 to D7, the circuit structure shown in Figure 11 includes eight gate transistors T11 to T18. The gates of the eight gate transistors T11 to T18 are connected to the eight gate terminals D0 to D7 in a one-to-one correspondence.

[0179] A gate of the auxiliary control transistor T20 may be connected to the first clock terminal CLK1 , a first electrode of the auxiliary control transistor T20 may be connected to the second clock terminal CLK2 , and a second electrode of the auxiliary control transistor T20 may be connected to the intermediate node N.

[0180] A gate of the first pre-charging transistor T31 may be connected to the intermediate node N, a first electrode of the first pre-charging transistor T31 may be connected to the first clock terminal CLK1 , and a second electrode of the first pre-charging transistor T31 may be connected to the control node P.

[0181] The gate and the first electrode of the second pre-charging transistor T32 may both be connected to the first clock terminal CLK1 , and the second electrode of the second pre-charging transistor T32 may be connected to the control node P.

[0182] One end of the first storage capacitor Cst1 may be connected to the second power terminal VGL, and the other end of the first storage capacitor Cst1 may be connected to the control node P. That is, the first storage capacitor Cst1 may be connected in series between the second power terminal VGL and the control node P.

[0183] Optionally, referring to FIG. 11 , it can be seen that the front-stage pull-down control circuit 15 may include: a first pull-down control transistor T41 , a second pull-down control transistor T42 , a third pull-down control transistor T43 , a fourth pull-down control transistor T44 and a second storage capacitor Cst2 .

[0184] The gate of the first pull-down control transistor T41 can be connected to the control node P, the first electrode of the first pull-down control transistor T41 can be connected to the second electrode of the second pull-down control transistor T42, and the second electrode of the first pull-down control transistor T41 can be connected to the previous stage pull-down node QB.

[0185] A gate of the second pull-down control transistor T42 may be connected to the third clock terminal CLK3 , and a first electrode of the second pull-down control transistor T42 may be connected to the second clock terminal CLK2 .

[0186] A gate of the third pull-down control transistor T43 may be connected to the second clock terminal CLK2 , a first electrode of the third pull-down control transistor T43 may be connected to the second power supply terminal VGL, and a second electrode of the third pull-down control transistor T43 may be connected to the previous stage pull-down node QB.

[0187] The gate of the fourth pull-down control transistor T44 may be connected to the previous pull-up node Q, the first electrode of the fourth pull-down control transistor T44 may be connected to the second clock terminal CLK2, and the second electrode of the fourth pull-down control transistor T44 may be connected to the previous pull-down node QB.

[0188] One end of the second storage capacitor Cst2 may be connected to the first power terminal VGH, and the other end of the second storage capacitor Cst2 may be connected to the previous pull-down node QB. That is, the second storage capacitor Cst2 may be connected in series between the first power terminal VGH and the previous pull-down node QB.

[0189] Optionally, with continued reference to FIG. 11 , it can be seen that the front-stage pull-down circuit 16 may include: a first pull-down transistor T50 , and at least two second pull-down transistors T51 . . . T5n.

[0190] A gate of the first pull-down transistor T50 may be connected to the previous pull-down node QB, a first electrode of the first pull-down transistor T50 may be connected to the first power supply terminal VGH, and a second electrode of the first pull-down transistor T50 may be connected to the previous pull-up node Q.

[0191] The gates of at least two second pull-down transistors T51...T5n can be connected to the previous-stage pull-down node QB, the first electrodes of at least two second pull-down transistors T51...T5n can be connected to the first power supply terminal VGH, and the second electrodes of at least two second pull-down transistors T51...T5n can be connected one-to-one with at least two previous-stage output terminals Scout1...Scoutn. It can be understood that because the structure shown in Figure 10 includes four output circuits O4 corresponding to the four output terminals Scout(i) to Scout(i+3), the circuit structure shown in Figure 11 includes four second pull-down transistors T51, T52, T53, and T54. The second electrodes of the four second pull-down transistors T51 to T54 can be connected one-to-one with the four previous-stage output terminals Scout(i) to Scout(i+3).

[0192] Optionally, referring to FIG11 , it can be seen that the first front-stage isolation circuit 17 may include a first isolation transistor T60 , and each isolation sub-circuit 181 in the second front-stage isolation circuit 18 may include a second isolation transistor T6x.

[0193] The gate of the first isolation transistor T60 can be connected to the second power supply terminal VGL, the first electrode of the first isolation transistor T60 can be connected to the control node P, and the second electrode of the first isolation transistor T60 can be connected to the previous-stage pull-down control circuit 15. It is understood that the second electrode of the first isolation transistor T60 can be connected to the gate of the first pull-down control transistor T41 in the previous-stage pull-down control circuit 15. In other words, the gate of the first pull-down control transistor T41 can be indirectly connected to the control node P through the first isolation transistor T60.

[0194] The gate of the second isolation transistor T6x can be connected to the second power supply terminal VGL, the first electrode of the second isolation transistor T6x can be connected to the previous stage pull-up node Q, and the second electrode of the second isolation transistor T6x can be connected to a corresponding previous stage output circuit 14. It is understood that it can be connected to the output node here. For example, based on the structure including four isolation sub-circuits 181 shown in Figure 10, the circuit structure shown in Figure 11 includes four second isolation transistors T61, T62, T63 and T64. The four second isolation transistors T61 to T64 are connected to the four output nodes Q1 to Q4 of the four previous stage output circuits 04 in a one-to-one correspondence.

[0195] Optionally, with continued reference to FIG. 11 , it can be seen that the charging circuit 12 may include: a first charging transistor T71 , a second charging transistor T72 , and a third charging transistor T73 .

[0196] A gate of the first charging transistor T71 may be connected to the control node P, a first electrode of the first charging transistor T71 may be connected to the second power supply terminal VGL, and a second electrode of the first charging transistor T71 may be connected to a first electrode of the second charging transistor T72.

[0197] A gate electrode of the second charging transistor T72 may be connected to the third clock terminal CLK3 , and a second electrode of the second charging transistor T72 may be connected to the previous-stage pull-up node Q.

[0198] A gate of the third charging transistor T73 may be connected to the second clock terminal CLK2 , a first electrode of the third charging transistor T73 may be connected to the third clock terminal CLK3 , and a second electrode of the third charging transistor T73 may be connected to the previous-stage pull-up node Q.

[0199] Optionally, with continued reference to FIG. 11 , it can be seen that the reset circuit 13 may include: a first reset transistor T81 and a second reset transistor T82 .

[0200] Among them, the gate of the first reset transistor T81 and the gate of the second reset transistor T82 can both be connected to the reset terminal TRS, the first electrode of the first reset transistor T81 and the first electrode of the second reset transistor T82 can both be connected to the first power supply terminal VGH, the second electrode of the first reset transistor T81 can be connected to the control node P, and the second electrode of the second reset transistor T82 can be connected to the previous stage pull-up node Q.

[0201] Optionally, with continued reference to FIG. 11 , it can be seen that each pre-stage output circuit 14 may include: an output transistor T9 x and a third storage capacitor Cst3 x .

[0202] Among them, the gate of the output transistor T9x can be connected to the previous stage pull-up node Q, the first electrode of the output transistor T9x can be connected to the corresponding output clock terminal, and the second electrode of the output transistor T9x can be connected to the corresponding previous stage output terminal.

[0203] One end of the third storage capacitor Cst3 x may be connected to the previous-stage pull-up node Q, and the other end of the third storage capacitor Cst3 x may be connected to the corresponding previous-stage output terminal.

[0204] It is understood that, based on the inclusion of the second front-stage isolation circuit 18, the gate of the output transistor T9x can be indirectly connected to the front-stage pull-up node Q through the second isolation transistor T6x. Also, one end of the third storage capacitor Cst3x can be indirectly connected to the front-stage pull-up node Q through the second isolation transistor T6x. The connection node between the gate of the output transistor T9x and one end of the third storage capacitor Cst3x and the second isolation transistor T6x is called an output node. For example, based on the structure including four front-stage output circuits 14 shown in Figure 9, the circuit structure shown in Figure 10 includes four output transistors T91, T92, T93, and T94, and four third storage capacitors Cst31, Cst32, Cst33, and Cst34. The gates of the four output transistors T91 to T94 are connected in a one-to-one correspondence to the four output nodes Q1 to Q4, the first electrodes of the four output transistors T91 to T94 are connected in a one-to-one correspondence to the four output clock terminals CLKS1 to CLKS4, and the second electrodes of the four output transistors T91 to T94 are connected in a one-to-one correspondence to the four previous-stage output terminals Scout(i) to Scout(i+3). One end of the four third storage capacitors Cst31, Cst32, Cst33, and Cst34 are connected in a one-to-one correspondence to the four output nodes Q1 to Q4, and the other ends of the four third storage capacitors Cst31, Cst32, Cst33, and Cst34 are connected in a one-to-one correspondence to the four previous-stage output terminals Scout(i) to Scout(i+3).

[0205] Optionally, each transistor in the circuit structure shown in Figures 5 to 8, and Figure 11 is a P-type transistor. Accordingly, as described above, the first potential can be a low potential, and the second potential can be a high potential. Of course, in some other embodiments, each transistor can also be an N-type transistor. On this basis, as described above, the first potential can be a high potential, and the second potential can be a low potential; or, some transistors can be set as P-type transistors and other transistors can be set as N-type transistors.

[0206] Optionally, based on the front-stage decoding circuit 11 including four front-stage output circuits 14, referring to the structural diagram of another shift register unit shown in FIG12, it can be seen that the shift register unit may include four rear-stage driving circuits 00, labeled EM GOA1 to EM GOA4.

[0207] Furthermore, as previously described, the four subsequent-stage driver circuits 00 (i.e., EM GOA1 through EM GOA4) can be connected in a one-to-one correspondence to the four subsequent-stage output terminals (e.g., EM1 through EM4), to four different input clock terminals CLKP1 through CLKP4, and to four different control clock terminals CLKE10, CLKE11, CLKE12, and CLKE1. Furthermore, the four subsequent-stage driver circuits 00 can be connected to the same control node P as the same previous-stage decoding circuit 10 (denoted as decoder GOA). For example, FIG13 shows a circuit structure diagram of another shift register unit based on FIG12 and in combination with FIG6 and FIG11.

[0208] In summary, an embodiment of the present disclosure provides a shift register unit. The shift register unit includes: a front-stage decoding circuit and at least two rear-stage driving circuits. The front-stage decoding circuit is capable of controlling the potential of a control node based on a gating signal provided by at least one gating terminal and a clock signal provided by a clock terminal. In each rear-stage driving circuit, the input circuit and the rear-stage pull-down control circuit are capable of controlling the potential of the rear-stage pull-up node and the potential of the rear-stage pull-down node respectively based on the potential of the control node, so that the rear-stage pull-down circuit outputs a first power signal to the rear-stage output terminal based on the potential of the rear-stage pull-down node, and the rear-stage output circuit outputs a second power signal to the rear-stage output terminal based on the potential of the rear-stage pull-up node. In this way, partition gating can be achieved by flexibly setting the gating signal, so that each rear-stage driving circuit in different shift register units flexibly outputs a light-emitting control signal to multiple rows of pixels to drive multiple rows of pixels to emit light. That is, the shift register unit provided by the embodiment of the present disclosure can flexibly refresh pixels according to the partitioning of the display screen.

[0209] FIG14 is a flow chart of a method for driving a shift register unit according to an embodiment of the present disclosure, wherein the method is used to drive a shift register unit as shown in any one of FIG1 to FIG13. As shown in FIG14, the method includes:

[0210] Step 1401, in the first stage, in the pre-decoding circuit, the precharge circuit controls the first clock terminal to be connected to the control node in response to the selection signal provided by each of the at least two selection terminals, the first clock signal provided by the first clock terminal, and the second clock signal provided by the second clock terminal.

[0211] Step 1402, the second stage, in each post-stage driving circuit, the post-stage input circuit controls the input clock terminal to be connected with the post-stage pull-up node in response to the potential of the control node, the control clock signal provided by the control clock terminal, and the input clock signal provided by the input clock terminal, the post-stage pull-down control circuit controls the control clock terminal to be connected with the post-stage pull-down node in response to the potential of the control node, and the post-stage pull-down circuit controls the first power supply terminal to be connected with the post-stage output terminal in response to the potential of the post-stage pull-down node.

[0212] Step 1403, the third stage, in each post-stage driving circuit, the post-stage input circuit controls the input clock terminal and the post-stage pull-up node to be connected in response to the input clock signal, the post-stage pull-down control circuit controls the control clock terminal and the post-stage pull-down node to be connected in response to the potential of the control node, and controls the first power supply terminal and the post-stage pull-down node to be connected in response to the potential of the post-stage pull-up node, and the post-stage output circuit controls the second power supply terminal and the post-stage output terminal to be connected in response to the potential of the post-stage pull-up node.

[0213] It is understandable that since the driving method has substantially the same technical effects as those of the aforementioned shift register unit embodiment, the technical effects of the driving method will not be described repeatedly for the purpose of brevity.

[0214] FIG15 is a schematic diagram of a light emitting control circuit according to an embodiment of the present disclosure. As shown in FIG15 , the light emitting control circuit includes: multiple groups of shift register units GOA0, each group of shift register units GOA0 includes: at least two shift register units GOA shown in FIG1 to FIG13.

[0215] Among them, each group of shift register units GOA shares the first clock terminal CLK1, the second clock terminal CLK2, the control clock terminal CLKE, the input clock terminal CLKP and the selection terminals D0...Dm, and each group of shift register units GOA can be configured to receive different selection signals provided by at least two selection terminals.

[0216] In addition, based on FIG. 10 and in combination with FIG. 15 , it can be seen that each group of shift register units GOA also shares a first clock terminal CLK1 , a second clock terminal CLK2 , a third clock terminal CLK3 , and output clock terminals CLKS1 . . . CLKSn.

[0217] For example, in the light-emitting control circuit shown in FIG15 , each group of shift register units GOA0 includes three shift register units GOA. Furthermore, each shift register unit GOA may include a pre-stage decoding circuit 10 (i.e., Gate GOA) and at least two post-stage driving circuits 00 (i.e., EM GOA). Each pre-stage decoding circuit Gate GOA is connected to four pre-stage output terminals Scout(i) to Scout(i+3). For example, the first pre-stage decoding circuit Gate GOA1 is connected to four pre-stage output terminals Scout(1) to Scout(4); the second pre-stage decoding circuit Gate GOA2 is connected to four pre-stage output terminals Scout(5) to Scout(8); and so on. Accordingly, each shift register unit GOA may include four post-stage driving circuits connected to the four post-stage output terminals EM(i) to EM(i+3) in a one-to-one correspondence. For example, the four post-stage driving circuits EM GOA1 to EM GOA4 are connected to EM1 to EM4 in a one-to-one correspondence.

[0218] Furthermore, referring to FIG15 , the first clock terminal CLK1, the second clock terminal CLK2, and the third clock terminal CLK3 can be connected to three clock signal lines, which are also labeled CLK1 to CLK3. The four output clock terminals CLKS1 to CLKS4 corresponding to the four front-stage output terminals Scout(i) to Scout(i+3) can be connected to the twelve clock signal lines CLKE1 to CLKE12. The four input clock terminals CLKP1 to CLKP4 corresponding to the four rear-stage driver circuits can be connected to the six clock signal lines CLKP1 to CLKP6. Furthermore, the four control clock terminals CLKE corresponding to the four rear-stage driver circuits can be shared with four clock signal lines (e.g., CLKE10, CLKE11, CLKE12, and CLKE1) of the twelve clock signal lines CLKE1 to CLKE12. In this way, wiring can be simplified.

[0219] In addition, referring to FIG15 , each group of shift register units GOA0 shown therein is connected to eight strobe terminals D0 to D7. The difference is that the first group of shift register units GOA0 receives strobe signals provided by the eight strobe terminals D0 to D7; the second group of shift register units GOA0 receives strobe signals provided by the eight strobe terminals D0′ and D1 to D7. The strobe signal provided by D0′ is the inverse of the strobe signal provided by D0. For example, if the strobe signal provided by D0 is 1, indicating a high potential, the strobe signal provided by D0′ is 0, indicating a low potential.

[0220] For example, FIG13 is combined with the structure shown in FIG15 as an example, FIG16 shows a timing diagram of the operation of a shift register unit. In addition, FIG16 shows a timing diagram corresponding to the shift register unit connecting the pixels in rows 1 to 4. Referring to FIG16 , it can be seen that the operation of the shift register unit can be divided into 6 stages t01 to t06. It can be understood that in FIG16 , the four front-stage output terminals are respectively identified as Scout (1) to Scout (4); and the four rear-stage output terminals are respectively identified as EM (1) to EM (4).

[0221] Before stage t01, the reset terminal TRS can first provide a low-level reset signal, so that the first reset transistor T81 and the second reset transistor T82 are both turned on, thereby causing the second power supply terminal VGH to transmit a high-level second power supply signal to both the control node P and the previous stage pull-up node Q.

[0222] At stage t01, the clock signal line CLK1 connected to the first clock terminal CLK1 can provide a low-potential first clock signal, turning on both the auxiliary control transistor T20 and the second pre-charge transistor T32. This allows the first clock terminal CLK1 to transmit the low-potential first clock signal to the control node P, and allows the second clock terminal CLK2 to transmit the high-potential second clock signal to the intermediate node N. That is, at stage t01, the potential of the control node P can be set low. Accordingly, stage t01 is also referred to as the point P setting stage. Furthermore, referring to FIG16 , it can be seen that at stage t01, the eight selection terminals D0 to D7 all provide low-potential selection signals, meaning that the potentials of the selection signals are all set low, and the selection stage has not yet begun.

[0223] In phase t02, first, since each shift register unit is connected to eight select terminals D0 to D7, it can be seen that the select signals provided by the eight select terminals D0 to D7 can correspond to 256 states. Moreover, in phase t02, for the first 16 output terminals Scout (1) to Scout (16) connected to the first group of shift register units, the potentials of the select signals provided by the eight select terminals D0 to D7 are all high potentials. Accordingly, the eight select transistors T11 to T18 in the first group of shift register units can be turned off, and the potential of the intermediate node N can maintain the high potential of the previous stage. For the 16 output terminals Scout (17) to Scout (32) connected to the second group of shift register units, the potential of the select signal provided by the select terminal D0 among the eight select terminals D0 to D7 can be low potential, and the potentials of the select signals provided by the remaining select terminals can be high potentials. Accordingly, at least the selection transistor T11 in the second group of shift register units can be turned on, thereby enabling the second clock terminal CLK2 to transmit the second clock signal to the intermediate node N. In addition, at stage t02, because the clock signal line CLK2 connected to the second clock terminal CLK2 can provide a low-potential second clock signal, the potential of the intermediate node N can be lowered through the turned-on selection transistor T11.

[0224] At stage t03, the clock signal line CLKP1 connected to the input clock terminal CLKP1 can provide a high-level input clock signal, and the clock signal line CLKE10 connected to the control clock terminal CLKE10 can provide a low-level control clock signal, turning on both the third transistor T3 and the ninth transistor T9. Furthermore, because the potential of the control node P can be maintained at the low potential from the previous stage by the first storage capacitor Cst1, both the first transistor T1 and the eighth transistor T8 can be turned on. This allows the input clock terminal CLKP1 to transmit a high-level input clock signal to the subsequent-stage pull-up node Q_em, and the control clock terminal CLKE10 to transmit a low-level control clock signal to the subsequent-stage pull-down node QB_em. In other words, at stage t03, the potential of the subsequent-stage pull-up node Q_em can be increased, while the potential of the subsequent-stage pull-down node QB_em can be decreased. Furthermore, the fifth transistor T5 can be turned on, causing the first power supply terminal VGH to transmit a high-level first power supply signal to the subsequent-stage output terminal EM. That is, at stage t03, the voltage level of the subsequent output terminal EM can be increased, which may refer to the first subsequent output terminal EM (1).

[0225] At stage t04, the clock signal line CLK3 connected to the third clock terminal CLK3 can first provide a low-level third clock signal, turning on the second charging transistor T72. Furthermore, because the potential of the control node P can be maintained at the low level of the previous stage by the first storage capacitor Cst1, the first charging transistor T71 can also be turned on, thereby enabling the first power supply terminal VGL to transmit the low-level first power signal to the pull-up node Q. Because the four second isolation transistors T61 to T64 can remain turned on based on the low-level first power signal, the potentials of the four output nodes Q1 to Q4 can be further set low, thereby enabling the four output transistors T91 to T94 to be turned on. Furthermore, with the potentials of the control node P and the third clock signal both low, and the potential of the pull-up node Q low, the first pull-down control transistor T41, the second pull-down control transistor T42, and the fourth pull-down control transistor T44 can all be turned on, thereby enabling the first clock terminal CLK1 and the second clock terminal CLK2 to transmit the first clock signal and the second clock signal, respectively, to the pull-down control node QB. Because the potentials of the first and second clock signals are both high in phase t04, the potential of the pull-down control node QB can be raised. Furthermore, the clock signal line CLK3 can provide a high-potential third clock signal. At this time, coupled by the third storage capacitor Cst3, the potentials of the four output nodes Q1 to Q4 are further lowered, fully turning on the four output transistors T91 to T94. The clock signal lines CLKE1 to CLKE4 connected to the four output clock terminals CLKS1 to CLKS4 sequentially provide low-potential clock signals. Consequently, low-potential signals can be sequentially output to the four output terminals Scout1 to Scout4.

[0226] At stage t05, the clock signal line CLKP1 connected to the input clock terminal CLKP1 can provide a low-potential input clock signal, and the clock signal line CLKE10 connected to the control clock terminal CLKE10 can provide a high-potential control clock signal, so that the seventh transistor T7 is turned on, and the input clock terminal CLKP1 can transmit a low-potential input clock signal to the subsequent pull-up node Q_em. That is, at stage t03, the potential of the subsequent pull-up node Q_em can be lowered. Because the fourth transistor T4 is normally open, the tenth transistor T10 can be turned on, and the second transistor T2 can also be turned on. This allows the first power supply terminal VGH to transmit a high-potential first power supply signal to the subsequent pull-down node QB_em, and the second power supply terminal VGL to transmit a low-potential second power supply signal to the subsequent output terminal EM. That is, at stage t03, the potential of the subsequent pull-down node QB_em can also be increased, and the potential of the subsequent output terminal EM can be lowered. This may refer to the first subsequent output terminal EM (1).

[0227] At stage t06, the selection signal provided by selection terminal D0 of the eight selection terminals D0 to D7 jumps to a low level, enabling the second group of shift register units and de-enabling the first group of shift register units. At this point, the selection transistor T11 included in the second group of shift register units can be turned on, and the second clock terminal CLK2 can transmit a low-level second clock signal to the intermediate node N, lowering the level of the intermediate node N. Accordingly, the first pre-charge transistor T31 can be turned on, and the first clock terminal CLK1 can transmit a low-level first clock signal to the control node P, lowering the level of the control node P. Combined with the low-level third clock signal provided by the third clock terminal CLK3, the first pull-down control transistor T41 and the second pull-down control transistor T42 can be turned on. The second clock terminal CLK2 also transmits a low-level second clock signal to the pull-down control node QB, lowering the level of the pull-down control node QB. Accordingly, the first pull-down transistor T50 and the four second pull-down transistors T51 to T54 are all turned on, thereby causing the second power supply terminal VGH to output a high-potential second power supply signal to the front-stage pull-up node Q and the four front-stage output terminals Scout1 to Scout4, thereby setting the potential of the front-stage pull-up node Q and the potential of the signals output by the four front-stage output terminals Scout1 to Scout4 high. Based on the high potential of the front-stage pull-up node Q, because the four second isolation transistors T61 to T64 can remain turned on based on the low-potential first power supply signal, the potential of the four output nodes Q1 to Q4 can be further increased. This phase t06 can also be called a reset phase, and this phase t06 can be repeatedly executed when the shift register unit is not selected.

[0228] It can be understood that, in conjunction with FIG. 16 , it can be seen that stage t06 can actually be divided into three stages t06a, t06b and t06c that are executed in sequence.

[0229] In stage t06a, the clock signal line CLK2 connected to the second clock terminal CLK2 can provide a low-potential second clock signal, while the potentials of the first clock signal and the third clock signal can both be high, and the potential of the selection signal provided by the selection terminal D0 can be low. Accordingly, the third pull-down control transistor T43 and the selection transistor T11 can both be turned on, thereby causing the second clock terminal CLK2 to transmit the low-potential second clock signal to the intermediate node N, and causing the second power supply terminal VGL to transmit the low-potential second power supply signal to the pull-down control node QB, that is, setting the potentials of the intermediate node N and the pull-down control node QB to low. Accordingly, the first pre-charge transistor T31 can be turned on, thereby causing the first clock terminal CLK1 to transmit the first clock signal to the control node P. Since the potential of the first clock signal is high in stage t06a, the potential of the control node P can be high. Furthermore, the first pull-down transistor T50 and the four second pull-down transistors T51 to T54 can all be turned on, thereby enabling the first power supply terminal VGH to output a high-potential first power supply signal to the front-stage pull-up node Q and the four front-stage output terminals Scout1 to Scout4. In other words, the potential of the front-stage pull-up node Q and the potential of the signals output by the four output terminals Scout1 to Scout4 can all be set high. With the potential of the front-stage pull-up node Q set high, the four output transistors T91 to T94 can all be turned off.

[0230] In stage t06b, the clock signal line CLK3 connected to the third clock terminal CLK3 can provide a low-potential second clock signal, while the potential of the first clock signal and the potential of the second clock signal can both be high, and the potential of the gating signal provided by the gating terminal D0 can be low. Accordingly, the gating transistor T11 can be turned on, and the second clock terminal CLK2 can then transmit a high-potential second clock signal to the intermediate node N, i.e., raising the potential of the intermediate node N, so that the first pre-charge transistor T31 is turned off. In addition, because the potential of the first clock signal is high, the second pre-charge transistor T32 can also be turned off. It can be seen from this that in this stage t06b, the control node P can be in a floating state, maintaining the high potential of the previous stage (i.e., stage t06a). Accordingly, the first pull-down control transistor T41 can be turned off. And, under the storage effect of the second storage capacitor Cst2, the potential of the pull-down control node QB can also maintain the low potential of the previous stage (i.e., stage t06a).

[0231] At stage t06c, the clock signal line CLK1 connected to the first clock terminal CLK1 can provide a low-level first clock signal, while the second and third clock signals can both be high-level, and the selection signal provided by the selection terminal D0 can be low-level. Accordingly, the selection transistor T11, the auxiliary control transistor T20, and the second pre-charge transistor T32 can all be turned on, thereby causing the first clock terminal CLK1 to transmit the low-level first clock signal to the control node P, and causing the second clock terminal CLK2 to transmit the high-level second clock signal to the intermediate node N. This means that the control node P can be low-level and the intermediate node N can be high-level.

[0232] Moreover, taking the structure shown in FIG15 as an example, combined with the foregoing description, it can be seen that for multiple groups of shift register units GOA0, the potential of the selection signal provided by the eight selection terminals D0 to D7 can be controlled to select the pre-stage decoding circuit Gate GOA in any group of shift register units GOA0, so that the selected group of shift register units GOA0 can output the gate drive signal to the connected pixels through the pre-stage output terminal, and the other groups of shift register units GOA0 that are not selected will not output the gate drive signal, thereby flexibly controlling the refresh frequency of the pixels connected to any group of shift register units.

[0233] In addition, Figure 17 also shows a timing diagram of a strobe signal. Referring to Figure 17 , it can be seen that, among the eight strobe terminals D0 to D7, the frequencies of the strobe signals provided by the first strobe terminal D0 through the eighth strobe terminal D7 can also be sequentially reduced as described above. In Figure 17 , taking the first strobe terminal D0 as an example, D0 can refer to a strobe signal with an inactive potential provided by strobe terminal D0, and De0 can refer to a strobe signal with an active potential provided by strobe terminal D0. The same applies to the other strobe terminals and will not be further described here.

[0234] It is understandable that since the gate driving circuit has substantially the same technical effects as those of the aforementioned shift register unit embodiment, the technical effects of the gate driving circuit will not be described repeatedly for the purpose of brevity.

[0235] FIG18 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure. As shown in FIG18 , the display device includes: a display panel 100 and a light emitting control circuit 000 as shown in FIG15 .

[0236] The display panel 100 includes a plurality of pixels, and the light emitting control circuit 000 is connected to the plurality of pixels and is used to transmit light emitting control signals to the plurality of pixels to drive the plurality of pixels to emit light.

[0237] It is understood that the light emitting control circuit 000 may include a pre-decoding circuit 10 and a post-driving circuit 00. Only a portion of the pre-decoding circuit 10 may function as a gate driving circuit to transmit gate driving signals to a plurality of pixels.

[0238] Optionally, Figure 19 shows a schematic diagram of the circuit structure of a pixel. As shown in Figure 19, the pixel may include a pixel circuit and a light-emitting element L1. The pixel circuit may include seven transistors M1 to M7 and a capacitor Cst. And the pixel circuit is respectively connected to six signal lines: a pull-up power line ELVDD, a gate line Scan(i), a reset control line Scan(i-1), a light-emitting control line EM(i), a data signal line Data, and a reset line Init. The pixel circuit of this architecture is also called a 7T-1C-6L (i.e., 7 transistors, 1 capacitor, and 6 signal lines) circuit architecture. In addition, the light-emitting element L1 is also connected to the pull-down power line ELVSS.

[0239] Among them, transistor M1 is a driving transistor, and transistors M2 through M7 are switching transistors. The gate-source voltage difference Vgs of transistor T1 can be stored in capacitor Cst, and the driving current I is determined based on grayscale data. Furthermore, transistors M2 and M7, under the control of signals provided by six signal lines, can control transistor M1 to output a driving current as a light-emitting driving signal to light-emitting element L1, allowing light-emitting element L1 to reliably emit light based on this light-emitting driving signal and the pull-down power signal provided by the pull-down power line ELVSS. Among transistors M2 through M7, M5 and M6 are primarily used to control the connection between transistor M1 and light-emitting element L1 based on a signal provided by the light-emitting control line EM(i), thereby blocking the driving current I or allowing the driving current I to flow into light-emitting element L1. Accordingly, it can be seen that the signal provided by the light-emitting control line EM(i) can be used for dimming.

[0240] Optionally, the light-emitting element L1 may be an organic light-emitting diode (OLED), and Figure 19 also schematically illustrates a parasitic capacitor Coled formed between the cathode and anode of the OLED. In addition, each transistor in the pixel shown in Figure 19 is a P-type transistor.

[0241] Taking the structure shown in Figure 19 as an example, Figure 20 schematically shows a working timing diagram of a pixel. Referring to Figure 20, it can be seen that the pixel light emission can include phase 1, phase 2 and phase 3.

[0242] In stage 1, the reset control line Scan(i-1) can provide a reset control signal with an effective potential, turning on transistor M4, thereby causing the reset line Init to output a reset signal to the gate of transistor M1 to reset the gate of transistor M1. In stage 2, the gate line Scan(i) can provide a gate drive signal with an effective potential, turning on transistors M2, M3, and M7, thereby causing the data line Data to output a data signal to the first electrode of transistor M1, causing the reset line Init to output a reset signal to the light-emitting element L1 to reset the light-emitting element L1 and turn on the gate and second electrode of transistor M1. In stage 3, the light-emitting control line EM(i) can provide a light-emitting control signal with an effective potential, turning on transistors M5 and M6, thereby causing transistor M1 to generate a drive current and output the drive current to the light-emitting element L1, thereby driving the light-emitting element L1 to emit light.

[0243] It can be seen from this that in the light-emitting control circuit provided by the embodiment of the present disclosure, the rear-stage output terminal EM(i) of the shift register unit can be connected to the light-emitting control line EM(i) in the pixel shown in Figure 19, and is used to output a light-emitting control signal as shown in Figure 20 to the light-emitting control line EM(i), thereby driving the pixel to emit light.

[0244] In addition, the front-stage output terminal Scout(i) of the shift register unit can be connected to the gate line Scan(i) in the pixel shown in Figure 19, and is used to output the gate drive signal shown in Figure 20 to the gate line Scan(i), thereby driving the pixel to emit light.

[0245] Optionally, the display device described in the embodiments of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator.

[0246] It is understood that the terms used in the embodiments of the present disclosure are only used to explain the embodiments of the present disclosure and are not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the common meanings understood by people with ordinary skills in the field to which the present disclosure belongs.

[0247] For example, the words “first”, “second” or “third” and similar words used in the patent application specification and claims of this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as “a” or “an” do not indicate a quantitative limitation, but rather indicate the existence of at least one. Words such as “include” or “comprise” mean that the elements or objects appearing before “include” or “comprise” include the elements or objects listed after “include” or “comprise” and their equivalents, and do not exclude other elements or objects. “Up”, “down”, “left” or “right” are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. “Connected” means electrically connected. “And / or” means that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character “ / ” generally indicates that the objects related to each other are in an “or” relationship.

[0248] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A shift register unit, comprising: A front-stage decoding circuit and at least two rear-stage driving circuits; The pre-stage decoding circuit includes: a pre-charging circuit, which is respectively connected to at least two strobe terminals, a first clock terminal, a second clock terminal, and a control node, and is used to control the connection and disconnection between the first clock terminal and the control node in response to a strobe signal provided by each of the strobe terminals, a first clock signal provided by the first clock terminal, and a second clock signal provided by the second clock terminal; each of the post-stage driving circuits includes: an input circuit, connected to the control node, the control clock terminal, the input clock terminal, and the subsequent pull-up node, respectively, and configured to control the connection and disconnection between the input clock terminal and the subsequent pull-up node in response to the potential of the control node, the control clock signal provided by the control clock terminal, and the input clock signal provided by the input clock terminal; a rear-stage pull-down control circuit, connected to the control node, the control clock terminal, the rear-stage pull-up node, the first power terminal, and the rear-stage pull-down node, respectively, and configured to control the connection and disconnection between the control clock terminal and the rear-stage pull-down node in response to the potential of the control node, and to control the connection and disconnection between the first power terminal and the rear-stage pull-down node in response to the potential of the rear-stage pull-up node; a subsequent pull-down circuit, connected to the subsequent pull-down node, the first power supply terminal, and the subsequent output terminal, respectively, and configured to control the connection and disconnection between the first power supply terminal and the subsequent output terminal in response to the potential of the subsequent pull-down node; The post-stage output circuit is respectively connected to the post-stage pull-up node, the second power supply terminal and the post-stage output terminal, and is used to control the on-off of the second power supply terminal and the post-stage output terminal in response to the potential of the post-stage pull-up node, so as to output a light-emitting control signal through the post-stage output terminal.

2. The shift register unit according to claim 1, wherein: The latter stage pull-down control circuit comprises: a first pull-down control subcircuit, connected to the control node, the control clock terminal, and the subsequent pull-down node, respectively, and configured to control the connection and disconnection between the control clock terminal and the subsequent pull-down node in response to the potential of the control node; The second pull-down control subcircuit is connected to the rear pull-up node, the first power supply terminal and the rear pull-down node respectively, and is used to control the first power supply terminal in response to the potential of the rear pull-up node. The connection and disconnection between the source end and the subsequent pull-down node.

3. The shift register unit according to claim 2, wherein: The first pull-down control subcircuit includes: a first transistor; The gate of the first transistor is connected to the control node, the first electrode of the first transistor is connected to the control clock terminal, and the second electrode of the first transistor is connected to the subsequent pull-down node.

4. The shift register unit according to claim 2 or 3, wherein: The second pull-down control subcircuit includes: a second transistor; The gate of the second transistor is connected to the subsequent pull-up node, the first electrode of the second transistor is connected to the first power supply terminal, and the second electrode of the second transistor is connected to the subsequent pull-down node.

5. The shift register unit according to any one of claims 2 to 4, wherein: The post-stage driving circuit further includes: The first holding circuit is connected between the first pull-down control sub-circuit and the subsequent pull-down node, and is also connected to the control clock terminal, and is used to control the on-off of the first pull-down control sub-circuit and the subsequent pull-down node in response to the control clock signal. The shift register unit according to claim 5 , wherein: The first holding circuit includes: a third transistor; The gate of the third transistor is connected to the control clock terminal, the first electrode of the third transistor is connected to the first pull-down control sub-circuit, and the second electrode of the third transistor is connected to the subsequent pull-down node.

7. The shift register unit according to any one of claims 1 to 6, wherein: The post-stage driving circuit further includes: The second holding circuit is connected to the first power supply terminal and the subsequent pull-down node respectively, and is used to maintain the potential of the subsequent pull-down node based on a first power supply signal provided by the first power supply terminal.

8. The shift register unit according to claim 7, wherein: The second holding circuit includes: a first capacitor; One end of the first capacitor is connected to the first power supply end, and the other end of the first capacitor is connected to the subsequent pull-down node.

9. The shift register unit according to any one of claims 1 to 8, wherein: The post-stage driving circuit further includes: The subsequent stage isolation circuit is connected between the subsequent stage pull-up node and the subsequent stage output circuit, and is also connected to the second power supply terminal, and is used to control the subsequent stage pull-up node and the subsequent stage output circuit to be conductive in response to the second power supply signal.

10. The shift register unit according to claim 9, wherein: The post-stage isolation circuit includes: a fourth transistor; The gate of the fourth transistor is connected to the second power supply terminal, the first electrode of the fourth transistor is connected to the subsequent pull-up node, and the second electrode of the fourth transistor is connected to the subsequent output circuit.

11. The shift register unit according to any one of claims 1 to 10, wherein: The rear-stage pull-down circuit includes: a fifth transistor; The gate of the fifth transistor is connected to the subsequent pull-down node, the first electrode of the fifth transistor is connected to the first power supply terminal, and the second electrode of the fifth transistor is connected to the subsequent output terminal.

12. The shift register unit according to claim 11, wherein: The fifth transistor includes: a first sub-transistor and a second sub-transistor connected in series; The gate of the first sub-transistor and the gate of the second sub-transistor are both connected to the subsequent pull-down node, the first electrode of the first sub-transistor is connected to the first power supply terminal, the second electrode of the first sub-transistor is connected to the first electrode of the second sub-transistor, and the second electrode of the second sub-transistor is connected to the subsequent output terminal; the subsequent driving circuit further includes: The anti-leakage circuit is respectively connected to the post-stage output terminal, the second power supply terminal and the series node of the first sub-transistor and the second sub-transistor, and is used to control the connection and disconnection of the second power supply terminal and the series node in response to the potential of the post-stage output terminal.

13. The shift register unit according to claim 12, wherein: The anti-leakage circuit includes: a sixth transistor; The gate of the sixth transistor is connected to the subsequent output terminal, the first electrode of the sixth transistor is connected to the second power supply terminal, and the second electrode of the sixth transistor is connected to the series node.

14. The shift register unit according to any one of claims 1 to 13, wherein: The input circuit includes: a seventh transistor, an eighth transistor and a ninth transistor; The gate electrode and the first electrode of the seventh transistor are both connected to the input clock terminal, and the second electrode of the seventh transistor is connected to the subsequent pull-up node; The gate of the eighth transistor is connected to the control node, the first electrode of the eighth transistor is connected to the second electrode of the ninth transistor, and the second electrode of the eighth transistor is connected to the subsequent pull-up node; The gate of the ninth transistor is connected to the control clock terminal, and the first electrode of the ninth transistor is connected to the input clock terminal.

15. The shift register unit according to any one of claims 1 to 14, wherein: The post-stage output circuit includes: a tenth transistor and a second capacitor; The gate of the tenth transistor is connected to the subsequent stage pull-up node, the first electrode of the tenth transistor is connected to the second power supply terminal, and the second electrode of the tenth transistor is connected to the subsequent stage output terminal; One end of the second capacitor is connected to the subsequent stage pull-up node, and the other end of the second capacitor is connected to the subsequent stage output terminal.

16. The shift register unit according to any one of claims 1 to 15, wherein: The pre-charging circuit is further connected to the second power supply terminal and is used to store the potential of the control node based on the second power supply signal; The pre-stage decoding circuit further includes: a charging circuit, connected to the control node, the second clock terminal, the third clock terminal, the second power supply terminal, and the previous-stage pull-up node, respectively, and configured to control the connection and disconnection between the second power supply terminal and the previous-stage pull-up node in response to the potential of the control node and a third clock signal provided by the third clock terminal, and to control the connection and disconnection between the third clock terminal and the previous-stage pull-up node in response to the second clock signal; The reset circuit is respectively connected to the reset terminal, the first power terminal, the control node and the previous stage The pull-up node is connected to the first power supply terminal and is used to control the connection and disconnection between the first power supply terminal and the control node, and control the connection and disconnection between the first power supply terminal and the previous stage pull-up node in response to a reset signal provided by the reset terminal; At least two front-stage output circuits are respectively connected to the front-stage pull-up node, the at least two output clock terminals corresponding to each other, and the at least two front-stage output terminals corresponding to each other, each of the front-stage output circuits being configured to control the connection and disconnection between a corresponding output clock terminal and a corresponding front-stage output terminal in response to the potential of the front-stage pull-up node; a front-stage pull-down control circuit, connected to the control node, the second clock terminal, the third clock terminal, the first power terminal, the second power terminal, the front-stage pull-up node, and the front-stage pull-down node, respectively, and configured to control the connection and disconnection between the second clock terminal and the front-stage pull-down node in response to the potential of the control node and the third clock signal, control the connection and disconnection between the second power terminal and the front-stage pull-down node in response to the second clock signal, control the connection and disconnection between the second clock terminal and the front-stage pull-down node in response to the potential of the front-stage pull-up node, and store the potential of the front-stage pull-down node based on the first power signal; The front-stage pull-down circuit is respectively connected to the front-stage pull-down node, the first power supply terminal, the front-stage pull-up node and the at least two front-stage output terminals, and is used to control the on-off connection between the first power supply terminal and the front-stage pull-up node in response to the potential of the front-stage pull-down node, and to control the on-off connection between the first power supply terminal and each of the front-stage output terminals, so as to output a gate drive signal through the front-stage output terminal.

17. The shift register unit according to claim 16, wherein: The pre-stage decoding circuit further includes: a first front-stage isolation circuit, connected between the control node and the front-stage pull-down control circuit, and further connected to the second power supply terminal, and configured to control conduction between the control node and the front-stage pull-down control circuit in response to the second power supply signal; The second front-stage isolation circuit is connected between the front-stage pull-up node and the at least two front-stage output circuits, and is also connected to the second power supply terminal, and is used to control the front-stage pull-up node and the at least two front-stage output circuits to be conductive in response to the second power supply signal.

18. A method for driving a shift register unit, for driving the shift register unit according to any one of claims 1 to 17; the method comprising: In the first stage, in the pre-decoding circuit, the precharge circuit responds to each of the at least two selection terminals. The gating signal provided by the pass terminal, the first clock signal provided by the first clock terminal and the second clock signal provided by the second clock terminal control the first clock terminal to be conductive with the control node; In the second stage, in each subsequent-stage driving circuit, the subsequent-stage input circuit controls the input clock terminal to be conductively connected to the subsequent-stage pull-up node in response to the potential of the control node, the control clock signal provided by the control clock terminal, and the input clock signal provided by the input clock terminal; the subsequent-stage pull-down control circuit controls the control clock terminal to be conductively connected to the subsequent-stage pull-down node in response to the potential of the control node; and the subsequent-stage pull-down circuit controls the first power supply terminal to be conductively connected to the subsequent-stage output terminal in response to the potential of the subsequent-stage pull-down node; In the third stage, in each of the post-stage driving circuits, the post-stage input circuit controls the input clock terminal and the post-stage pull-up node to be connected in response to the input clock signal, the post-stage pull-down control circuit controls the control clock terminal and the post-stage pull-down node to be connected in response to the potential of the control node, and controls the first power supply terminal and the post-stage pull-down node to be connected in response to the potential of the post-stage pull-up node, and the post-stage output circuit controls the second power supply terminal and the post-stage output terminal to be connected in response to the potential of the post-stage pull-up node.

19. A light emitting control circuit, comprising: A plurality of groups of shift register units, each group of shift register units comprising: at least two shift register units according to any one of claims 1 to 17; Each group of shift register units shares a first clock terminal, a second clock terminal, a control clock terminal, an input clock terminal and a strobe terminal, and each group of shift register units is configured to receive different strobe signals provided by at least two of the strobe terminals.

20. A display device, comprising: A display panel, and a light emitting control circuit as claimed in claim 19; The display panel includes a plurality of pixels, and the light emitting control circuit is connected to the plurality of pixels and is used to transmit a light emitting control signal to the plurality of pixels to drive the plurality of pixels to emit light.

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