Integrated circuit for calibration of offset voltage mismatch between comparators in analog-to-digital converter and method

Abstract

The present disclosure relates to an integrated circuit for calibration of an offset voltage mismatch between comparators in an analog-to-digital converter and a method. The integrated circuit comprises a successive-approximation analog-to-digital converter comprising N+1 comparators, and N calibration circuits. The input end of any calibration circuit is connected to the output end of the successive-approximation analog-to-digital converter, and the output end of any calibration circuit is connected to the input end of a different comparator. The successive-approximation analog-to-digital converter is used for converting an input signal into a multi-bit digital code. Each calibration circuit is used for determining mismatch information on the basis of the multi-bit digital code, wherein the mismatch information is used for correcting an offset voltage of the comparator connected to the calibration circuit. According to embodiments of the present disclosure, calibration circuits are used to increase the conversion rate and improve the quantization precision of an analog-to-digital converter, and reduce hardware complexity and non-ideal effects.

Description

Integrated circuit and method for calibrating offset voltage mismatch of comparator in analog-to-digital converter Technical Field

[0001] The present disclosure relates to the field of integrated circuits, and in particular to an integrated circuit and method for calibrating a comparator offset voltage mismatch in an analog-to-digital converter. Background Art

[0002] Calibration circuits can be used in analog mixed-signal integrated circuits to correct for non-ideal factors in analog circuits. Calibration circuits typically consist of both analog and digital circuits, combining them to achieve accuracy requirements that cannot be achieved by analog circuits alone. An analog-to-digital converter (ADC) is an electronic system that converts analog signals into digital signals, typically implemented using an integrated circuit (chip). The successive approximation register analog-to-digital converter (SAR ADC) is a commonly used ADC architecture with a wide range of applications, adapting to a variety of ADC specifications, from high-precision and low-power to ultra-high-speed and low-precision.

[0003] Summary of the Invention

[0004] In view of this, the present disclosure proposes an integrated circuit and method for calibrating comparator offset voltage mismatch in an analog-to-digital converter.

[0005] According to one aspect of the present disclosure, an integrated circuit is provided, comprising: a successive approximation analog-to-digital converter having N+1 comparators, and N calibration circuits, where N is an integer greater than or equal to 1, the input of any calibration circuit being connected to the output of the successive approximation analog-to-digital converter, and the output of any calibration circuit being connected to the input of a different comparator, wherein the successive approximation analog-to-digital converter is configured to convert an input signal into a multi-bit digital code; and the calibration circuit is configured to determine mismatch information based on the multi-bit digital code, and the mismatch information is used to correct an offset voltage of the comparator connected to the calibration circuit.

[0006] In one possible implementation, the calibration circuit is used to determine mismatch information based on the multi-bit digital code, including: the calibration circuit is used to determine the mismatch information based on the difference between two adjacent bits of digital code in the multi-bit digital code, or the difference between one bit of digital code in the multi-bit digital code and a preset value.

[0007] In one possible implementation, the calibration circuit includes a subtractor, an averaging module, and a comparison module connected in series in sequence, wherein the subtractor is used to determine the difference between two adjacent bits of digital codes in a multi-bit digital code, or the difference between a bit of digital code in the multi-bit digital code and a preset value; the averaging module is used to determine the average value of the difference; and the comparison module is used to determine the mismatch information based on the comparison result of the average value and the zero value.

[0008] In one possible implementation, the input end of the i-th calibration circuit is connected to the output end of the successive approximation analog-to-digital converter, the output end of the i-th calibration circuit is connected to the input end of the i+1-th comparator, and the i-th calibration circuit is used to determine mismatch information based on the difference between the N-i+1th last bit digital code in the multi-bit digital code and a preset value, and the mismatch information is used to correct the offset voltage of the i+1-th comparator, where i is any integer between 1 and N.

[0009] In one possible implementation, the input end of the i-th calibration circuit is connected to the output end of the successive approximation analog-to-digital converter, the output end of the i-th calibration circuit is connected to the input end of the i+1-th comparator, and the i-th calibration circuit is used to determine mismatch information based on the difference between the N-i+1th bit digital code and the N-i+2th bit digital code in the multi-bit digital code, and the mismatch information is used to correct the offset voltage of the i+1-th comparator, where i is any integer between 1 and N.

[0010] In a possible implementation, the comparator includes a comparator having a current pump structure.

[0011] According to another aspect of the present disclosure, a calibration method is provided. The calibration method is applied to an integrated circuit, the integrated circuit comprising: a successive approximation analog-to-digital converter having N+1 comparators, and N calibration circuits, where N is an integer greater than 1, the input of any calibration circuit being connected to the output of the successive approximation analog-to-digital converter, and the output of any calibration circuit being connected to the input of a different comparator. The calibration method comprises: the successive approximation analog-to-digital converter converting an input signal into a multi-bit digital code; the calibration circuit determining mismatch information based on the multi-bit digital code, and the mismatch information being used to correct an offset voltage of the comparator connected to the calibration circuit.

[0012] In a possible implementation, the calibration circuit determines the mismatch information based on the multi-bit digital code, including: the calibration circuit determines the mismatch information based on a difference between two adjacent bits of the multi-bit digital code, or a difference between a bit of the multi-bit digital code and a preset value.

[0013] In one possible implementation, the calibration circuit includes a subtractor, an average value module, and a comparison module connected in series in sequence. The calibration circuit determines the mismatch information based on the difference between two adjacent bits of digital codes in a multi-bit digital code, or the difference between one bit of digital code in the multi-bit digital code and a preset value. The calibration circuit includes: the subtractor is used to determine the difference between two adjacent bits of digital codes in the multi-bit digital code, or the difference between one bit of digital code in the multi-bit digital code and a preset value; the average value module is used to determine the average value of the difference; and the comparison module is used to determine the mismatch information based on the comparison result of the average value and a zero value.

[0014] In one possible implementation, the input end of the i-th calibration circuit is connected to the output end of the successive approximation analog-to-digital converter, the output end of the i-th calibration circuit is connected to the input end of the i+1-th comparator, and the calibration circuit determines the mismatch information based on the difference between a bit digital code in the multi-bit digital code and a preset value, including: the i-th calibration circuit determines the mismatch information based on the difference between the N-i+1th last bit digital code in the multi-bit digital code and the preset value, and the mismatch information is used to correct the offset voltage of the i+1-th comparator, where i is any integer from 1 to N.

[0015] In one possible implementation, the input end of the i-th calibration circuit is connected to the output end of the successive approximation analog-to-digital converter, the output end of the i-th calibration circuit is connected to the input end of the i+1-th comparator, and the calibration circuit determines the mismatch information based on the difference between two adjacent bits of the multi-bit digital code, including: the i-th calibration circuit determines the mismatch information based on the difference between the N-i+1th bit digital code and the N-i+2th bit digital code in the multi-bit digital code, and the mismatch information is used to correct the offset voltage of the i+1-th comparator, where i is any integer from 1 to N.

[0016] In a possible implementation, the comparator includes a comparator having a current pump structure.

[0017] According to another aspect of the present disclosure, an analog-to-digital converter is provided, comprising the integrated circuit as described above.

[0018] According to another aspect of the present disclosure, a chip is provided, comprising the integrated circuit as described above.

[0019] According to another aspect of the present disclosure, an electronic device is provided, comprising the integrated circuit as described above.

[0020] An integrated circuit according to an embodiment of the present disclosure includes: a successive approximation analog-to-digital converter having N+1 comparators, and N calibration circuits, where N is an integer greater than or equal to 1, the input of any calibration circuit being connected to the output of the successive approximation analog-to-digital converter, and the output of any calibration circuit being connected to the input of a different comparator, wherein the successive approximation analog-to-digital converter is configured to convert an input signal into a multi-bit digital code; and the calibration circuit is configured to determine mismatch information based on the multi-bit digital code, and the mismatch information is used to correct the offset voltage of the comparator connected to the calibration circuit.

[0021] In this way, the calibration circuit can be used to extract the mismatch information of the comparator offset voltage, which can be performed entirely in the background of the digital circuit domain, eliminating the reset operation at the comparator input and the comparison operation with 0 as input, thereby improving the overall conversion rate and conversion accuracy. At the same time, it also eliminates the short-circuit switch and its control logic circuit required for the reset operation, reducing hardware complexity and avoiding the introduction of additional non-ideal effects.

[0022] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0024] FIG1 is a schematic diagram showing the working principle of a successive approximation analog-to-digital converter in the related art.

[0025] FIG2 is a schematic diagram showing the working principle of a successive approximation analog-to-digital converter based on a ping-pong comparator in the related art.

[0026] FIG3 shows a schematic diagram of performing background calibration for offset voltage mismatch between two comparators.

[0027] FIG4 shows an analog diagram of a successive approximation analog-to-digital converter and a negative feedback loop.

[0028] FIG5 is a schematic diagram showing the distribution of the residual voltage at the comparator input terminal in the last two conversions of the successive approximation analog-to-digital converter.

[0029] FIG6 is a schematic diagram showing a negative feedback loop of a successive approximation analog-to-digital converter based on a ping-pong comparator.

[0030] FIG7 is a schematic diagram showing a comparison of the residual voltage waveforms in a SAR ADC based on a ping-pong comparator and a SAR ADC with a single comparator.

[0031] FIG8 is a schematic diagram showing the distribution of the last two digital codes output under different comparator offset voltages.

[0032] FIG9 shows a schematic diagram of an integrated circuit according to an embodiment of the present disclosure.

[0033] FIG10 shows a schematic diagram of a calibration circuit according to an embodiment of the present disclosure.

[0034] FIG11 is a schematic diagram showing a calibration circuit according to an embodiment of the present disclosure applied to a successive approximation analog-to-digital converter based on a ping-pong comparator.

[0035] FIG12 shows a circuit diagram of a comparator with a current pump structure according to an embodiment of the present disclosure.

[0036] FIG13 shows a flowchart of a calibration method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0038] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0039] In addition, numerous specific details are provided in the following detailed description to better illustrate the present disclosure. Those skilled in the art will appreciate that the present disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art are not described in detail in order to highlight the main points of the present disclosure.

[0040] FIG1 shows a schematic diagram of the working principle of a successive approximation analog-to-digital converter in the related art. As shown in FIG1 , the successive approximation analog-to-digital converter is composed of three parts: a comparator, a successive approximation logic circuit, and a capacitor digital-to-analog converter (CDAC). Among them, the operation of a comparator comparison, a successive approximation logic circuit data transmission, a capacitor digital-to-analog converter difference, and a comparator reset is called a conversion. Each conversion will output a 1-bit digital code. The successive approximation analog-to-digital converter makes the output digital code D of the successive approximation analog-to-digital converter through successive conversions. out Approximate input voltage V inBecause successive approximation ADCs (SAADCs) are digital modules that consume no quiescent current, they are energy-efficient and very resistant to process evolution, making them widely used in industry. However, since each conversion only produces a 1-bit digital code output, and N-bit quantization accuracy requires N conversions, the total conversion time of SAADCs is long, making it difficult to increase the sampling rate.

[0041] FIG2 is a schematic diagram illustrating the operating principle of a ping-pong comparator-based successive approximation analog-to-digital converter (ADC) in the related art. Compared to the ping-pong comparator ADC shown in FIG1 , the ping-pong comparator-based ADC shown in FIG2 can improve the sampling rate. The ping-pong comparator-based ADC uses two comparators to perform comparisons and resets alternately. For example, during the kth conversion, comparator 1 performs comparisons and comparator 2 performs resets. During the k+1th conversion, comparator 2 performs comparisons and comparator 1 performs resets. This operating mode moves the comparator reset operation outside the critical timing path, effectively improving the conversion rate of the SAR ADC. However, in actual chips, mismatches between the two comparators are inevitable. Mismatches in their offset voltages can significantly reduce quantization accuracy and seriously affect the performance of the ADC. Therefore, this operating mode requires background calibration of the offset voltage mismatch between the two comparators.

[0042] In a ping-pong comparator-based successive approximation analog-to-digital converter, there is an offset voltage mismatch between the two comparators. FIG3 shows a schematic diagram of background calibration for the offset voltage mismatch between the two comparators. As shown in FIG3 , after the quantization conversion of each cycle is completed, the input end of the comparator is reset through a short-circuit switch, and the comparator performs a comparison with 0 as the input. The sign of the comparator offset voltage can be extracted based on the polarity of the comparison result. If the comparison result is 1, the comparator offset voltage is positive. If the comparison result is 0, the comparator offset voltage is negative. In this way, the offset voltage of the comparator can be calibrated to 0. In order to calibrate the offset voltage mismatch between the two comparators, this scheme extracts the offset voltages of the two comparators alternately in two adjacent cycles. That is, in the nth cycle, after the quantization conversion is completed, comparator 1 performs comparison with 0 as input and extracts the offset voltage. In the n+1th cycle, comparator 2 performs comparison with 0 as input and extracts the offset voltage. And so on. The offset voltages of the two comparators can be calibrated to 0 in turn, thereby achieving the calibration of the offset voltage mismatch between the two.

[0043] It can be seen that the calibration method for comparator offset voltage mismatch provided by the related art requires an additional reset operation of the comparator input and a comparison operation with 0 as input when extracting the comparator offset voltage, which increases the overall conversion time of the successive approximation analog-to-digital converter and reduces the sampling rate. In addition, resetting the comparator input requires adding a short-circuit switch and its control logic circuit to the comparator input, resulting in increased hardware complexity. In addition, the short-circuit switch added to the comparator input will also increase the nonlinear parasitic capacitance of the top plate in the capacitive digital-to-analog converter, thereby introducing additional non-ideal effects and limiting its application in industrial products.

[0044] In view of this, the embodiments of the present disclosure compare a successive approximation analog-to-digital converter (A / D converter) with a negative feedback loop. Utilizing the distribution characteristics of the multi-bit digital code output by the A / D converter, an integrated circuit is proposed, comprising a A / D converter having N+1 comparators and N calibration circuits. The calibration circuit can determine mismatch information for calibrating the offset voltage of the comparators based on the multi-bit digital code output by the A / D converter. In this way, the calibration circuit performs background calibration of the offset voltage mismatch between the comparators without reducing the conversion rate of the A / D converter. Compared to the related art, which requires the addition of a shorting switch and its control logic circuit for comparator offset voltage mismatch calibration, the calibration circuit in the embodiments of the present disclosure reduces hardware complexity and avoids the introduction of additional non-ideal effects.

[0045] Figure 4 shows an analog diagram of a successive approximation ADC and a negative feedback loop. The comparator in the successive approximation ADC can convert an input signal V in Converted to 0 or 1 level, so it can be compared to a high-gain amplifier in a negative feedback loop (amplification factor a>>1), and the capacitive digital-to-analog converter in the successive approximation analog-to-digital converter can be compared to the unity gain feedback in the negative feedback loop (f=1). In the negative feedback loop, when the loop gain af>>1, the error voltage V e It will converge to 0 under the action of the negative feedback loop, which can be called the "virtual ground point". Analogously applying this conclusion to the successive approximation analog-to-digital converter, the residual voltage V res The SAR ADC will converge to the comparator offset voltage V os Consider the case where there is thermal noise in the comparator, and in the last few conversions of the successive approximation ADC (for example, the last two conversions), the residual voltage V resThe distribution is approximately normal. The operations of one comparator comparison, one successive approximation logic circuit data transfer, one capacitive DAC difference, and one comparator reset are called one conversion, and each conversion outputs a 1-bit digital code.

[0046] Figure 5 shows the residual voltage V at the comparator input in the last two conversions of the successive approximation ADC. res The schematic diagram of the distribution is shown in Figure 5. The horizontal axis represents different voltage values, and the vertical axis represents the residual voltage V res is the probability density of a certain voltage value. In the last two conversions of the successive approximation analog-to-digital converter, the residual voltage V res The distribution is approximately normal, and the comparator offset voltage V os It can be seen that in the last two conversions of the successive approximation ADC, the probability of the comparator result being 0 or 1 is equal, that is, the average value of the last two bits of output digital code is 0.5.

[0047] It can be seen that in a successive approximation analog-to-digital converter containing a comparator, the residual voltage V res The distribution center will converge to the comparator offset voltage V under the action of the successive approximation analog-to-digital converter (which can be compared to a negative feedback loop). os The conclusions drawn from the analogy with a successive approximation ADC and a negative feedback loop can be extended to a successive approximation ADC containing multiple comparators. This is explained below using a successive approximation ADC based on a ping-pong comparator as an example.

[0048] FIG6 is a schematic diagram of a negative feedback loop of a ping-pong comparator-based SAR ADC. As shown in FIG6 , the ping-pong comparator-based SAR ADC includes two comparators, which perform successive conversions alternately using the two comparators. Each conversion outputs a 1-bit digital code in a descending order, until the ping-pong comparator-based SAR ADC outputs a multi-bit digital code D. out Approximate input voltage V in Among them, since the successive approximation analog-to-digital converter based on the ping-pong comparator contains two comparators, it forms two negative feedback loops, namely loop 1 and loop 2 in Figure 6. It is worth noting that these two negative feedback loops share a "virtual ground", that is, the input terminal shared by the two comparators. Therefore, the residual voltage V res It will be affected by two negative feedback loops at the same time, both of which want to reduce the residual voltage V res The distribution center converges to the offset voltage of each comparator. For example, loop 1 hopes to convert the residual voltage V res The distribution center converges to the offset voltage Vos1 , loop 2 hopes to make the residual voltage V res The distribution center converges to the offset voltage V os2 .

[0049] FIG7 is a schematic diagram showing a comparison of the residual voltage waveforms in a SAR ADC based on a ping-pong comparator and a SAR ADC with a single comparator, wherein the abscissa represents the number of conversions and the ordinate represents different voltage values.

[0050] As shown in Figure 7, the right part shows the waveform of the residual voltage in a successive approximation analog-to-digital converter containing a comparator. The residual voltage V res Under the action of the successive approximation analog-to-digital converter (which can be compared to a negative feedback loop), it converges to the comparator's offset voltage V os Among them, last represents the last conversion, V res,last Represents the comparator residual voltage at the last conversion, D last Represents the single-digit code obtained from the last conversion, that is, the multi-digit code D output by the successive approximation analog-to-digital converter containing a comparator out The last digit in the V res,last-1 It represents the comparator residual voltage at the second to last conversion, D last-1 The single-digit code obtained by the penultimate conversion, that is, the multi-digit code D output by the successive approximation analog-to-digital converter containing a comparator out The second to last one.

[0051] As shown in Figure 7, the left part shows the waveform of the residual voltage in the successive approximation analog-to-digital converter based on the ping-pong comparator. The odd-numbered loops represent the offset voltage V of the comparator in loop 1. os1 , even numbers represent the offset voltage V of the comparator in loop 2 os2 When the offset voltage of the two comparators V os1 and offset voltage V os2 When there is mismatch, without loss of generality, assume that the offset voltage V os2 >Offset voltage V os1 When the comparator of loop 1 compares (see the odd-numbered times in the waveform on the left side of Figure 7), the residual voltage V res The distribution center of the voltage will be drawn to the offset voltage V by the action of loop 1. os1 When the comparator of loop 2 compares (see the even number of times in the waveform on the left side of Figure 7), the residual voltage V res The distribution center will be led to V by loop 2. os2 Among them, last represents the last conversion, V res,lastThe residual voltage of the comparator in loop 2 at the last conversion, D last It represents the single-digit code obtained by the last conversion, that is, the multi-digit code D output by the successive approximation analog-to-digital converter based on the ping-pong comparator. out The last digit in the V res,last-1 The residual voltage of the comparator in loop 1 during the second-to-last conversion, D last-1 It represents the single-digit code obtained by the penultimate conversion, that is, the multi-digit code D output by the successive approximation analog-to-digital converter based on the ping-pong comparator. out The second to last one.

[0052] FIG8 is a schematic diagram showing the distribution of the last two digital codes output under different comparator offset voltages. As shown in FIG8 , the horizontal axis represents different voltage values, and the vertical axis represents the residual voltage V res is the probability density of a certain voltage value. When the offset voltages of the two comparators are equal, that is, the offset voltage V os2 =Offset voltage V os1 (For ease of explanation, in the first row of Figure 8, V os =V os1 =V os2 ), similar to a successive approximation analog-to-digital converter with a comparator, the last two conversions are the residual voltage V at the comparator input. res,last-1 and V res,last The distribution center will converge to the comparator offset voltage V os , and the last two bits output digital code D last-1 and D last Average value and Both are 0.5.

[0053] When the offset voltages of the two comparators are mismatched, the two negative feedback loops will conflict, causing the residual voltage V res,last-1 and V res,last The distribution center converges to the offset voltage of the two comparators. Without loss of generality, assume that the penultimate conversion is compared by the comparator of loop 1 and the last conversion is compared by the comparator of loop 2. os2 >Offset voltage V os1 In the case of , the convergence result of the residual voltage at the final comparator input is Among them, last represents the last conversion. represents the average value of the residual voltage of the comparator in loop 2 at the last conversion, last-1 represents the second to last conversion, represents the average value of the residual voltage of the comparator in loop 1 during the second-to-last conversion. Therefore, during the second-to-last comparison, due to The result of the comparator of loop 1 will be more biased towards 1, and the digital code D of the second to last conversion will be last-1 Average value For the same reason, in the last comparison, due to D last Average value Then there is

[0054] Similarly, the offset voltage V os2 <Offset voltage V os1 In the case of , the final convergence result is Therefore, in the penultimate comparison, due to The result of the comparator of loop 1 will be more biased towards 0, and the digital code D of the second to last conversion will be last-1 Average value For the same reason, in the last comparison, due to D last Average value Then there is

[0055] Among them, due to the residual voltage V at the input of the comparator in the last conversion res,last The quantization noise is greater than the residual voltage V at the input of the penultimate conversion comparator. res,last-1 Lower, so the variance of its distribution is smaller, which is manifested as a narrower width of the waveform.

[0056] It should be understood that the distribution of the multi-bit digital code output by the successive approximation analog-to-digital converter including multiple comparators can refer to the distribution of the multi-bit digital code output by the successive approximation analog-to-digital converter based on the ping-pong comparator shown in Figures 7 and 8. The distribution of the multi-bit digital code output by the successive approximation analog-to-digital converter including multiple comparators can be used to design a calibration circuit to calibrate the offset voltage mismatch of different comparators in the successive approximation analog-to-digital converter.

[0057] FIG9 shows a schematic diagram of an integrated circuit according to an embodiment of the present disclosure. As shown in FIG9 , the integrated circuit includes: a successive approximation analog-to-digital converter having N+1 comparators 1 (e.g., comparator 1_1 to comparator 1_N+1), and N calibration circuits 2 (e.g., calibration circuit 2_1 to calibration circuit 2_N), where N is an integer greater than or equal to 1. The input of any calibration circuit 2 is connected to the output of the successive approximation analog-to-digital converter, and the output of any calibration circuit 2 is connected to the input of a different comparator 1. The successive approximation analog-to-digital converter is used to convert the input signal V in Convert to multi-bit digital code D out The calibration circuit 2 is used according to the multi-bit digital code D out Determine mismatch information, where the mismatch information is used to correct an offset voltage of the comparator 1 connected to the calibration circuit 2 .

[0058] Among them, the successive approximation analog-to-digital converter is composed of N+1 comparators 1_1 to comparator 1_N+1, a successive approximation logic circuit 3, and a capacitive digital-to-analog converter 4. For example, it includes a successive approximation analog-to-digital converter based on a ping-pong comparator, a loop-unrolled successive approximation analog-to-digital converter, a single-conversion multi-bit successive approximation analog-to-digital converter, etc. The embodiments of the present disclosure do not limit the type of successive approximation analog-to-digital converter in the integrated circuit, nor the specific number of comparators 1 included in the successive approximation analog-to-digital converter, and can be set according to the actual application scenario.

[0059] The successive approximation analog-to-digital converter can use N+1 comparators 1 to perform successive conversions alternately. Each conversion outputs a 1-bit digital code until the successive approximation analog-to-digital converter outputs a multi-bit digital code D. out Approximate input voltage V in .

[0060] In the example, the input signal V in It can be any analog voltage to be converted into a multi-bit digital code, for example, including temperature, light, humidity, pressure, speed, position, distance, quantity, electrocardiogram, radio frequency, audio, radio and other signals collected by analog circuit systems or sensors. The embodiments of the present disclosure process the input signal V in There is no restriction on the source and category.

[0061] In this example, the operations of one comparison by the comparator 1 , one data transfer by the SAR logic circuit 3 , one difference operation by the CDAC 4 and one reset of the comparator 1 are called one conversion. Each conversion outputs a 1-bit digital code.

[0062] The input end of the calibration circuit 2_1 is connected to the output end of the successive approximation analog-to-digital converter (i.e., the output end of the successive approximation logic circuit 3), and the output end of the calibration circuit 2_1 is connected to the input end of the comparator 1_2. The calibration circuit 2_1 can be configured to generate a multi-bit digital code D out , determine the mismatch information for correcting the offset voltage of the comparator 1_2; the input end of the calibration circuit 2_2 is connected to the output end of the successive approximation analog-to-digital converter (that is, the output end of the successive approximation logic circuit 3), and the output end of the calibration circuit 2_2 is connected to the input end of the comparator 1_3. The calibration circuit 2_2 can be based on the multi-bit digital code D out , determine the mismatch information for correcting the offset voltage of the comparator 1_3; and similarly, the input end of the calibration circuit 2_N is connected to the output end of the successive approximation analog-to-digital converter (that is, the output end of the successive approximation logic circuit 3), and the output end of the calibration circuit 2_N is connected to the input end of the comparator 1_N+1. The calibration circuit 2_N can be connected to the comparator 1_N+1 according to the multi-bit digital code D out , determining mismatch information for correcting the offset voltage of comparator 1_N+1.

[0063] In a possible implementation, the calibration circuit 2 is configured to: out Determining mismatch information includes: the calibration circuit 2 is used to determine the mismatch information according to the multi-bit digital code D out The difference between two adjacent bits of digital code, or the multi-bit digital code D out The mismatch information is determined by the difference between the one-bit digital code and the preset value (eg, 0.5). In this way, the flexibility of the offset voltage mismatch calibration between comparators is improved to be applicable to more application scenarios.

[0064] In a possible implementation, FIG10 shows a schematic diagram of a calibration circuit according to an embodiment of the present disclosure. As shown in FIG10 , the calibration circuit 2 includes a subtractor 21, an average value module 22, and a comparison module 23 connected in series. The subtractor 21 is used to determine the multi-bit digital code D out The difference between two adjacent bits of digital code, or the multi-bit digital code D out The average value module 22 is used to determine the average value of the difference; the comparison module 23 is used to determine the mismatch information D according to the comparison result of the average value and the zero value. cal .

[0065] The comparison module 23 is a logic comparator for comparing the input signal in the digital domain. The average module 22 can be a counter accumulator, which is reset according to a preset number of times (for example, M times). In this way, the average module 22 receives M differences and then performs an averaging operation on the M differences, so that the comparison module 23 generates a mismatch information D.cal It should be understood that by adjusting the size of the preset number M, the rate at which the calibration circuit 2 calibrates the offset voltage mismatch of the comparator 1 can be adjusted, wherein the larger the preset number M, the slower the calibration rate, and the smaller the preset number M, the faster the calibration rate. The embodiments of the present disclosure do not limit the specific value of the preset number M.

[0066] The calibration circuit 2 of the embodiment of the present disclosure can be applied to successive approximation analog-to-digital converter products containing multiple comparator structures, such as successive approximation analog-to-digital converters based on ping-pong comparators, loop-expanded successive approximation analog-to-digital converters, single-conversion multi-bit successive approximation analog-to-digital converters, etc., to calibrate the offset voltage mismatch between the comparators. It has extremely wide applications and can be adapted to various successive approximation analog-to-digital converter products. In addition, the calibration circuit 2 extracts the offset voltage mismatch of the comparator 1 completely in the background of the digital circuit domain, which is suitable for advanced low-voltage process implementation and has low hardware complexity and power consumption. The calibration circuit 2 does not require additional reset and comparison operations, eliminates the short-circuit switch and its control logic circuit required for reset, improves the quantization accuracy of the 1-bit successive approximation analog-to-digital converter, and the conversion rate of the successive approximation analog-to-digital converter, reduces hardware complexity, and avoids the introduction of additional non-ideal effects.

[0067] In the example, it is assumed that circuit 2_i is the i-th calibration circuit among N calibration circuits 2_1 to calibration circuit 2_N, the value range of i is [1, N], the input end of the i-th calibration circuit 2_i is connected to the output end of the successive approximation analog-to-digital converter, and the output end of the i-th calibration circuit 2_i is connected to the input end of the i+1-th comparator 1_i+1.

[0068] Optionally, the i-th calibration circuit 2_i is configured to: out The N-i+1th last bit digital code D out The difference between [N-i+1] and the preset value (e.g. 0.5) determines the mismatch information D cal [i+1], the mismatch information D cal [i+1] is used to correct the offset voltage of the i+1th comparator 1_i+1.

[0069] For example, as shown in FIG9 , when i=N, the calibration circuit 2_N can be used to calculate the multi-bit digital code D out The last digit of the code D out The difference between [1] and a preset value (e.g., 0.5) determines the mismatch information D used to calibrate the offset voltage mismatch of comparator 1_N+1. cal [N+1]. Where D out [1] This is the D mentioned above. last .

[0070] Similarly, when i=N-1, the calibration circuit 2_N-1 can be used to calibrate the multi-bit digital code D out The second to last bit of the digital code D out [2] The difference between the preset value (e.g., 0.5) determines the mismatch information D used to calibrate the offset voltage mismatch of the comparator 1_N. cal [N]. Among them, D out [2] This is the D mentioned above. last-1 .

[0071] Similarly, when i=1, the calibration circuit 2_1 can be used to calculate the value of the multi-bit digital code D out The Nth last bit digital code D out The difference between [N] and a preset value (e.g., 0.5) determines the mismatch information D used to calibrate the offset voltage mismatch of the comparator 1_2. cal [2]. Among them, D out [N] also known as D last-N+1 .

[0072] In this way, the average value of the last bit of the digital code output by the SAR ADC can be compared with a preset value (eg, 0.5) to extract information about the offset voltage mismatch between the comparators 1 .

[0073] Optionally, the i-th calibration circuit 2_i is configured to: out The N-i+1th last bit digital code D out [N-i+1] and the N-i+2th last bit digital code D out The difference between [N-i+2] determines the mismatch information D cal [i+1], the mismatch information D cal [i+1] is used to correct the offset voltage of the i+1th comparator 1_i+1.

[0074] For example, as shown in FIG9 , when i=N, the calibration circuit 2_N can be used to calculate the multi-bit digital code D out The last digit of the code D out [1] and the second to last bit digital code D out The difference between [2] determines the mismatch information D used to calibrate the offset voltage mismatch of comparator 1_N+1. cal [N+1]. Where D out [1] This is the D mentioned above. last , D out [2] This is the D mentioned above. last-1 .

[0075] Similarly, when i=N-1, the calibration circuit 2_N-1 can be used to calibrate the multi-bit digital code D out The second to last bit of the digital code D out [2] and the third-to-last bit digital code D out The difference between [3] determines the mismatch information D used to calibrate the offset voltage mismatch of the comparator 1_N. cal [N]. Among them, D out [2] This is the D mentioned above. last-1 , D out [3] That is, D last-2 .

[0076] Similarly, when i=1, the calibration circuit 2_1 can be used to calculate the value of the multi-bit digital code D out The Nth last bit digital code D out [N] and the N+1th last bit digital code D out The difference between [N+1] determines the mismatch information D used to calibrate the offset voltage mismatch of comparator 1_2. cal [2]. Among them, D out [N] also known as D last-N+1 , D out [N+1] is also D last-N .

[0077] In this way, the last two adjacent bits of the digital codes output by the successive approximation analog-to-digital converter can be compared to extract information about the offset voltage mismatch between the comparators 1, that is, the average values ​​of the digital codes output by two adjacent comparators 1 are compared, and then one of the comparators 1 is calibrated.

[0078] It should be understood that D out The value num in [num] represents the multi-bit digital code D out For example, for a successive approximation analog-to-digital converter with K-bit quantization accuracy, the output K-bit digital code D out , D out [K] is the first digit code, that is, the Kth digit code from the end; D out [K-1] is the second digit code, that is, the K-1th digit code from the end; and so on, D out [1] is the Kth digital code, that is, the last digital code. For example, for the 8-bit digital code D out =1000 0000, the last digit is D out [1] is the rightmost 0 in 1000 0000.

[0079] In the above process, whenever the successive approximation analog-to-digital converter converts the input signal V inConvert to multi-bit digital code D out When the number of times reaches the preset number M, the N calibration circuits 2_1 to 2_N simultaneously correct the offset voltages of the comparators 1 connected thereto until the offset voltages of the N+1 comparators 1_1 to 1_N+1 are equal.

[0080] FIG11 is a schematic diagram illustrating a calibration circuit according to an embodiment of the present disclosure applied to a ping-pong comparator-based successive approximation analog-to-digital converter. As shown in FIG11 , the ping-pong comparator-based successive approximation analog-to-digital converter includes a capacitive digital-to-analog converter 4, a successive approximation logic circuit 3, a calibration circuit 2_1, and two comparators 1_1 and 1_2. The input of calibration circuit 2_1 is connected to the output of the successive approximation analog-to-digital converter (i.e., the output of successive approximation logic circuit 3), and the output of calibration circuit 2_1 is connected to the input of comparator 1_2.

[0081] The capacitive DAC 4 may include a capacitor array 41 and a switch array 42. If the resolution of the SAR DAC output is an n-bit digital code, the capacitor array 41 may be composed of n capacitors arranged in binary weights (the capacitors C in FIG. 11 are shown in FIG. 11 ). LSB ~C MSB ), and the empty capacitor C LSB An array of 16 bits, where LSB represents the least significant bit, MSB represents the most significant bit, and CLK S represents the sampling clock, V refp Indicates a fixed reference voltage.

[0082] Assume that a ping-pong comparator-based successive approximation analog-to-digital converter is used to convert the input voltage V in Converted into 8-bit digital code D out In the successive approximation analog-to-digital converter based on the ping-pong comparator, the 8-bit digital code D can be converted into out The last two bits of the output digital code D8 and D7 are subtracted (where D8 represents the last digit of the code D out [1], D7 represents the penultimate digit code D out [2]), the average value of the difference is calculated by using the average module 22, and the average value of the difference between the last two bits of the output digital code D8 and D7 is compared with 0 based on the comparison module 23, thereby extracting the mismatch information D of the offset voltage between the comparator 1_2 and the comparator 1_1 cal [2], the offset voltage of comparator 1_2 is corrected.

[0083] In this way, the calibration circuit 2_1 can be used according to the 8-bit digital code D outThe distribution of the last two bits of output digital code (D7 and D8) in the output of the comparator 1_1 and the offset voltage mismatch information D between the comparator 1_2 cal [2] is extracted and the offset voltage of comparator 1_2 is corrected until the offset voltages of the two comparators are equal. Compared with the related art which requires additional reset and comparison operations, the embodiment of the present disclosure can directly replace the reset and comparison operations with a conversion that adds 1 bit of normal quantization. Its total conversion time is not only still less than that of the solution in the related art, but also, while improving the conversion rate, it can also increase the quantization accuracy of the successive approximation analog-to-digital converter by 1 bit.

[0084] In a specific application, a comparator offset voltage adjustment method can be used to correct the comparator 1_2. For example, an adjustment method based on a current pump structure can be used to adjust the comparator 1_2 in the sampling phase of the successive approximation analog-to-digital converter (see the clock signal CLK in FIG. 11). S ) to modify the comparator 1_2. In addition, the load capacitance may be changed at the integration point of the comparator 1_2 for adjustment, and the embodiments of the present disclosure are not limited thereto.

[0085] In one possible implementation, the comparator includes a comparator with a current pump structure. FIG12 shows a circuit diagram of a comparator with a current pump structure according to an embodiment of the present disclosure. As shown in FIG12 , taking the comparator 1_2 with a current pump structure in FIG11 as an example, the comparator 1_2 with a current pump structure may include a current pump, and transistors M1 to M2. 14 , wherein the transistors M1 to M3, the transistors M6 to M8 are PMOS transistors, the transistors M4, M5, M9 to M 14 It is an NMOS transistor.

[0086] As shown in FIG12 , the gate of transistor M1, the gate of transistor M3, the gate of transistor M6, the gate of transistor M7, and the gate of transistor M 11 The gate of transistor M 14 The gates are connected to the same point to receive the clock signal CLK c2 The source of transistor M1, the source of transistor M2, the source of transistor M3, the source of transistor M6, the source of transistor M7, and the source of transistor M8 are connected to the input power supply; the drain of transistor M1, the drain of transistor M2, the drain of transistor M4, the gate of transistor M8, and the gate of transistor M9 are connected to the same point; the gate of transistor M2, the gate of transistor M4, the drain of transistor M8, the drain of transistor M9, and the drain of transistor M6 are connected to the same point; the drain of transistor M3, the source of transistor M4, the drain of transistor M5, and the drain of transistor M 12The drain of transistor M7, the source of transistor M9, and the drain of transistor M 10 The drain of transistor M 13 The drain of transistor M5 is connected to the same point; the source of transistor M 10 The source of transistor M 11 The drains of transistors M are connected to the same point; 12 The source of transistor M 13 The source of transistor M 14 The drains of transistors M are connected to the same point; 11 The source of transistor M 14 The source of the transistor M5 is connected to the ground; the gate of the transistor M5 is used to receive the voltage signal V to be compared cp , transistor M 10 The gate is used to receive the voltage signal V to be compared cn , transistor M 13 The gate is used to connect a fixed voltage signal V cm , transistor M 12 The gate is used to connect an adjustable current pump.

[0087] The current pump may include switches S1 to S4, capacitor C p1 , capacitor C p2 , capacitor C cal The first end of the switch S1 is connected to the power supply, the second end of the switch S1, the first end of the switch S2, and the capacitor C p1 The first end of the switch S2, the first end of the switch S3, and the capacitor C cal The first end of the transistor M 12 The gates of the switches S3 and S4 are connected to the same point, the second end of the switch S3, the first end of the switch S4, and the capacitor C p2 The first end of the capacitor C is connected to the same point p1 The second end of the capacitor C p2 The second end of the capacitor C cal The second end of the switch S4 is connected to the ground.

[0088] Among them, in the non-sampling phase, the clock signal CLK S =0, clock signal CLK S Logical NOT signal Switches S1 and S4 are closed, switches S2 and S3 are open, and capacitor C p1 Charged to the power supply voltage, capacitor C p2 Discharge to 0. During the sampling phase, the clock signal CLK s =1, clock signal CLK S Logical NOT signal Switch S1 and switch S4 are disconnected, if the calibration circuit 2_1 feeds back the mismatch information D to the comparator 1_2 cal [2]=1, then switch S3 is closed, switch S2 is open, capacitor C cal With capacitor C p2 The charge on the capacitor C is shared. cal Part of the charge on the capacitor is distributed to the capacitor C p2 , therefore, transistor M 12 The gate voltage decreases, and the offset voltage V os2 If the mismatch information D fed back by the calibration circuit 2_1 to the comparator 1_2 cal [2] logical NOT signal Then switch S2 is closed, switch S3 is open, and capacitor C cal With capacitor C p1 The charge on the capacitor C is shared. p1 Part of the charge on the capacitor is distributed to the capacitor C cal , therefore, transistor M 12 The gate voltage increases, and the offset voltage V os2 reduce.

[0089] In this way, in addition to the gate of transistor M5 and transistor M 10 The gates of the two gates form an input pair for receiving the voltage signal V to be compared. cp And the voltage signal V cn , you can also use transistor M 12 The gate of transistor M 13 The gates of the MOSFETs form an additional input pair for receiving a fixed voltage signal V cm and an adjustable voltage from the current pump, which is determined by the mismatch information fed back by the calibration circuit 2. Providing the comparator 1 with a current pump structure is beneficial for improving the efficiency and accuracy of comparator 1 offset voltage mismatch calibration.

[0090] In summary, the embodiments of the present disclosure, based on the analogy between a successive approximation analog-to-digital converter and a negative feedback loop, find that in a successive approximation analog-to-digital converter having a plurality of comparators 1, the residual voltage at the input of the comparator 1 has different distributions due to the offset voltage mismatch between the comparators 1. Based on this, the successive approximation analog-to-digital converter can output a multi-bit digital code D out The calibration circuit 2 is used to extract the mismatch information of the offset voltage between the comparators 1, and can be applied to a successive approximation analog-to-digital converter containing multiple comparator structures, such as a successive approximation analog-to-digital converter based on a ping-pong comparator, a loop-expanded successive approximation analog-to-digital converter, a single-conversion multi-bit successive approximation analog-to-digital converter, etc., with a wide range of application scenarios.

[0091] Compared with the related art, the comparator offset voltage mismatch extraction scheme using the calibration circuit 2 of the embodiment of the present disclosure can be performed in the background of the digital circuit domain, eliminating the reset operation of the input end of the comparator 1 and the comparison operation with 0 as input, thereby improving the overall conversion rate. At the same time, it also improves the quantization accuracy of the 1-bit successive approximation analog-to-digital converter, eliminates the short-circuit switch and its control logic circuit required for the reset operation, reduces the hardware complexity, and avoids the introduction of additional non-ideal effects.

[0092] It can be understood that the above-mentioned embodiments mentioned in the present disclosure can be combined with each other to form combined embodiments without violating the principle logic. Due to space limitations, the present disclosure will not elaborate on them.

[0093] FIG13 is a flowchart of a calibration method according to an embodiment of the present disclosure. As shown in FIG13 , the calibration method is applied to an integrated circuit, the integrated circuit including: a successive approximation analog-to-digital converter having N+1 comparators, and N calibration circuits, where N is an integer greater than 1, the input of any calibration circuit being connected to the output of the successive approximation analog-to-digital converter, and the output of any calibration circuit being connected to the input of a different comparator. The calibration method includes:

[0094] In step S11, the successive approximation analog-to-digital converter converts the input signal into a multi-bit digital code;

[0095] In step S12 , the calibration circuit determines mismatch information according to the multi-bit digital code, and the mismatch information is used to correct an offset voltage of the comparator connected to the calibration circuit.

[0096] In a possible implementation, step S12 may include: the calibration circuit determining the mismatch information according to a difference between two adjacent bits of the multi-bit digital code, or a difference between one bit of the multi-bit digital code and a preset value.

[0097] In one possible implementation, the calibration circuit includes a subtractor, an average value module, and a comparison module connected in series in sequence. The calibration circuit determines the mismatch information based on the difference between two adjacent bits of digital codes in a multi-bit digital code, or the difference between one bit of digital code in the multi-bit digital code and a preset value. The calibration circuit includes: the subtractor is used to determine the difference between two adjacent bits of digital codes in the multi-bit digital code, or the difference between one bit of digital code in the multi-bit digital code and a preset value; the average value module is used to determine the average value of the difference; and the comparison module is used to determine the mismatch information based on the comparison result of the average value and a zero value.

[0098] In one possible implementation, the input end of the i-th calibration circuit is connected to the output end of the successive approximation analog-to-digital converter, the output end of the i-th calibration circuit is connected to the input end of the i+1-th comparator, and the calibration circuit determines the mismatch information based on the difference between a bit digital code in the multi-bit digital code and a preset value, including: the i-th calibration circuit determines the mismatch information based on the difference between the N-i+1th last bit digital code in the multi-bit digital code and the preset value, and the mismatch information is used to correct the offset voltage of the i+1-th comparator, where i is any integer from 1 to N.

[0099] In one possible implementation, the input end of the i-th calibration circuit is connected to the output end of the successive approximation analog-to-digital converter, the output end of the i-th calibration circuit is connected to the input end of the i+1-th comparator, and the calibration circuit determines the mismatch information based on the difference between two adjacent bits of the multi-bit digital code, including: the i-th calibration circuit determines the mismatch information based on the difference between the N-i+1th bit digital code and the N-i+2th bit digital code in the multi-bit digital code, and the mismatch information is used to correct the offset voltage of the i+1-th comparator, where i is any integer from 1 to N.

[0100] In a possible implementation, the comparator includes a comparator having a current pump structure.

[0101] In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments. For the sake of brevity, it will not be repeated here.

[0102] According to another aspect of the present disclosure, an analog-to-digital converter is provided, comprising the integrated circuit as described above.

[0103] According to another aspect of the present disclosure, a chip is provided, comprising the integrated circuit as described above.

[0104] According to another aspect of the present disclosure, an electronic device is provided, comprising the integrated circuit described above. The electronic device may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, or the like, although the present disclosure is not intended to limit this aspect.

[0105] While various embodiments of the present disclosure have been described above, the foregoing description is intended to be illustrative, non-exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or technological improvements in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. An integrated circuit, characterized in that: include: A successive approximation analog-to-digital converter having N+1 comparators and N calibration circuits, where N is an integer greater than or equal to 1, the input of any calibration circuit being connected to the output of the successive approximation analog-to-digital converter, and the output of any calibration circuit being connected to the input of a different comparator, wherein: The successive approximation analog-to-digital converter is used to convert an input signal into a multi-bit digital code; The calibration circuit is used to determine mismatch information according to the multi-bit digital code, and the mismatch information is used to correct the offset voltage of the comparator connected to the calibration circuit.

2. The integrated circuit according to claim 1, wherein: The calibration circuit is configured to determine mismatch information according to the multi-bit digital code, comprising: The calibration circuit is used to determine the mismatch information according to a difference between two adjacent bits of the multi-bit digital code, or a difference between one bit of the multi-bit digital code and a preset value.

3. The integrated circuit according to claim 1, wherein: The calibration circuit includes a subtractor, an average module, and a comparison module connected in series. The subtractor is used to determine the difference between two adjacent bits of the multi-bit digital code, or the difference between one bit of the multi-bit digital code and a preset value; The average value module is used to determine the average value of the difference; The comparison module is configured to determine the mismatch information according to a comparison result between the average value and the zero value.

4. The integrated circuit according to any one of claims 1 to 3, characterized in that The input end of the i-th calibration circuit is connected to the output end of the successive approximation analog-to-digital converter, and the output end of the i-th calibration circuit is connected to the input end of the i+1-th comparator. The i-th calibration circuit is used to determine mismatch information based on the difference between the N-i+1th last bit digital code in the multi-bit digital code and a preset value. The mismatch information is used to correct the offset voltage of the i+1-th comparator, where i is any integer between 1 and N.

5. The integrated circuit according to any one of claims 1 to 3, characterized in that The input end of the i-th calibration circuit is connected to the output end of the successive approximation analog-to-digital converter, and the output end of the i-th calibration circuit is connected to the input end of the i+1-th comparator. The i-th calibration circuit is used to determine mismatch information based on the difference between the (N-i+1)th-to-last bit digital code and the (N-i+2)th-to-last bit digital code in the multi-bit digital code. The mismatch information is used to correct the offset voltage of the (i+1)th comparator, where i is any integer between 1 and N.

6. The integrated circuit according to any one of claims 1 to 3, characterized in that The comparator includes a comparator having a current pump structure.

7. A calibration method, characterized in that: The calibration method is applied to an integrated circuit, the integrated circuit comprising: a successive approximation analog-to-digital converter having N+1 comparators, and N calibration circuits, where N is an integer greater than 1, the input of any calibration circuit being connected to the output of the successive approximation analog-to-digital converter, and the output of any calibration circuit being connected to the input of a different comparator, the calibration method comprising: The successive approximation analog-to-digital converter converts the input signal into a multi-bit digital code; The calibration circuit determines mismatch information according to the multi-bit digital code, and the mismatch information is used to correct an offset voltage of the comparator connected to the calibration circuit.

8. An analog-to-digital converter, characterized in that The analog-to-digital converter comprises an integrated circuit as claimed in any one of claims 1 to 6.

9. A chip, characterized in that: The chip comprises the integrated circuit according to any one of claims 1 to 6.

10. An electronic device, characterized in that: The electronic device comprises the integrated circuit according to any one of claims 1 to 6.

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