Compilation method, memory operation detection method, and related device

Abstract

A compilation method and a memory operation detection method, for implementing detection of illegal memory operations. In the present solution, a memory operation instruction in a code is identified in the compilation process of the code, and a corresponding stub function is inserted into the code for the memory operation instruction, so that a memory operation executed by the memory operation instruction in the code during running is captured by the stub function and is stored in a first storage space as a memory operation parameter. In this way, after the code has finished running, the memory operation executed in the running process of the code can be restored on the basis of the stored memory operation parameter, so as to facilitate the detection of an illegal memory operation. In the present solution, only parameter information related to the memory operation is captured during memory operation capture, and no additional memory space needs to be allocated to implement real-time detection, so that no additional occupancy of limited memory space is caused, reducing the amount of memory space occupied by memory detection.

Description

Compilation method, memory operation detection method and related device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on February 8, 2024, with application number 202410179636.0 and application name “A compilation method, memory operation detection method and related devices”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of computer technology, and in particular to a compilation method, a memory operation detection method, and related devices. Background Art

[0003] The application of artificial intelligence (AI) has triggered a huge demand for heterogeneous platforms, and an increasing number of chip manufacturers are beginning to venture into heterogeneous platforms. A heterogeneous platform typically refers to a computing platform that deploys a central processing unit (CPU) and an AI-specific domain-specific architecture (DSA) processor. On a heterogeneous platform, the CPU typically performs conventional logical operations, while the AI ​​DSA performs specialized AI operations.

[0004] Memory operation detection technology is an essential debugging tool in the computer field. It is also necessary to detect memory operations performed by AI DSA on heterogeneous platforms to identify any illegal memory operations that occur during the operation of the AI ​​DSA. Currently, the method for detecting illegal memory operations on heterogeneous platforms is to allocate additional shadow memory for detecting the legitimacy of memory operations while allocating memory for the operation object, thereby achieving real-time detection of the legitimacy of memory operations based on shadow memory. The size of the shadow memory is fixed in proportion to the size of the memory allocated for the operation object. For example, for every 8 bytes of memory allocated for the operation object, 1 byte of shadow memory is required.

[0005] Since the existing memory operation detection method requires additional allocation of shadow memory to detect the legitimacy of memory operations, and the size of the shadow memory is positively correlated with the memory size used for actual operations, a large amount of memory will be additionally occupied during the operation of heterogeneous platforms, resulting in a significant reduction in the memory space that can actually be used to perform AI operations on the heterogeneous platforms, affecting the efficiency of performing AI operations on the heterogeneous platforms.

[0006] Summary of the Invention

[0007] The present application provides a compilation method and a memory operation detection method, which can compile an executable file that is convenient for implementing memory operation detection, and the implementation of memory operation detection will not cause additional occupation of limited memory space, thereby reducing the amount of memory space occupied by memory detection.

[0008] In a first aspect, the present application provides a compilation method, comprising: obtaining a first code, wherein the first code includes a plurality of memory operation instructions, wherein the first code is code to be compiled, such as source code or intermediate code obtained after preliminary compilation of the source code.

[0009] Then, based on the position of a plurality of memory operations instructions in the first code, in the first code, insert a plurality of pile functions, to obtain the second code.Wherein, a plurality of pile functions are corresponding with a plurality of memory operations instructions, and a plurality of pile functions are used to capture the memory operations that a plurality of memory operations instructions are performed and the plurality of memory operations parameters captured are stored in the first storage space, and a plurality of memory operations parameters are used to restore the performed operation of a plurality of memory operations instructions.Wherein, the memory operations that the memory operations instruction is performed is the operation of pointer for internal memory, for example allocates operations such as internal memory, read-write memory.And the first storage space can be the storage space that capacity is larger and cost is lower, need not adopt high speed but the storage space with less capacity to store memory operations parameter, thereby guarantees that the storage of the memory operations parameter captured can not take up the employed high-speed storage space of program operation.

[0010] Among the present scheme, by the memory operations instruction in the identification code in the compilation process of code, and in code, insert corresponding pile function at the memory operations instruction, make the memory operations that the memory operations instruction in the code was carried out when running be captured by pile function and be stored on the first storage space with the form of memory operations parameter.Like this, after code operation is finished, can restore the memory operations carried out in the code running process based on the stored memory operations parameter, so that realize the detection of internal memory illegal operation.Owing to having just captured the parameter information that memory operations is relevant when carrying out memory operations capture among the present scheme, do not need extra allocation memory headroom to realize real-time detection, therefore can not cause additional occupancy to limited memory headroom, reduce memory detection for the occupied capacity of memory headroom.

[0011] In one possible implementation, the multiple memory operation instructions include one or more of the following instructions: a memory allocation instruction, a memory move instruction, a memory access instruction, or a memory release instruction. Each memory operation instruction in the multiple memory operation instructions uniquely corresponds to a memory operation type. Different memory operation instructions in the multiple memory operation instructions may correspond to the same memory operation type or may correspond to different memory operation types, so that the multiple memory operation instructions may include one or more different types of instructions mentioned above.

[0012] In a possible implementation, each of the multiple memory operation parameters includes a destination address of the memory operation and a type of the memory operation.

[0013] In this solution, by indicating a few simple parameters such as the type of memory operation and the address of the memory operation in the memory operation parameters, the memory operation can be well described, which facilitates the subsequent restoration of the memory operation based on the memory operation parameters and ensures that the captured memory operation parameters only occupy a small amount of storage space and do not occupy a large amount of memory space due to memory operation detection.

[0014] In one possible implementation, the target memory operation parameter among the multiple memory operation parameters also includes the execution time of the memory operation, wherein the memory operation indicated by the target memory operation parameter is an operation performed on the shared memory, and the shared memory is a memory that can be accessed by different processing cores, and different processing cores are allocated different storage space on the shared memory.

[0015] In this solution, in order to facilitate recording the order in which the processing cores execute memory operations on the shared memory and to determine whether memory trampling occurs between the processing cores on the shared memory, the execution time of the memory operations on the shared memory can be recorded in the target memory operation parameters, thereby facilitating determination of the memory operation time of each processing core on the shared memory.

[0016] In a possible implementation, before inserting pile function for the first code, can be to obtain earlier the capture instruction list, this capture instruction list is used to indicate the type of the memory operation instruction that needs to insert pile function and the insertion position of pile function.That is, the capture instruction list is equivalent to a rule file that is used to instruct compiler to insert pile function, has indicated in the capture instruction list which instructions need to insert pile function, and content and the insertion position of the pile function that need insert.

[0017] Then, based on capturing the instruction list, identify a plurality of memory operations instructions in the first code.Secondly, based on capturing the position of each memory operations instruction in the first code in the insertion position of the indicated pile function of the instruction list and a plurality of memory operations instructions, in first code, insert a corresponding pile function for each memory operations instruction.Wherein, the insertion position of the pile function that each memory operations instruction is corresponding can be the front position of memory operations instruction, also can be the back position of memory operations instruction.

[0018] In this solution, by providing a capture instruction list to guide the compiler to identify memory operation instructions in the code and insert corresponding stub functions for the memory operation instructions, the compiler can insert stub functions for the code during the compilation process without making too many changes to the existing compiler, thereby improving the feasibility of the solution.

[0019] In a possible implementation, the second code is used to compile and obtain an executable file that runs on an AI DSA of a heterogeneous platform, where the heterogeneous platform includes a CPU and an AI DSA.

[0020] In one possible implementation, the AI ​​DSA includes one or more of the following hardware: a graphics processing unit (GPU), a neural network processing unit (NPU), or a field programmable gate array (FPGA).

[0021] A second aspect of the present application provides a memory operation detection method, comprising: obtaining multiple memory operation parameters, each of the multiple memory operation parameters is used to indicate the memory operation corresponding to the memory operation instruction during execution, and the multiple memory operation parameters are obtained by capturing the memory operations performed by the multiple memory operation instructions through multiple stub functions, and the multiple stub functions and the multiple memory operation instructions are located in the same executable file.

[0022] Then, based on the multiple memory operation parameters, the memory operations performed by the multiple memory operation instructions are restored in sequence according to the execution order of the multiple memory operation instructions to detect memory violations that occur during the execution of the multiple memory operation instructions. For example, if an access operation occurs to a certain address that has not yet been allocated, it indicates that a memory violation of the type of unassigned access has occurred.

[0023] The present application provides a memory operation detection method, which captures the memory operation parameters corresponding to the memory operation performed by the memory operation instruction through the stub function in the executable file, and can restore the memory operation performed by the memory operation instruction based on the memory operation parameters after the executable file is executed, so as to facilitate offline detection of illegal memory operations occurring during the execution of the memory operation instruction. Since this solution only collects memory operation parameters when the program is running and does not perform real-time detection, but performs offline analysis based on the memory operation parameters after the program is run, there is no need to allocate additional memory space to achieve real-time detection, reducing the amount of memory space occupied by memory detection and avoiding the additional occupation of computing resources due to real-time detection of memory.

[0024] In a possible implementation, the multiple memory operation instructions include one or more of the following instructions: a memory allocation instruction, a memory move instruction, a memory access instruction, or a memory release instruction.

[0025] In one possible implementation, the multiple memory operation parameters include a destination address of the memory operation and a type of the memory operation.

[0026] In a possible implementation, the multiple memory operation parameters include memory operation parameters generated by different processing cores, and the memory operation parameters generated by different processing cores are stored in different storage areas.

[0027] The target memory operation parameter among the multiple memory operation parameters also includes the execution time of the memory operation, wherein the memory operation indicated by the target memory operation parameter is an operation performed on the shared memory, the shared memory is a memory that can be accessed by different processing cores, and different processing cores are allocated different storage space on the shared memory, and the execution time of the memory operation is used to determine the memory operation restoration order between the target memory operation parameters.

[0028] By storing the memory operation parameters generated by different processing cores in different storage spaces, the execution order of the memory operations performed by the same processing core can be determined based on the storage order of the memory operation parameters in the same storage space. However, for the memory operations performed on the shared memory by different processing cores, the execution order of these memory operations on the shared memory cannot be determined based on the storage order of the memory operation parameters. Therefore, in this solution, when the processing core executes the memory operation on the shared memory, the execution time of the memory operation can be recorded in the generated target memory operation parameters, thereby determining the order of the memory operations performed by each processing core on the shared memory.

[0029] In a possible implementation, it is assumed that a plurality of memory operation parameters include a first memory operation parameter, and the first memory operation parameter is any one of the plurality of memory operation parameters. Based on the first memory space indicated by the first memory operation parameter, the second memory space can be determined. The first memory space is the operation object of the memory operation indicated by the first memory operation parameter, that is, the first memory space is a memory space determined based on the destination address indicated in the first memory operation parameter. The second memory space is a memory space reallocated for the first memory space, and the second memory space has a corresponding relationship with the first memory space, and the second memory space is used to record the usage status of the first memory space.

[0030] Then, based on the type of memory operation indicated by the first memory operation parameter, the usage status recorded in the second memory space is updated. Wherein, any memory space can be represented by four states: unallocated state, allocated but uninitialized state, allocated and initialized state, and error state.

[0031] Furthermore, before updating the usage status recorded in the second memory space, if the memory operation indicated by the first memory operation parameter and the usage status recorded in the second memory space meet a preset condition, an illegal operation notification is generated, wherein the illegal operation notification is used to indicate that the memory operation indicated by the first memory operation parameter is an illegal memory operation.

[0032] In this solution, a reallocated memory space is used to represent the memory space used during the execution of the executable file. Memory operations are then restored in the reallocated memory space based on memory operation parameters, thereby continuously updating the memory space usage status. Thus, based on the memory space usage status and the memory operations performed on the memory space, it is possible to determine whether illegal memory operations have occurred, thereby completing the detection of illegal memory operations.

[0033] In one possible implementation, if the memory operation indicated by the first memory operation parameter is a memory access operation, and the usage status recorded in the second memory space is an unallocated state or an error state, an illegal operation notification is generated to indicate that the type of the illegal memory operation is unrequested access. That is, for a memory space in an unallocated state or an error state, if the memory operation is a memory access operation, then the memory operation can be considered to be an illegal memory operation, and the type of the illegal memory operation is unrequested access.

[0034] Alternatively, if the memory operation indicated by the first memory operation parameter is a memory access operation, and the usage status recorded in part of the memory space in the second memory space is an unallocated state, an illegal operation notification is generated to indicate that the memory illegal operation type is a memory out-of-bounds access.

[0035] In one possible implementation, if the memory operation indicated by the first memory operation parameter is a write operation of the first processing core on the shared memory, and the usage status of the second memory space is recorded based on the write operation of the second processing core on the shared memory, an illegal operation notification is generated to indicate that the type of illegal memory operation is inter-core trampling.

[0036] In this solution, for the memory space belonging to the shared memory, based on the usage status recorded on the corresponding memory space and the processing core information that triggers the recording of the usage status, it is possible to determine whether there are any illegal memory operations between cores on the actually used shared memory, thereby realizing memory operation detection on the shared memory and improving the feasibility of the solution.

[0037] In a possible implementation, the first memory space is a memory space used by the AI ​​DSA of the heterogeneous platform, and the second memory space is a memory space used by the CPU of the heterogeneous platform.

[0038] In one possible implementation, after the executable file is executed, multiple memory operation parameters may be read from the first storage space used by the AI ​​DSA of the heterogeneous platform. The multiple memory operation parameters are generated by the AI ​​DSA when running the executable file and stored in the first storage space.

[0039] A third aspect of the present application provides a compilation device, comprising: an acquisition module, used to acquire a first code, the first code including multiple memory operation instructions; a processing module, used to insert multiple stub functions into the first code based on the positions of the multiple memory operation instructions in the first code to obtain a second code, wherein the multiple stub functions are used to capture the memory operations performed by the multiple memory operation instructions and store the captured multiple memory operation parameters in a first storage space, and the multiple memory operation parameters are used to restore the memory operations performed by the multiple memory operation instructions.

[0040] In a possible implementation, the multiple memory operation instructions include one or more of the following instructions: a memory allocation instruction, a memory move instruction, a memory access instruction, or a memory release instruction.

[0041] In one possible implementation, the multiple memory operation parameters include a destination address of the memory operation and a type of the memory operation.

[0042] In one possible implementation, the target memory operation parameter among the multiple memory operation parameters also includes the execution time of the memory operation, wherein the memory operation indicated by the target memory operation parameter is an operation performed on the shared memory, and the shared memory is a memory that can be accessed by different processing cores, and different processing cores are allocated different storage space on the shared memory.

[0043] In a possible implementation, acquisition module is also used to obtain the capture instruction list, and the capture instruction list is used to indicate the type of the memory operation instruction and the insertion position of the pile function that need be inserted into the pile function; Processing module is also used to identify a plurality of memory operation instructions in the first code based on the capture instruction list; Processing module is also used to capture the position of each memory operation instruction in the first code in the insertion position of the indicated pile function of the capture instruction list and a plurality of memory operation instructions, and in the first code, inserts a corresponding pile function for each memory operation instruction.

[0044] In a possible implementation, the second code is used to compile and obtain an executable file that runs on an AI DSA of a heterogeneous platform, where the heterogeneous platform includes a central processing unit (CPU) and an AI DSA.

[0045] In one possible implementation, the AI ​​DSA includes one or more of the following hardware: GPU, NPU, or FPGA.

[0046] A fourth aspect of the present application provides a memory operation detection device, comprising: an acquisition module for acquiring multiple memory operation parameters, each of the multiple memory operation parameters is used to indicate the memory operation corresponding to the memory operation instruction during execution, and the multiple memory operation parameters are obtained by capturing the memory operations performed by the multiple memory operation instructions through multiple stub functions, and the multiple stub functions and the multiple memory operation instructions are located in the same executable file; based on the multiple memory operation parameters, the memory operations performed by the multiple memory operation instructions are restored in sequence according to the execution order of the multiple memory operation instructions to detect illegal memory operations occurring during the execution of the multiple memory operation instructions.

[0047] In a possible implementation, the multiple memory operation instructions include one or more of the following instructions: a memory allocation instruction, a memory move instruction, a memory access instruction, or a memory release instruction.

[0048] In one possible implementation, the multiple memory operation parameters include a destination address of the memory operation and a type of the memory operation.

[0049] In one possible implementation, multiple memory operation parameters include memory operation parameters generated by different processing cores, and the memory operation parameters generated by different processing cores are stored in different storage areas; the target memory operation parameter in the multiple memory operation parameters also includes the execution time of the memory operation, wherein the memory operation indicated by the target memory operation parameter is an operation performed on the shared memory, the shared memory is a memory that can be accessed by different processing cores, and different processing cores are allocated different storage space on the shared memory, and the execution time of the memory operation is used to determine the memory operation restoration order between the target memory operation parameters.

[0050] In one possible implementation, the processing module is also used to: determine the second memory space based on the first memory space indicated by the first memory operation parameter, wherein the first memory operation parameter is any one of multiple memory operation parameters, the first memory space is the operation object of the memory operation indicated by the first memory operation parameter, the second memory space has a corresponding relationship with the first memory space, and the second memory space is used to record the usage status of the first memory space; based on the type of memory operation indicated by the first memory operation parameter, update the usage status recorded in the second memory space; before updating the usage status recorded in the second memory space, if the memory operation indicated by the first memory operation parameter and the usage status recorded in the second memory space meet preset conditions, generate an illegal operation notification, and the illegal operation notification is used to indicate that the memory operation indicated by the first memory operation parameter is an illegal memory operation.

[0051] In one possible implementation, the processing module is also used to: if the memory operation indicated by the first memory operation parameter is a memory access operation, and the usage status recorded in the second memory space is an unallocated state or an error state, then generate an illegal operation notification indicating that the memory illegal operation type is an unrequested access; or, if the memory operation indicated by the first memory operation parameter is a memory access operation, and the usage status recorded in part of the memory space in the second memory space is an unallocated state, then generate an illegal operation notification indicating that the memory illegal operation type is a memory out-of-bounds access.

[0052] In one possible implementation, the processing module is also used to: if the memory operation indicated by the first memory operation parameter is a write operation of the first processing core on the shared memory, and the usage status of the second memory space is recorded based on the write operation of the second processing core on the shared memory, then generate an illegal operation notification indicating that the type of illegal memory operation is inter-core trampling.

[0053] In a possible implementation, the first memory space is a memory space used by the AI ​​DSA of the heterogeneous platform, and the second memory space is a memory space used by the CPU of the heterogeneous platform.

[0054] In one possible implementation, the acquisition module is further used to: after the executable file is executed, read multiple memory operation parameters from the first storage space used by the AI ​​DSA of the heterogeneous platform, where the multiple memory operation parameters are generated by the AI ​​DSA when running the executable file and stored in the first storage space.

[0055] In a fifth aspect, the present application provides a compilation device, which may include a processor coupled to a memory, wherein the memory stores program instructions. When the program instructions stored in the memory are executed by the processor, the method of the first aspect or any implementation of the first aspect is implemented. For details of the steps in each possible implementation of the first aspect executed by the processor, please refer to the first aspect and will not be repeated here.

[0056] In a sixth aspect, the present application provides a memory operation detection device, which may include a processor coupled to a memory, wherein the memory stores program instructions. When the program instructions stored in the memory are executed by the processor, the method of the second aspect or any implementation of the second aspect is implemented. For details of the steps in each possible implementation of the first aspect executed by the processor, please refer to the second aspect and will not be repeated here.

[0057] In a seventh aspect, the present application provides a computer-readable storage medium, in which a computer program is stored. When the computer-readable storage medium is run on a computer, the computer executes a method implemented in any one of the first and second aspects.

[0058] In an eighth aspect, the present application provides a circuit system, which includes a processing circuit, and the processing circuit is configured to execute a method implemented in any one of the first or second aspects.

[0059] In a ninth aspect, the present application provides a computer program product, which, when executed on a computer, enables the computer to execute the method implemented in any one of the first or second aspects.

[0060] In a tenth aspect, the present application provides a chip system, which includes a processor for supporting an electronic device to implement the functions involved in any implementation of the first or second aspect above, for example, processing the data and / or information involved in the above method. In one possible design, the chip system also includes a memory for storing program instructions and data necessary for the electronic device. The chip system can be composed of a chip or can include a chip and other discrete devices.

[0061] The beneficial effects of the third to tenth aspects mentioned above can be referred to the introduction of the first and second aspects mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] FIG1 is a schematic diagram of a mapping relationship between shadow memory and regular memory provided in an embodiment of the present application;

[0063] FIG2 is a schematic diagram of an application scenario provided by an embodiment of the present application;

[0064] FIG3 is a schematic diagram of an execution flow of a compilation method provided in an embodiment of the present application;

[0065] FIG4 is a flow chart of a memory operation detection method provided in an embodiment of the present application;

[0066] FIG5 is a flow chart of a core method provided in an embodiment of the present application;

[0067] FIG6 is a schematic diagram of a system architecture provided in an embodiment of the present application;

[0068] FIG7 is a schematic diagram of a heterogeneous platform provided in an embodiment of the present application;

[0069] FIG8 is a schematic diagram of a parameter storage area provided in an embodiment of the present application;

[0070] FIG9 is a schematic diagram of a memory analysis provided by an embodiment of the present application;

[0071] FIG10 is a schematic diagram of the structure of a compilation device provided in an embodiment of the present application;

[0072] FIG11 is a schematic structural diagram of a memory operation detection device provided in an embodiment of the present application;

[0073] FIG12 is a schematic structural diagram of an execution device provided in an embodiment of the present application;

[0074] FIG13 is a schematic diagram of the structure of a computer-readable storage medium provided in an embodiment of the present application. DETAILED DESCRIPTION

[0075] In order to make the purpose, technical solutions and advantages of this application more clear, the embodiments of this application are described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only embodiments of a part of this application, rather than all embodiments. It is known to those skilled in the art that with the emergence of new application scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0076] The terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the descriptions used in this way can be interchangeable where appropriate so that the embodiments can be implemented in a sequence other than that illustrated or described in this application. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or modules is not necessarily limited to those steps or modules clearly listed, but may include other steps or modules that are not clearly listed or that are inherent to these processes, methods, products or devices. The naming or numbering of steps in this application does not mean that the steps in the method flow must be executed in the time / logical sequence indicated by the naming or numbering. The named or numbered process steps can change the execution order according to the technical purpose to be achieved, as long as the same or similar technical effects can be achieved. The division of units in this application is a logical division. In actual application, there may be other division methods. For example, multiple units can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, and the indirect coupling or communication connection between units can be electrical or other similar forms, which are not limited in this application. Moreover, the units or sub-units described as separate components may or may not be physically separated, may or may not be physical units, or may be distributed into multiple circuit units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this application.

[0077] To facilitate understanding, some technical terms involved in the embodiments of this application are first introduced below.

[0078] (1) Heterogeneous platforms

[0079] A heterogeneous platform typically refers to a computing platform that is deployed with a CPU and an AI DSA. An AI DSA typically refers to a processor specifically designed to handle AI operations, such as a graphics processing unit (GPU), a neural network processing unit (NPU), or a field programmable gate array (FPGA). Generally speaking, a heterogeneous platform can also be referred to as a platform that is deployed with a CPU + xPU.

[0080] (2) Compilation

[0081] Compilation is the process of converting source code into an executable file using a compiler. Simply put, compilation converts source code written in a high-level language into binary system that computers can understand. Since computers only understand 1s and 0s, the compiler essentially converts the familiar language into binary system.

[0082] Generally speaking, the process of a compiler translating a source code into an executable file is divided into five stages: lexical analysis; syntax analysis; semantic analysis and intermediate code generation; code optimization; and target code generation.

[0083] (3) Source code

[0084] Source code is an uncompiled text file written in a specific programming language. It is a series of human-readable computer language instructions. In modern programming languages, source code can be in the form of books or tapes, but the most common format is a text file. This typical format is used to compile computer programs. The ultimate goal of computer source code is to translate human-readable text into binary instructions that can be executed by a computer. This process is called compilation and is accomplished by a compiler.

[0085] (4) Executable file

[0086] An executable file is a file that can be run directly on a computer.

[0087] (5) AI Model

[0088] An AI model is a mathematical model that learns and predicts data that exhibits certain regularities and predictability. Currently, AI models are generally constructed using neural networks. During the operation of an AI model, the computational process of learning from data is called training, and the process of predicting the results of input data is called inference.

[0089] (6) Operator

[0090] Operators are the basic computing units of AI models. Each operator represents specific computational semantics. Common operators represent computational semantics such as convolution, pooling, and activation functions.

[0091] (7) Kernel function

[0092] The kernel function is the execution entity of the operator at runtime, that is, the kernel function is actually a binary instruction code that can be directly executed on the device hardware.

[0093] (8) Bytecode

[0094] Bytecode is a binary file containing an executable program, consisting of a sequence of opcode / data pairs. Compared to machine instruction code, which can be directly executed by hardware, bytecode is actually an intermediate code—an instruction encoding that needs to be interpreted and executed by software code, and cannot be directly executed by hardware.

[0095] (9) Machine Instructions

[0096] Machine instructions are instructions that computer hardware (such as the Central Processing Unit (CPU)) can directly recognize and execute. They are represented by binary code. Machine instructions typically consist of two parts: an opcode and an operand. The opcode specifies the operation to be performed by the machine instruction, i.e., its function; the operand specifies the object involved in the operation and the location where the result of the operation is stored.

[0097] (10) Global Memory

[0098] Global memory refers to the memory space within device hardware (such as a GPU) used to store global and static variables. Variables stored in global memory can be accessed and modified by all objects running within the device hardware. In other words, global memory is shared by multiple cores and can be accessed by all processing cores within the device hardware, as well as by the host hardware.

[0099] (11) Local Memory

[0100] Local memory refers to the private memory space allocated to each processing core in the device hardware. It can only be accessed by the corresponding processor core and cannot be accessed by other processor cores.

[0101] (12) Insertion

[0102] Instrumentation involves inserting probes into the program under test while ensuring the original logical integrity of the program under test. Probes are essentially code segments that collect information, such as assignment statements or function calls that collect coverage information. The execution of probes generates characteristic data about the program's execution. This analysis of characteristic data reveals control and data flow information, and furthermore, dynamic information such as logic coverage, achieving the testing objective.

[0103] Currently, the method for detecting illegal memory operations on heterogeneous platforms is to allocate additional shadow memory for checking the legitimacy of memory operations when allocating memory for operands. This allows for real-time legitimacy detection of memory operations based on shadow memory. All operations performed on the memory allocated for operands are written to the shadow memory. This allows for a read of the shadow memory before each access to the memory allocated for the operand to confirm the legitimacy of the memory access, thus enabling memory operation detection.

[0104] For example, please refer to Figure 1, which is a schematic diagram of the mapping relationship between shadow memory and regular memory provided in an embodiment of the present application. As shown in Figure 1, the size of shadow memory is fixed in proportion to the size of regular memory allocated for the operand. Specifically, for every 8 bytes of regular memory allocated for the operand, 1 byte of shadow memory is allocated to record the availability of these 8 bytes of regular memory. Furthermore, shadow memory cannot be directly read or written by the user; the compiler must generate relevant code to access it.

[0105] Every allocation and release operation on regular memory will be written to shadow memory. Before each read or write to regular memory, shadow memory will be read to obtain the access validity of this regular memory (that is, whether the regular memory has been allocated or released).

[0106] Specifically, the shadow memory address is calculated by dividing the regular memory address by 8 and adding an offset. Because the stack is located at either end of the virtual memory address space, the shadow memory falls in the middle. If a user unexpectedly accesses the shadow memory, the shadow memory's "shadow memory" will fall into an illegal range. By verifying the legitimacy of the value recorded in the shadow memory, the access problem can be determined.

[0107] However, this method of detecting illegal memory operations requires real-time calculation of shadow memory values ​​during execution, which consumes a certain amount of processor resources and reduces the efficiency of the original program. Furthermore, the presence of shadow memory also squeezes out an additional portion of memory, reducing the memory available for the original program to allocate and use, resulting in a reduction in the original program's computational scale. AI computing is highly sensitive to both computational scale and performance, and this existing method of detecting illegal memory operations reduces AI computing efficiency.

[0108] Based on this, the present embodiment provides a kind of compilation method and memory operation detection method, by the memory operation instruction in the identification code in the compilation process of code, and in code, insert corresponding pile function at the memory operation instruction, make the memory operation that the memory operation instruction in the code is carried out when running be captured by pile function and be stored on the first storage space with the form of memory operation parameter.Like this, after code operation is finished, can restore the memory operation carried out in the code running process based on the memory operation parameter that is stored, so that realize the detection of internal memory illegal operation.Owing to having just captured the parameter information that memory operation is relevant when carrying out memory operation capture among the programme, do not need extra allocation memory headroom to realize real-time detection, therefore can not cause extra occupancy to limited memory headroom, reduce memory and detect the occupied capacity for memory headroom.

[0109] In addition, this solution only collects memory operation parameters when the program is running and does not perform real-time detection. Instead, it performs offline analysis based on the memory operation parameters after the program is finished running. Therefore, there is no need to allocate additional memory space to achieve real-time detection, which reduces the amount of memory space occupied by memory detection and avoids the additional occupation of computing resources due to real-time memory detection. Ultimately, it can effectively improve the computing scale and performance of AI computing.

[0110] For ease of understanding, the following first introduces the system architecture used by the compilation method and memory operation detection method provided in the embodiments of the present application.

[0111] Please refer to Figure 2, which is a schematic diagram of an application scenario provided by an embodiment of the present application. As shown in Figure 2, the system architecture includes a heterogeneous platform. The heterogeneous platform includes host hardware and device hardware. Among them, the host hardware includes the CPU and the memory used by the CPU; the device hardware includes the AI ​​DSA and the memory used by the AI ​​DSA. Host software, such as compilers and memory analysis tools, can be run on the host hardware. Among them, the compiler can also be executed on other devices (such as a dedicated compilation server), that is, only the memory analysis tool is run on the host hardware of the heterogeneous platform, which is not specifically limited here.

[0112] Device software can be run on the device hardware. The device software is, for example, an executable file compiled by a compiler based on the compilation method provided in this embodiment. The executable file is, for example, an operator in the AI ​​field and needs to be run using an AI DSA.

[0113] When using a compiler to compile source code, the source code can first be converted into intermediate code. Memory operation instructions in the intermediate code are then identified, and corresponding stub functions are inserted into the intermediate code for these memory operation instructions. The intermediate code is then further compiled to produce a core operator, which is essentially an executable file.

[0114] The core operator is passed to the device hardware for execution. When the device hardware runs the core operator and performs memory operations, the device hardware captures the memory operations performed by the device hardware based on the instructions of the stub function in the core operator and stores the captured memory operation parameters. In this way, the memory analysis tool running on the host hardware can obtain the memory operation parameters from the device hardware after the core operator is completed. Based on the memory operation parameters, it can restore the memory operations performed by the device hardware when running the core operator, thereby detecting illegal memory operations.

[0115] The above describes the system architecture to which the method provided in this embodiment is applied. The following describes in detail the compilation method and memory operation detection method provided in this embodiment.

[0116] Please refer to Figure 3, which is a schematic diagram of the execution flow of a compilation method provided in an embodiment of the present application. As shown in Figure 3, the compilation method provided in this embodiment includes the following steps 301-303.

[0117] Step 301: Obtain a first code, where the first code includes a plurality of memory operation instructions.

[0118] In this embodiment, the compilation method is executed by, for example, a compiler. The first code is the code to be compiled, such as source code or intermediate code obtained after preliminary compilation of the source code. The compilation method provided in this embodiment will be described below using the first code as the intermediate code as an example.

[0119] For the multiple memory operation instructions in the first code, the multiple memory operation instructions may include one or more of the following instructions: a memory allocation instruction, a memory move instruction, a memory access instruction, or a memory release instruction. Specifically, each memory operation instruction in the multiple memory operation instructions uniquely corresponds to a memory operation type. Different memory operation instructions in the multiple memory operation instructions may correspond to the same memory operation type or may correspond to different memory operation types, so that the multiple memory operation instructions may include one or more different types of instructions mentioned above.

[0120] Memory allocation instructions are instructions that allocate memory for an operand. Memory move instructions are instructions that move data from a source address to a destination address. Memory access instructions are instructions that read or write memory. Memory release instructions are instructions that release memory space.

[0121] Step 302, based on the position of a plurality of memory operations instructions in the first code, in the first code, insert a plurality of pile functions, to obtain the second code, wherein a plurality of pile functions are used to capture the executed memory operations of a plurality of memory operations instructions and the captured multiple memory operations parameters are stored in the first storage space, and a plurality of memory operations parameters are used to restore the executed operation of a plurality of memory operations instructions.

[0122] In the present embodiment, in the process that first code is compiled, can the memory operation instruction in the first code be identified, thereby identify a plurality of memory operation instructions in the first code and determine the position of each memory operation instruction in the first code.Based on the position of each memory operation instruction in the first code, can in first code, insert corresponding pile function respectively for each first code, thereby obtain inserting second code with a plurality of pile functions.

[0123] Wherein, pile function is that the memory operation parameter that will be captured is to be stored in the first storage space.The first storage space is for example the storage space in the equipment of the executable file that carries out based on the second code compile, for example large-capacity storage spaces such as memory headroom or hard disk spaces.That is, the first storage space can be the storage space that capacity is large and cost is lower, need not adopt high speed but the storage space with less capacity to store memory operation parameter, thereby guarantees that the storage of the memory operation parameter that captures can not take up the employed high-speed storage space of program operation.

[0124] Optional, can accurately identify the memory operation instruction that needs to insert pile function and for the ease of compiler and insert accurate pile function for memory operation instruction, can provide a capture instruction list to instruct compiler to carry out compilation process for compiler in the present embodiment.

[0125] Exemplarily, before inserting pile function for the first code, can be to obtain earlier the capture instruction list, this capture instruction list is used to indicate the type of the memory operation instruction that needs to insert pile function, the content of pile function and the insertion position of pile function.In simple terms, the capture instruction list is equivalent to a rule file that is used to instruct compiler to insert pile function, has indicated which instructions need to insert pile function in the capture instruction list, and content and the insertion position of the pile function that need insert.Wherein, the capture instruction list can be to be pre-placed in the compiler, also can be that compiler is provided by the user through the external interface (for example application programming interface (Application Programming Interface, API)) on the compiler, is used to instruct compiler to realize the insertion of pile function.

[0126] Based on capturing the instruction list, compiler can identify a plurality of memory operation instructions that obtain in the first code.And, based on capturing the position of each memory operation instruction in the first code in the indicated pile function of the instruction list and a plurality of memory operation instructions, compiler can be for each memory operation instruction to insert a corresponding pile function in the first code, thereby obtains second code.Wherein, the insertion position of the pile function that each memory operation instruction is corresponding can be the front position of memory operation instruction, also can be the back position of memory operation instruction.That is, pile function can be inserted before the memory operation instruction, or after the memory operation instruction, specifically can determine according to the writing situation of actual code, is not specifically limited at this.

[0127] In this solution, by providing a capture instruction list to guide the compiler to identify memory operation instructions in the code and insert corresponding stub functions for the memory operation instructions, the compiler can insert stub functions for the code during the compilation process without making too many changes to the existing compiler, thereby improving the feasibility and versatility of the solution.

[0128] In addition, for a plurality of pile functions that are inserted for a plurality of memory operations instructions, each pile function all can capture the memory operations that a corresponding memory operations instruction is carried out at runtime, thereby generates corresponding memory operations parameter.Like this, at a plurality of memory operations parameters that a plurality of pile functions are captured, each memory operations parameter in a plurality of memory operations parameters all can comprise the destination address of memory operations and the type of memory operations.For example, for the corresponding memory operations parameter of memory allocation instruction, the type that can indicate memory operations in this memory operations parameter is memory allocation, and the destination address of memory allocation (namely the address of the internal memory that needs to distribute) is address 1.

[0129] It should be noted that, when the type of the memory operation is memory move, the memory operation parameters may further include a source address of the memory operation, that is, a source address of data to be moved during the memory move.

[0130] In this solution, by indicating a few simple parameters such as the type of memory operation and the address of the memory operation in the memory operation parameters, the memory operation can be well described, which facilitates the subsequent restoration of the memory operation based on the memory operation parameters and ensures that the captured memory operation parameters only occupy a small amount of storage space and do not occupy a large amount of memory space due to memory operation detection.

[0131] Optionally, the target memory operation parameter among the multiple memory operation parameters further includes an execution time of the memory operation. The memory operation indicated by the target memory operation parameter is an operation performed on shared memory. Shared memory is memory accessible to different processing cores, and different processing cores are allocated different storage spaces on the shared memory.

[0132] Generally speaking, when executing kernel functions, device hardware uses multiple processing cores to execute the kernel function simultaneously to improve kernel computational efficiency. Each core has its own local memory, a private memory space that is inaccessible to other cores. Multiple cores also have shared memory, a global memory shared by all cores. However, different cores are typically allocated different storage spaces within shared memory to isolate them and prevent memory congestion.

[0133] Therefore, in order to facilitate recording the order in which the processing cores execute memory operations on the shared memory and to determine whether memory trampling occurs between the processing cores on the shared memory, the execution time of the memory operations on the shared memory can be recorded in the target memory operation parameters, thereby facilitating determination of the memory operation time of each processing core on the shared memory.

[0134] Furthermore, regarding the memory operations performed by a processing core on local memory, memory operations performed by the same processing core are executed sequentially, meaning that the same processing core cannot execute multiple memory operations simultaneously. Therefore, in this embodiment, the memory operations performed by each processing core on local memory can be recorded sequentially. This allows the execution order of the memory operations to be determined based on the order in which the memory operation parameters are stored, eliminating the need to record the execution time of the processing core's memory operations on local memory, thus saving storage space.

[0135] Step 303: compile the second code to obtain an executable file.

[0136] Since the second code itself is the code after inserting the stub function on the basis of source code or intermediate code, the present embodiment can continue to further compile the second code according to the existing compilation process, thereby obtaining the executable file.

[0137] Optionally, the second code may be compiled to obtain an executable file that runs on an AI DSA of a heterogeneous platform. The heterogeneous platform includes a CPU and an AI DSA. For example, the executable file is specifically a kernel function that runs on the AI ​​DSA.

[0138] Optionally, the AI ​​DSA includes one or more of the following hardware: GPU, NPU, or FPGA.

[0139] After the first code is compiled based on the above-mentioned compilation method and an executable file is obtained, the executable file can be run by the device hardware. For example, on a heterogeneous platform, the CPU assigns a computing task to the AI ​​DSA and passes the executable file corresponding to the computing task to the AI ​​DSA, which then completes the computing task by executing the executable file. When the AI ​​DSA runs the executable file, since the executable file includes a stub function corresponding to each memory operation instruction, the AI ​​DSA captures the memory operation performed when the AI ​​DSA runs the memory operation instruction by running the stub function and stores the generated memory operation parameters in the first storage space. In this way, after the executable file is executed, the memory operation detection method provided in this embodiment can be executed by obtaining the memory operation parameters in the first storage space, thereby detecting illegal memory operations.

[0140] Please refer to Figure 4, which is a flow chart of a memory operation detection method provided by an embodiment of the present application. As shown in Figure 4, the memory operation detection method includes the following steps 401-402.

[0141] Step 401, obtains multiple memory operation parameters, each memory operation parameter in multiple memory operation parameters is all used to indicate the corresponding memory operation of memory operation instruction during execution, and multiple memory operation parameters are to capture the memory operation performed by multiple memory operation instructions by multiple pile functions to obtain, and multiple pile functions and multiple memory operation instructions are located in same executable file.

[0142] Specifically, after the compiling method based on the above-described embodiment obtains executable file, in the process of executable file operation, the memory operations that the memory operations instruction in the executable file is carried out can be captured by the pile function in the operation executable file, and generate above-mentioned multiple memory operations parameters.Therefore, by obtaining a plurality of memory operations parameters generated based on executable file, the memory operations in the executable file execution process can be obtained.

[0143] For example, after the executable file is executed, the CPU can read multiple memory operation parameters from the first storage space used by the AI ​​DSA of the heterogeneous platform. These multiple memory operation parameters are generated by the AI ​​DSA when running the executable file and stored in the first storage space. In other words, on the heterogeneous platform, the AI ​​DSA runs the executable file to perform the computing task and stores the memory operation parameters captured during the execution of the computing task in the first storage space. In this way, the CPU on the heterogeneous platform executes the memory operation detection method provided in this embodiment by reading multiple memory operation parameters from the first storage space, thereby achieving offline detection of memory operations during the execution of the executable file.

[0144] Of course, when the executable file is executed by the CPU itself, the multiple memory operation parameters obtained by the CPU from executing the executable file are often stored in the memory space used by the CPU. In other words, the first memory space is the memory space used by the CPU. In this way, after the executable file is executed, the CPU retrieves the multiple memory operation parameters from the first memory space used by itself to perform memory operation detection.

[0145] Step 402 : Based on multiple memory operation parameters, the memory operations executed by the multiple memory operation instructions are restored in sequence according to the execution order of the multiple memory operation instructions to detect illegal memory operations occurring during the execution of the multiple memory operation instructions.

[0146] In this embodiment, each of the multiple memory operation parameters includes a destination address of the memory operation and the type of the memory operation. Therefore, based on the execution order of each memory operation parameter, the memory operations executed by the multiple memory operation instructions can be restored according to the execution order of the multiple memory operation instructions, thereby detecting illegal memory operations that occur during the execution of the multiple memory operation instructions. For example, if an access operation occurs to a certain address that has not yet been allocated, it indicates that an illegal memory operation of the type of unrequested access has occurred.

[0147] Optionally, the aforementioned multiple memory operation parameters include memory operation parameters generated by different processing cores, and the memory operation parameters generated by different processing cores are stored in different storage areas. Generally speaking, an AI DSA (e.g., a GPU) has multiple processing cores, which use these multiple processing cores to execute computing tasks in parallel, thereby improving the execution efficiency of computing tasks. Therefore, multiple processing cores on an AI DSA may often execute the same executable file, thereby capturing the memory operations performed by each processing core. Thus, by pre-allocating different storage areas to different processing cores, the memory operation parameters captured by different processing cores can be stored in different storage areas. Based on the storage areas of the acquired memory operation parameters, it is possible to determine which processing core generated each memory operation parameter, that is, to determine the processing core identifier corresponding to each memory operation parameter. Furthermore, in the storage area corresponding to each processing core, the memory operation parameters are stored in a certain order. The storage order corresponding to the memory operation parameters represents the order in which the memory operation parameters were generated on the same processing core, and thus represents the execution order of the memory operations.

[0148] In addition, the target memory operation parameter among the multiple memory operation parameters also includes the execution time of the memory operation. The memory operation indicated by the target memory operation parameter is an operation performed on shared memory, which is memory accessible to different processing cores, and different processing cores are allocated different storage spaces on the shared memory. The execution time of the memory operation in the target memory operation parameter is used to determine the order in which the memory operations are restored between the target memory operation parameters.

[0149] It is understandable that by storing the memory operation parameters generated by different processing cores in different storage spaces, the execution order of the memory operations performed by the same processing core can be determined based on the storage order of the memory operation parameters in the same storage space. However, for the memory operations performed on the shared memory by different processing cores, the execution order of these memory operations on the shared memory cannot be determined based on the storage order of the memory operation parameters. Therefore, in this embodiment, when the processing core executes the memory operation on the shared memory, the execution time of the memory operation can be recorded in the generated target memory operation parameters, thereby determining the order of the memory operations performed by each processing core on the shared memory.

[0150] In the implementation process, can be in the compilation process of executable file, in advance in pile function, specify when capturing the memory operations for shared memory, the execution time of record memory operations, thereby can generate above-mentioned target memory operation parameter when making follow-up executable file.Perhaps, all pile functions in executable file can specify the execution time of needs record memory operations, thereby make all memory operations parameters all carry the execution time of memory operations.

[0151] For ease of understanding, the following describes a process of restoring memory operations performed by multiple memory operation instructions, thereby detecting illegal memory operations occurring during the execution of multiple memory operation instructions.

[0152] Specifically, since the process of detecting illegal memory operations is performed after the executable file has completed execution, in this embodiment, a memory space can be reallocated to restore the memory operations that occurred during the execution of the executable file. Furthermore, the reallocated memory space corresponds to the memory space used during the execution of the executable file, that is, the memory space usage during the execution of the executable file is simulated by the reallocated memory space.

[0153] Exemplarily, assuming that a plurality of memory operation parameters include a first memory operation parameter, the first memory operation parameter is any one of the plurality of memory operation parameters. Based on the first memory space indicated by the first memory operation parameter, the second memory space can be determined. The first memory space is the operation object of the memory operation indicated by the first memory operation parameter, that is, the first memory space is a memory space determined based on the destination address indicated in the first memory operation parameter. The second memory space is a memory space reallocated for the first memory space, and the second memory space has a corresponding relationship with the first memory space, and the second memory space is used to record the usage status of the first memory space.

[0154] Then, based on the type of memory operation indicated by the first memory operation parameter, the usage status recorded in the second memory space can be updated. Specifically, for any memory space, four states can be used to represent it, namely: unallocated state, allocated but uninitialized state, allocated and initialized state, and error state. Among them, the initial state of each memory space is unallocated state. If the usage status recorded in the second memory space is the unallocated state, and the type of memory operation indicated by the first memory operation parameter is a memory allocation operation, the usage status recorded in the second memory space can be updated to the allocated but uninitialized state; if the usage status recorded in the second memory space is the allocated but uninitialized state, and the type of memory operation indicated by the first memory operation parameter is a memory write operation, the usage status recorded in the second memory space can be updated to the allocated and initialized state.

[0155] It should be noted that before updating the usage status recorded in the second memory space, if the memory operation indicated by the first memory operation parameter and the usage status recorded in the second memory space meet a preset condition, an illegal operation notification is generated. The illegal operation notification is used to indicate that the memory operation indicated by the first memory operation parameter is an illegal memory operation.

[0156] In other words, in this embodiment, for each memory operation parameter, a corresponding memory space is first located, and the usage status recorded in the located memory space is determined, thereby determining whether the memory operation indicated by the current memory operation parameter is legal under the usage status. If the memory operation indicated by the current memory operation parameter is illegal under the usage status, an illegal operation notification may be generated.

[0157] It is understood that when a memory space is in a specific state, if a memory operation occurs with respect to the memory space that is not permitted under the state it is in, the memory operation with respect to the memory space can be considered an illegal memory operation. Therefore, if the memory operation indicated by the first memory operation parameter and the usage status recorded by the second memory space meet a preset condition, the memory operation indicated by the first memory operation parameter can be considered an illegal memory operation.

[0158] In this solution, a reallocated memory space is used to represent the memory space used during the execution of the executable file. Memory operations are then restored in the reallocated memory space based on memory operation parameters, thereby continuously updating the memory space usage status. Thus, based on the memory space usage status and the memory operations performed on the memory space, it is possible to determine whether illegal memory operations have occurred, thereby completing the detection of illegal memory operations.

[0159] Exemplarily, if the memory operation indicated by the first memory operation parameter is a memory access operation, and the usage status recorded in the second memory space is an unallocated state or an error state, an illegal operation notification is generated indicating that the type of the illegal memory operation is unrequested access. That is, for a memory space in an unallocated state or an error state, if the memory operation is a memory access operation, then the memory operation can be considered to be an illegal memory operation, and the type of the illegal memory operation is unrequested access.

[0160] Alternatively, if the memory operation indicated by the first memory operation parameter is a memory access operation, and the usage status recorded in part of the memory space in the second memory space is an unallocated state, an illegal operation notification is generated to indicate that the memory illegal operation type is a memory out-of-bounds access.

[0161] Alternatively, if the memory operation indicated by the first memory operation parameter is a memory move operation or a computing-type memory access operation (for example, writing the calculated data to the memory), the first address detection can also be performed on the destination address indicated by the first memory operation parameter according to the access alignment requirement of the memory slice. If the destination address indicated by the first memory operation parameter does not meet the access alignment requirement, an address misalignment access error is reported. For example, assuming that the access alignment requirement of the memory slice is based on 32 bytes as the basis for dividing the memory slice, then if the first address of the destination address indicated by the first memory operation parameter is not a multiple of 32 (such as 0, 32, 64, etc.), it can be considered that it does not meet the access alignment requirement, and an address misalignment access error is reported.

[0162] The above are some possible examples for detecting illegal memory operations. In actual applications, other illegal memory operations may be detected based on the usage status of the memory space and the memory operation detection of the memory space, which is not specifically limited here.

[0163] Optionally, in some embodiments, if the memory operation indicated by the first memory operation parameter is a write operation of the first processing core on the shared memory, and the usage status of the second memory space is recorded based on the write operation of the second processing core on the shared memory, an illegal operation notification is generated to indicate that the type of illegal memory operation is inter-core trampling.

[0164] That is to say, for the memory space on the shared memory, if the memory space has been written by a processing core, and data is subsequently written to the memory space by another processing core, it means that there is an illegal memory operation between cores in the memory space.

[0165] In this embodiment, for the memory space belonging to the shared memory, based on the usage status recorded on the corresponding memory space and the processing core information that triggers the recording of the usage status, it can be determined whether there are any illegal memory operations between cores on the actually used shared memory, thereby realizing memory operation detection on the shared memory and improving the feasibility of the solution.

[0166] Optionally, the first memory space is, for example, the memory space used by the AI ​​DSA of the heterogeneous platform, and the second memory space is the memory space used by the CPU of the heterogeneous platform. In other words, a corresponding memory space can be established on the CPU side for the memory space used by the AI ​​DSA when executing the executable file, thereby establishing a mapping relationship between the memory space used to restore illegal memory operations and the memory space of the actual operation, ensuring that after the executable file is executed, another memory space can be used to implement offline detection of illegal memory operations.

[0167] To facilitate understanding, the joint execution process of the compilation method and the memory operation detection method provided in this embodiment will be described in detail below with reference to specific examples.

[0168] Please refer to Figure 5, which is a flowchart of a core method provided in an embodiment of the present application. As shown in Figure 5, the core method provided in this embodiment includes the following steps 501-504.

[0169] Step 501: The compiler compiles source code and inserts a stub function for capturing memory operations during the compilation of the source code to compile and obtain an executable file.

[0170] Wherein, can be after source code is compiled into intermediate code in the present embodiment, in intermediate code, insert the pile function that is used to capture memory operation again, finally compile intermediate code and obtain executable file.Also can be directly to insert pile function in source code, finally compile and obtain executable file in the present embodiment.

[0171] Step 502: Run the executable file, capture the memory operations performed by the executable file during the running process, and store the captured memory operation parameters in a designated storage space.

[0172] Because comprise memory operation instruction and pile function simultaneously in the executable file, therefore when running the executable file, can carry out memory operation instruction wherein and pile function accordingly, thereby capture the memory operation that the executable file is carried out in running process.And the memory operation parameter that captures can be stored on the storage space (i.e. above-mentioned first storage space) of appointment, for example memory space or the hard disk space that AI DSA uses.

[0173] Step 503: After the executable file is finished running, the memory operation parameters stored in the designated storage space are read and passed to the memory analysis tool for offline analysis.

[0174] For example, the executable file can be executed by the AI ​​DSA on the heterogeneous platform, and the CPU on the heterogeneous platform can read the memory operation parameters from the specified storage space after the AI ​​DSA completes executing the executable file, so that the memory analysis tool can realize offline detection of memory operations.

[0175] Step 504: The memory analysis tool establishes a dynamic analysis model based on the number of processing cores used when the executable file is running, and analyzes illegal memory operations.

[0176] Specifically, since each processing core has its own private memory (i.e., local memory), the memory analysis tool can establish a corresponding dynamic analysis model for each processing core based on the number of processing cores used when the executable file is running, thereby detecting illegal memory operations.

[0177] Can consult Fig. 6, the schematic diagram of a kind of system architecture that Fig. 6 provides for embodiment of the application.As shown in Figure 6, comprise compiler and memory analysis tool in the system architecture.Wherein, compiler is used for compiling and obtains the executable file that comprises pile function.Memory analysis tool then obtains the memory operation parameter that executable file generates during operation, and restores memory operation based on memory operation parameter, realizes the off-line detection of illegal operation of internal memory.

[0178] In the compiler, newly-added memory detection option, by opening the memory detection option, can enable the compiler to carry out inserting piles to the code that needs to compile, promptly inserts the pile function that is used to capture memory operation.Also newly-added pile inserting module in the compiler, be used for in the code compiling process, for the memory operation instruction in the code inserts corresponding pile function, thereby captures memory operation instruction by pile function when executing corresponding memory operation.In addition, also newly-added a mark function in the compiler, after the memory detection option is opened, can insert mark attribute for the executable file of generation, thereby mark in this executable file to insert pile function, need to carry out memory illegal detection.

[0179] The executable file includes a host-side stub function and a device-side stub function. The host-side stub function is used to trigger the host-side CPU to apply for a storage space on the device side for storing memory operation parameters. That is, the CPU will notify the device-side AI DSA to allocate a storage space for storing memory operation parameters based on the host-side stub function. The device-side stub function is used to capture memory operations that occur during the execution of the executable file and store the captured memory operation parameters in a specific storage space.

[0180] The memory analysis tool includes an information collection module, an information parsing module, a memory operation parameter analysis module, an anomaly detection module, and a result output module. The information collection module is used to collect stub information from the host and device sides into the detection process. The information parsing module is used to parse the memory space header information, verify the version number, etc., to implement the parsing of the collected stub information. The memory operation parameter analysis module is used to analyze the collected memory operation parameters and update the usage status recorded in the memory space. The anomaly detection module is used to screen out abnormal memory operation behaviors based on the process executed by the memory operation parameter analysis module and detect illegal memory operations. The result output module is used to output illegal memory operations.

[0181] Please refer to Figure 7, which is a schematic diagram of a heterogeneous platform provided in an embodiment of the present application. As shown in Figure 7, the heterogeneous platform includes a CPU and an NPU. The CPU and the NPU are in a master-slave relationship, also known as the host side and the device side. There is a memory space that is commonly accessed between the CPU and the NPU. In addition, the memory used by the host-side CPU is usually called host memory, such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR). The memory used by the device-side NPU is usually called device memory, such as High Bandwidth Memory (HBM).

[0182] In addition, the device side usually has multiple levels of memory, including unified buffer (UB), L1, L0A, L0B, L0C, etc. Access to these memory areas may result in illegal operations, which is the memory space to be detected by the method involved in this embodiment.

[0183] Specifically, during the code compilation process, the compiler can implement the following multiple functions.

[0184] Function 1, address space derivation.

[0185] When compiling an executable file, the memory application of any memory slice of a chip with a multi-level memory architecture (such as the NPU shown in Figure 7) is automatically mapped to a slice identifier through the address space attribute, so that the identifier of the corresponding memory slice can be automatically obtained according to the space attribute when accessing the memory.

[0186] Function 2, multi-level memory allocation.

[0187] When compiling code, the compiler identifies memory allocation instructions and allocates objects without allocating additional marker memory. The compiler then obtains the starting address and size of the allocated memory. Furthermore, the compiler provides a secure allocation interface for low-cost memory space, allowing customization of the starting address and size based on chip characteristics. This low-cost memory space is used to store subsequently captured memory operation parameters.

[0188] Function 3: Encapsulation of memory operation instructions.

[0189] During the compilation process, memory move and access instructions are shielded from hardware differences, retaining the source and destination address starting addresses and configuration parameters. The source and destination address starting addresses can be obtained using function 2, and the address spaces to which the source and destination addresses belong can be obtained using function 1. Configuration parameters require the ability to calculate the length of the source and destination addresses for memory operations.

[0190] Function 4: Capture of memory operation instructions.

[0191] Compiler can obtain the capture instruction list that preset capture instruction list or the target capture instruction interface provide when compiling, and inserts corresponding position according to the described insertion position of capture instruction the pile function that will capture memory operation.Like this, executable file is at runtime, and pile function can capture the parameter information in the memory operation instruction, and obtains the address space of the internal memory that memory operation instruction operates, and the processing core mark that current memory operation instruction is carried out.Wherein, pile function is stored in the memory headroom of appointment with the parameter information that captures at runtime.In addition, pile function is at runtime according to whether the address space analysis of the internal memory that memory operation instruction operates is the operation to shared memory; If so, then catch the execution time of this memory operation instruction simultaneously.

[0192] Function 5: Management of memory operation logs.

[0193] Through the secure allocation interface for low-cost memory space provided by function 2 above, a specified memory space is allocated within the low-cost memory space, and the first address of the specified memory space is passed to the AI ​​DSA. During runtime, the AI ​​DSA allocates a specified memory space based on the configuration of the secure allocation interface and divides it into equal parts based on the number of processing cores in use. Memory operation parameters generated by different processing cores are written to the corresponding segments, eliminating competition between the segments.

[0194] Function 6, target capture command interface design.

[0195] The target capture instruction interface can be used for providing compiler with outside capture instruction list.Wherein, the capture instruction list can be provided by user or manufacturer, and the capture instruction list content comprises: need insert the attribute description of the type of the instruction of pile function, pile function insertion position and whether capture contents such as execution time.

[0196] In general, taking the heterogeneous platform shown in Figure 7 as an example, when the compiler compiles the executable file executed on the NPU side, if the compiler turns on the memory detection function, a stub function is inserted before or after the memory operation instruction in the intermediate code when compiling the intermediate code, and a memory detection-related flag bit is added to the final compiled executable file to indicate that the executable file supports memory detection.

[0197] In this way, after obtaining an executable file, the CPU on a heterogeneous platform can check whether the executable file contains a memory detection flag. If the executable file contains a memory detection flag, the CPU allocates a specified amount of memory space on the low-cost memory used by the NPU based on the number of processing cores on the NPU. The specified memory space is evenly distributed across multiple processing cores.

[0198] The CPU then serializes the allocated memory space's starting address and length into a string and passes it as a parameter to the NPU. Each processing core in the NPU stores its allocated memory space in a reserved stack within the core. The CPU also passes the executable file to the NPU, instructing it to execute the executable file to perform the computation.

[0199] For example, please refer to Figure 8, which is a schematic diagram of a parameter storage area provided in an embodiment of the present application. As shown in Figure 8, when the NPU has N processing cores, each processing core will be allocated a 32-megabyte (MB) parameter storage area for storing the memory operation parameters obtained by the processing core. In addition, each processing core will store the first address and length information of the parameter storage area on its own reserved stack to facilitate determining the location of the parameter storage area. In addition, each processing core will have multiple memory slices, namely a unified buffer (UB), an L1 memory slice, an L0A memory slice, an L0B memory slice, and an L0C memory slice.

[0200] During the execution of the executable file, the NPU stores the memory operation parameters captured by the stub function one by one in the allocated memory space, so as to facilitate subsequent memory analysis based on these memory operation parameters.

[0201] The above introduces the compilation process of the executable file. The following will continue to introduce the process of memory violation detection.

[0202] First, the CPU retrieves the memory operation parameters from the device. Specifically, a listening stub is inserted at the end of the executable file, so when the executable terminates, the CPU can detect the end of the executable. When the CPU detects the end of the executable, it copies the memory operation parameters from the device-specified memory space to the memory used by the CPU. Before the executable runs, the CPU can obtain the total size of each memory slice on the processing core, as well as the total size of shared memory.

[0203] During device-side on-chip memory detection, the CPU establishes a separate detection model for the memory operation parameters of each processing core. Specifically, the CPU creates a mapped memory of the same size and corresponding to the on-chip memory of the device-side processing core in the host memory, and records the mapping relationship between the first address of the mapped memory and the first address of the detected memory. The last two bits of each byte in the mapped memory represent the status of the byte of memory on the detected memory. That is, the mapped memory uses two bits to record the usage status of the byte of memory on the detected memory. There are four memory usage states: unallocated, allocated but uninitialized, allocated and initialized, and error. When the value of the two bits is 0, the usage state is unallocated; when the value of the two bits is 1, the usage state is allocated but uninitialized; when the value of the two bits is 2, the usage state is allocated and initialized; and when the value of the two bits is 3, the usage state is error. Of course, the size ratio between the mapped memory and the detected memory can also be other ratios, such as 2:8, and is not specifically limited here.

[0204] According to the storage order of the memory operation parameters, the memory operation parameters of each processing core are analyzed in turn. Specifically, if the memory operation indicated by the memory operation parameter is a memory allocation operation, the location of the corresponding mapped memory is found according to the mapping relationship and the status is updated to allocated but not initialized. If the memory operation indicated by the memory operation parameter is a memory access operation, according to the destination address indicated by the memory operation parameter, the status of the mapped memory corresponding to the detected memory is checked to be legal before the usage status of the mapped memory is updated. If it is detected that all the mapped memory is unallocated or in an error state, the erroneous memory address information is recorded and an unrequested access error is reported; if it is detected that part of the mapped memory is unallocated, a memory out-of-bounds access error is reported; if it is detected that the mapped memory is in an allocated but uninitialized state, a warning is reported.

[0205] For memory movement instructions and computing-type memory access instructions, while performing mapped memory status detection, the first address must also be detected according to the access alignment requirements of the memory segment. If the access alignment requirements are not met, an address misalignment access error is reported.

[0206] Similarly, during the device-side shared memory detection process, a dynamic proportional analysis model is established based on the number of processing cores running the executable file. Taking 64 processing cores as an example, each 1 Byte of mapped memory corresponds to 1 Byte of physical memory on the device. The first 6 bits of the mapped memory 1 Byte indicate which processing core is operating the shared memory space, and the last 2 bits indicate the status of the 1 Byte of shared memory space. There are four shared memory usage states: unallocated, allocated but uninitialized, allocated and initialized, and error. Furthermore, shared memory is divided into 64 KB blocks, and a mapping relationship is established between the mapped memory and the device-side shared memory. During the specific analysis, instructions are sorted based on their execution time. The destination address and processing core identifier in the memory operation parameters are sequentially analyzed, and the mapped memory status is updated to determine the access validity. If the processing core of the current write operation to the same shared memory address is different from the processing core of the previous write operation, an inter-core stampede alarm is issued. If a read or write access exceeds the bounds or a read or write operation is performed when it is not allowed, a read or write exception error is reported.

[0207] For example, please refer to FIG9 , which is a schematic diagram of a memory analysis provided by an embodiment of the present application. As shown in FIG9 , in step S1, for the device memory to be detected, a corresponding piece of memory can be pre-divided on the host memory, thereby establishing a mapping relationship between the device memory to be detected and the host memory. Among them, the memory on the host memory corresponding to the device memory to be detected can be called mapped memory, and the mapped memory is used to record the usage status of the corresponding device memory. Among them, the device memory is divided according to 64KB, and each 64KB is divided into one block; in this way, the mapped memory is also divided in the same way as the device memory, thereby obtaining mapped memory block M0, mapped memory block M1...mapped memory block Mn.

[0208] In step S2, based on the destination address indicated by the memory operation parameter and the type of memory operation, the usage status recorded in the mapped memory block is updated. Specifically, based on the memory operation parameter, it can be known that the memory operation instruction is a memory allocation instruction (0x0=mall0c(2)), and the destination address of the memory allocation is the first 2B. Therefore, based on the memory operation parameter, the usage status recorded in the first 2B of the mapped memory block M0 can be updated to 1, that is, allocated but not initialized.

[0209] In step S3, based on step S2, the usage status recorded in the mapped memory block is updated based on the destination address indicated by the memory operation parameter and the type of memory operation. Specifically, based on the next memory operation parameter, it can be seen that the memory operation instruction is a memory write instruction (store (0x0, 2) core id = 2), and the destination address of the memory access is the first 2B. Therefore, based on the memory operation parameter, the usage status recorded in the first 2B in the mapped memory block M0 can be updated to 2, that is, the allocated and initialized state.

[0210] In step S4, on the basis of step S3, the usage status recorded in the mapped memory block is updated based on the destination address indicated by the memory operation parameter and the type of memory operation. Specifically, based on the two subsequent memory operation parameters, it can be known that the following two memory operation instructions are a memory allocation instruction (0x10000=malloc(65536)), and a memory move instruction (memcpy(0x10000,0x0,2) core id=2). Therefore, based on the two memory operation parameters, the usage status recorded in all bytes in the mapped memory block M1 can be updated to 1, that is, an allocated but uninitialized state; and then the usage status recorded in the first 2B of the mapped memory block M1 can be updated to 2, that is, an allocated and initialized state.

[0211] The above describes in detail the method provided by the embodiment of the present application. Next, the device provided by the embodiment of the present application for executing the above method will be introduced.

[0212] Refer to Figure 10, which is a structural diagram of a compiling device provided by an embodiment of the present application. As shown in Figure 10, a compiling device provided by an embodiment of the present application includes: an acquisition module 1001, which is used to obtain a first code, wherein the first code includes a plurality of memory operation instructions; a processing module 1002, which is used to insert a plurality of stub functions into the first code based on the positions of the plurality of memory operation instructions in the first code to obtain a second code, wherein the plurality of stub functions are used to capture the memory operations performed by the plurality of memory operation instructions and store the captured plurality of memory operation parameters in a first storage space, and the plurality of memory operation parameters are used to restore the memory operations performed by the plurality of memory operation instructions.

[0213] In a possible implementation, the multiple memory operation instructions include one or more of the following instructions: a memory allocation instruction, a memory move instruction, a memory access instruction, or a memory release instruction.

[0214] In one possible implementation, the multiple memory operation parameters include a destination address of the memory operation and a type of the memory operation.

[0215] In one possible implementation, the target memory operation parameter among the multiple memory operation parameters also includes the execution time of the memory operation, wherein the memory operation indicated by the target memory operation parameter is an operation performed on the shared memory, and the shared memory is a memory that can be accessed by different processing cores, and different processing cores are allocated different storage space on the shared memory.

[0216] In a possible implementation, acquisition module 1001 is also used to obtain the capture instruction list, and the capture instruction list is used to indicate the type of the memory operation instruction and the insertion position of the pile function that need insert pile function; Processing module 1002 is also used for identifying a plurality of memory operation instructions in the first code based on the capture instruction list; Processing module 1002 is also used for the position of each memory operation instruction in the first code based on the insertion position of the indicated pile function of the capture instruction list and a plurality of memory operation instructions, and in the first code, inserts a corresponding pile function for each memory operation instruction.

[0217] In a possible implementation, the second code is used to compile and obtain an executable file that runs on an AI DSA of a heterogeneous platform, where the heterogeneous platform includes a central processing unit (CPU) and an AI DSA.

[0218] In one possible implementation, the AI ​​DSA includes one or more of the following hardware: GPU, NPU, or FPGA.

[0219] Refer to Figure 11, which is a schematic diagram of the structure of a memory operation detection device provided by an embodiment of the present application. As shown in Figure 11, the memory operation detection device provided by an embodiment of the present application includes: an acquisition module 1101, which is used to obtain multiple memory operation parameters, each of the multiple memory operation parameters is used to indicate the memory operation corresponding to the memory operation instruction during execution, and the multiple memory operation parameters are obtained by capturing the memory operations performed by the multiple memory operation instructions through multiple stub functions, and the multiple stub functions and the multiple memory operation instructions are located in the same executable file; based on the multiple memory operation parameters, the memory operations performed by the multiple memory operation instructions are restored in sequence according to the execution order of the multiple memory operation instructions to detect memory illegal operations that occur during the execution of the multiple memory operation instructions.

[0220] In a possible implementation, the multiple memory operation instructions include one or more of the following instructions: a memory allocation instruction, a memory move instruction, a memory access instruction, or a memory release instruction.

[0221] In one possible implementation, the multiple memory operation parameters include a destination address of the memory operation and a type of the memory operation.

[0222] In one possible implementation, multiple memory operation parameters include memory operation parameters generated by different processing cores, and the memory operation parameters generated by different processing cores are stored in different storage areas; the target memory operation parameter in the multiple memory operation parameters also includes the execution time of the memory operation, wherein the memory operation indicated by the target memory operation parameter is an operation performed on the shared memory, the shared memory is a memory that can be accessed by different processing cores, and different processing cores are allocated different storage space on the shared memory, and the execution time of the memory operation is used to determine the memory operation restoration order between the target memory operation parameters.

[0223] In one possible implementation, the processing module 1102 is also used to: determine the second memory space based on the first memory space indicated by the first memory operation parameter, wherein the first memory operation parameter is any one of multiple memory operation parameters, the first memory space is the operation object of the memory operation indicated by the first memory operation parameter, the second memory space has a corresponding relationship with the first memory space, and the second memory space is used to record the usage status of the first memory space; based on the type of memory operation indicated by the first memory operation parameter, update the usage status recorded in the second memory space; before updating the usage status recorded in the second memory space, if the memory operation indicated by the first memory operation parameter and the usage status recorded in the second memory space meet preset conditions, generate an illegal operation notification, and the illegal operation notification is used to indicate that the memory operation indicated by the first memory operation parameter is an illegal memory operation.

[0224] In one possible implementation, the processing module 1102 is further used to: if the memory operation indicated by the first memory operation parameter is a memory access operation, and the usage status recorded in the second memory space is an unallocated state or an error state, then generate an illegal operation notification indicating that the memory illegal operation type is an unrequested access; or, if the memory operation indicated by the first memory operation parameter is a memory access operation, and the usage status recorded in part of the memory space in the second memory space is an unallocated state, then generate an illegal operation notification indicating that the memory illegal operation type is a memory out-of-bounds access.

[0225] In one possible implementation, the processing module 1102 is further used to: if the memory operation indicated by the first memory operation parameter is a write operation of the first processing core on the shared memory, and the usage status of the second memory space is recorded based on the write operation of the second processing core on the shared memory, then generate an illegal operation notification indicating that the type of illegal memory operation is inter-core trampling.

[0226] In a possible implementation, the first memory space is a memory space used by the AI ​​DSA of the heterogeneous platform, and the second memory space is a memory space used by the CPU of the heterogeneous platform.

[0227] In one possible implementation, the acquisition module 1101 is further used to: after the executable file is executed, read multiple memory operation parameters from the first storage space used by the AI ​​DSA of the heterogeneous platform, where the multiple memory operation parameters are generated by the AI ​​DSA when running the executable file and stored in the first storage space.

[0228] Please refer to Figure 12, which is a structural diagram of an execution device provided in an embodiment of the present application. As shown in Figure 12, the execution device 1200 is used to execute the compilation method or memory operation detection method introduced in the above embodiment, and the execution device 1200 can be specifically expressed as a server, which is not limited here. Specifically, the execution device 1200 includes: a receiver 1201, a transmitter 1202, a processor 1203 and a memory 1204 (wherein the number of processors 1203 in the execution device 1200 can be one or more, and Figure 12 takes one processor as an example), wherein the processor 1203 may include an application processor 12031 and a communication processor 12032. In some embodiments of the present application, the receiver 1201, the transmitter 1202, the processor 1203 and the memory 1204 may be connected via a bus or other means.

[0229] The memory 1204 may include a read-only memory and a random access memory, and provides instructions and data to the processor 1203. A portion of the memory 1204 may also include non-volatile random access memory (NVRAM). The memory 1204 stores processor and operation instructions, executable modules, or data structures, or subsets or extended sets thereof. The operation instructions may include various operation instructions for implementing various operations.

[0230] Processor 1203 controls the operation of the execution device. In specific applications, the various components of the execution device are coupled together via a bus system. In addition to a data bus, the bus system may also include a power bus, a control bus, and a status signal bus. However, for clarity, all bus systems are referred to as a bus system in the figure.

[0231] The method disclosed in the above embodiment of the present application can be applied to the processor 1203, or implemented by the processor 1203. The processor 1203 can be an integrated circuit chip with signal processing capabilities. During the implementation process, each step of the above method can be completed by an integrated logic circuit of the hardware in the processor 1203 or an instruction in the form of software. The above-mentioned processor 1203 can be a general-purpose processor, a digital signal processor (digital signal processing, DSP), a microprocessor or a microcontroller, and can further include an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.

[0232] The processor 1203 can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present application. A general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the embodiments of the present application can be directly embodied as being executed by a hardware decoding processor, or can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium mature in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory 1204, and the processor 1203 reads the information in the memory 1204 and completes the steps of the above method in combination with its hardware.

[0233] Receiver 1201 can be used to receive input digital or character information and generate signal input related to executing device-related settings and function control. Transmitter 1202 can be used to output digital or character information through the first interface. Transmitter 1202 can also be used to send instructions to the disk group through the first interface to modify data in the disk group. Transmitter 1202 can also include a display device such as a display screen.

[0234] The execution device provided in the embodiments of the present application may specifically be a chip, which includes: a processing unit and a communication unit. The processing unit may be, for example, a processor, and the communication unit may be, for example, an input / output interface, a pin, or a circuit. The processing unit may execute computer-executable instructions stored in the storage unit so that the chip in the execution device executes the method described in the above embodiment. Optionally, the storage unit is a storage unit in the chip, such as a register, a cache, etc. The storage unit may also be a storage unit located outside the chip in the wireless access device, such as a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM), etc.

[0235] Please refer to Figure 13, which is a schematic diagram of the structure of a computer-readable storage medium provided in an embodiment of the present application. The present application also provides a computer-readable storage medium. In some embodiments, the method disclosed in Figures 3 or 4 above can be implemented as computer program instructions encoded in a machine-readable format on a computer-readable storage medium or on other non-transitory media or products.

[0236] 13 schematically illustrates a conceptual partial view of an example computer-readable storage medium including a computer program for executing a computer process on a computing device, arranged in accordance with at least some embodiments presented herein.

[0237] In one embodiment, computer readable storage medium 1300 is provided using signal bearing medium 1301. Signal bearing medium 1301 may include one or more program instructions 1302 that, when executed by one or more processors, may provide the functionality or portions of the functionality described above with respect to FIG. 3 or FIG.

[0238] In some examples, signal bearing medium 1301 may include computer readable medium 1303 such as, but not limited to, a hard drive, compact disk (CD), digital video disk (DVD), digital tape, memory, ROM or RAM, and the like.

[0239] In some embodiments, the signal-bearing medium 1301 may include a computer-recordable medium 1304, such as, but not limited to, a memory, a read / write (R / W) CD, a R / W DVD, or the like. In some embodiments, the signal-bearing medium 1301 may include a communication medium 1305, such as, but not limited to, a digital and / or analog communication medium (e.g., a fiber optic cable, a waveguide, a wired communication link, a wireless communication link, or the like). Thus, for example, the signal-bearing medium 1301 may be communicated via a wireless form of the communication medium 1305 (e.g., a wireless communication medium conforming to the IEEE 802.X standard or other transmission protocol).

[0240] The one or more program instructions 1302 may be, for example, computer-executable instructions or logic-implemented instructions. In some examples, the computing device may be configured to provide various operations, functions, or actions in response to the program instructions 1302 communicated to the computing device via one or more of computer-readable media 1303, computer-recordable media 1304, and / or communication media 1305.

[0241] It should also be noted that the device embodiments described above are merely illustrative, in which the units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment. In addition, in the drawings of the device embodiments provided in this application, the connection relationship between the modules indicates that there is a communication connection between them, which can be specifically implemented as one or more communication buses or signal lines.

[0242] Through the description of the above embodiments, those skilled in the art can clearly understand that the present application can be implemented by means of software plus necessary general hardware, and of course can also be implemented by special hardware including application-specific integrated circuits, special CPUs, special memories, special components, etc. In general, all functions performed by computer programs can be easily implemented with corresponding hardware, and the specific hardware structures used to implement the same function can also be various, such as analog circuits, digital circuits or special circuits, etc. However, for the present application, software program implementation is a better implementation method in most cases. Based on such an understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a readable storage medium, such as a computer's floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk or optical disk, etc., and includes a number of instructions to enable a computer device (which can be a personal computer, training equipment, or network equipment, etc.) to execute the methods of each embodiment of the present application.

[0243] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware, or any combination thereof. When implemented by software, all or part of the embodiments may be implemented in the form of a computer program product.

[0244] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, training equipment or data center to another website, computer, training equipment or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that a computer can store or a data storage device such as a training equipment, data center, etc. that includes one or more available media integrations. Available media can be magnetic media, (e.g., floppy disk, hard disk, tape), optical media (e.g., DVD), or semiconductor media (e.g., solid-state drive (SSD)), etc.

Claims

1. A compilation method, characterized in that: include: Obtaining a first code, where the first code includes a plurality of memory operation instructions; Based on the position of described multiple memory operations instructions in described first code, in described first code, insert multiple pile functions, to obtain second code, wherein said multiple pile functions are used to capture the performed memory operations of described multiple memory operations instructions and the multiple memory operations parameters captured are stored in the first storage space, and described multiple memory operations parameters are used to restore the performed operation of described multiple memory operations instructions.

2. The method according to claim 1, characterized in that The multiple memory operation instructions include one or more of the following instructions: a memory allocation instruction, a memory move instruction, a memory access instruction, or a memory release instruction.

3. The method according to claim 1 or 2, characterized in that The multiple memory operation parameters include a destination address of the memory operation and a type of the memory operation.

4. The method according to any one of claims 1 to 3, characterized in that The target memory operation parameter among the multiple memory operation parameters also includes the execution time of the memory operation, wherein the memory operation indicated by the target memory operation parameter is an operation performed on the shared memory, and the shared memory is a memory that can be accessed by different processing cores, and the different processing cores are allocated different storage spaces on the shared memory.

5. The method according to any one of claims 1 to 4, characterized in that The method further comprises: Obtain capture instruction list, described capture instruction list is used to indicate the type of the memory operation instruction that needs to insert pile function and the insertion position of pile function; The method of inserting a plurality of stub functions into the first code based on the positions of the plurality of memory operation instructions in the first code comprises: Based on the captured instruction list, identifying the plurality of memory operation instructions in the first code; Based on the insertion position of the pile function indicated by the capture instruction list and the position of each memory operation instruction in the first code in the multiple memory operation instructions, a corresponding pile function is inserted for each memory operation instruction in the first code.

6. The method according to any one of claims 1 to 5, characterized in that The second code is used to compile an executable file that runs on an artificial intelligence AI dedicated domain architecture processor DSA on a heterogeneous platform, and the heterogeneous platform includes a central processing unit CPU and the AIDSA.

7. The method according to claim 6, characterized in that The AIDSA includes one or more of the following hardware: a graphics processor GPU, a neural network processor NPU or a field programmable gate array FPGA.

8. A memory operation detection method, characterized in that: include: Obtain multiple memory operation parameters, each memory operation parameter in the described multiple memory operation parameters is all used for indicating the corresponding memory operation of memory operation instruction during execution, and described multiple memory operation parameters are to capture the memory operation that multiple memory operation instruction is carried out by multiple pile functions to obtain, and described multiple pile functions and described multiple memory operation instruction are positioned in same executable file; Based on the multiple memory operation parameters, the memory operations executed by the multiple memory operation instructions are restored in sequence according to the execution order of the multiple memory operation instructions to detect illegal memory operations occurring during the execution of the multiple memory operation instructions.

9. The method according to claim 8, characterized in that The multiple memory operation instructions include one or more of the following instructions: a memory allocation instruction, a memory move instruction, a memory access instruction, or a memory release instruction.

10. The method according to claim 8 or 9, characterized in that The multiple memory operation parameters include a destination address of the memory operation and a type of the memory operation.

11. The method according to any one of claims 8 to 10, characterized in that: The multiple memory operation parameters include memory operation parameters generated by different processing cores, and the memory operation parameters generated by different processing cores are stored in different storage areas; The target memory operation parameter among the multiple memory operation parameters also includes the execution time of the memory operation, wherein the memory operation indicated by the target memory operation parameter is an operation performed on the shared memory, the shared memory is a memory that can be accessed by different processing cores, and the different processing cores are allocated different storage spaces on the shared memory, and the execution time of the memory operation is used to determine the memory operation restoration order between the target memory operation parameters.

12. The method according to any one of claims 8 to 11, characterized in that: The step of sequentially restoring the memory operations executed by the plurality of memory operation instructions based on the plurality of memory operation parameters includes: Determining a second memory space based on a first memory space indicated by a first memory operation parameter, wherein the first memory operation parameter is any one of the multiple memory operation parameters, the first memory space is an operation object of the memory operation indicated by the first memory operation parameter, the second memory space has a corresponding relationship with the first memory space, and the second memory space is used to record a usage status of the first memory space; Based on the type of memory operation indicated by the first memory operation parameter, updating the usage status recorded in the second memory space; Before updating the usage status recorded in the second memory space, if the memory operation indicated by the first memory operation parameter and the usage status recorded in the second memory space meet the preset conditions, an illegal operation notification is generated, and the illegal operation notification is used to indicate that the memory operation indicated by the first memory operation parameter is an illegal memory operation.

13. The method according to claim 12, characterized in that If the memory operation indicated by the first memory operation parameter and the usage status recorded in the second memory space meet a preset condition, generating an illegal operation notification includes: If the memory operation indicated by the first memory operation parameter is a memory access operation, and the usage status recorded in the second memory space is an unallocated state or an error state, generating an illegal operation notification indicating that the type of the illegal memory operation is an unrequested access; Alternatively, if the memory operation indicated by the first memory operation parameter is a memory access operation, and the usage status recorded in part of the memory space in the second memory space is an unallocated state, an illegal operation notification is generated to indicate that the memory illegal operation type is a memory out-of-bounds access.

14. The method according to claim 12 or 13, characterized in that If the memory operation indicated by the first memory operation parameter and the usage status recorded in the second memory space meet a preset condition, generating an illegal operation notification includes: If the memory operation indicated by the first memory operation parameter is a write operation of the first processing core on the shared memory, and the usage status of the second memory space is recorded based on the write operation of the second processing core on the shared memory, an illegal operation notification is generated to indicate that the type of the memory illegal operation is inter-core trampling.

15. The method according to any one of claims 12 to 14, characterized in that: The first memory space is a memory space used by AIDSA of the heterogeneous platform, and the second memory space is a memory space used by the CPU of the heterogeneous platform.

16. The method according to any one of claims 8 to 15, characterized in that: The obtaining of multiple memory operation parameters includes: After the executable file is executed, the plurality of memory operation parameters are read from the first storage space used by AIDSA of the heterogeneous platform, wherein the plurality of memory operation parameters are generated by AIDSA when running the executable file and stored in the first storage space.

17. A compiling device, characterized in that: include: An acquisition module, configured to acquire a first code, wherein the first code includes a plurality of memory operation instructions; Processing module, be used for the position based on described multiple memory operations instruction in described first code, in described first code, insert multiple pile functions, to obtain second code, wherein said multiple pile functions are used to capture the memory operations that described multiple memory operations instruction performs and the multiple memory operations parameters that capture are stored in the first storage space, and described multiple memory operations parameters are used to restore the performed operation of described multiple memory operations instruction.

18. The device according to claim 17, characterized in that The multiple memory operation instructions include one or more of the following instructions: a memory allocation instruction, a memory move instruction, a memory access instruction, or a memory release instruction.

19. The device according to claim 17 or 18, characterized in that The multiple memory operation parameters include a destination address of the memory operation and a type of the memory operation.

20. The device according to any one of claims 17 to 19, characterized in that The target memory operation parameter among the multiple memory operation parameters also includes the execution time of the memory operation, wherein the memory operation indicated by the target memory operation parameter is an operation performed on the shared memory, and the shared memory is a memory that can be accessed by different processing cores, and the different processing cores are allocated different storage spaces on the shared memory.

21. The device according to any one of claims 17 to 20, characterized in that Described acquisition module is also used to obtain capture instruction list, and described capture instruction list is used to indicate the type of the memory operation instruction that needs to insert pile function and the insertion position of pile function; The processing module is further configured to identify the plurality of memory operation instructions in the first code based on the captured instruction list; Described processing module is also used for the position of each memory operation instruction in described first code in the insertion position of the indicated pile function of described capture instruction list and described multiple memory operation instructions, and in described first code, is that described each memory operation instruction inserts a corresponding pile function.

22. A memory operation detection device, characterized in that: include: Acquisition module is used to obtain a plurality of memory operation parameters, each memory operation parameter in the described a plurality of memory operation parameters is all used to indicate the corresponding memory operation of memory operation instruction during execution, and described a plurality of memory operation parameters are to capture the memory operation that a plurality of memory operation instruction is carried out by a plurality of pile functions to obtain, and described a plurality of pile functions and described a plurality of memory operation instruction are positioned in same executable file; Based on the multiple memory operation parameters, the memory operations executed by the multiple memory operation instructions are restored in sequence to detect illegal memory operations occurring during the execution of the multiple memory operation instructions.

23. The device according to claim 22, characterized in that The processing module is further configured to: Determining a second memory space based on a first memory space indicated by a first memory operation parameter, wherein the first memory operation parameter is any one of the multiple memory operation parameters, the first memory space is an operation object of the memory operation indicated by the first memory operation parameter, the second memory space has a corresponding relationship with the first memory space, and the second memory space is used to record a usage status of the first memory space; Based on the type of memory operation indicated by the first memory operation parameter, updating the usage status recorded in the second memory space; Before updating the usage status recorded in the second memory space, if the memory operation indicated by the first memory operation parameter and the usage status recorded in the second memory space meet the preset conditions, an illegal operation notification is generated, and the illegal operation notification is used to indicate that the memory operation indicated by the first memory operation parameter is an illegal memory operation.

24. The device according to claim 23, characterized in that The processing module is further configured to: If the memory operation indicated by the first memory operation parameter is a memory access operation, and the usage status recorded in the second memory space is an unallocated state or an error state, generating an illegal operation notification indicating that the type of the illegal memory operation is an unrequested access; Alternatively, if the memory operation indicated by the first memory operation parameter is a memory access operation, and the usage status recorded in part of the memory space in the second memory space is an unallocated state, an illegal operation notification is generated to indicate that the memory illegal operation type is a memory out-of-bounds access.

25. The device according to claim 23 or 24, characterized in that The processing module is further configured to: If the memory operation indicated by the first memory operation parameter is a write operation of the first processing core on the shared memory, and the usage status of the second memory space is recorded based on the write operation of the second processing core on the shared memory, an illegal operation notification is generated to indicate that the type of the memory illegal operation is inter-core trampling.

26. A compiling device, characterized in that: The device comprises a memory and a processor; the memory stores codes, the processor is configured to execute the codes, and when the codes are executed, the device executes the method according to any one of claims 1 to 7.

27. A memory operation detection device, characterized in that: The device comprises a memory and a processor; the memory stores codes, and the processor is configured to execute the codes. When the codes are executed, the device executes the method according to any one of claims 8 to 16.

28. A computer storage medium, characterized in that The computer storage medium stores instructions, which, when executed by a computer, cause the computer to implement the method according to any one of claims 1 to 16.

29. A computer program product, characterized in that The computer program product stores instructions, which, when executed by a computer, cause the computer to implement the method according to any one of claims 1 to 16.

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