Data processing method and related apparatus

Abstract

A data processing method. The method comprises: acquiring a target logical address; on the basis of the target logical address and a target index, determining a target hash table corresponding to the target logical address, wherein the target index indicates mapping relationships between logical addresses and hash tables, the target hash table indicates mapping relationships between the logical addresses and physical addresses, and different hash tables indicated by the target index comprise logical addresses of different ranges; and on the basis of the target hash table, determining a target physical address corresponding to the target logical address. The present application reduces time overheads compared to a solution that only uses index information, and reduces computational overheads compared to an address mapping solution that only uses hash tables, thereby achieving a balance between time overheads and computational overheads.

Description

A data processing method and related device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on February 7, 2024, with application number 202410176404.X and application name “A data processing method and related devices”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of communication technology, and specifically to a data processing method and related devices. Background Art

[0003] The flash translation layer (FTL) is a key component in solid-state drives (SSDs). Its primary responsibility is to translate logical addresses visible to the host into physical addresses accessible to the SSD. This significantly impacts the SSD's read and write performance, load balancing, and lifespan.

[0004] In the existing technology, the physical address is directly confirmed through index information (for example, the logical address is input as the key value and the physical address is output as the value). Although the calculation overhead of the index information is less than that of the scheme that only uses a hash table for physical address mapping (no complex hash operation is required), when the number of logical addresses is large, the address mapping process through index information requires a large time overhead.

[0005] Summary of the Invention

[0006] The present application provides a data processing method that reduces time overhead compared to a solution that only uses index information, and reduces computational overhead compared to an address mapping solution that only uses a hash table, thereby achieving a balance between time overhead and computational overhead.

[0007] In a first aspect, the present application provides a data processing method, comprising: obtaining a target logical address; determining a target hash table corresponding to the target logical address based on the target logical address and a target index, wherein the target index indicates a mapping relationship between the logical address and the hash table, and the target hash table indicates a mapping relationship between the logical address and the physical address, and different hash tables indicated by the target index include logical addresses in different ranges; and determining a target physical address corresponding to the target logical address based on the target hash table.

[0008] In the existing technology, the physical address is directly confirmed through index information (for example, the logical address is input as the key value and the physical address is output as the value). Although the computational overhead of the index information is less than that of the scheme that only uses a hash table for physical address mapping (no complex hash operation is required), however, when the number of logical addresses is large, the address mapping process through index information requires a large time overhead. In the embodiment of the present application, the index information does not need to map the logical address to the physical address, but is mapped to the hash table corresponding to the logical address, which reduces the time overhead. Different hash tables maintain different logical addresses, which is equivalent to splitting a large hash table into small hash tables, thereby reducing the computational overhead. In other words, the embodiment of the present application reduces the time overhead compared to the scheme that only uses index information, and reduces the computational overhead compared to the address mapping scheme that only uses a hash table, thereby achieving a balance between time overhead and computational overhead.

[0009] In a possible implementation, the target hash table indicates that there is a unique correspondence between the logical address and the physical address.

[0010] A perfect hash table ensures that each existing address mapping pair uniquely occupies a position in the index array, resulting in a storage efficiency advantage over both three-level page tables and traditional hash tables. While the metadata in a perfect hash table incurs some additional space overhead, appropriate compression algorithms can reduce the storage space occupied, making the space overhead negligible compared to the space saved by the index data.

[0011] In one possible implementation, the target index is stored in the memory of a computing device, and the target hash table is stored in a host. The computing device is different from the host, and the computing device also includes a network processor; determining the target hash table corresponding to the target logical address based on the target logical address and the target index includes: the computing device determines the target hash table corresponding to the target logical address by accessing the target index in the memory based on the target logical address; determining the target physical address corresponding to the target logical address based on the target hash table includes: the computing device determines the target physical address corresponding to the target logical address based on the target hash table through communication with the host.

[0012] In an embodiment of the present application, the target index can be stored in the memory of a computing device. The computing device can be a device including a network processor. The computing device is different from the host. For example, it can be a DPU, a programmable switch, a router and other network computing devices. The target hash table is stored in the host (for example, the host's DMA buffer); the computing device can determine the target hash table corresponding to the target logical address by accessing the target index in the memory according to the target logical address; the computing device can determine the target physical address corresponding to the target logical address according to the target hash table through communication with the host.

[0013] In some scenarios, such as the DPU, the host has more storage resources, while the DPU has more parallel computing resources. Index information is stored in the DPU, which performs relevant processing on the index information. The hash table is stored in the host. The DPU communicates with the host to use the hash table to determine the relevant processing for the physical address, allowing the host to fully utilize its storage resources and be responsible for storing and maintaining the hash table and actual index data. To fully utilize the DPU's computing resources, a space-efficient learned index is loaded into the DPU's memory space, reducing the number of communications between the DPU and the host. Each microkernel requires only a minimal amount of memory to complete tasks such as using the learned index to infer the hash table location, decompressing the hash table metadata, and performing hash table calculations. Due to the large number of DPU microkernels and their independent stack space, the system can achieve extremely high parallelism in calculating FTL index locations, allowing a single DPU to simultaneously handle a large number of data access requests.

[0014] In one possible implementation, the target index includes multiple segments; accessing the target index in the memory includes: sending a first request to the memory, the first request indicating reading data of a first segment among the multiple segments; when performing an operation based on the data of the first segment, sending a second request to the memory, the second request indicating reading data of a second segment in the target index.

[0015] The DPU processor needs to access the memory to obtain data from multiple segments and perform operations (the process of determining the logical address range including the segment of the target logical address from multiple segments). Due to the limited reading bandwidth, it can often only access the data of a small part of the segment at a time. Therefore, multiple accesses are required, and in each access process, the DPU processor needs to send a data acquisition request to the memory. After that, it takes a certain amount of time to move the data from the memory to the DPU's internal data stack to perform operations. If you wait for the operation execution process to be completed before continuing to obtain other parts of the segment, it will result in a large time overhead (equivalent to the data reading and operation being performed serially, and the time overhead is the sum of the two). In order to speed up the above process, in the embodiment of the present application, a part of the segment data can be read first, and then a data acquisition request can be sent to the memory while performing the operation on this part of the segment data. While performing data operations, data is also being moved from the memory to the DPU's internal data stack, thereby reducing the overall time overhead.

[0016] In a possible implementation, the data of the first segment includes floating-point numbers, and the operation includes: quantizing the floating-point numbers into integer data, and performing the operation based on the integer data.

[0017] In a possible implementation, determining the target physical address corresponding to the target logical address according to the target hash table includes: determining a storage location of the target physical address where the target logical address is located according to the target hash table, and obtaining the target physical address from the storage location.

[0018] In a possible implementation, the target index is a learning index, which includes a multi-level index, each level of index includes at least one segment, and each segment included in the last level of index of the multi-level index corresponds to a hash table.

[0019] In one possible implementation, the method further includes: receiving update information, the update information being used to indicate an update of a mapping relationship between a logical address and a physical address; the logical address to be updated indicated by the update information belongs to a range of logical addresses included in the target hash table; and updating the target hash table according to the update information.

[0020] Specifically, when the modification information for the mapping relationship between the logical address and the physical address is obtained, a local update can be performed. The so-called local update means that only the hash table is updated, and the target index table is not updated. The reason is that: no matter whether the modification operation is editing, deleting or adding, the logical address included in the information to be modified is often within the range of logical addresses already maintained in the target index table. The logical address in the modification information can always be mapped to a hash table. Therefore, even if the target index table is not updated, it will not affect the correctness of the address conversion. In this case, only a local update is required.

[0021] In a possible implementation, when the target hash table is updated, the target hash table does not meet the first preset condition; when the target hash table is updated, the target hash table meets the first preset condition.

[0022] In one possible implementation, when updating the target hash table, the target hash table does not satisfy the first preset condition (for example, it is in a locked state, more specifically, all the values ​​in the hash table are set to preset fixed values). In this case, when accessing the hash table, it can be known that it is in an updated state and can be re-accessed (for example, re-accessed after waiting for a certain period of time). That is, when it is determined by accessing the target hash table that the target hash table does not satisfy the first preset condition, the target hash table is re-accessed until it is determined by accessing the target hash table that the target hash table satisfies the first preset condition, the storage location of the target physical address where the target logical address is located is determined, and the target physical address is obtained from the storage location.

[0023] In one possible implementation, the target index is a multi-layer index, which includes the last layer segment and an internal segment. The method also includes: based on the currently included logical address, calculating multiple hash tables including the target hash table; determining the error constraint according to the multiple hash tables, and obtaining the target index according to the error constraint; wherein the first parameter is the error constraint of the last layer segment, and the first parameter is the maximum error constraint that can minimize the logical address range contained in the root segment; or, the first parameter is the error constraint of the internal segment, and the first parameter is the minimum error constraint that can prevent the level of the internal segment from increasing.

[0024] In a possible implementation, when calculating the target index table, the target index table does not satisfy the second preset condition; when calculating the target index table, the target index table satisfies the second preset condition.

[0025] In one possible implementation, determining the target hash table corresponding to the target logical address based on the logical address and the target index includes: when it is determined by accessing the target index table that the target index table does not meet the second preset condition, re-accessing the target index table after a waiting period of time until it is determined by accessing the target index table that the target index table meets the second preset condition, and determining the target hash table corresponding to the target logical address based on the logical address and the target index.

[0026] In one possible implementation, when calculating the index table (for example, during a global update), multiple hash tables including the target hash table can be calculated based on the currently included logical addresses, and the error constraint can be determined based on the multiple hash tables, and the target index can be obtained based on the error constraint; wherein, the first parameter is the error constraint of the last layer segment, and the first parameter is the maximum error constraint that can minimize the logical address range contained in the root segment; or, the first parameter is the error constraint of the internal segment, and the first parameter is the minimum error constraint that can prevent the level of the internal segment from increasing.

[0027] For example, when the agreed time is reached, which is often a relatively idle time for the system, the host starts to perform a global update by issuing instructions to the DPU to modify the root segment, indicating that the entire index is locked. After that, all query operations of the DPU are suspended, and all data in the Table Array are reordered according to the key. According to the construction time constraint, the largest epsilon is found to minimize the number of leaf segments. The found epsilon is used to build all leaf segments, including the PTHash and sharding the Table Array. On top of the leaf segment, the smallest epsilon_recursive is found according to the layer number constraint of the inner segment to minimize the error constraint of the inner segment. The found epsilon_recursive is used to iteratively build the inner segment, and the new inner segment is sent to the DPU's memory storage, indicating that the entire index is unlocked and the response to the DPU query is restored.

[0028] The index structure proposed in the embodiment of the present application can dynamically adjust the index structure according to the storage capacity of the multi-core DPU, thereby achieving better performance while adapting to the resource constraints of different architectures and scenarios.

[0029] In a second aspect, the present application provides a data processing device, comprising:

[0030] An acquisition module is used to obtain a target logical address;

[0031] A processing module is used to determine a target hash table corresponding to the target logical address based on the target logical address and the target index, wherein the target index indicates a mapping relationship between the logical address and the hash table, the target hash table indicates a mapping relationship between the logical address and the physical address, and different hash tables indicated by the target index include logical addresses in different ranges; and determine a target physical address corresponding to the target logical address based on the target hash table.

[0032] In a possible implementation, the target hash table indicates that there is a unique correspondence between the logical address and the physical address.

[0033] In one possible implementation, the target index is stored in a memory of a computing device, the target hash table is stored in a host, the computing device and the host are different, and the computing device further includes a network processor;

[0034] The processing module is specifically used to:

[0035] The computing device determines, according to the target logical address, a target hash table corresponding to the target logical address by accessing a target index in the memory;

[0036] The computing device determines the target physical address corresponding to the target logical address according to the target hash table through communication with the host.

[0037] In a possible implementation, the computing device is a DPU, a programmable switch, or a router.

[0038] In a possible implementation, the target index is a learned index, and the target index includes multiple segments; the processing module is specifically configured to:

[0039] Sending a first request to the memory, where the first request indicates reading data of a first segment among the multiple segments;

[0040] When performing an operation based on the data of the first segment, a second request is sent to the memory, where the second request indicates to read the data of the second segment in the target index.

[0041] In a possible implementation, the data of the first segment includes floating-point numbers, and the processing module is specifically configured to:

[0042] The floating-point number is quantized into integer data, and calculation is performed based on the integer data.

[0043] In a possible implementation, the processing module is specifically configured to:

[0044] According to the target hash table, a storage location of a target physical address where the target logical address is located is determined, and the target physical address is obtained from the storage location.

[0045] In a possible implementation, the target index is a learning index, which includes a multi-level index, each level of index includes at least one segment, and each segment included in the last level of index of the multi-level index corresponds to a hash table.

[0046] In a possible implementation, the processing module is specifically configured to:

[0047] When it is determined by accessing the target hash table that the target hash table does not satisfy the first preset condition, the target hash table is re-accessed until it is determined by accessing the target hash table that the target hash table satisfies the first preset condition, a storage location of the target physical address where the target logical address is located is determined, and the target physical address is obtained from the storage location.

[0048] In a possible implementation, the processing module is further configured to:

[0049] receiving update information, the update information being used to indicate an update of a mapping relationship between a logical address and a physical address; the logical address to be updated indicated by the update information belongs to a range of logical addresses included in the target hash table;

[0050] The target hash table is updated according to the update information.

[0051] In a possible implementation, when the target hash table is updated, the target hash table does not meet the first preset condition; when the target hash table is updated, the target hash table meets the first preset condition.

[0052] In a possible implementation, the processing module is specifically configured to:

[0053] When it is determined by accessing the target index table that the target index table does not meet the second preset condition, the target index table is re-accessed after a waiting period of time until it is determined by accessing the target index table that the target index table meets the second preset condition, and the target hash table corresponding to the target logical address is determined according to the logical address and the target index.

[0054] In a possible implementation, the target index is a multi-layer index including a last layer segment and an internal segment. The processing module is further configured to:

[0055] Based on the currently included logical addresses, a plurality of hash tables including the target hash table are calculated;

[0056] Determine an error constraint based on the multiple hash tables, and obtain the target index based on the error constraint; wherein,

[0057] The first parameter is the error constraint of the last layer segment, and the first parameter is the maximum error constraint that can minimize the logical address range included in the root segment; or

[0058] The first parameter is an error constraint of an internal segment, and the first parameter is a minimum error constraint that enables the level of the internal segment not to increase.

[0059] In a possible implementation, when calculating the target index table, the target index table does not satisfy the second preset condition; when calculating the target index table, the target index table satisfies the second preset condition.

[0060] In a third aspect, an embodiment of the present application provides a data processing device, which may include a memory, a processor, and a bus system, wherein the memory is used to store programs, and the processor is used to execute the programs in the memory to perform the first aspect and any optional method thereof.

[0061] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, in which a computer program is stored. When the computer-readable storage medium is run on a computer, the computer executes the above-mentioned first aspect and any optional method thereof.

[0062] In a fifth aspect, an embodiment of the present application provides a computer program, which, when executed on a computer, enables the computer to execute the above-mentioned first aspect and any optional method thereof.

[0063] In a sixth aspect, the present application provides a chip system comprising a processor configured to support the execution of a data processing device to implement the functions described in the aforementioned aspects, such as transmitting or processing the data or information described in the aforementioned methods. In one possible design, the chip system further comprises a memory configured to store program instructions and data necessary for executing the device or training the device. The chip system may consist of a single chip or may include a chip and other discrete components. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Figures 1 to 3 are schematic diagrams of the application system framework of the present invention;

[0065] FIG4 is a flowchart of a data processing method provided in an embodiment of the present application;

[0066] FIG5 is a schematic diagram of an application system framework provided in an embodiment of the present application;

[0067] FIG6 is a schematic diagram of a data processing method provided in an embodiment of the present application;

[0068] FIG7 is a schematic diagram of an application system framework provided in an embodiment of the present application;

[0069] FIG8 is a schematic diagram of a calculation provided in an embodiment of the present application;

[0070] FIG9 is a schematic diagram of a calculation provided in an embodiment of the present application;

[0071] FIG10 is a schematic diagram of a calculation provided in an embodiment of the present application;

[0072] FIG11 is a schematic structural diagram of a data processing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0073] The following describes the embodiments of the present invention in conjunction with the accompanying drawings. The terms used in the embodiments of the present invention are only used to explain the specific embodiments of the present invention, and are not intended to limit the present invention.

[0074] The embodiments of the present application are described below in conjunction with the accompanying drawings. Those skilled in the art will appreciate that, with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0075] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, and this is merely a way of distinguishing the objects of the same attributes when describing them in the embodiments of the present application. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, so that the process, method, system, product or equipment comprising a series of units need not be limited to those units, but may include other units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0076] As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation, not as terms of degree, and are intended to take into account the inherent variations in measurements or calculations that one of ordinary skill in the art would recognize. Furthermore, the use of "may" when describing embodiments of the present invention refers to "one or more possible embodiments." As used herein, the terms "use," "using," and "used" may be considered synonymous with the terms "utilize," "utilizing," and "utilized," respectively. Additionally, the term "exemplary" is intended to refer to an example or illustration.

[0077] First, some terms involved in this application are introduced:

[0078] (1) The flash translation layer (FTL) is a key component in SSDs. Its main responsibility is to translate logical addresses visible to the host into physical addresses accessible to the SSD. It has a significant impact on SSD read / write performance, load balancing, and lifespan. Typically, FTL implementations remain transparent to the host and applications, and are managed and maintained by the SSD's controller and DRAM cache. However, this approach has certain problems. On the one hand, the FTL algorithms integrated into SSDs are usually designed for general use and are limited to fixed computing and storage resources, which imposes limitations on the scalability of their performance. On the other hand, the emergence of large-scale computing and storage models has introduced complex I / O patterns, placing higher demands on SSD performance. In response, host-side FTL solutions (Host-Target FTL) have come into view to fully utilize the potential of flash chips. In this case, the host-side FTL is paired with the flash chip array, and the chip array is directly managed by the host. The business can adjust the FTL algorithm and structure according to the data load and demand, thereby ensuring excellent performance and meeting the strict requirements for extremely low latency. Most existing FTL structures are based on simple page tables and learned indexes, which cannot meet the high space utilization and high response time requirements of host-side FTL.

[0079] (2) As a new type of heterogeneous accelerator, the data processing unit (DPU) is usually used to accelerate network packet processing, data preprocessing near the data side, and other tasks. It has high-performance network processing capabilities and can achieve a processing speed of hundreds of gigabytes of network packets in data-intensive scenarios such as data centers and computing centers. This is due to its dedicated hardware accelerator, powerful data parallel processing capabilities, and flexible programmability. In recent years, related research and technology fields are gradually exploring and practicing the wider and deeper application of DPU in data centers.

[0080] (3) A perfect hash table is a special hash table that is designed to resolve the collision problem of traditional hash tables. In a perfect hash table, each key can be uniquely mapped to a location in the hash table, which is superior to traditional hash tables in terms of query time. The implementation principle of a perfect hash table is to build an "internal hash function" inside each bucket based on the traditional hash table so that the keys in the same bucket can be mapped to different locations again. Therefore, the perfect hash table consumes additional computing time and storage space during construction to ensure that the position of each key in the same bucket and between different buckets will not conflict. It should be noted that the construction time of a perfect hash table may increase exponentially with the number of keys.

[0081] (4) A learned index is a new type of index structure. Unlike traditional index structures, it uses machine learning techniques to learn from data distribution and construct an index. The construction of a learned index often includes an additional step of model training, which trains a machine learning model, such as a regression model, based on selected features to predict the location of a specified key. After the model training is completed, the index can insert the key into the predicted location or search for the specified key from the predicted location. Compared with traditional index structures, it has greater potential in terms of storage space and query time. It should be noted that model predictions often have errors, and different learned indexes will adopt different measures to tolerate errors. In addition, the computational cost of model training and the cost of model updates are also challenges that learned indexes often encounter in use.

[0082] The embodiments of the present application can be applied to a communication system. The communication system may include a host and a computing device independent of the host. The computing device may include a network processor. The computing device may be a DPU, a programmable switch, a router, or other network computing device. The present application does not limit the specific type of computing device.

[0083] For the convenience of description, the following description takes the computing device as a DPU as an example.

[0084] FIG1 is a diagram of the system architecture involved in a data processing method provided in an embodiment of the present application. Referring to FIG1 , the system includes a host 101 and a DPU 102. A communication connection is established between the host 101 and the DPU 102. Communication between the host 101 and the DPU 102 can comply with a block protocol (i.e., a protocol related to block devices). In other words, the DPU 102 reports to the host 101 as a block device.

[0085] The host 101 is configured to obtain and output a block protocol command. Optionally, the host 101 is configured to output the block protocol command to the DPU 102. Exemplarily, the host is configured to obtain a data access command initiated by an application in the data system and convert the data access command into a block protocol command. The host 101 is further configured to send a block protocol command to the DPU, instructing the DPU 102 to obtain and execute the data access command. The host 101 is further configured to obtain an execution result from the DPU 102.

[0086] Optionally, the data access command includes a non-block protocol command. That is, the host 101 is used to convert the non-block protocol command into a block protocol command. It should be noted that the block protocol command is a command that complies with the block protocol, and the non-block protocol command is a command that complies with the non-block protocol. Block protocols include NVMe protocol, SCSI protocol, etc.

[0087] DPU102 is used to receive block protocol commands sent by the host 101, parse the block protocol commands, obtain data access commands initiated by applications of the data system, execute the data access commands, obtain execution results, and feed back the execution results to the host 101.

[0088] Referring to Figure 2, Figure 2 is a schematic diagram of an application architecture of an embodiment of the present application. As shown in Figure 2, the DPU interface card 100 is coupled to the host 200 via a peripheral component interconnect express (PCIe) bus or other bus. In addition, the DPU interface card 100 includes a printed circuit board 1011, an interface 1012, a DPU chip 101 and software 1013, and the interface 1012 and the DPU chip 101 are installed on the printed circuit board 1011. Specifically, the interface 1012 can be a PCIe interface. The software 1013 can be the operating system of the DPU interface card 100, and the operating system includes a system service component unit 102, a soft reset unit 103, a memory supervision unit 104, and a microkernel unit 105. Furthermore, the DPU interface card 100 can also include a micro reset unit 106 and the like. The software shown in FIG. 2 may be specifically implemented in the memory of the DPU interface card; the software shown in FIG. 2 may also be embedded, etc., which is not limited in the embodiment of the present invention.

[0089] The DPU chip 101 is used to control the DPU interface card 100 to provide storage services for the host 200, that is, to process storage-type services, such as non-volatile memory express (NVMe), virtiofs (see https: / / virtio-fs.gitlab.io / for details), virtio_scsi, etc. Alternatively, the DPU chip 101 can also control the DPU interface card 100 to provide computing services for the host 200, that is, to process computing-type services. In addition, when the operating system and other software of the DPU interface card 100 are restarted, the DPU chip 101 can control the DPU interface card 100 to resume the interrupted services (such as the above-mentioned storage-type services or computing-type services, etc.).

[0090] The system service component unit 102 includes multiple service components in the operating system kernel, and these multiple service components can use the memory in the DPU interface card 100 to provide services for the operating system in the DPU interface card 100, such as the driver component, file system component, memory management component, and network protocol component shown in Figure 2. The driver component is used to drive data communication between the DPU interface card 100 and the host 200, and can include a driver framework and a set of entity business drivers; the file system component is used to provide file system services, such as storing, reading, and managing data in the form of files; the memory management component is used to provide memory management services, such as allocating, reclaiming, and isolating memory areas; and the network protocol component is used to provide network protocol services, such as Hypertext Transfer Protocol (HTTP).

[0091] The soft reset unit 103 is used to reset the hardware units in the DPU interface card 100 and restart the software such as the operating system of the DPU interface card 100.

[0092] The memory supervision unit 104 is used to perform fault monitoring, fault repair, fault isolation, and redundant area replacement on the memory in the DPU interface card 100 to ensure the reliability, availability, and serviceability (RAS) of the memory in the DPU interface card 100.

[0093] The microkernel unit 105 is used to manage resources in the DPU interface card 100 and split the service components of the kernel so that the service components of the kernel can be restarted separately.

[0094] The micro-reset unit 106 is used to control the service components in the kernel of the operating system to be restarted separately through the micro-kernel architecture.

[0095] Please refer to Figure 3, which is a schematic diagram of the structure of a computer device according to an embodiment of the present application. The computer device is the host 101 or DPU 102 shown in Figure 1 or Figure 2. The computer device includes one or more processors 301, a communication bus 302, a memory 303, and one or more communication interfaces 304.

[0096] The processor 301 is a general-purpose central processing unit (CPU), a network processing unit (NP), a data processing unit (DPU), a microprocessor, or one or more integrated circuits for implementing the solution of the present application, such as an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. Optionally, the PLD is a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. Optionally, the host 101 includes a CPU.

[0097] The communication bus 302 is used to transmit information between the above components. Optionally, the communication bus 302 is divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is used in the figure, but this does not mean that there is only one bus or one type of bus.

[0098] Optionally, the memory 303 is a read-only memory (ROM), a random access memory (RAM), an electrically erasable programmable read-only memory (EEPROM), an optical disc (including a compact disc read-only memory (CD-ROM), a compact disc, a laser disc, a digital versatile disc, a Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 303 exists independently and is connected to the processor 301 via the communication bus 302, or the memory 303 is integrated with the processor 301.

[0099] The communication interface 304 uses any transceiver-like device for communicating with other devices or communication networks. The communication interface 304 includes a wired communication interface and, optionally, a wireless communication interface. Examples of wired communication interfaces include Ethernet interfaces. Optionally, the Ethernet interface is an optical interface, an electrical interface, or a combination thereof. The wireless communication interface is a wireless local area network (WLAN) interface, a cellular network communication interface, or a combination thereof.

[0100] Optionally, in some embodiments, the computer device includes multiple processors, such as processor 301 and processor 305 shown in Figure 3. Each of these processors is a single-core processor or a multi-core processor. Optionally, the processor herein refers to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0101] In a specific implementation, as an embodiment, the computer device further includes an output device 306 and an input device 307. The output device 306 communicates with the processor 301 and can display information in a variety of ways. For example, the output device 306 is a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector. The input device 307 communicates with the processor 301 and can receive user input in a variety of ways. For example, the input device 307 is a mouse, a keyboard, a touch screen device, or a sensor device.

[0102] In some embodiments, the memory 303 is used to store program code 310 for executing the solution of the present application, and the processor 301 can execute the program code 310 stored in the memory 303. The program code includes one or more software modules, and the computer device can execute the program code 310 in the processor 301 and the memory 303.

[0103] The present invention can be applied to the LPT-FTL architecture, which mainly includes two parts: a learned index located in the internal storage of the DPU and a perfect hash table (PTHash) and an index array (Index Array) located in the host memory. The learned index is used to calculate the perfect hash table position of the current key, and the perfect hash table is used to calculate the unique position of the key in the index array. The perfect hash table dynamically determines whether to perform further sharding (Partition) based on the data distribution, thereby adapting to the requirements of the hardware data processing width. When the DPU receives an IO request from the network port, the microcode core (Ucode Core) takes over the IO request and uses the indexes on the DPU side and the host side to complete the task of converting the logical address (lva) therein into a physical address (pa).

[0104] As business processing demands evolve, the computing power requirements for the central processing unit (CPU) are becoming increasingly demanding. Currently, a data processing unit (DPU) interface card can serve as a CPU offload engine, collaborating with the CPU to achieve more efficient data processing capabilities. The DPU interface card can include an application-specific integrated circuit (ASIC), a processor, and memory. The ASIC and processor provide computing power for the CPU, while the memory temporarily stores the DPU interface card's business information.

[0105] In addition to being applied to host-side FTL scenarios, this technical solution can also be applied to various scenarios of DPU-based data access acceleration.

[0106] For example, in an RDMA scenario, the DPU can use the index structure proposed in this invention to complete address translation and execute data access instructions issued by the peer node without involving the host CPU. In this case, only support for RDMA instruction execution in addition to the support in this invention needs to be implemented in the DPU.

[0107] In the cloud computing scenario, DPU often serves as the base of virtualization, realizing the offloading and acceleration of some common basic functions of virtual machines, while managing the resources of virtual machines. In this scenario, the DPU-based index offloading proposed by the present invention can be used as the management interface of storage resources (memory and external memory) shared by virtual machines, realizing unified management of multiple storage resources and providing lower mapping conversion latency and higher bandwidth. The technical solution at this time is transformed into embedding the index proposed by the present invention into the existing DPU virtualization function pool, and the DPU takes over the address conversion operation when each virtual machine accesses the actual storage.

[0108] The present invention provides a data processing method. The data processing method of the present invention is described in detail below with reference to the accompanying drawings.

[0109] Referring to Figure 4, Figure 4 is a flow chart of a data processing method provided in an embodiment of the present application. As shown in Figure 1, a data processing method provided in an embodiment of the present application may include steps 401 to 403, and these steps are described in detail below.

[0110] 401. Obtain the target logical address.

[0111] In one possible implementation, the computing device may obtain a data access request, such as a data read request, a data write request, or a read-write request, etc. The data access request may carry a logical address, that is, the logical address of the storage space to be accessed.

[0112] For example, the data access request may be an I / O read request.

[0113] The computing device may be a DPU, a host, or a smart network card.

[0114] In an embodiment of the present application, when the computing device obtains a data access request, it can execute the step of converting the logical address into a physical address. In an embodiment of the present application, the logical address can be converted into a physical address by executing a query of the LPT-FTL index.

[0115] For example, when the DPU receives an IO read request from the outside world, it will perform a query of the LPT-FTL index to find the pa (physical address) corresponding to the lva (logical address) contained in the request.

[0116] 402. Determine a target hash table corresponding to the target logical address based on the target logical address and the target index, where the target index indicates a mapping relationship between a logical address and a hash table, and the target hash table indicates a mapping relationship between a logical address and a physical address, and different hash tables indicated by the target index include different ranges of logical addresses.

[0117] 403. Determine a target physical address corresponding to the target logical address according to the target hash table.

[0118] In an embodiment of the present application, the conversion between the logical address and the physical address is performed by combining an index with a hash table (perfect hash table), wherein the index (such as the target index described in the embodiment of the present application) can be used to indicate the mapping relationship between the logical address and the hash table, and the hash table can indicate the mapping relationship between the logical address and the physical address.

[0119] In the existing technology, the physical address is directly confirmed through index information (for example, the logical address is input as the key value, and the physical address is output as the value value). Although the computational overhead of the index information is less than that of the scheme that only uses a hash table for physical address mapping (no complex hash operation is required), however, when the number of logical addresses is large, the address mapping process through index information requires a large time overhead. In the embodiment of the present application, the index information does not need to map the logical address to the physical address, but is mapped to the hash table corresponding to the logical address, thereby reducing the time overhead. Different hash tables maintain different logical addresses, which is equivalent to splitting a large hash table into small hash tables, thereby reducing the computational overhead. In other words, the embodiment of the present application reduces the time overhead compared to the scheme that only uses index information, and reduces the computational overhead compared to the address mapping scheme that only uses a hash table, thereby achieving a balance between time overhead and computational overhead.

[0120] Next, we will introduce indexes and hash tables respectively.

[0121] About indexes:

[0122] In an embodiment of the present application, the index may input the logical address as a key value and the indication information of the hash table (eg, the identifier of the hash table) as a value value as input.

[0123] In a possible implementation, the target index is a learning index, which includes a multi-level index, each level of index includes at least one segment, and each segment included in the last level of index of the multi-level index corresponds to a hash table.

[0124] Among them, each segment maintains a functional relationship (for example, a linear relationship), the input of which is the logical address, and the logical address is used as the key value. The segment can map the key value to the output value through the functional relationship maintained by itself. When the segment is not the last level index, the segment corresponding to the logical address in the next level index can be determined based on the value (since the result obtained based on the functional relationship may not be accurate, the range of the segment corresponding to the logical address in the next level index can be determined based on the value obtained based on the functional relationship, that is, which segments, and then determine which specific one it is from multiple segments), and so on, until the corresponding segment in the index of the bottom layer (that is, the last level index) is determined. Since each segment included in the last level index corresponds to a hash table, the hash table corresponding to the logical address can be determined.

[0125] The target structure can be a tree structure, the index at the head can be the root segment, and the index at the bottom can be the leaf segment. As the index approaches the bottom, the number of segments increases, and the range of logical addresses maintained by the segments decreases.

[0126] About hash tables:

[0127] The target hash table indicates a mapping relationship between logical addresses and physical addresses.

[0128] The hash table may be a perfect hash table. For example, the target hash table may indicate that a unique correspondence exists between a logical address and a physical address. In other words, a physical address can be uniquely determined based on a logical address.

[0129] A perfect hash table ensures that each existing address mapping pair uniquely occupies a position in the index array, resulting in a storage efficiency advantage over both three-level page tables and traditional hash tables. While the metadata in a perfect hash table incurs some additional space overhead, appropriate compression algorithms can reduce the storage space occupied, making the space overhead negligible compared to the space saved by the index data.

[0130] When building a perfect hash table, each logical address (key) maintained in a leaf segment can be inserted into a bucket of the hash table. The perfect hash table maintains an additional pilot number for each bucket to avoid conflicts. When calculating the actual location of the key, the final mapping location is determined by combining the hash of the key itself with the hash value of the pilot of the bucket it belongs to, thereby improving the query efficiency of the last layer.

[0131] In one possible implementation, the hash table may indicate a mapping relationship between a logical address and a storage location where a physical address is located, and then based on the storage location where the physical address is located, the physical address may be obtained. For example, referring to FIG. 5 , the PT hash shown in FIG. 5 may be a target hash table, and the table array may carry a physical address. Based on the PT hash, the storage location where the physical address is located (e.g., an address offset) is determined, and based on the storage location where the physical address is located, the physical address may be obtained from the table array.

[0132] In an embodiment of the present application, the target index can be stored in the memory of a computing device. The computing device can be a device including a network processor. The computing device is different from the host. For example, it can be a DPU, a programmable switch, a router and other network computing devices. The target hash table is stored in the host (for example, the host's DMA buffer); the computing device can determine the target hash table corresponding to the target logical address by accessing the target index in the memory according to the target logical address; the computing device can determine the target physical address corresponding to the target logical address according to the target hash table through communication with the host.

[0133] In some scenarios, the host has more storage resources, while the DPU has more parallel computing resources. Index information is stored in the DPU, which performs relevant processing on the index information. The hash table is stored in the host. The DPU communicates with the host to use the hash table to determine the relevant processing for the physical address, allowing the host to fully utilize its storage resources and be responsible for storing and maintaining the perfect hash table and the actual index data. To fully utilize the DPU's computing resources, a space-efficient learned index is loaded into the DPU's memory space, reducing the number of communications between the DPU and the host. Each microkernel requires only a minimal amount of memory to complete tasks such as inferring the perfect hash table location using the learned index, decompressing the perfect hash table metadata, and calculating the hash table. Because there are many DPU microkernels and they each have independent stack space, the system can achieve extremely high parallelism in calculating the FTL index location, allowing a single DPU to simultaneously handle a large number of data access requests.

[0134] Next, we will introduce the specific implementation method of determining the physical address corresponding to the logical address based on the index and hash table:

[0135] In one possible implementation, the DPU processor (e.g., microkernel Ucode) can determine the hash table corresponding to the logical address by accessing the index in the content. When the index is a multi-level index, the DPU processor needs to obtain the segment data (e.g., when the segment maintains a linear function relationship, the segment data is the slope k and intercept b. In addition, the segment data may also include the range of the maintained logical address), and the DPU processor needs to perform operations based on the data.

[0136] For example, the above operations may include but are not limited to:

[0137] The output is calculated based on the input (such as the logical address) and the functional relationship indicated by the segment data (such as the linear function indicated by the slope k and the intercept b). Based on the output, the segments corresponding to the next level can be determined (for example, including the first segment and the second segment). For example, based on the output, the corresponding only segment can be determined, but since the functional relationship may be inaccurate, that is, the target logical address is not within the logical address range maintained by the segment, it is necessary to obtain multiple segments near the determined only segment (for example, the maintained logical addresses are adjacent to the segment determined by the functional relationship). The segment whose maintained logical address range includes the target logical address is selected from the multiple segments. The hash table corresponding to the segment is the hash table corresponding to the target logical address. The above process of determining the segment whose logical address range includes the target logical address from multiple segments also needs to be executed by the DPU processor.

[0138] In the above process, the DPU processor needs to access the memory to obtain the data of multiple segments and perform operations (the process of determining the logical address range including the segment of the target logical address from multiple segments). Due to the limited reading bandwidth, it is often only possible to access the data of a small part of the segment at a time. Therefore, multiple accesses are required, and in each access process, the DPU processor needs to send a data acquisition request to the memory. After that, it takes a certain amount of time to move the data from the memory to the internal data stack of the DPU to perform the operation. If you wait for the operation execution process to be completed before continuing to obtain other parts of the segment, it will result in a large time overhead (equivalent to the data reading and operation being performed serially, and the time overhead is the sum of the two). In order to speed up the above process, in the embodiment of the present application, the data of a part of the segment can be read first, and then a data acquisition request can be sent to the memory while performing the operation on the data of this part of the segment. While performing the data operation, the data is also being moved from the memory to the internal data stack of the DPU, thereby reducing the overall time overhead.

[0139] For example, the first segment among multiple segments can be read first (for example, the data of the first segment can be read from the memory through a first request). The first segment can include at least one segment. Afterwards, when the DPU processor performs an operation based on the data of the first segment, it can send a second request to the memory. The second request indicates to read the data of the second segment in the target index.

[0140] For example, the segment determined based on the functional relationship is number 4, and multiple segments (1 to 7) near number 4 need to be obtained. The DPU processor can first request to read the data of segments 1 to 4. At this time, the memory works. After obtaining the data of segments 1 to 4, the DPU processor can read the data of segments 5 to 8 at the same time. At this time, the DPU processor and memory are both in working state.

[0141] As shown in Figure 6, there is an error when using a learned index to infer the inner segment. When the calculated position is pos, a local search is required from the pos-epsilon_recursive position, starting from the front and working backwards. Each segment is retrieved in turn and its first_key is compared to determine the final segment. As mentioned earlier, LPT-FTL selects the smallest possible epsilon_recursive during training. However, in practice, the number of layers has a greater impact on the inference latency of the learned index. Therefore, LPT-FTL assumes that the number of layers will not be increased, which to some extent increases the error. To address this issue, LPT-FTL takes the memory access characteristics of the DPU into consideration during implementation. On the one hand, it uses a wider SM access API to prefetch the next segment that may be accessed. On the other hand, it utilizes pipelining principles to issue memory access requests for segments 5-8 while accessing segments 1-4. At this time, the computing core of the DPU and the SM are working at the same time. After the access to segments 1-4 is completed, segments 5-8 have also been moved from the SM to the internal data stack of the DPU core, thereby improving memory access efficiency.

[0142] In a possible implementation, the data of the first segment includes floating-point numbers, and the operation includes: quantizing the floating-point numbers into integer data, and performing the operation based on the integer data.

[0143] As shown in Figure 7, in some scenarios, the DPU is a heterogeneous network accelerator based on a many-core architecture, with hundreds of microcode cores capable of simultaneously executing network, storage, and compute tasks. The DPU is also equipped with a dedicated storage accelerator, Smart Memory, which not only provides shared memory between microcode cores but also provides access accelerators for data structures such as linear lists, hash tables, and bitmaps. Microcode cores can invoke various hardware accelerators through their peripheral hardware circuits, including sending DMA requests to the host using the CPI. Each microcode core has its own KB-level stack space and temporary storage space, SPRAM, to support parallel computing of simple tasks.

[0144] The learning index based on linear function essentially expresses the mapping relationship between the key and its position through a piecewise linear function: y=K*x+b. During the training process, the learning index obtains a slope K of the mapping relationship that covers as many as possible by linear fitting, so this K is a floating point number. In some embedded processor architectures, only integer arithmetic instructions are supported, and floating-point arithmetic instructions are not supported. Therefore, in the embodiment, the embodiment of the present application designs two schemes based on simulated floating-point numbers and software simulated floating-point numbers based on the IEEE 754 standard, which can be selected based on the measurement of the DPU core computing performance and memory access performance.

[0145] Refer to Figure 8, which is a schematic diagram of integer simulation of floating-point operations. The principle of integer simulation of floating-point operations is shown in Figure 8. In the embodiment of the present application, a MASK value is used to convert the floating-point number K into an integer K' with minimal loss of precision, and K' is used to participate in the calculation of the linear function. The integer simulation method will not cause incorrect query results due to loss of precision. First of all, the query of the leaf segment has been converted into a deterministic perfect hash table query, which is not affected by errors. In the process of searching for the inner segment, the process of converting K to the integer K' may overflow, causing the final calculated pos to be smaller than the actual one. Start from the position of pos-epsilon and search from small to large until a segment is found, whose range just contains the target key. A small pos may slightly expand the search range, but it will not cause the correct segment to be found.

[0146] This embodiment of the application implements the IEEE754 floating-point representation method. Based on 32-bit single precision, a 32-bit unsigned integer is divided into a sign bit, an exponent, and a mantissa, and is defined as soft_f32. Based on the IEEE754 standard, the following floating-point arithmetic methods are implemented according to the calculation requirements:

[0147] soft_f32 Int_to_f32(int64): accepts a signed 64-bit integer variable and converts it to a soft_f32 type, soft_f32 f32_mul(soft_f32,soft_f32): accepts two soft_f32 type variables to perform floating-point multiplication and return the result, soft_f32 f32_add(soft_f32,soft_f32): accepts two soft_f32 type variables to perform floating-point addition and return the result, int64 f32_to_int(soft_f32): accepts a soft_f32 type variable and converts it to a signed 64-bit integer.

[0148] During the host's LFP-FTL index construction process, the common float type is used to represent floating-point numbers in the learned index model. This allows for computational acceleration using a hardware-implemented floating-point arithmetic unit. After index construction is complete, the float type variables in the learned index are converted to 32-bit unsigned integers and saved to the DPU's internal memory. Depending on the selected solution, the DPU performs learned index calculations using either integer emulation or software emulation.

[0149] In addition, in some scenarios, the DPU supports accessing memory in the form of a linear list, storing data in the memory in a 16-byte aligned manner, and each microcode core can access the linear table through a unique linear table index to obtain the data therein. The present invention re-represents the learning index trained by the host in the form of a linear table, as shown in Figure 9. Each segment contains a 64-bit integer data first_key, a 64-bit integer data intercept and a 32-bit floating point number slope, so one unit in the linear table is used to store a segment. The tree-shaped learning index is traversed hierarchically and all segments of each layer are stored in the near memory from back to front. In addition, a level_offsets array must be stored to represent the number of segments each layer has. In this way, the learning index is unloaded. When the microcode core queries through a key, the level_offsets array is first obtained from the memory, and the offset of the root segment is determined. Next, a loop is executed, each time a segment is obtained from the memory and an inference calculation is performed using the model data stored therein (Y=slope*X+intercept) to obtain the serial number (s_idx) of the next layer of segments, and its offset in the linear table is determined based on level_offset. It should be noted that the search of the learned index is not an exact search, and the position obtained by the model calculation may be erroneous. Therefore, it is necessary to perform a binary search within the error constraint around the inferred position, and obtain the value of each segment in turn and compare it based on the first_key to determine the correct segment position. The loop stops after the serial number of the last layer of segments is determined. The serial number of the PTHash where the key is located can be determined by the s_idx serial number at this time.

[0150] The calculation process of the perfect hash table is shown in Figure 10. The corresponding bucket number is obtained according to the key-value hash, and then the pilot value in the bucket is obtained. The hash of the pilot value is merged with the key hash to obtain the actual location of the current key. The number of buckets is determined by the total number of keys in the current hash table, and the array composed of the pilots in all buckets is compressed and stored by prefix compression. In addition to the pilot, metadata such as bucket_size, key_size, and prefix length are also needed in the calculation process of the perfect hash table. Because the last layer in the learned index, that is, the determination of the leaf segment, only requires first_key, and the slope and intercept fields are not used. Therefore, this part of the metadata of the perfect hash table can be stored in these locations, so that when the leaf segment is obtained through the calculation of the learned index, the metadata of the perfect hash table can be obtained at the same time, avoiding additional memory access.

[0151] In addition, the DMA address of the pilot array and the DMA address of the Table Array in each PTHash are also stored in memory in 16-byte units and indexed by s_idx obtained from the leaf segment.

[0152] In some scenarios, because indexes and hash tables are static structures, when the mapping between logical addresses and physical addresses changes (for example, additions, edits, or deletions), the indexes or hash tables need to be updated accordingly. During this update, the FTL will be unable to provide services. To shorten the intervals during which service is unavailable and improve the availability of the LPT-FTL, the present invention proposes a delayed update strategy for hybrid indexes based on the structural characteristics of the LPT-FTL.

[0153] Specifically, when the modification information for the mapping relationship between the logical address and the physical address is obtained, a local update can be performed. The so-called local update means that only the hash table is updated, and the target index table is not updated. The reason is that: no matter whether the modification operation is editing, deleting or adding, the logical address included in the information to be modified is often within the range of logical addresses already maintained in the target index table. The logical address in the modification information can always be mapped to a hash table. Therefore, even if the target index table is not updated, it will not affect the correctness of the address conversion. In this case, only a local update is required.

[0154] However, in some cases, the logical address in the modification information is very small or very large. Such logical addresses may correspond to some special segments, such as segments with extremely small maintained logical addresses (for example, segment_(-∞)) and segments with extremely large maintained logical addresses (for example, segment_(+∞)). If the target index table is not updated, the number of logical addresses in the above two segments will increase with the accumulation of time. In order to ensure the overall performance, the index table and hash table need to be recalculated so that the distribution of logical addresses in each segment is more balanced. At this time, the update process of the index table and hash table can be called a global update.

[0155] The following is a detailed process diagram: First, the LPT-FTL scans for update information, which indicates updates to the mapping between logical and physical addresses. This update information can be performed in batches. For logical pages already in the existing index structure, the LPT-FTL can locate the physical address indicated in the hash table based on the existing index and update it in place. Supporting in-place updates is an advantage of the LPT-FTL over FTL structures based on learned indexes.

[0156] Optionally, LPT-FTL can update leaf segments during index updates. LPT-FTL sorts the remaining operations by key and partitions them according to the key range of the leaf segments in the existing index structure. It then processes each leaf segment in ascending order. The remaining operations involve inserting new logical page-to-physical page mapping pairs and deleting old logical pages. LPT-FTL merges the insertions and deletions into the table array corresponding to the existing leaf segments and trains and updates the perfect hash table on the new table array. The leaf segment boundaries remain unchanged. For the inner segment, the mapping from key to leaf segment is essentially the mapping to the leaf segment boundaries, so the existing inner segment can still be used to find the correct leaf segment. For the case where the new insertion key is not within the existing leaf segment boundaries, two special leaf segments, segment_(-∞) and segment_(+∞), are added for these cases. All keys not within the existing leaf segment range are inserted into these two segments. In this case, batch updates only require changing the data structure of the bottom-level leaf segments and the perfect hash table, without having to update the inner segment in the DPU. Besides the leaf segment being rebuilt, the other leaf segments and their key ranges continue to function normally. As the number of batch updates increases, segment_(-∞) and segment_∞ grow larger, and the number of keys in the remaining leaf segments also gradually increases, increasing the time it takes to build the perfect hash table. Therefore, LPT-FTL periodically triggers a bottom-up retraining of the entire index structure to ensure a balance between build time and leaf segment size.

[0157] In one possible implementation, during a local update, update information may be received, the update information being used to indicate an update to a mapping relationship between a logical address and a physical address; the logical address to be updated indicated by the update information belongs to a range of logical addresses included in the target hash table; and the target hash table is updated based on the update information.

[0158] In one possible implementation, when updating the target hash table, the target hash table does not satisfy the first preset condition (for example, it is in a locked state, more specifically, all the values ​​in the hash table are set to preset fixed values). In this case, when accessing the hash table, it can be known that it is in an update state, and re-access can be made after waiting for a certain period of time. That is, when it is determined by accessing the target hash table that the target hash table does not satisfy the first preset condition, the target hash table is re-accessed until it is determined by accessing the target hash table that the target hash table satisfies the first preset condition, the storage location of the target physical address where the target logical address is located is determined, and the target physical address is obtained from the storage location.

[0159] In one possible implementation, when the target hash table is updated and the target index table is not updated (that is, during a partial update), the target hash table can be set to not satisfy the first preset condition; when the update of the target hash table is completed, the target hash table can be unlocked so that it satisfies the first preset condition (for example, updated to a newly calculated hash table).

[0160] For example, when performing a local update, the host can perform a local update after receiving a batch of index update requests. For multiple update operations, they are sorted by key and divided according to the key range of the leaf segment. Local updates are performed on each leaf segment in order from small to large keys, and all metadata of PTHash are set to specific values, indicating that the leaf segment is locked. After that, all queries for this leaf segment are suspended, the data in the Table Array is reordered, and all operations are performed: insert, delete, and update pa. After that, PTHash can be rebuilt and updated on the new Table Array, indicating that the leaf segment is unlocked.

[0161] In one possible implementation, when performing the calculation to update the target index table (that is, global update), the target index table is set to not satisfy the second preset condition; when the calculation of the target index table is completed, the target index table is set to satisfy the second preset condition.

[0162] Furthermore, when it is determined by accessing the target index table that the target index table does not meet the second preset condition, the target index table can be re-accessed after a waiting period of time until it is determined by accessing the target index table that the target index table meets the second preset condition, and the target hash table corresponding to the target logical address is determined based on the logical address and the target index.

[0163] In one possible implementation, when calculating the index table (for example, during a global update), multiple hash tables including the target hash table can be calculated based on the currently included logical addresses, and the error constraint can be determined based on the multiple hash tables, and the target index can be obtained based on the error constraint; wherein, the first parameter is the error constraint of the last layer segment, and the first parameter is the maximum error constraint that can minimize the logical address range contained in the root segment; or, the first parameter is the error constraint of the internal segment, and the first parameter is the minimum error constraint that can prevent the level of the internal segment from increasing.

[0164] For example, when the agreed time is reached, which is often a relatively idle time for the system, the host starts to perform a global update by issuing instructions to the DPU to modify the root segment, indicating that the entire index is locked. After that, all query operations of the DPU are suspended, and all data in the Table Array are reordered according to the key. According to the construction time constraint, the largest epsilon is found to minimize the number of leaf segments. The found epsilon is used to build all leaf segments, including the PTHash and sharding the Table Array. On top of the leaf segment, the smallest epsilon_recursive is found according to the layer number constraint of the inner segment to minimize the error constraint of the inner segment. The found epsilon_recursive is used to iteratively build the inner segment, and the new inner segment is sent to the DPU's memory storage, indicating that the entire index is unlocked and the response to the DPU query is restored.

[0165] The index structure proposed in the embodiment of the present application can dynamically adjust the index structure according to the storage capacity of the multi-core DPU, and obtain better performance under the premise of adapting to the resource constraints of different architectures and scenarios. The correspondence between the learned index and the perfect hash is shown in Figure 10. The learned index establishes a linear function (also called a segment) for a series of ordered keys based on the error constraint (epsilon). The larger the error constraint, the more keys a segment can contain. These segments represent the mapping relationship between keys and values, which are called leaf segments. Above the leaf segment, LPT-FTL continues to build the learned index, which is called the inner segment, representing the mapping relationship between keys and segments. LPT-FTL builds segments layer by layer until there is only one segment at a certain layer. In order to solve the query error problem of the learned index, LPT-FTL converts each leaf segment into a perfect hash table, thereby fixing the query time of the last layer to O(1). When building a perfect hash table, LPT-FTL inserts each key in a leaf segment into a bucket of the hash table. The perfect hash table maintains an additional pilot number for each bucket to avoid conflicts. When calculating the actual location of a key, the final mapping position is determined by combining the key's hash value with the hash value of the pilot in its bucket, thereby improving query efficiency at the final level. At this point, epsilon no longer affects leaf segment query time, but primarily affects the index's DPU space overhead. However, adjusting epsilon is still constrained by the perfect hash table's build time. A larger epsilon results in larger leaf segments, which in turn results in more keys in a perfect hash table. Consequently, more time is spent searching for a non-collision pilot for each bucket. One approach is to find the maximum epsilon within a specific build time constraint to minimize the number of generated segments, thereby reducing the size of the learned index and lowering DPU space overhead. Another key parameter is the error bound for building inner segments (epsilon_recursive), which primarily affects the number of inner segments and query time. Because the number of inner segments is greatly reduced compared to leaf segments, epsilon_recursive mainly affects the query time of the index.If the number of inner segments is too large, the inner segment level will increase, which will cause more calculations. Therefore, one approach is to find the minimum epsilon_recursive while ensuring that the inner segment level does not increase so that the error when querying the inner segment is minimized. In an embodiment of the present application, we use a binary algorithm to find the maximum epsilon and epsilon_recursive that meet the conditions according to time and space constraints when building the index, thereby maximizing the space utilization of the DPU and query efficiency.

[0166] The embodiment of the present application ensures the consistency of the index through read-write separation and fine-grained update locks. The DPU is only responsible for processing index queries, and the above-mentioned update operations are all completed by the host, thereby avoiding the huge overhead of synchronization between the many micro-cores of the DPU. Before the host executes the index update, part of the data structure will be modified through atomic operations. Therefore, after the DPU executes the query operation to obtain the corresponding data structure, it will know that the data to be accessed at this time is being updated, so the DPU will wait for a period of time and re-initiate the request. As mentioned above, the update of the index structure is divided into two types: local update and full update. Among them, the local update only involves the update of PTHash and Table Array. Before rebuilding PTHash, the host first sets all metadata in PTHash, including pilot, to a specific number, such as the maximum value, to indicate that the current partial perfect hash table is being retrained. At this time, all DPU access to this perfect hash table will be suspended until the host restores the metadata of PTHash to the correct value after the construction is completed. For a full update, the host first sends an instruction to the DPU to modify the top-level segment and set it to a specific value, thereby notifying the DPU that a full update is currently being performed. All query operations are suspended until the host completes the update and sends the new inner segment value.

[0167] Next, we will introduce a specific process diagram of converting a logical address into a physical address in an embodiment of the present application.

[0168] When the DPU receives an IO read request from the outside world, it will execute a query of the LPT-FTL index to find the pa (physical address) corresponding to the lva (logical address) contained in the request, access the root segment in the DPU memory storage, and determine whether it is currently in the full update phase. If so, wait for a while and re-initiate the request to access the root segment. If not, access the next layer based on the segment's reasoning results until the corresponding leaf segment is found. Go to the next step and determine whether it is currently in the local update phase based on the content of the leaf segment. If so, wait for a while and re-initiate the request for the leaf segment. If not, calculate the location of the data corresponding to the specified lva based on the data in the leaf segment, go to the next step, and access the pa through the calculated location.

[0169] 11 , which is a schematic diagram of the structure of a data processing device provided in an embodiment of the present application. As shown in FIG11 , a data processing device provided in an embodiment of the present application, the device 1100 includes:

[0170] An acquisition module 1101 is configured to acquire a target logical address;

[0171] The description of the acquisition module 1101 can refer to the introduction of step 401 in the above embodiment, and will not be repeated here.

[0172] Processing module 1102 is used to determine the target hash table corresponding to the target logical address based on the target logical address and the target index, the target index indicates the mapping relationship between the logical address and the hash table, the target hash table indicates the mapping relationship between the logical address and the physical address, and different hash tables indicated by the target index include logical addresses in different ranges; based on the target hash table, determine the target physical address corresponding to the target logical address.

[0173] The description of the processing module 1102 may refer to the introduction of steps 402 and 403 in the above embodiment, and will not be repeated here.

[0174] In a possible implementation, the target hash table indicates that there is a unique correspondence between the logical address and the physical address.

[0175] In one possible implementation, the target index is stored in a memory of a computing device, the target hash table is stored in a host, the computing device and the host are different, and the computing device further includes a network processor;

[0176] The processing module is specifically used to:

[0177] The computing device determines, according to the target logical address, a target hash table corresponding to the target logical address by accessing a target index in the memory;

[0178] The computing device determines the target physical address corresponding to the target logical address according to the target hash table through communication with the host.

[0179] In a possible implementation, the computing device is a DPU, a programmable switch, or a router.

[0180] In a possible implementation, the target index is a learned index, and the target index includes multiple segments; the processing module is specifically configured to:

[0181] Sending a first request to the memory, where the first request indicates reading data of a first segment among the multiple segments;

[0182] When performing an operation based on the data of the first segment, a second request is sent to the memory, where the second request indicates to read the data of the second segment in the target index.

[0183] In a possible implementation, the data of the first segment includes floating-point numbers, and the processing module is specifically configured to:

[0184] The floating-point number is quantized into integer data, and calculation is performed based on the integer data.

[0185] In a possible implementation, the processing module is specifically configured to:

[0186] According to the target hash table, a storage location of a target physical address where the target logical address is located is determined, and the target physical address is obtained from the storage location.

[0187] In a possible implementation, the target index is a learning index, which includes a multi-level index, each level of index includes at least one segment, and each segment included in the last level of index of the multi-level index corresponds to a hash table.

[0188] In a possible implementation, the processing module is specifically configured to:

[0189] When it is determined by accessing the target hash table that the target hash table does not satisfy the first preset condition, the target hash table is re-accessed until it is determined by accessing the target hash table that the target hash table satisfies the first preset condition, a storage location of the target physical address where the target logical address is located is determined, and the target physical address is obtained from the storage location.

[0190] In a possible implementation, the processing module is further configured to:

[0191] receiving update information, the update information being used to indicate an update of a mapping relationship between a logical address and a physical address; the logical address to be updated indicated by the update information belongs to a range of logical addresses included in the target hash table;

[0192] The target hash table is updated according to the update information.

[0193] In a possible implementation, when the target hash table is updated, the target hash table does not meet the first preset condition; when the target hash table is updated, the target hash table meets the first preset condition.

[0194] In a possible implementation, the processing module is specifically configured to:

[0195] When it is determined by accessing the target index table that the target index table does not meet the second preset condition, the target index table is re-accessed after a waiting period of time until it is determined by accessing the target index table that the target index table meets the second preset condition, and the target hash table corresponding to the target logical address is determined according to the logical address and the target index.

[0196] In a possible implementation, the target index is a multi-layer index including a last layer segment and an internal segment. The processing module is further configured to:

[0197] Based on the currently included logical addresses, a plurality of hash tables including the target hash table are calculated;

[0198] Determine an error constraint based on the multiple hash tables, and obtain the target index based on the error constraint; wherein,

[0199] The first parameter is the error constraint of the last layer segment, and the first parameter is the maximum error constraint that can minimize the logical address range included in the root segment; or

[0200] The first parameter is an error constraint of an internal segment, and the first parameter is a minimum error constraint that enables the level of the internal segment not to increase.

[0201] In a possible implementation, when calculating the target index table, the target index table does not satisfy the second preset condition; when calculating the target index table, the target index table satisfies the second preset condition.

[0202] To implement the various functions of the methods provided in the embodiments of the present application, the data reading system or the data writing system may include hardware structures and / or software modules, and the aforementioned functions may be implemented in the form of hardware structures, software modules, or a combination of hardware structures and software modules. Whether a particular function is implemented in the form of hardware structures, software modules, or a combination of hardware structures and software modules depends on the specific application and design constraints of the technical solution.

[0203] An embodiment of the present application also provides a computer-readable storage medium, including computer-readable instructions. When the computer-readable instructions are executed on a computer, the computer executes any one of the implementation methods shown in the aforementioned method embodiments.

[0204] An embodiment of the present application also provides a computer program product, which includes a computer program or instructions. When the computer program or instructions are run on a computer, the computer executes any one of the implementation methods shown in the aforementioned method embodiments.

[0205] The present application also provides a chip or chip system, which may include a processor. The chip may also include a memory (or storage module) and / or a transceiver (or communication module), or the chip is coupled to a memory (or storage module) and / or a transceiver (or communication module), wherein the transceiver (or communication module) can be used to support the chip for wired and / or wireless communication, and the memory (or storage module) can be used to store a program or a set of instructions, and the processor calls the program or the set of instructions to implement the above-mentioned method embodiment, the operation performed by the terminal or network device in any possible implementation of the method embodiment. The chip system may include the above chip, and may also include the above chip and other discrete devices, such as memory (or storage module) and / or transceiver (or communication module).

[0206] It should also be noted that the device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed across multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment. In addition, in the drawings of the device embodiments provided in this application, the connection relationship between the modules indicates that there is a communication connection between them, which can be specifically implemented as one or more communication buses or signal lines.

[0207] Through the description of the above embodiments, those skilled in the art can clearly understand that the present application can be implemented by means of software plus necessary general-purpose hardware, and of course can also be implemented by dedicated hardware including application-specific integrated circuits, dedicated CPUs, dedicated memories, dedicated components, etc. In general, all functions performed by computer programs can be easily implemented by corresponding hardware, and the specific hardware structures used to implement the same function can also be diverse, such as analog circuits, digital circuits, or dedicated circuits. However, for the present application, software program implementation is a better implementation method in most cases. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a readable storage medium, such as a computer floppy disk, USB flash drive, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, etc., and includes a number of instructions for causing a computer device (which can be a personal computer, training equipment, or network equipment, etc.) to execute the methods described in each embodiment of the present application.

[0208] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware, or any combination thereof. When implemented by software, all or part of the embodiments may be implemented in the form of a computer program product.

[0209] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, training equipment or data center to another website, computer, training equipment or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that a computer can store or a data storage device such as a training device, data center, etc. that includes one or more available media integrations. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a high-density digital video disc (DVD)), or a semiconductor medium (e.g., a solid-state drive (SSD)).

Claims

1. A data processing method, characterized in that: The method comprises: Get the target logical address; Determining a target hash table corresponding to the target logical address according to the target logical address and a target index, wherein the target index indicates a mapping relationship between a logical address and a hash table, the target hash table indicates a mapping relationship between a logical address and a physical address, and different hash tables indicated by the target index include different ranges of logical addresses; Determine a target physical address corresponding to the target logical address according to the target hash table.

2. The method according to claim 1, characterized in that The target hash table indicates that there is a unique correspondence between the logical address and the physical address.

3. The method according to claim 1 or 2, characterized in that The target index includes multiple segments, each segment includes a different logical address range, and each segment corresponds to a hash table. Determining the target hash table corresponding to the target logical address according to the target logical address and the target index includes: A target segment corresponding to the logical address range where the target logical address is located is selected from the multiple segments, and the hash table corresponding to the target segment is the target hash table.

4. The method according to any one of claims 1 to 3, characterized in that: The target index is stored in a memory of a computing device, the target hash table is stored in a host, the computing device and the host are different, and the computing device further includes a network processor; The determining, according to the target logical address and the target index, a target hash table corresponding to the target logical address includes: The computing device determines, according to the target logical address, a target hash table corresponding to the target logical address by accessing a target index in the memory; Determining, according to the target hash table, a target physical address corresponding to the target logical address, comprising: The computing device determines the target physical address corresponding to the target logical address according to the target hash table through communication with the host.

5. The method according to claim 4, characterized in that The computing device is a DPU, a programmable switch or a router.

6. The method according to claim 4 or 5, characterized in that The target index includes multiple segments; and accessing the target index in the memory includes: Sending a first request to the memory, where the first request indicates reading data of a first segment among the multiple segments; When performing an operation based on the data of the first segment, a second request is sent to the memory, where the second request indicates to read the data of the second segment in the target index.

7. The method according to claim 6, characterized in that The data of the first segment includes floating-point numbers, and the operation includes: The floating-point number is quantized into integer data, and calculation is performed based on the integer data.

8. The method according to any one of claims 1 to 7, characterized in that: The determining, according to the target hash table, a target physical address corresponding to the target logical address includes: The target physical address storage location where the target logical address is located is determined according to the target hash table, and the target physical address is obtained from the storage location.

9. The method according to any one of claims 1 to 8, characterized in that: The target index is a learning index, which includes a multi-level index, each level of index includes at least one segment, and each segment included in the last level of index of the multi-level index corresponds to a hash table.

10. The method according to claim 8 or 9, characterized in that The determining, according to the target hash table, a target physical address corresponding to the target logical address includes: When it is determined by accessing the target hash table that the target hash table does not satisfy the first preset condition, the target hash table is re-accessed until it is determined by accessing the target hash table that the target hash table satisfies the first preset condition, a storage location of the target physical address where the target logical address is located is determined, and the target physical address is obtained from the storage location.

11. The method according to any one of claims 1 to 10, characterized in that: The method further comprises: receiving update information, the update information being used to indicate an update of a mapping relationship between a logical address and a physical address; the logical address to be updated indicated by the update information belongs to a range of logical addresses included in the target hash table; The target hash table is updated according to the update information.

12. The method according to claim 10 or 11, characterized in that The method further comprises: When updating the target hash table and not updating the target index table, setting the target hash table to not satisfy the first preset condition; When the update of the target hash table is completed, the target hash table is set to meet the first preset condition.

13. The method according to any one of claims 1 to 12, characterized in that: The determining, according to the logical address and the target index, a target hash table corresponding to the target logical address includes: When it is determined by accessing the target index table that the target index table does not meet the second preset condition, the target index table is re-accessed after a waiting period of time until it is determined by accessing the target index table that the target index table meets the second preset condition, and the target hash table corresponding to the target logical address is determined according to the logical address and the target index.

14. The method according to any one of claims 1 to 13, characterized in that: The target index is a multi-layer index, and the multi-layer index includes a last layer segment and an internal segment. The method further includes: Based on the currently included logical addresses, a plurality of hash tables including the target hash table are calculated; Determine an error constraint based on the multiple hash tables, and obtain the target index based on the error constraint; wherein, The first parameter is the error constraint of the last layer segment, and the first parameter is the maximum error constraint that can minimize the logical address range included in the root segment; or The first parameter is an error constraint of an internal segment, and the first parameter is a minimum error constraint that enables the level of the internal segment not to increase.

15. The method according to claim 13 or 14, characterized in that The method further comprises: When performing calculation to update the target index table, setting the target index table to not satisfy the second preset condition; When the calculation of the target index table is completed, the target index table is set to meet the second preset condition.

16. A data processing device, characterized in that: The device comprises: An acquisition module is used to obtain a target logical address; A processing module is used to determine a target hash table corresponding to the target logical address based on the target logical address and the target index, wherein the target index indicates a mapping relationship between the logical address and the hash table, the target hash table indicates a mapping relationship between the logical address and the physical address, and different hash tables indicated by the target index include logical addresses in different ranges; and determine a target physical address corresponding to the target logical address based on the target hash table.

17. A data processing device, characterized in that: include: a memory for storing computer-readable instructions; The method further comprises: a processor coupled to the memory, configured to execute the computer-readable instructions in the memory to perform the method according to any one of claims 1 to 15.

18. A computer-readable storage medium, characterized in that When the instructions are executed on a computer, the computer is caused to perform the method according to any one of claims 1 to 15.

19. A computer program product comprising instructions, characterized in that When the instructions are executed on a computer, the computer is caused to perform the method according to any one of claims 1 to 15.

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